Chip heat center positioning method based on pulse thermal excitation

Abstract

The application discloses a chip heat center positioning method based on pulse thermal excitation, comprising: obtaining physical geometric parameters of a chip including an effective heat-emitting area, controlling the opening and closing of corresponding flow channel valves in a multi-stage flow channel heat dissipation structure according to the effective heat-emitting area, matching the flow channel coverage range with the chip, applying a thermal pulse excitation to the chip and continuously sampling at a high frequency through a sensor array to obtain temperature time evolution information, extracting temperature rise rate characteristics and steady-state temperature amplitude characteristics and fusing the same to obtain a fusion weight matrix, calculating the heat distribution centroid coordinates of the chip according to the fusion weight matrix by using a weighted centroid algorithm, driving a multi-dimensional displacement table to perform physical alignment compensation according to the deviation of the centroid from a cooling center, and after the alignment is completed, performing double-variable closed-loop regulation on the flow rate and temperature of the fluid based on the real-time thermal state of the chip. The application realizes accurate positioning of the chip heat center and adaptive dynamic regulation and control of heat dissipation.

Description

Technical Field

[0001] This application relates to the field of integrated circuit chip heat dissipation testing technology, specifically to a method for locating the heat center of a chip based on pulsed thermal excitation. Background Technology

[0002] With the rapid development of technologies such as artificial intelligence, big data, and cloud computing, the computing power demand for high-performance integrated circuit chips is growing exponentially, leading to a sharp increase in their power density and heat generation. The thermal design power (TDP) of typical chips such as AI (Artificial Intelligence) accelerator chips and data center processors has exceeded the kilowatt level, with local hotspot heat flux densities reaching hundreds of watts per square centimeter. Related statistics show that approximately 55% of electronic product failures are directly related to thermal issues; for every 10°C increase in chip junction temperature, its reliability and lifespan decrease by about half. Microchannel liquid cooling technology, due to its high heat dissipation efficiency and compact structure, has become one of the mainstream solutions for addressing the heat dissipation challenges of high-power chips.

[0003] In related technologies, the fluid distribution and thermal management strategies of microchannel liquid cooling systems are mainly based on fixed flow channel configurations at the chip's geometric center, relying on average temperature feedback control from a small number of temperature monitoring points, and hotspot identification methods based on steady-state temperature field analysis of the chip surface. These methods have the following shortcomings in practical applications: fixed flow channel configurations cannot dynamically adjust the heat dissipation coverage according to the actual chip size, leading to wasted flow channels on the periphery of small-sized chips and insufficient heat dissipation in the edge areas of large-sized chips; positioning methods based on steady-state temperature amplitude do not fully utilize the transient response characteristics during the heat diffusion process, and the positioning accuracy decreases significantly when there are multiple adjacent heat sources inside the chip or when heat diffuses laterally; furthermore, they lack a complete control chain from precise heat source positioning to flow channel orientation matching to closed-loop heat dissipation adjustment, making it difficult to achieve precise matching of heat dissipation resources with the actual thermal distribution of the chip.

[0004] Therefore, how to accurately locate the heat center inside the chip, adaptively configure the flow channel coverage according to the actual size of the chip, and then form a closed-loop control between the heat center location result and the heat dissipation system is a technical problem that urgently needs to be solved in the field of chip heat dissipation management technology. Summary of the Invention

[0005] The main purpose of this application is to provide a chip heat center positioning method based on pulse thermal excitation, so as to solve the technical problem that the heat dissipation resources of the prior art cannot be matched with the actual heat distribution of the chip, and to achieve the technical effect of accurate positioning of the chip heat center and adaptive configuration of the flow channel coverage according to the actual size of the chip.

[0006] To achieve the above objectives, a first aspect of this application proposes a method for locating the chip heating center based on pulsed thermal excitation, comprising: Obtain the physical geometric parameters of the chip, wherein the physical geometric parameters include at least the effective heat-generating area; Based on the effective heat-generating area, the opening or closing of the flow channel valves in the multi-stage flow channel heat dissipation structure is controlled so that the heat dissipation coverage of the multi-stage flow channel heat dissipation structure matches the chip. The multi-stage flow channel heat dissipation structure is used to dissipate heat from the chip. The chip is subjected to thermal pulse excitation, and during the loading of the thermal pulse excitation, the chip is sampled at high frequency and continuously using a sensor array to obtain temperature time evolution information. Based on the temperature-time evolution information, a temperature rise rate matrix and a steady-state temperature amplitude matrix are constructed, and the temperature rise rate matrix and the steady-state temperature amplitude matrix are fused to obtain a fusion weight matrix; The weighted centroid algorithm is used to calculate the centroid coordinates of the heat distribution of the chip based on the fusion weight matrix; The cooling center coordinates of the multi-stage heat dissipation structure are obtained. Based on the deviation between the heat distribution centroid coordinates and the cooling center coordinates, the multi-dimensional displacement stage used to support the multi-stage heat dissipation structure is driven to move so that the cooling center of the multi-stage heat dissipation structure is aligned with the heat distribution centroid of the chip. After alignment, the flow rate and temperature of the fluid are adjusted in a two-variable closed-loop manner based on the real-time thermal state of the chip.

[0007] In some embodiments of this application, obtaining the physical geometric parameters of the chip specifically includes: During the process of the motor-driven clamp slider retracting towards the center, the change in motor current is monitored in real time. The clamp slider is used to contact the chip edge to sense the chip boundary. When the motor current exceeds the preset load threshold, it is determined that the slider has contacted the edge of the chip and stops retracting; The chip side length is calculated based on the shrinkage displacement of the slider and the mechanical transmission ratio, and the effective heating area of ​​the chip is deduced based on the chip side length.

[0008] In some embodiments of this application, the multi-stage heat dissipation structure includes independent central and peripheral heat dissipation channels. Valves are provided at the inlets of the central and peripheral heat dissipation channels. The opening or closing of the valves in the multi-stage heat dissipation structure is controlled according to the effective heat-generating area to match the heat dissipation coverage of the multi-stage heat dissipation structure with the chip. Specifically, this includes: The effective heating area is compared with a preset area threshold. If the effective heating area is less than the area threshold, the valve corresponding to the central channel of the multi-stage flow channel heat dissipation structure will be opened. If the effective heating area is greater than or equal to the area threshold, the valves of the central region and the outer flow channel are opened to form a parallel flow channel structure that matches the chip size.

[0009] In some embodiments of this application, the thermal pulse excitation of the chip includes: A low-power probe pulse is applied in advance to obtain the thermal time constant of the chip; The target pulse width is determined based on the thermal time constant and the preset multiple range; The first power limit is calculated based on the chip's rated power, and the second power limit is calculated based on the safe temperature rise threshold. The smaller value between the first power limit and the second power limit is taken as the target applied power. The chip is thermally pulse-excited based on the target pulse width and the target applied power.

[0010] In some embodiments of this application, the step of constructing a temperature rise rate matrix and a steady-state temperature amplitude matrix based on the temperature time evolution information, and fusing the temperature rise rate matrix and the steady-state temperature amplitude matrix to obtain a fusion weight matrix, specifically includes: Extract the temperature rise rate and steady-state temperature amplitude at each sensor location in the sensor array from the temperature time evolution information; A temperature rise rate matrix is ​​constructed based on the temperature rise rate at each sensor location, and a steady-state temperature amplitude matrix is ​​constructed based on the steady-state temperature amplitude at each sensor location. The temperature rise rate matrix and the steady-state temperature amplitude matrix are normalized respectively; Set a weighting coefficient for the temperature rise rate and a weighting coefficient for the steady-state temperature amplitude, wherein the weighting coefficient for the temperature rise rate is greater than the weighting coefficient for the steady-state temperature amplitude. Based on the weighting coefficients of the temperature rise rate and the steady-state temperature amplitude, the normalized temperature rise rate matrix and the normalized steady-state temperature amplitude matrix are weighted and fused to obtain the fused weight matrix.

[0011] In some embodiments of this application, the step of calculating the centroid coordinates of the heat distribution of the chip based on the fusion weight matrix using a weighted centroid algorithm includes: Extract the response timestamp matrix of each sensor in the sensor array when it reaches a preset temperature rise ratio; The spatiotemporal joint analysis of the fusion weight matrix is ​​performed using the timestamp matrix to generate a spatiotemporal joint weight matrix; Substituting the spatiotemporal joint weight matrix into the weighted centroid algorithm, the centroid coordinates of the heat distribution are calculated.

[0012] In some embodiments of this application, after performing spatiotemporal joint analysis on the fusion weight matrix using the timestamp matrix to generate the spatiotemporal joint weight matrix, the method further includes: Identify edge region sensors in the spatiotemporal joint weight matrix that correspond to the chip edge region; Calculate the geometric distance between the edge region sensor and the physical edge of the chip, and obtain the edge heat dissipation compensation correction factor that is a function of the geometric distance; Multiply the fusion weights of the edge region sensors by the edge heat dissipation compensation correction factor to obtain the corrected spatiotemporal joint weight matrix; Substituting the modified spatiotemporal joint weight matrix into the weighted centroid algorithm, the modified centroid coordinates of the heat distribution are calculated.

[0013] In some embodiments of this application, the step of calculating the centroid coordinates of the heat distribution of the chip based on the fusion weight matrix using a weighted centroid algorithm includes: Determine the maximum weight value in the fusion weight matrix, and use a predetermined proportion of the maximum weight value as a segmentation threshold to perform threshold segmentation on the fusion weight matrix, and extract high-temperature regions with weights greater than the segmentation threshold. A connected component labeling algorithm is used to identify independent high-temperature clusters within the high-temperature region; If a single independent high-temperature cluster is identified, the centroid coordinates of the single independent high-temperature cluster are determined as the centroid coordinates of the heat distribution. If two or more independent high-temperature clusters are identified, the centroid coordinates of each high-temperature cluster and the weighted sum of each high-temperature cluster are calculated respectively. Based on the weighted sum of each high-temperature cluster, the centroid coordinates of each high-temperature cluster are weighted and averaged to obtain the comprehensive centroid coordinates. The comprehensive centroid coordinates are determined as the centroid coordinates of the heat distribution.

[0014] In some embodiments of this application, driving the multidimensional displacement stage used to support the multi-stage flow channel heat dissipation structure to move according to the deviation between the coordinates of the heat distribution centroid and the coordinates of the cooling center includes: The coordinates of the heat distribution centroid and the coordinates of the cooling center are vector subtracted to generate a compensation vector containing the horizontal and vertical axis offsets. The compensation vector is converted into a drive control signal for the multidimensional displacement stage, which controls the test head of the multidimensional displacement stage to perform displacement compensation in the horizontal plane. After displacement compensation is completed, thermal pulse excitation is applied again for verification until the deviation between the coordinates of the heat distribution centroid and the coordinates of the cooling center is less than the preset tolerance.

[0015] In some embodiments of this application, the multi-stage flow channel heat dissipation structure further includes a gear pump and a constant temperature water bath. The dual-variable closed-loop regulation of fluid flow rate and temperature based on the chip's real-time thermal state specifically includes: Obtain the chip's steady-state temperature, chip input power, and coolant inlet temperature; The actual heat transfer coefficient is calculated based on the chip input power, the effective heating area, the steady-state temperature, and the coolant inlet temperature. The target heat transfer coefficient is calculated based on the chip input power, the effective heating area, the chip set temperature, and the coolant inlet temperature. The difference between the target heat transfer coefficient and the current actual heat transfer coefficient is used as the control error; The target speed of the gear pump and the target set temperature of the constant temperature water bath are calculated based on the control error. The gear pump speed is set to the target speed, and the set temperature of the constant temperature water bath is adjusted to the target set temperature to change the inlet temperature of the coolant. Repeat the above steps until the control error converges to a preset error threshold range.

[0016] The technical solutions provided by the embodiments of this application may include the following beneficial effects: This application achieves precise positioning of the heat source by actively applying pulsed thermal excitation and acquiring transient temperature response. It utilizes the dual feature fusion of temperature rise rate and steady-state temperature amplitude. Simultaneously, based on a chip size adaptive control multi-stage flow channel opening strategy, the heat dissipation coverage is precisely matched with the actual chip size, avoiding the waste of cooling resources for small chips and insufficient heat dissipation at the edges of large chips caused by fixed flow channel structures. Furthermore, the heat source positioning results are organically combined with multi-dimensional displacement stage alignment compensation and bivariate closed-loop regulation to form a complete control system from precise heat source perception to directional delivery of cooling resources and dynamic adaptation of heat dissipation capacity. This significantly improves the positioning accuracy, coolant utilization efficiency, and temperature control stability of high-power chip heat dissipation testing. Attached Figure Description

[0017] Figure 1 A flowchart of the chip heating center localization method based on pulsed thermal excitation provided in this application; Figure 2 A schematic diagram of the chip heating center positioning device based on pulse thermal excitation provided in this application; Figure 3 This is a schematic diagram of the structure of an electronic device provided in this application. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0021] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0022] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linked," and "socketing" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0023] Reference Figure 1This paper illustrates a chip heating center localization method based on pulsed thermal excitation provided in an embodiment of this application. The method specifically includes: Step 101: Obtain the physical geometry parameters of the chip, which include at least the effective heat-generating area.

[0024] Among them, the physical geometric parameters of the chip refer to the set of parameters that characterize the physical size of the chip, including at least the effective heat-generating area of ​​the chip. The effective heat-generating area is the area of ​​the upper surface region of the chip that actually participates in heat transfer. This area directly affects the configuration decision of the subsequent flow channel coverage and the calculation basis of the heat transfer coefficient.

[0025] In some embodiments of the present invention, step 101, "obtaining the physical geometric parameters of the chip," may specifically include the following sub-steps: During the process of the motor-driven clamp slider retracting towards the center, the change in motor current is monitored in real time. The clamp slider is used to contact the chip edge to sense the chip boundary. When the motor current exceeds the preset load threshold, it is determined that the slider has contacted the edge of the chip and stops retracting; The chip side length is calculated based on the shrinkage displacement of the slider and the mechanical transmission ratio, and the effective heating area of ​​the chip is deduced based on the chip side length.

[0026] The clamp slider is a mechanical actuator driven by a motor, reciprocating along a guide rail towards the center of the chip. Its inner surface directly faces the chip edge, achieving chip boundary sensing and positioning through physical contact. The preset load threshold is a pre-set current critical value. When the motor current reaches this value, it indicates that the contact force between the slider and the chip edge has reached the strength standard for determining contact. The mechanical transmission ratio is the proportional relationship between the rotational motion of the drive motor and the linear displacement of the slider in the slider linkage mechanism. It is used to convert the rotation recorded by the encoder into the linear movement distance of the slider. The encoder is a displacement detection element integrated on the drive motor or slider linkage mechanism, used to convert the actual movement distance of the slider into a recordable numerical signal.

[0027] In the specific implementation of this invention, the motor drives the clamp slider to retract toward the center of the chip, and the current change of the motor is monitored in real time during the retraction process; when the motor current exceeds the preset load threshold, it is determined that the slider has contacted the edge of the chip and the retraction is stopped immediately; the chip side length is calculated based on the retraction displacement of the slider from the reference position to the stop position and the mechanical transmission ratio of the slider linkage mechanism, and the effective heating area is calculated based on the geometry of the chip.

[0028] Taking a square chip with a side length of 15mm as an example, the slider is driven by an aperture mechanism to retract towards the center until it contacts the edge of the chip. The amount of retraction displacement is recorded, and combined with the mechanical transmission ratio, the side length of the chip is calculated to be 15mm. Therefore, the effective heating area is calculated to be 225mm².2 The area value is compared with a preset area threshold to determine whether to open the central flow channel or open both the central flow channel and the outer flow channel at the same time.

[0029] By acquiring the chip's physical geometry parameters, especially the effective heat-generating area, the configuration of the subsequent flow channel coverage no longer relies on manual input or fixed settings, but is automatically decided based on the chip's actual size, providing a quantitative basis for the precise matching of heat dissipation resources and chip size.

[0030] Step 102: Based on the effective heat dissipation area, control the opening or closing of the flow channel valves in the multi-stage flow channel heat dissipation structure so that the heat dissipation coverage of the multi-stage flow channel heat dissipation structure matches the chip. The multi-stage flow channel heat dissipation structure is used to dissipate heat from the chip.

[0031] Among them, the multi-stage flow channel heat dissipation structure is a heat dissipation device that includes multiple independent fluid channel layers. Each channel layer corresponds to a different heat dissipation coverage area. The heat dissipation coverage range can be adjusted by selectively opening the corresponding channel layer. The flow channel valve is an on / off control element set at the inlet of each flow channel. By opening or closing, it changes the flow path of the coolant, thereby determining which flow channels participate in heat dissipation.

[0032] In the specific implementation of this invention, based on the obtained effective heat-generating area, the opening or closing of each flow channel valve in the multi-stage flow channel heat dissipation structure is controlled. By selecting different flow channel combinations, the effective heat dissipation coverage of the multi-stage flow channel heat dissipation structure is adjusted so that the coverage matches the actual size of the chip. The multi-stage flow channel heat dissipation structure is used to dissipate heat from the chip.

[0033] In some embodiments of this application, the multi-stage flow channel heat dissipation structure includes a central flow channel and peripheral flow channels that are independent of each other. The inlet of the central flow channel and the peripheral flow channel are respectively provided with valves. Step 102 may specifically include the following sub-steps: The effective heating area is compared with a preset area threshold. If the effective heating area is less than the area threshold, the valve corresponding to the central channel of the multi-stage flow channel heat dissipation structure will be opened. If the effective heating area is greater than or equal to the area threshold, the valves of the central region and the outer flow channel are opened to form a parallel flow channel structure that matches the chip size.

[0034] Among them, the area threshold is a preset area critical value used to distinguish between small-sized chips and large-sized chips. This value corresponds to the maximum heat dissipation area that the central channel in the multi-level channel heat dissipation structure can cover. The peripheral channel is a ring channel surrounding the central channel, used to expand the heat dissipation coverage to match large-sized chips.

[0035] In the specific implementation of this invention, the effective heat-generating area is first compared with a preset area threshold. If the effective heat-generating area is less than the area threshold, only the valve corresponding to the central channel in the multi-stage flow channel heat dissipation structure is opened. If the effective heat-generating area is greater than or equal to the area threshold, the valves of the central channel and the peripheral channel are opened simultaneously, so that the central channel and the peripheral channel form a parallel flow channel structure, thereby achieving a heat dissipation coverage range that matches the chip size.

[0036] In one embodiment of the present invention, the multi-stage heat dissipation structure is specifically a multi-stage manifold microchannel, which is designed in a nested pattern around a central perimeter. The central channel covers the central area of ​​the chip, corresponding to the heat dissipation requirements of the smallest chip, such as a 10mm × 10mm chip; the peripheral channels surround the outer perimeter of the central channel in a ring shape to expand the heat dissipation coverage to accommodate larger chips. Valves are provided at the inlets of the central and peripheral channels, and each valve is independently controlled. By selectively opening or closing different channels, dynamic matching between the heat dissipation coverage and the actual size of the chip is achieved. In terms of vertical structure, the multi-stage flow channel heat dissipation structure consists of four functional flat plates stacked from bottom to top. The first layer is a microchannel liquid injection layer, which has a dense array of micro-spray holes. The spray holes directly face the microchannel heat sink above the chip, and the coolant is sprayed onto the surface of the heat sink through the spray holes to achieve convective heat transfer. The second layer is a static pressure buffer layer, which contains multiple independent annular chambers, namely a central core chamber and an edge expansion chamber. The central core chamber corresponds to the coverage area of ​​the central flow channel, and the edge expansion chamber corresponds to the coverage area of ​​the outer flow channel. The static pressure buffer layer is used to eliminate the jet impact of the upper fluid and convert the dynamic pressure of the fluid into uniform static pressure to ensure that the flow rate is consistent at all points at the spray hole outlet. The third layer is a logic switch layer, which is embedded with micro-solenoid valves or proportional regulating valves. Each valve is set between the main inlet and each zone buffer chamber. The logic switch layer receives valve control signals from the controller. When the effective heat-generating area is less than 100 mm, the valves are activated. When the area threshold is reached, only the valve leading to the central core cavity is opened, allowing the coolant to flow only through the central channel. When the effective heat-generating area is greater than or equal to the area threshold, the valves leading to the central core cavity and the edge expansion cavity are opened simultaneously, allowing the coolant to flow through both the central and peripheral channels, forming a parallel channel structure. The fourth layer is the main distribution layer, which has two layers of micro channels. The top channel is arranged as an inlet channel network, and the bottom channel is arranged as a return channel network. The inlet and return channel networks are H-shaped. The end of the inlet channel delivers the coolant downward to the logic switch layer through vertically penetrating injection holes. The logic switch layer collects the heat flow after heat exchange and delivers the heat flow to the return channel network through another set of vertically penetrating return holes, finally converging at the main outlet for discharge. Each end node of the H-shaped inlet channel network is directly opposite the valve inlet of the logic switch layer below, ensuring that each valve has an independent supply path.

[0037] Taking the aforementioned square chip with a side length of 15mm and an effective heat-generating area of ​​225mm² as an example, if the determination result is greater than the area threshold, then the central flow channel valve and the peripheral flow channel valve are opened simultaneously. The coolant is sprayed into the central area and the edge area of ​​the chip after being connected in parallel through the central flow channel and the peripheral flow channel, forming a full-coverage heat dissipation that matches the 225mm² area.

[0038] This invention achieves automatic decision-making on the flow channel coverage range through area threshold comparison. Small chips only activate the central flow channel to avoid coolant waste, while large chips activate all flow channels to ensure sufficient heat dissipation in the edge areas. This makes the coolant flow distribution accurately match the actual size of the chip, improving the adaptability and energy utilization efficiency of the heat dissipation system.

[0039] Step 103: Apply thermal pulse excitation to the chip, and perform high-frequency continuous temperature sampling of the chip through a sensor array during the thermal pulse excitation to obtain temperature time evolution information.

[0040] Among them, thermal pulse excitation refers to applying a short-duration, controllable power electrothermal energy impact to the chip to generate a transient thermal diffusion process inside the chip; the sensor array is a temperature measurement point array composed of multiple temperature sensors arranged in rows and columns, each sensor having known spatial coordinates, used to synchronously collect the temperature at different locations on the chip surface; high-frequency continuous temperature sampling refers to repeatedly reading the sensor array at millisecond intervals to acquire temperature data at multiple consecutive time points during pulse loading; temperature time evolution information refers to the data set of temperature changes over time at each sensor location.

[0041] In some embodiments of this application, step 103, "performing thermal pulse excitation on the chip," may specifically include the following sub-steps: A low-power probe pulse is applied in advance to obtain the thermal time constant of the chip; The target pulse width is determined based on the thermal time constant and a preset multiple range; The first power limit is calculated based on the chip's rated power, and the second power limit is calculated based on the safe temperature rise threshold. The smaller of the first power limit and the second power limit is taken as the target applied power. The chip is thermally excited based on the target pulse width and the target applied power.

[0042] The thermal time constant is a time quantity characterizing the thermal inertia of the chip, equal to the time it takes for the temperature change to reach a predetermined proportion of the total temperature change as the chip rises from a reference temperature to its steady-state temperature. The preset multiplier range is a pre-defined range of pulse widths relative to the thermal time constant, ensuring that the pulse width elicits a sufficient temperature response without causing the chip to enter complete thermal equilibrium. The safe temperature rise threshold is the maximum allowable temperature rise on the chip surface, preventing thermal shock damage from a single pulse.

[0043] In the specific implementation of this application, before applying the formal thermal pulse to the chip, a low-power probe pulse is applied first. The thermal time constant of the chip is obtained by analyzing the response of the probe pulse. Based on the matching relationship between the thermal time constant and the preset multiple range, the target pulse width of the formal test pulse is determined so that the target pulse width is within the preset multiple range of the thermal time constant. Then, a first power upper limit is calculated based on the rated power of the chip, and a second power upper limit is calculated based on the safe temperature rise threshold. The smaller value between the first power upper limit and the second power upper limit is selected as the target applied power. Finally, based on the determined target pulse width and target applied power, the formal thermal pulse excitation is applied to the chip.

[0044] Taking a 100W rated power chip as an example, a 10ms long, 5W probe pulse is first applied. The temperature at the chip's center is measured to rise from a reference temperature of 25℃ to a steady-state temperature of 42℃, with a total temperature rise of 17℃. Assuming that 63.2% of the total temperature rise is taken as the predetermined proportion of the temperature change, the corresponding temperature rise is approximately 10.7℃. The time required for the temperature to rise from 25℃ to 35.7℃ is recorded as 45ms, and the thermal time constant of the chip is determined to be 45ms. 20% of the rated power of 100W yields the first power limit of 20W. Assuming a safe temperature rise threshold of 15℃, the safe temperature rise threshold of 15℃ is divided by the package thermal resistance of 0.8℃ / W to obtain the second power limit of 18.75W. The smaller value of the two, 18.75W, is taken as the target applied power. Finally, a formal thermal pulse excitation is applied to the chip with a pulse width of 45ms and a power of 18.75W.

[0045] This application obtains the thermal inertia characteristics of the chip in advance by probing pulses, so that the width of the formal test pulse can be adaptively adjusted according to the chip with different package types and power levels. This avoids insufficient temperature rise due to excessively short pulses and excessive heat diffusion due to excessively long pulses, which would obscure the location of the heat source. The dual power upper limit constraint ensures that the pulse power is within a safe range, taking into account both the sufficiency of temperature response and the safety of chip operation.

[0046] Step 104: Based on the temperature time evolution information, construct the temperature rise rate matrix and the steady-state temperature amplitude matrix, and fuse the temperature rise rate matrix and the steady-state temperature amplitude matrix to obtain the fusion weight matrix.

[0047] The temperature rise rate is the rate at which the temperature at each sensor location rises over time during the thermal pulse loading period, equal to the temperature change per unit time. The steady-state temperature amplitude is the change in the stable temperature reached at each sensor location after the thermal pulse loading ends, relative to the reference temperature before the pulse application. The fusion weight matrix is ​​a comprehensive weight matrix obtained by combining the temperature rise rate matrix and the steady-state temperature amplitude matrix according to their respective weight coefficients. Each element reflects the comprehensive contribution of the corresponding sensor location to the localization of the heat center.

[0048] In some embodiments of the present invention, step 104 may specifically include the following sub-steps: Extract the temperature rise rate and steady-state temperature amplitude at each sensor location in the sensor array from the temperature time evolution information; A temperature rise rate matrix is ​​constructed based on the temperature rise rate at each sensor location, and a steady-state temperature amplitude matrix is ​​constructed based on the steady-state temperature amplitude at each sensor location. The temperature rise rate matrix and the steady-state temperature amplitude matrix are normalized respectively. Set a weighting coefficient for the temperature rise rate and a weighting coefficient for the steady-state temperature amplitude, wherein the weighting coefficient for the temperature rise rate is greater than the weighting coefficient for the steady-state temperature amplitude; Based on the weighting coefficients of the temperature rise rate and the steady-state temperature amplitude, the normalized temperature rise rate matrix and the normalized steady-state temperature amplitude matrix are weighted and fused to obtain the fused weight matrix.

[0049] The normalization process is a calculation that scales the values ​​of each element in the matrix to a preset range to eliminate the numerical differences between the temperature rise rate and the steady-state temperature amplitude caused by the different dimensions. The temperature rise rate weighting coefficient is the weighting ratio assigned to the temperature rise rate matrix, and the steady-state temperature amplitude weighting coefficient is the weighting ratio assigned to the steady-state temperature amplitude matrix.

[0050] In the specific implementation of this application, the temperature rise rate value and steady-state temperature amplitude of each sensor position in the sensor array are extracted from the temperature time evolution information. According to the row and column positions of each sensor in the array, all temperature rise rate values ​​are organized into a temperature rise rate matrix, and all steady-state temperature amplitudes are organized into a steady-state temperature amplitude matrix. The temperature rise rate matrix and the steady-state temperature amplitude matrix are normalized respectively. A weighting coefficient for the temperature rise rate and a weighting coefficient for the steady-state temperature amplitude are set, with the temperature rise rate weighting coefficient being greater than the steady-state temperature amplitude weighting coefficient. The normalized temperature rise rate matrix is ​​multiplied by the temperature rise rate weighting coefficient, and the normalized steady-state temperature amplitude matrix is ​​multiplied by the steady-state temperature amplitude weighting coefficient. The two product matrices are then added to obtain the fusion weight matrix. In one embodiment of this application, the temperature rise rate weighting coefficient is greater than the steady-state temperature amplitude weighting coefficient to strengthen the dominant role of the temperature rise rate in the fusion process.

[0051] Taking the aforementioned 16×16 sensor array as an example, the temperature rise rate and steady-state temperature amplitude at each sensor location are extracted, and 16×16 temperature rise rate matrices and steady-state temperature amplitude matrices are constructed respectively. The maximum value in the temperature rise rate matrix is ​​8℃ / 10ms, and the minimum value is 0.5℃ / 10ms. The maximum value in the steady-state temperature amplitude matrix is ​​15℃, and the minimum value is 2℃. The minimum-maximum normalization method is used to map the element values ​​of the two matrices to the interval between 0 and 1 respectively. The weighting coefficient of the temperature rise rate is set to 0.6, and the weighting coefficient of the steady-state temperature amplitude is set to 0.4. Each element of the normalized temperature rise rate matrix is ​​multiplied by 0.6, and each element of the normalized steady-state temperature amplitude matrix is ​​multiplied by 0.4. The corresponding positions of the two matrices are added to obtain a 16×16 fusion weight matrix.

[0052] This application eliminates the numerical difference between the temperature rise rate and the steady-state temperature amplitude due to their different dimensions through normalization processing, so that the two features are at the same numerical level before fusion. By setting the weighting coefficient of the temperature rise rate to be greater than that of the steady-state temperature amplitude, the temperature rise rate, which is less affected by the lateral diffusion of heat and has high positioning accuracy, takes the lead in the fusion process. At the same time, the steady-state temperature amplitude participates in the positioning as auxiliary information. The two features complement each other and enhance the accuracy and anti-interference ability of the heating center positioning.

[0053] Step 105: Calculate the centroid coordinates of the chip's heat distribution based on the fusion weight matrix using the weighted centroid algorithm.

[0054] The weighted centroid algorithm treats each element in the fusion weight matrix as the thermal mass at that location. It calculates the average position of the heat distribution center point by weighting all sensor position coordinates with their corresponding fusion weight values. The heat distribution centroid coordinates represent the concentrated location of the chip's heat generation energy.

[0055] In the specific implementation of this invention, the fusion weight value at each sensor position in the fusion weight matrix is ​​used as the thermal mass weight of that point. The horizontal and vertical coordinates of all sensor positions in the sensor array are weighted and averaged respectively. The calculated weighted average position coordinates are the centroid coordinates of the heat distribution of the chip.

[0056] Taking the aforementioned 16×16 sensor array and fusion weight matrix as an example, each sensor position corresponds to a known physical coordinate. Let the coordinates of the central region sensor be (0, 0), and the coordinates of the edge sensors be (-7.5, 0), (7.5, 0), (0, -7.5), and (0, 7.5), respectively, in mm. Multiply the horizontal coordinate value of each sensor by its fusion weight, sum the results, and then divide by the sum of all fusion weights to obtain the horizontal coordinate of the centroid. Multiply the vertical coordinate value of each sensor by its fusion weight, sum the results, and then divide by the sum of all fusion weights to obtain the vertical coordinate of the centroid. If the calculated centroid coordinates are (0.8, -1.2) mm, it indicates that the heat dissipation center of the chip is located slightly to the right and below the chip's geometric center.

[0057] In some embodiments of this application, step 105 may specifically include the following sub-steps: Extract the response timestamp matrix of each sensor in the sensor array when it reaches the preset temperature rise ratio; The spatiotemporal joint analysis of the fusion weight matrix is ​​performed using the timestamp matrix to generate the spatiotemporal joint weight matrix. Substituting the spatiotemporal joint weight matrix into the weighted centroid algorithm, the centroid coordinates of the heat distribution are calculated.

[0058] Among them, the preset temperature rise ratio is a pre-set critical value for the percentage temperature rise, used to determine the time point required for each sensor to rise to the specified ratio from the start of pulse excitation; the response timestamp refers to the length of time from the start of thermal pulse excitation to the moment when the sensor temperature first reaches the preset temperature rise ratio, reflecting the time taken for the thermal diffusion wavefront to propagate from the heat source to the sensor location; spatiotemporal joint analysis is a process of jointly analyzing the time dimension information represented by the response timestamp matrix and the spatial dimension information represented by the fusion weight matrix, used to generate a joint weight matrix containing spatiotemporal features.

[0059] In the specific implementation process of this application, the time required for each sensor in the sensor array to rise to a preset temperature rise ratio from the start of thermal pulse excitation is first extracted; then, the time length is organized into a response timestamp matrix according to the position of each sensor in the array; then, the response timestamp matrix is ​​used to perform spatiotemporal joint analysis on the fusion weight matrix, and the time dimension information and spatial dimension information are fused to generate a spatiotemporal joint weight matrix; each element value in the spatiotemporal joint weight matrix is ​​used as the thermal mass weight of that position and substituted into the weighted centroid algorithm to calculate the coordinates of the heat distribution centroid.

[0060] Taking the aforementioned 16×16 sensor array and a preset temperature rise ratio of 50% of the peak temperature rise as an example, the time length from the start of the pulse to the temperature reaching 50% of its peak temperature rise for each sensor is extracted. It is assumed that the sensors in the central area of ​​the chip reach 50% of the peak temperature rise in about 20ms after the start of the pulse, while the sensors in the edge areas take about 100ms to 150ms to reach the same ratio. These time lengths are organized into a 16×16 response timestamp matrix according to the sensor array positions. Then, this matrix is ​​used to perform spatiotemporal joint analysis on the fusion weight matrix. For sensor positions with smaller response timestamps, it indicates that the position is closer to the heat source, and a higher weight is assigned in the spatiotemporal joint weight matrix. For positions with larger response timestamps, it indicates that the position is farther from the heat source, and the weight is reduced accordingly. The spatiotemporal joint weight matrix is ​​substituted into the weighted centroid algorithm to calculate the centroid coordinates of the heat distribution.

[0061] This application utilizes the physical characteristics of heat diffusion wavefront propagation and uses the response timestamp as the criterion for the distance to the heat source. The earlier the sensor responds, the closer it is to the heat source, and the later the sensor responds, the farther it is from the heat source. It introduces time dimension information independent of temperature amplitude into the centroid calculation and forms a spatiotemporal joint positioning with the fusion weight matrix, which further improves the accuracy of the heat center positioning and the anti-interference ability against the lateral diffusion of heat.

[0062] In some embodiments of this application, after the sub-step "using the timestamp matrix to perform spatiotemporal joint analysis on the fusion weight matrix to generate the spatiotemporal joint weight matrix", the following sub-step is also included: Identify edge region sensors corresponding to the chip edge region in the spatiotemporal joint weight matrix; Calculate the geometric distance between the sensor in the edge region and the physical edge of the chip, and obtain the edge heat dissipation compensation correction factor that is a function of the geometric distance; Multiply the fusion weights of the edge region sensors by the edge heat dissipation compensation correction factor to obtain the corrected spatiotemporal joint weight matrix; Substituting the modified spatiotemporal joint weight matrix into the weighted centroid algorithm, the modified centroid coordinates of the heat distribution are calculated.

[0063] Among them, the edge region sensor is a sensor located in the sensor array close to the physical edge of the chip, and its geometric distance from the chip edge is less than a preset distance value; the edge heat dissipation compensation correction factor is a pre-established correction coefficient that is functionally related to the distance from the sensor to the chip edge, used to compensate for the temperature measurement deviation caused by heat loss from the edge region to the outside air of the chip; the corrected spatiotemporal joint weight matrix is ​​a corrected weight matrix obtained by multiplying the weight value of the edge region sensor by the compensation correction factor on the basis of the original spatiotemporal joint weight matrix.

[0064] Taking a 16×16 sensor array covering a 15mm×15mm chip area as an example, with each sensor spaced 1mm apart, the sensors at the chip edge are those less than 2mm from the chip edge, i.e., the outermost two rings of sensors. If an edge sensor in a corner area detects a distance of 1mm from the chip edge, the corresponding edge heat dissipation compensation correction factor is 1.35. The original fusion weight value of this sensor in the spatiotemporal joint weight matrix would then be corrected to 0.6×1.35=0.81. If the sensor is 2mm from the edge, the corresponding correction factor is 1.15, and the correction value would be 0.6×1.15=0.69. After correcting the fusion weights of all edge sensors in the above manner, the corrected spatiotemporal joint weight matrix is ​​obtained. This matrix is ​​then re-substituted into the weighted centroid algorithm to calculate the corrected centroid coordinates of the heat distribution.

[0065] This application compensates for the weight of edge region sensors by using an edge heat dissipation compensation correction factor. This effectively solves the problem that the temperature measurement value of edge sensors is too low due to heat loss to the outside air at the chip edge, and the contribution of edge sensors in the centroid calculation is incorrectly underestimated. This allows heat sources near the edge to be accurately located, avoids centroid calculation deviation caused by edge effects, and further improves the accuracy of locating the heat center in the entire chip area.

[0066] In some embodiments of the present invention, step 105 may further include the following sub-steps: Determine the maximum weight value in the fusion weight matrix, and use a predetermined proportion of the maximum weight value as the segmentation threshold to perform threshold segmentation on the fusion weight matrix, extracting high-temperature regions with weights greater than the segmentation threshold. A connected component labeling algorithm is used to identify independent high-temperature clusters in high-temperature regions; If a single independent high-temperature cluster is identified, the centroid coordinates of the single independent high-temperature cluster are determined as the centroid coordinates of the heat distribution. If two or more independent high-temperature clusters are identified, calculate the centroid coordinates of each high-temperature cluster and the total weight of each high-temperature cluster. Based on the total weight of each high-temperature cluster, perform a weighted average on the centroid coordinates of each high-temperature cluster to obtain the comprehensive centroid coordinates. The comprehensive centroid coordinates are then determined as the centroid coordinates of the heat distribution.

[0067] The segmentation threshold is a critical point obtained by multiplying the maximum weight value in the fusion weight matrix by a predetermined ratio, used to distinguish the boundary between high-temperature and non-high-temperature regions. Threshold segmentation is a binarization method that compares the values ​​of each element in the fusion weight matrix with the segmentation threshold, retaining the element regions with values ​​greater than the threshold and discarding the element regions with values ​​less than the threshold. The connected component labeling algorithm is an image processing algorithm used to identify interconnected regions in the binarized image. By traversing each element and marking interconnected adjacent elements, different connected regions are divided into independent clusters. Independent high-temperature clusters refer to the regions where high-temperature elements that are not interconnected in the fusion weight matrix are clustered. Each independent high-temperature cluster corresponds to an independent heat source unit on the chip. The total weight of a high-temperature cluster is the sum of the fusion weight values ​​of all elements within that high-temperature cluster, reflecting the relative heating intensity of that heat source unit.

[0068] In the specific implementation of this application, the maximum weight value in the fusion weight matrix is ​​determined, and the value obtained by multiplying the maximum weight value by a predetermined ratio is used as the segmentation threshold. The elements in the fusion weight matrix are segmented by the threshold to extract the high-temperature region composed of all elements with a weight greater than the segmentation threshold. The extracted high-temperature region is subjected to connectivity analysis using a connected component labeling algorithm to identify independent high-temperature clusters that are not connected to each other. If only a single independent high-temperature cluster is identified, the centroid coordinates of the high-temperature cluster are directly calculated and determined as the centroid coordinates of the heat distribution of the chip. If two or more independent high-temperature clusters are identified, the centroid coordinates of each high-temperature cluster and the sum of the weights of each high-temperature cluster are calculated separately. The centroid coordinates of each high-temperature cluster are weighted and averaged using the sum of the weights of each high-temperature cluster as the weight. The comprehensive centroid coordinates obtained by the weighted average are determined as the centroid coordinates of the heat distribution of the chip.

[0069] Taking the aforementioned 16×16 fusion weight matrix as an example, the maximum weight value in the matrix is ​​0.95, the predetermined ratio is 70%, and the segmentation threshold is 0.665. All elements in the matrix with a weight greater than 0.665 are extracted as high-temperature regions. After identification by the connected component labeling algorithm, two independent high-temperature clusters that are not connected to each other are found. Cluster A is located in the upper left region of the chip, containing 36 sensor positions, with a total weight of 18.5 and centroid coordinates of (-3.2mm, 2.8mm); Cluster B is located in the lower right region of the chip, containing 25 sensor positions, with a total weight of 12.8 and centroid coordinates of (4.5mm, -3.1mm). Since there are two independent high-temperature clusters, a weighted average is calculated based on the sum of their respective weights: the abscissa of the comprehensive centroid = (-3.2×18.5+4.5×12.8) / (18.5+12.8) = (-59.2+57.6) / 31.3 = -0.05mm, and the ordinate of the comprehensive centroid = (2.8×18.5-3.1×12.8) / 31.3 = (51.8-39.7) / 31.3 = 0.39mm. The coordinates of (-0.05mm, 0.39mm) are determined as the centroid coordinates of the heat distribution of the chip.

[0070] This application achieves effective identification and processing of multi-heat source scenarios through threshold segmentation and connected component labeling. When there are multiple independent heating units inside the chip, it can identify each heat source separately and perform weighted summation based on its heating intensity, so that the final determined centroid coordinates can scientifically reflect the overall heat distribution center under the combined action of multiple heat sources, avoiding the problem of inaccurate positioning in multi-heat source scenarios by single centroid algorithms; when there is only a single heat source, it directly outputs the centroid coordinates of the heat source, which is efficient and concise in calculation.

[0071] Step 106: Obtain the coordinates of the cooling center of the multi-stage heat dissipation structure. Based on the deviation between the coordinates of the heat distribution centroid and the coordinates of the cooling center, drive the multi-dimensional displacement stage used to support the multi-stage heat dissipation structure to move, so that the cooling center of the multi-stage heat dissipation structure coincides with the heat distribution centroid of the chip in space.

[0072] The cooling center coordinates represent the location of the area with the strongest cooling capacity in the multi-stage flow channel heat dissipation structure within a spatial coordinate system. This location corresponds to the geometric center or flow weighting center of the flow channel spray hole array. The multi-dimensional displacement stage is a two-dimensional moving platform capable of generating precise displacements along the horizontal and vertical axes in a horizontal plane. It is used to support the multi-stage flow channel heat dissipation structure and change its position in space.

[0073] In some embodiments of this application, step 106, "driving the multi-dimensional displacement stage used to support the multi-stage flow channel heat dissipation structure to move according to the deviation between the coordinates of the heat distribution centroid and the coordinates of the cooling center," may specifically include the following sub-steps: The coordinates of the heat distribution centroid and the coordinates of the cooling center are vector subtracted to generate a compensation vector containing the horizontal and vertical axis offsets. The compensation vector is converted into a drive control signal for the multidimensional displacement stage, which controls the test head of the multidimensional displacement stage to perform displacement compensation in the horizontal plane. After displacement compensation is completed, thermal pulse excitation is applied again for verification until the deviation between the coordinates of the heat distribution centroid and the coordinates of the cooling center is less than the preset tolerance.

[0074] Among them, the compensation vector is the vector difference obtained by subtracting the coordinates of the cooling center from the coordinates of the centroid of the heat distribution, which is used to characterize the direction and distance that the cooling center needs to move; the drive control signal is a motion command that the compensation vector is converted into a motion command that can be recognized by the multi-dimensional displacement stage drive mechanism, which is used to control the amount of movement of the displacement stage in the horizontal and vertical directions in the horizontal plane; the preset tolerance is a pre-set allowable position deviation critical value, which is used to determine whether the alignment accuracy meets the requirements.

[0075] In the specific implementation of this application, the coordinates of the cooling center of the multi-stage heat dissipation structure are obtained. The coordinates of the heat distribution centroid are compared with the coordinates of the cooling center to obtain the offset components in the horizontal and vertical directions. Based on the offset, the multi-dimensional displacement stage used to support the multi-stage heat dissipation structure is driven to move in the horizontal plane so that the cooling center of the multi-stage heat dissipation structure coincides with the heat distribution centroid of the chip in space. After the displacement compensation is completed, a thermal pulse excitation is applied again for verification. The deviation between the verified heat distribution centroid coordinates and the cooling center coordinates is calculated. If the deviation is still greater than or equal to the preset tolerance, the above steps are repeated until the deviation is less than the preset tolerance.

[0076] Taking the calculated centroid coordinates of the heat distribution as (0.8mm, -1.2mm) as an example, and the cooling center coordinates of the multi-stage flow channel heat dissipation structure as (0, 0), the deviation in the horizontal axis direction is 0.8mm, and the deviation in the vertical axis direction is -1.2mm. That is, the centroid of the heat distribution is located 0.8mm to the right and 1.2mm below the cooling center. This deviation is converted into the number of driving pulses of the multi-dimensional displacement stage in the horizontal and vertical axes. The displacement stage is controlled to move the multi-stage flow channel heat dissipation structure to the right by 0.8mm and downward by 1.2mm, so that the cooling center moves to (0.8mm, -1.2mm) and coincides with the centroid of the heat distribution in space. After the displacement is completed, thermal pulse excitation is applied again for verification. If the deviation between the coordinates of the heat distribution centroid and the coordinates of the cooling center obtained from the verification is less than the preset tolerance of 0.1mm, the alignment is completed; if the deviation is still greater than or equal to 0.1mm, the next compensation is performed until the tolerance requirement is met.

[0077] This application accurately calculates the positional deviation between the cooling center and the heating center by vector subtraction, and converts the deviation into a drive signal that can be executed by the displacement stage, thereby realizing precise spatial movement of the cooling center to the heating center. The alignment effect is verified by a verification mechanism and iteratively corrected when the deviation exceeds the tolerance, ensuring that the cooling center and the heating center achieve sufficient alignment accuracy.

[0078] Step 107: After alignment, based on the real-time thermal state of the chip, the flow rate and temperature of the fluid are adjusted in a two-variable closed-loop manner.

[0079] Real-time thermal status is a collection of thermally relevant parameters such as temperature and power of the chip under current operating conditions, used to characterize the chip's current heat generation intensity and heat dissipation requirements. Dual-variable closed-loop regulation is a feedback control method that uses fluid flow rate and fluid temperature as two independent adjustable variables. These two variables work together to improve heat dissipation capacity from the dimensions of coolant mass flow rate and inlet temperature, respectively, causing the chip temperature to approach the preset target value.

[0080] In the specific implementation of this application, after the cooling center of the multi-stage flow channel heat dissipation structure is spatially aligned with the heat distribution centroid of the chip, the current thermal state parameters such as the chip's temperature and power are acquired in real time. The preset target junction temperature is used as the control target, and the fluid flow rate and fluid inlet temperature are used as two adjustment variables for closed-loop feedback regulation to maintain the chip's steady-state temperature within the preset target range.

[0081] In some embodiments of this application, the multi-stage flow channel heat dissipation structure further includes a gear pump and a constant temperature water bath. Step 107, "based on the real-time thermal state of the chip, performs dual-variable closed-loop regulation of the fluid flow rate and temperature," specifically includes the following sub-steps: Obtain the chip's steady-state temperature, chip input power, and coolant inlet temperature; The actual heat transfer coefficient is calculated based on the chip input power, effective heating area, steady-state temperature, and coolant inlet temperature. The target heat transfer coefficient is calculated based on the chip input power, effective heating area, chip set temperature, and coolant inlet temperature. The difference between the target heat transfer coefficient and the current actual heat transfer coefficient is used as the control error; The target speed of the gear pump and the target set temperature of the constant temperature water bath are calculated based on the control error. The gear pump speed is set to the target speed, and the temperature of the constant temperature water bath is adjusted to the target set temperature to change the inlet temperature of the coolant. Repeat the above steps until the control error converges to the preset error threshold range.

[0082] The gear pump is a power component that drives the coolant to circulate within the multi-stage flow channel heat dissipation structure. Adjusting the gear pump's speed changes the coolant's mass flow rate. The constant-temperature water bath is a temperature-controlled device for the coolant; adjusting its set temperature changes the coolant's inlet temperature upon entering the multi-stage flow channel heat dissipation structure. The current actual heat transfer coefficient is a value representing the actual heat dissipation capacity calculated based on the chip's current steady-state temperature, input power, effective heat-generating area, and coolant inlet temperature. The target heat transfer coefficient is a value representing the target heat dissipation capacity calculated based on the chip's set temperature, input power, effective heat-generating area, and coolant inlet temperature. Control error refers to the difference between the current heat dissipation capacity and the target heat dissipation capacity. The preset error threshold is a pre-set allowable control error threshold used to determine whether the closed-loop regulation has reached convergence.

[0083] In the specific implementation process of this application, the steady-state temperature of the chip when it reaches dynamic equilibrium, the current input power of the chip, and the inlet temperature of the coolant are first obtained. Then, the current actual heat transfer coefficient is calculated based on the chip input power, effective heating area, steady-state temperature, and coolant inlet temperature. In addition, the target heat transfer coefficient is calculated based on the chip input power, effective heating area, chip set temperature, and coolant inlet temperature. The difference between the target heat transfer coefficient and the current actual heat transfer coefficient is used as the control error. The target speed of the gear pump and the target set temperature of the constant temperature water bath are calculated based on the control error. The speed of the gear pump is adjusted to the target speed to change the mass flow rate of the coolant, and the set temperature of the constant temperature water bath is adjusted to the target set temperature to change the inlet temperature of the coolant. The above acquisition, calculation, and adjustment steps are repeated until the absolute value of the control error is less than or equal to the preset error threshold.

[0084] Taking a chip set temperature of 75℃ as an example, assuming the chip is in dynamic equilibrium and the steady-state temperature is 78℃, the input power is 150W, the coolant inlet temperature is 25℃, and the effective heat-generating area is 225mm². 2 According to the formula Calculate the current actual heat transfer coefficient, where P is the input power, A is the effective heating area, and T is the chip steady-state temperature. in The current is the coolant inlet temperature, i.e., h_current = 150 ÷ ​​(225 × (78 - 25)) ≈ 0.0126 W / (mm). 2 ·℃). According to the formula Calculate the target heat transfer coefficient, where T set Set the temperature for the chip, that is Therefore, control error A positive Δh indicates that the current heat dissipation capacity is slightly insufficient. Using Δh as the error input term for the PID controller, the output gear pump speed correction ΔRPM is calculated. Where Kp, Ki, and Kd represent the proportional coefficient, integral coefficient, and derivative coefficient, respectively. Assuming the output gear pump speed correction is 150 rpm, increasing the gear pump speed from 1500 rpm to 1650 rpm increases the coolant mass flow rate. Simultaneously, based on the error output temperature correction value for the constant temperature water bath, the water bath setting temperature is decreased from 25℃ to 24.5℃, lowering the coolant inlet temperature. By repeating the above steps, as the chip's steady-state temperature gradually decreases to 75℃, the actual heat transfer coefficient gradually increases to approach the target heat transfer coefficient, and the control error gradually converges to the preset error threshold range.

[0085] This step uses the heat transfer coefficient, rather than temperature, as the control target. The difference between the target heat transfer coefficient and the current actual heat transfer coefficient directly quantifies the gap in heat dissipation capacity, making the adjustment process more physically clear. The gear pump speed and the constant-temperature water bath temperature are treated as two independent adjustment variables, working synergistically to affect heat dissipation capacity from two physical dimensions: coolant mass flow rate and inlet temperature difference. The clear division of labor between coarse and fine adjustments, compared to control methods that use only flow rate as a single adjustment variable, results in higher temperature control accuracy and a smoother adjustment process. The cyclic execution mechanism until error convergence ensures that the system can automatically recover to the target state under various disturbances, achieving dynamic adaptive adjustment of heat dissipation capacity.

[0086] In this application, by actively applying pulsed thermal excitation and acquiring transient temperature response, the precise location of the heat center is achieved through the fusion of dual features of temperature rise rate and steady-state temperature amplitude. At the same time, based on the chip size adaptive control multi-level flow channel opening strategy, the heat dissipation coverage is precisely matched with the actual chip size, avoiding the waste of cooling resources for small chips and insufficient heat dissipation at the edges of large chips caused by fixed flow channel structure. Furthermore, the heat center positioning result is organically combined with multi-dimensional displacement stage alignment compensation and bivariate closed-loop regulation to form a complete control from precise heat source perception to directional delivery of cooling resources to dynamic adaptation of heat dissipation capacity, which significantly improves the positioning accuracy, coolant utilization efficiency and temperature control stability of high-power chip heat dissipation testing.

[0087] This embodiment also provides a chip heat dissipation center positioning and heat dissipation control device based on pulse thermal excitation. This device is used to implement the above embodiments and preferred embodiments, and details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0088] This embodiment provides chip heat dissipation center location and heat dissipation control based on pulse thermal excitation, such as... Figure 2 As shown, it includes: The physical parameter acquisition module 201 is used to acquire the physical geometric parameters of the chip, wherein the physical geometric parameters include at least the effective heat-generating area; The first heat dissipation control module 202 is used to control the opening or closing of the flow channel valves in the multi-stage flow channel heat dissipation structure according to the effective heat dissipation area, so that the heat dissipation coverage of the multi-stage flow channel heat dissipation structure matches the chip, and the multi-stage flow channel heat dissipation structure is used to dissipate heat from the chip. The information sampling module 203 is used to apply thermal pulse excitation to the chip and to perform high-frequency continuous temperature sampling of the chip through a sensor array during the application of the thermal pulse excitation to obtain temperature time evolution information. The fusion module 204 is used to construct a temperature rise rate matrix and a steady-state temperature amplitude matrix based on the temperature time evolution information, and to fuse the temperature rise rate matrix and the steady-state temperature amplitude matrix to obtain a fusion weight matrix. The centroid calculation module 205 is used to calculate the centroid coordinates of the heat distribution of the chip based on the fusion weight matrix using a weighted centroid algorithm. The second heat dissipation control module 206 is used to obtain the cooling center coordinates of the multi-level flow channel heat dissipation structure, and drive the multi-dimensional displacement stage used to support the multi-level flow channel heat dissipation structure to move according to the deviation between the heat distribution centroid coordinates and the cooling center coordinates, so that the cooling center of the multi-level flow channel heat dissipation structure is aligned with the heat distribution centroid of the chip. The adjustment module 207 is used to perform bivariate closed-loop adjustment of the fluid flow rate and temperature based on the real-time thermal state of the chip after alignment.

[0089] The chip heat dissipation and heat dissipation control device based on pulse thermal excitation provided in this application can execute the chip heat dissipation and heat dissipation control method based on pulse thermal excitation provided in any embodiment of this application, and has the corresponding functional modules and beneficial effects of the method. Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0090] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0091] Obviously, those skilled in the art should understand that the various units or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device, or fabricating them separately as individual integrated circuit modules, or fabricating multiple modules or steps into a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0092] Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0093] The following is a detailed reference. Figure 3 The diagram illustrates a structural schematic suitable for implementing the electronic device described in the embodiments of this application. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 301, which can perform various appropriate actions and processes based on a program stored in a read-only memory (i.e., ROM 302) or a program loaded from memory 308 into random access memory (i.e., RAM 303). The RAM 303 also stores various programs and data required for the operation of the electronic device. The processor 301, ROM 302, and RAM 303 are interconnected via a bus 304. Input / output (i.e., I / O interface 305) is also connected to the bus 304.

[0094] Typically, the following devices can be connected to I / O interface 305: input devices 306 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 307 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 308 including, for example, magnetic tapes, hard disks, etc.; and communication devices 309. Communication device 309 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 3 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0095] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication device 309, or installed from memory 308, or installed from ROM 302. When the computer program is executed by processor 301, it performs the functions defined in the chip heat center positioning and heat dissipation control based on pulse thermal excitation of embodiments of this application.

[0096] Figure 3 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0097] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the chip heat center localization method based on pulse thermal excitation shown in the above embodiments is implemented.

[0098] A portion of this application can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to this application through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0099] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for locating the chip heating center based on pulsed thermal excitation, characterized in that, Includes the following steps: Obtain the physical geometric parameters of the chip, wherein the physical geometric parameters include at least the effective heat-generating area; Based on the effective heat-generating area, the opening or closing of the flow channel valves in the multi-stage flow channel heat dissipation structure is controlled so that the heat dissipation coverage of the multi-stage flow channel heat dissipation structure matches the chip. The multi-stage flow channel heat dissipation structure is used to dissipate heat from the chip. The chip is subjected to thermal pulse excitation, and during the loading of the thermal pulse excitation, the chip is sampled at high frequency and continuously using a sensor array to obtain temperature time evolution information. Based on the temperature-time evolution information, a temperature rise rate matrix and a steady-state temperature amplitude matrix are constructed, and the temperature rise rate matrix and the steady-state temperature amplitude matrix are fused to obtain a fusion weight matrix; The weighted centroid algorithm is used to calculate the centroid coordinates of the heat distribution of the chip based on the fusion weight matrix; The cooling center coordinates of the multi-stage heat dissipation structure are obtained. Based on the deviation between the heat distribution centroid coordinates and the cooling center coordinates, the multi-dimensional displacement stage used to support the multi-stage heat dissipation structure is driven to move so that the cooling center of the multi-stage heat dissipation structure is aligned with the heat distribution centroid of the chip. After alignment, the flow rate and temperature of the fluid are adjusted in a two-variable closed-loop manner based on the real-time thermal state of the chip.

2. The method according to claim 1, characterized in that, The acquisition of the chip's physical geometric parameters specifically includes: During the process of the motor-driven clamp slider retracting towards the center, the change in motor current is monitored in real time. The clamp slider is used to contact the chip edge to sense the chip boundary. When the motor current exceeds the preset load threshold, it is determined that the slider has contacted the edge of the chip and stops retracting; The chip side length is calculated based on the shrinkage displacement of the slider and the mechanical transmission ratio, and the effective heating area of ​​the chip is deduced based on the chip side length.

3. The method according to claim 2, characterized in that, The multi-stage heat dissipation structure includes independent central and peripheral heat dissipation channels. Valves are provided at the inlets of the central and peripheral heat dissipation channels. The opening and closing of these valves are controlled according to the effective heat-generating area to ensure that the heat dissipation coverage of the multi-stage heat dissipation structure matches the chip. Specifically, this includes: The effective heating area is compared with a preset area threshold. If the effective heating area is less than the area threshold, the valve corresponding to the central channel of the multi-stage flow channel heat dissipation structure will be opened. If the effective heating area is greater than or equal to the area threshold, the valves of the central region and the outer flow channel are opened to form a parallel flow channel structure that matches the chip size.

4. The method according to claim 1, characterized in that, The thermal pulse excitation of the chip includes: A low-power probe pulse is applied in advance to obtain the thermal time constant of the chip; The target pulse width is determined based on the thermal time constant and the preset multiple range; The first power limit is calculated based on the chip's rated power, and the second power limit is calculated based on the safe temperature rise threshold. The smaller value between the first power limit and the second power limit is taken as the target applied power. The chip is thermally pulse-excited based on the target pulse width and the target applied power.

5. The method according to claim 1, characterized in that, Based on the temperature-time evolution information, a temperature rise rate matrix and a steady-state temperature amplitude matrix are constructed, and the temperature rise rate matrix and the steady-state temperature amplitude matrix are fused to obtain a fusion weight matrix, specifically including: Extract the temperature rise rate and steady-state temperature amplitude at each sensor location in the sensor array from the temperature time evolution information; A temperature rise rate matrix is ​​constructed based on the temperature rise rate at each sensor location, and a steady-state temperature amplitude matrix is ​​constructed based on the steady-state temperature amplitude at each sensor location. The temperature rise rate matrix and the steady-state temperature amplitude matrix are normalized respectively; Set a weighting coefficient for the temperature rise rate and a weighting coefficient for the steady-state temperature amplitude, wherein the weighting coefficient for the temperature rise rate is greater than the weighting coefficient for the steady-state temperature amplitude. Based on the weighting coefficients of the temperature rise rate and the steady-state temperature amplitude, the normalized temperature rise rate matrix and the normalized steady-state temperature amplitude matrix are weighted and fused to obtain the fused weight matrix.

6. The method according to claim 5, characterized in that, The step of calculating the centroid coordinates of the heat distribution of the chip using the weighted centroid algorithm based on the fusion weight matrix includes: Extract the response timestamp matrix of each sensor in the sensor array when it reaches a preset temperature rise ratio; The spatiotemporal joint analysis of the fusion weight matrix is ​​performed using the timestamp matrix to generate a spatiotemporal joint weight matrix; Substituting the spatiotemporal joint weight matrix into the weighted centroid algorithm, the centroid coordinates of the heat distribution are calculated.

7. The method according to claim 6, characterized in that, After performing spatiotemporal joint analysis on the fusion weight matrix using the timestamp matrix to generate the spatiotemporal joint weight matrix, the process further includes: Identify edge region sensors in the spatiotemporal joint weight matrix that correspond to the chip edge region; Calculate the geometric distance between the edge region sensor and the physical edge of the chip, and obtain the edge heat dissipation compensation correction factor that is a function of the geometric distance; Multiply the fusion weights of the edge region sensors by the edge heat dissipation compensation correction factor to obtain the corrected spatiotemporal joint weight matrix; Substituting the modified spatiotemporal joint weight matrix into the weighted centroid algorithm, the modified centroid coordinates of the heat distribution are calculated.

8. The method according to claim 5, characterized in that, The step of calculating the centroid coordinates of the heat distribution of the chip using the weighted centroid algorithm based on the fusion weight matrix includes: Determine the maximum weight value in the fusion weight matrix, and use a predetermined proportion of the maximum weight value as a segmentation threshold to perform threshold segmentation on the fusion weight matrix, and extract high-temperature regions with weights greater than the segmentation threshold. A connected component labeling algorithm is used to identify independent high-temperature clusters within the high-temperature region; If a single independent high-temperature cluster is identified, the centroid coordinates of the single independent high-temperature cluster are determined as the centroid coordinates of the heat distribution. If two or more independent high-temperature clusters are identified, the centroid coordinates of each high-temperature cluster and the weighted sum of each high-temperature cluster are calculated respectively. Based on the weighted sum of each high-temperature cluster, the centroid coordinates of each high-temperature cluster are weighted and averaged to obtain the comprehensive centroid coordinates. The comprehensive centroid coordinates are determined as the centroid coordinates of the heat distribution.

9. The method according to any one of claims 7 or 8, characterized in that, The step of driving the multi-dimensional displacement stage, which supports the multi-stage flow channel heat dissipation structure, to move based on the deviation between the coordinates of the heat distribution centroid and the coordinates of the cooling center includes: The coordinates of the heat distribution centroid and the coordinates of the cooling center are vector subtracted to generate a compensation vector containing the horizontal and vertical axis offsets. The compensation vector is converted into a drive control signal for the multidimensional displacement stage, which controls the test head of the multidimensional displacement stage to perform displacement compensation in the horizontal plane. After displacement compensation is completed, thermal pulse excitation is applied again for verification until the deviation between the coordinates of the heat distribution centroid and the coordinates of the cooling center is less than the preset tolerance.

10. The method according to claim 1, characterized in that, The multi-stage flow channel heat dissipation structure also includes a gear pump and a constant temperature water bath. The dual-variable closed-loop regulation of fluid flow and temperature based on the chip's real-time thermal state specifically includes: Obtain the chip's steady-state temperature, chip input power, and coolant inlet temperature; The actual heat transfer coefficient is calculated based on the chip input power, the effective heating area, the steady-state temperature, and the coolant inlet temperature. The target heat transfer coefficient is calculated based on the chip input power, the effective heating area, the chip set temperature, and the coolant inlet temperature. The difference between the target heat transfer coefficient and the current actual heat transfer coefficient is used as the control error; The target speed of the gear pump and the target set temperature of the constant temperature water bath are calculated based on the control error. The gear pump speed is set to the target speed, and the set temperature of the constant temperature water bath is adjusted to the target set temperature to change the inlet temperature of the coolant. Repeat the above steps until the control error converges to a preset error threshold range.

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