An adaptive near-data-computing storage method and system for uncertain power supply and multi-priority tasks

Abstract

The application discloses a kind of adaptive near-data computing storage methods and systems for uncertain power supply and multi-priority task, belong to embedded storage and computing system technical field, including: obtaining power supply end real-time state parameter generation dynamic power consumption budget;For the data processing request issued by host end distribution priority label, and the data processing request is mapped to corresponding submission queue;Based on the dynamic power consumption budget and the priority label of request in each submission queue, the arbitration weight of the submission queue, the execution position of request, and the computing complexity and storage medium concurrency degree restriction inside storage device are jointly decided across layers;Finally, according to the result of joint decision, data processing request is executed cooperatively.The application realizes the global optimization of the certainty of storage access, power consumption safety and data processing efficiency under the environment of battery power supply and dynamic change of task demand.

Description

Technical Field

[0001] This invention belongs to the field of embedded storage and computing system technology, specifically an adaptive near-data computing and storage method and system for uncertain power supply and multi-priority tasks. Background Technology

[0002] In the field of embedded storage and computing, with the popularization of NVMe (Non-volatile Memory Fast Channel) technology in edge devices, how to achieve a balance between high performance, low power consumption and task determinism has become the focus of attention in related technical fields.

[0003] Existing technologies typically address these issues from three separate dimensions: near-data computation, power management, and task scheduling. However, this leads to the following technical problems: In traditional NVMe scheduling strategies, the Submission Queue (SQ) is mainly processed by round-robin or weighted round-robin, making it difficult to simultaneously perceive the real-time priority of tasks and the overall physical power budget of the system. As a result, in weak power conditions, high-priority I / O may still be blocked by low-priority I / O.

[0004] In existing near-data computing solutions, the computation location is usually fixed (either within the SSD or solely on the host machine), making it impossible to dynamically migrate the execution location based on current power supply capabilities and task urgency. For example, when system power drops, the computing pipeline cannot be automatically degraded, potentially leading to premature system power outages.

[0005] Existing power management focuses primarily on the switching of ASPM (Active State Power Management) at the PCIe link layer or the transition of NVMe power states (PS states). Its management granularity is relatively coarse, making it difficult to delve into the SSD's internal workings to finely control the number of concurrent NAND flash channels and the power consumption of the computing engine, and it lacks linkage with task priorities.

[0006] In battery-powered scenarios, the large capacitor charging and multi-NAND initialization during the startup of a high-capacity NVMe SSD can easily cause a momentary voltage drop, leading to a reset of the weak battery system; existing tiered startup strategies do not establish dynamic binding with battery discharge curves and real-time internal resistance parameters.

[0007] To address the aforementioned issues, this invention proposes an adaptive storage system that deeply integrates the NVMe storage protocol, near-data computation acceleration, task priority scheduling, and system power consumption management, and also proposes a control method. Summary of the Invention

[0008] The purpose of this invention is to provide an adaptive near-data computing and storage method and system for uncertain power supply and multi-priority tasks, so as to solve the problem of the separation between storage I / O scheduling, near-data computing execution location, system power consumption management and task priority in the prior art as mentioned in the background.

[0009] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: An adaptive near-data computation and storage method for uncertain power supply and multi-priority tasks includes the following steps: Power consumption awareness steps: Obtain real-time status parameters of the power supply and generate a dynamic power consumption budget accordingly; Task queue mapping steps: Assign priority tags to data processing requests issued by the host and map the data processing requests to the corresponding submission queues; Cross-layer joint scheduling steps: Based on the dynamic power budget and the priority tags of requests in each submission queue, jointly decide the arbitration weight of the submission queue, the processing position of the request, and the computational complexity and storage medium concurrency limits within the storage device; wherein, the processing position includes execution on the host or execution offloaded to the near data computing engine within the storage device; Collaborative execution steps: Execute the data processing request based on the decision result of the cross-layer joint scheduling.

[0010] According to the above technical solution, in the cross-layer joint scheduling step, based on the comparison relationship between the dynamic power consumption budget and the preset threshold, the system joint scheduling is divided into at least three modes: Sufficient mode: Allows requests of all priorities to be executed, and unloads data processing requests with lower priorities and higher data volume than a set value to the near data computing engine to execute the complete computing pipeline; Constrained mode: Limits the concurrency of the storage medium and the computational pipeline complexity of the storage device. High-priority requests are executed by the host, while low-priority requests are either degraded within the storage device or migrated back to the host for execution. Emergency Mode: The near-data computing engine is shut down, allowing only high-priority requests to be written to the storage medium in a minimal form, while non-critical requests are postponed or discarded.

[0011] According to the above technical solution, the collaborative execution step also includes a preemption and recovery step for the near-data computing pipeline: When the near-data computing engine is executing a low-priority request computing pipeline, if a high-priority urgent request is received, the current computing pipeline is interrupted, and the intermediate computing results and execution status are persistently saved to the internal reservation area of ​​the storage device. After the high-priority emergency request is processed, the intermediate calculation results and execution status are restored from the internal reserved area to continue the interrupted computation pipeline.

[0012] According to the above technical solution, before the power consumption sensing step, a device hierarchical startup step is also included: Generate an initial power consumption budget based on the initial power supply parameters when the system is powered on. Based on the initial power consumption budget, the communication link bandwidth between the host and the storage device, the storage medium channel, and the near-data computing engine are enabled in stages to control power-on transient power consumption and limit system voltage drops to within allowable ranges.

[0013] According to the above technical solution, the method further includes a three-level collaborative sensing step implemented through hardware with different power consumption levels: Level 1: Uses an ultra-low power analog front-end to coarsely screen the raw physical signals, and generates a wake-up signal only when a valid event is detected to wake up the storage device and the host. Level 2: After the storage device is woken up, the near data computing engine is used to perform secondary feature preprocessing on the collected signal data; Level 3: Only when the extracted secondary features meet the preset conditions will the feature data be sent back to the host for final fine processing.

[0014] An adaptive near-data computing and storage system for uncertain power supply and multi-priority tasks, the system comprising: The power supply sensing module is used to acquire real-time status parameters of the power supply end and generate a dynamic power consumption budget. The task queue management module is used to assign priority tags to data processing requests on the host side and map the data processing requests to the corresponding submission queues; An adaptive scheduling decision-maker is used to jointly decide the arbitration weight of the submission queue, the processing position of the request, and the computational complexity and storage medium concurrency limit within the storage device, based on the dynamic power budget and the priority tags of the requests in each submission queue. The computing storage device has a built-in near-data computing engine, which receives the decision results of the adaptive scheduling decision-maker and works with the host to complete the execution of the data processing request.

[0015] According to the above technical solution, the computing storage device has the ability to dynamically allocate hardware resources: The firmware of the computing storage device supports weighted arbitration responses based on the priority tag; The computing storage device supports responding to power limiting instructions issued by the adaptive scheduling decision-maker, dynamically enabling or disabling concurrent channels of the physical storage medium to achieve hardware-level transient power consumption control.

[0016] According to the above technical solution, the computing storage device has an internal reserved area independent of the host memory: The computing storage device has hardware-level preemption control logic, which is used to persist the execution context state to the internal reserved area when a high-priority task is received during the execution of a low-priority computing pipeline, and to automatically restore the context state from the internal reserved area after the high-priority task is completed.

[0017] According to the above technical solution, the system also includes a hierarchical start controller: The hierarchical startup controller is used to establish basic communication connections, enable storage media channels in groups, expand communication links to full bandwidth, and finally enable the near-data computing engine in a step-by-step manner according to the dynamic power consumption budget during the system power-on phase.

[0018] According to the above technical solution, the system also includes a shared memory communication interface configured in the host memory: The adaptive scheduling decision-maker issues joint decision instructions containing execution location and pipeline definition in the form of a scheduling descriptor through the shared memory communication interface. After completing the computation using the near-data computing engine, the computing storage device only writes the result metadata indicating the addressing information to the shared memory communication interface and notifies the host through an interrupt mechanism.

[0019] Compared with the prior art, the present invention has the following beneficial effects: To address the issue that traditional NVMe scheduling polling in existing technologies cannot perceive physical layer power constraints, this invention breaks down the isolation barrier between protocol layer task scheduling and hardware layer power management. Through joint decision-making using dynamic power budget and task priority tags, it effectively avoids the blocking of high-priority critical I / O by low-priority tasks under weak power conditions, achieving deterministic response of high-priority tasks without power interruption, while maximizing the utilization of near-data computing resources when power consumption is sufficient.

[0020] Existing near-data computing solutions mostly employ static offloading strategies. This invention introduces a dynamic computing location allocation and pipeline degradation mechanism. When battery power decreases or internal resistance increases sharply, the system can automatically reduce the number of concurrent channels on the storage medium and degrade or forcibly revert the computing pipeline back to the host for execution. This significantly reduces the transient power consumption overhead inside the solid-state drive and effectively prevents premature system power failure or forced reset due to power overload.

[0021] To address the issue of solid-state drive (SSD) internal computing pipeline persistence, this invention proposes a preemption and state recovery mechanism based on an internal reserved area. If a high-priority task suddenly occurs during the execution of a low-priority pipeline, the system can directly interrupt the current pipeline at the underlying hardware level and persistently save the intermediate state. This not only ensures ultra-low latency response for urgent tasks but also allows interrupted tasks to automatically resume execution later, avoiding the waste of resources from recalculating from scratch.

[0022] To address the industry pain point of large-capacity storage devices experiencing a significant drop in system voltage during startup due to the charging of large capacitors, this invention introduces a tiered startup control mechanism. By dynamically binding to the initial power consumption budget, it sequentially establishes basic communication connections, enables storage media channels in groups, and finally enables the computing engine in a step-by-step manner. This effectively controls the transient peak power consumption at power-on, ensuring a smooth startup of battery-powered devices. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the overall hardware architecture of the system of the present invention; Figure 2 This is a software model block diagram of the NVMe driver and firmware of the present invention; Figure 3 This is a flowchart of the graded power-on initialization process of the present invention; Figure 4 This is a flowchart of the power consumption budget update and joint scheduling decision-making process during the runtime of this invention; Figure 5 This is a schematic diagram illustrating the preemption and recovery timing of the near-data computation pipeline in this invention; Figure 6 This is a framework diagram of an embodiment of the three-level collaborative sensing of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Example 1

[0025] In one specific implementation, such as Figures 1 to 6 As shown, the adaptive near-data computing and storage system for uncertain power supply and multi-priority tasks provided by the present invention includes the following specific processes for the collaborative operation of the hardware platform: initialization phase, runtime power budget update phase, task submission and marking phase, joint arbitration and execution location decision phase, preemption and recovery phase of computing pipeline, and result return and feedback closed loop phase.

[0026] Specifically, such as Figure 3 As shown, during the initialization phase, after the system powers on, the power sensing module (such as a PMIC chip) sends the battery discharge curve parameters to the NVMe driver. The driver calculates the safe startup power consumption limit and executes a graded power-on process, which specifically includes four stages: In stage one, the system first establishes a connection with the minimum PCIe link width (e.g., x1 link) and loads the simplified firmware; In stage two, the system enables NAND flash array channels in batches according to the power budget, and after each group is enabled, it checks whether the system voltage drop is within the allowable range. If it exceeds the allowable range, a rollback operation is performed and the waiting time is extended; In stage three, after the system voltage stabilizes and the expansion conditions are met, the system expands the PCIe link width to the preset full bandwidth and loads the full firmware; In stage four, after the full firmware is loaded, the system decides whether to enable the near-data computing engine in the storage device based on the remaining power budget.

[0027] Furthermore, during the runtime power budget update phase, the system periodically acquires the battery status, converts it into the maximum allowable instantaneous power consumption and the allowable average power consumption of the storage device, and updates the power consumption values ​​to the power policy register of the storage device controller.

[0028] Furthermore, during the task submission and tagging phase, I / O requests or computation requests initiated by the application, carrying priority tags including real-time critical, real-time non-critical, or background batch processing, are placed into the corresponding NVMe submission queue. Preferably, each submission queue declares its priority weight and whether it can be offloaded for near-data computation at the time of creation.

[0029] Furthermore, during the joint arbitration and execution location decision-making phase, the adaptive scheduling decision-maker switches the execution mode based on the current power budget when retrieving commands from the submission queue. Specifically, if the current power budget is sufficient and greater than the high threshold, the system allows all priority tasks to execute and automatically offloads low-priority tasks with large data volumes to the near-data computation engine inside the storage device for execution, returning only metadata to reduce data movement; if the power budget is at a medium level and between the high and low thresholds, the system limits the number of concurrent NAND channels inside the storage device, ensuring that high-priority tasks are executed in real time on the host, while low-priority tasks have their computation pipeline downgraded (e.g., skipping complex feature extraction and only performing data compression), or are forcibly migrated back to the host for execution to release power consumption inside the storage device; if the power budget is insufficient and less than the low threshold, the system switches to an emergency low-power mode, allowing only high-priority tasks to execute in a minimal form, the storage device switches to a low-power sequential write mode, the near-data computation engine is shut down, and all data processing is migrated back to the host for minimal processing.

[0030] Furthermore, such as Figure 4 As shown, during the preemption and recovery phase of the compute pipeline, when a set of near-data compute pipelines is being executed inside the storage device, if a high-priority urgent task is received, the storage device firmware interrupts the current pipeline and persistently saves the intermediate compute results and execution state to an NVMe reserved area that is not affected by host interference (e.g., ...). Figure 2 As shown), the storage device immediately processes the high-priority emergency task; after the emergency task is completed, the storage device restores the intermediate computing state from the NVMe reserved area and continues to execute the original pipeline.

[0031] Furthermore, in the result return and feedback closed-loop stage, after the near-data computing engine completes the calculation, it writes the result metadata to shared memory and notifies the host through a doorbell mechanism. The host then reads the metadata and directly accesses the processed data block. Simultaneously, the storage device firmware reports the actual power consumption statistics to the scheduler for calibrating the subsequent power budget model, thus forming a complete feedback closed loop.

[0032] In one specific embodiment, the present invention is applied to a portable intelligent surveillance camera. The hardware platform of this device employs an ARM Cortex-A system-on-a-chip, an external power management chip, and an NVMe M.2 solid-state drive with a built-in programmable DSP computing engine. Its tasks include continuous video acquisition, target recognition as a high-priority task, video recording, storage, and post-processing as a low-priority task, and log recording as a background task.

[0033] Specifically, at startup, the battery voltage is 3.7V, the internal resistance is 150mΩ, and the power management chip reports a peak power consumption of 5W. The driver selects a tiered power-up process: first, the x1 communication link is configured, two NAND channels are initialized, and the compute engine is temporarily disabled. After the system capacitors have charged to a steady state, the system then extends the link to x4 and all NAND channels, and enables the compute engine.

[0034] Furthermore, during operation, when the battery level is >50%, the video data is directly sent to the solid-state drive. The calculation command triggers the complete calculation pipeline, which sequentially executes the decoding operation, the target detection box drawing operation, and the H.265 encoding operation. The solid-state drive only sends back the detection box coordinates and thumbnails to the host, which then makes the alarm decision.

[0035] Furthermore, when the battery level drops to 25%, the power consumption budget is limited to 2.5W, the number of concurrent NAND channels in the solid-state drive is halved, the computing pipeline is downgraded to only perform decoding and compression operations sequentially, and the data is sent back to the host for lightweight testing.

[0036] Furthermore, when the battery level is less than 15%, the system enters an emergency low-power mode, shuts down the computing engine, and switches all I / O operations to sequential writing. High-priority events can still be recorded in real time, while medium and low-priority tasks are suspended.

[0037] In another specific embodiment, the present invention is applied to an industrial handheld vibration analyzer. The hardware platform of this device includes an ARM Cortex-A system-on-a-chip, an external power management chip, an NVMe solid-state drive with a DSP computing engine, and a three-axis MEMS accelerometer with a sampling rate of 25.6 kHz, connected to the main control chip via an SPI interface. This task requires simultaneous processing of real-time vibration spectrum analysis, continuous recording of raw waveforms, and comparison of historical data trends.

[0038] Specifically, the system creates three submission queues during initialization: SQ0 is the real-time critical queue, responsible for real-time vibration data acquisition and FFT spectrum feature extraction for immediate alarm judgment. This queue has the highest priority and cannot be offloaded to the solid-state drive computing engine; SQ1 is the real-time non-critical queue, responsible for continuous disk storage of raw high-frequency vibration waveforms. It allows offloading near-data computing tasks when power consumption is sufficient, but does not allow blocking SQ0; SQ2 is the background batch processing queue, responsible for tasks such as historical data analysis.

[0039] Specifically, in a scenario with sufficient battery power (i.e., remaining capacity > 50%), the on-site battery voltage is 7.8V, internal resistance is 80mΩ, and dynamic power consumption budget is 6W peak. The SQ0 task is directly executed by the host CPU, acquiring the latest 1024-point vibration data block and calculating the FFT, with a total latency of <2ms. Simultaneously, the SQ1's raw waveform write-to-disk task triggers near-data computation offloading. The host issues a custom computation command, and the DSP engine within the SSD executes a Huffman lossless compression pipeline on the data block, sequentially performing DMA data block read operations, DSP compression operations, and writing the compression results back to NAND flash memory. Subsequently, the SSD only writes the physical address list of the compressed data block to shared memory.

[0040] Furthermore, in scenarios where battery power decreases, i.e., when the remaining capacity is between 20% and 50%, the battery voltage drops to 6.5V, the internal resistance rises to 200mΩ, and the power consumption budget drops to 3W. The scheduler issues a power consumption policy through shared memory, limiting the number of concurrent operation channels for NAND flash memory from 4 channels to 2 channels. At this time, the compression offloading policy of SQ1 automatically degrades, and the raw data is directly written sequentially to NAND flash memory to eliminate computational power consumption overhead, while the task rate of SQ2 is limited.

[0041] Furthermore, in scenarios where the battery is nearly depleted (i.e., remaining capacity <15%), the battery's internal resistance increases dramatically, limiting the power consumption budget to 1.5W. The scheduler issues an emergency command to shut down the SSD's internal computing engine and redundant channels, retaining only single-channel sequential write capability. At this point, SQ0's host-side fault judgment logic switches to a simplified vibration RMS value judgment, abandoning FFT calculation; SQ1 degrades to recording only snapshot data 2 seconds before and after the alarm trigger moment; all background tasks in SQ2 are suspended. This mode effectively maintains critical fault alarms and limited data recording for over 15 minutes, preventing the loss of critical fault moments due to sudden power outages.

[0042] In another specific embodiment, the present invention is applied to an onboard data processing unit for a UAV. This unit's heterogeneous hardware platform includes an ARM Cortex-A core responsible for system management, a dedicated AI accelerator NPU for host-side fine processing, an external power management chip, an NVMe solid-state drive, and a sensor module. Preferably, the solid-state drive simultaneously integrates a programmable DSP computing engine and a RISC-V near-data computing engine dedicated to image preprocessing; the sensor module includes an ultra-low-power MEMS accelerometer, a barometer, and a 4K gimbal camera. This embodiment specifically demonstrates the operation of the invention's unique three-level collaborative sensing architecture.

[0043] Specifically, such as Figure 6 As shown, during the first-stage simulation screening phase, when the UAV is cruising in level flight, the main control chip, NPU, camera, and solid-state drive are all in sleep mode. Only the ultra-low-power MEMS accelerometer on the arm and its simulation front-end are active. This simulation front-end is equipped with a bandpass filter whose center frequency is the fundamental frequency of the UAV rotor rotation and its second harmonic. When the UAV rotor develops microcracks due to material fatigue, causing abnormal vibrations at its characteristic frequency, the output energy of the simulation bandpass filter exceeds a preset threshold for several consecutive cycles, causing the simulation comparator to flip, thereby generating a wake-up interrupt signal.

[0044] Furthermore, in the second-level near-data refinement stage, the wake-up signal wakes up the main control chip via the GPIO interface. Upon power-up, the main control chip immediately wakes up the solid-state drive (SSD) via the PCIe link. Since the system is in a cold-start state and the battery power budget is sufficient, the tiered power-up controller quickly completes SSD initialization and enables its computing engine. The main control chip instantly increases the sampling rate of the vibration sensor via the SPI interface to its maximum, and the acquired raw high-frequency vibration data stream is directly written to a preset circular buffer within the SSD via DMA. Simultaneously, the host computer instructs the RISC-V computing engine inside the SSD to perform a 256-point sliding FFT calculation on the consecutive data blocks in the circular buffer via shared memory to extract real-time spectral features. After the SSD completes the calculation, it only sends the spectral feature vector back to the shared memory.

[0045] Furthermore, in the third-level host fine processing stage, after the host obtains the spectral feature vector from shared memory, it immediately wakes up the AI ​​accelerator NPU and inputs the feature vector into a pre-deployed decision tree lightweight anomaly classification model. If the NPU determines that the fault is a level one symptom, it immediately sends an emergency status code to the flight control computer via the flight control bus, and simultaneously locks and permanently saves the raw vibration data of the corresponding time window from the circular buffer of the solid-state drive. Preferably, the total delay time from the simulation front-end waking up to the NPU providing the judgment result does not exceed 50ms, which can effectively support emergency decision-making during flight.

[0046] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0047] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An adaptive near-data computation and storage method for uncertain power supply and multi-priority tasks, characterized in that: Includes the following steps: Power consumption awareness steps: Obtain real-time status parameters of the power supply and generate a dynamic power consumption budget accordingly; Task queue mapping steps: Assign priority tags to data processing requests issued by the host and map the data processing requests to the corresponding submission queues; Cross-layer joint scheduling steps: Based on the dynamic power budget and the priority tags of requests in each submission queue, jointly decide the arbitration weight of the submission queue, the processing position of the request, and the computational complexity and storage medium concurrency limits within the storage device; wherein, the processing position includes execution on the host or execution offloaded to the near data computing engine within the storage device; Collaborative execution steps: Execute the data processing request based on the decision result of the cross-layer joint scheduling.

2. The adaptive near-data computation and storage method for uncertain power supply and multi-priority tasks according to claim 1, characterized in that: In the cross-layer joint scheduling step, based on the comparison between the dynamic power budget and the preset threshold, the system joint scheduling is divided into at least three modes: Sufficient mode: Allows requests of all priorities to be executed, and unloads data processing requests with lower priorities and higher data volume than a set value to the near data computing engine to execute the complete computing pipeline; Constrained mode: Limits the concurrency of the storage medium and the computational pipeline complexity of the storage device. High-priority requests are executed by the host, while low-priority requests are either degraded within the storage device or migrated back to the host for execution. Emergency Mode: The near-data computing engine is shut down, allowing only high-priority requests to be written to the storage medium in a minimal form, while non-critical requests are postponed or discarded.

3. An adaptive near-data computation and storage method for uncertain power supply and multi-priority tasks according to claim 1 or 2, characterized in that: The collaborative execution steps also include preemption and recovery steps for the near-data computation pipeline: When the near-data computing engine is executing a low-priority request computing pipeline, if a high-priority urgent request is received, the current computing pipeline is interrupted, and the intermediate computing results and execution status are persistently saved to the internal reservation area of ​​the storage device. After the high-priority emergency request is processed, the intermediate calculation results and execution status are restored from the internal reserved area to continue the interrupted computation pipeline.

4. The adaptive near-data computation and storage method for uncertain power supply and multi-priority tasks according to claim 1, characterized in that: Prior to the power consumption sensing step, a device hierarchical startup step is also included: Generate an initial power consumption budget based on the initial power supply parameters when the system is powered on. Based on the initial power consumption budget, the communication link bandwidth between the host and the storage device, the storage medium channel, and the near-data computing engine are enabled in stages to control power-on transient power consumption and limit system voltage drops to within allowable ranges.

5. The adaptive near-data computing and storage method and system for uncertain power supply and multi-priority tasks according to claim 1, characterized in that: The method also includes a three-level collaborative sensing step implemented through hardware with different power consumption levels: Level 1: Uses an ultra-low power analog front-end to coarsely screen the raw physical signals, and generates a wake-up signal only when a valid event is detected to wake up the storage device and the host. Level 2: After the storage device is woken up, the near data computing engine is used to perform secondary feature preprocessing on the collected signal data; Level 3: Only when the extracted secondary features meet the preset conditions will the feature data be sent back to the host for final fine processing.

6. An adaptive near-data computing and storage system for uncertain power supply and multi-priority tasks, used to implement the method as described in any one of claims 1 to 5, characterized in that: The system includes: The power supply sensing module is used to acquire real-time status parameters of the power supply end and generate a dynamic power consumption budget. The task queue management module is used to assign priority tags to data processing requests on the host side and map the data processing requests to the corresponding submission queues; An adaptive scheduling decision-maker is used to jointly decide the arbitration weight of the submission queue, the processing position of the request, and the computational complexity and storage medium concurrency limit within the storage device, based on the dynamic power budget and the priority tags of the requests in each submission queue. The computing storage device has a built-in near-data computing engine, which receives the decision results of the adaptive scheduling decision-maker and works with the host to complete the execution of the data processing request.

7. An adaptive near-data computing and storage system for uncertain power supply and multi-priority tasks according to claim 6, characterized in that: The computing storage device has the ability to dynamically allocate hardware resources: The firmware of the computing storage device supports weighted arbitration responses based on the priority tag; The computing storage device supports responding to power limiting instructions issued by the adaptive scheduling decision-maker, dynamically enabling or disabling concurrent channels of the physical storage medium to achieve hardware-level transient power consumption control.

8. An adaptive near-data computing and storage system for uncertain power supply and multi-priority tasks according to claim 6, characterized in that: The computing storage device has an internal reserved area that is independent of the host memory: The computing storage device has hardware-level preemption control logic, which is used to persist the execution context state to the internal reserved area when a high-priority task is received during the execution of a low-priority computing pipeline, and to automatically restore the context state from the internal reserved area after the high-priority task is completed.

9. An adaptive near-data computing and storage system for uncertain power supply and multi-priority tasks according to claim 6, characterized in that: The system also includes a tiered start controller: The hierarchical startup controller is used to establish basic communication connections, enable storage media channels in groups, expand communication links to full bandwidth, and finally enable the near-data computing engine in a step-by-step manner according to the dynamic power consumption budget during the system power-on phase.

10. An adaptive near-data computing and storage system for uncertain power supply and multi-priority tasks according to claim 6, characterized in that: The system also includes a shared memory communication interface configured in the host memory: The adaptive scheduling decision-maker issues joint decision instructions containing execution location and pipeline definition in the form of a scheduling descriptor through the shared memory communication interface. After completing the computation using the near-data computing engine, the computing storage device only writes the result metadata indicating the addressing information to the shared memory communication interface and notifies the host through an interrupt mechanism.

Images