Mixed access method, apparatus and medium for internal signals of a logic simulator

Abstract

The present application relates to the technical field of electronic design automation, and particularly relates to a mixed access method, device and medium for internal signals of a logic simulator, which dynamically detects whether a memory address acquisition extension interface is provided by the logic simulator at runtime, switches a read operation to a direct memory access operation only when the memory address acquisition extension interface exists and a returned physical memory address is valid, and otherwise automatically reverts to a Verilog program interface, so that adaptive selection of an access path is realized, high performance and compatibility can be considered under different logic simulator environments without modification of the same set of verification code; meanwhile, a read operation is directly connected to a memory, and a write operation keeps a read-write separation strategy of the Verilog program interface, so that a read operation performance bottleneck is eliminated by bypassing a Verilog program interface call chain, and it is ensured that a write operation is still processed by a logic simulator event scheduling mechanism, and correctness of signal propagation semantics is completely maintained.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and in particular to a method, device and medium for mixed access to signals inside a logic simulator. Background Technology

[0002] In the integrated circuit design and verification process, the logic simulator is a core tool for verifying the correctness of register-transfer-level (RTL) designs. The IEEE 1800 SystemVerilog standard defines the Verilog Procedural Interface (VPI) as the standard programming interface between the logic simulator and external C / C++ programs, allowing external code to access the internal signal values, module hierarchy, and simulation state of the logic simulator at runtime. In a Verilog Procedural Interface-based verification environment, external programs interact with the logic simulator through the standard Verilog Procedural Interface.

[0003] Existing technologies mainly include the standard Verilog procedural interface, the Direct Programming Interface (DPI) method, and the direct memory access method. While the standard Verilog procedural interface method offers good compatibility, each access requires handle lookup, type checking, value format conversion, and data copying, resulting in a 20% to 30% performance penalty. The DPI method reduces some overhead, but its ability to access internal signals is limited. The direct memory access method offers the best performance, but it heavily relies on specific logic simulators, cannot be reused across platforms, and carries the risk of inconsistent signal propagation and address instability. Furthermore, existing logic simulators typically use a traditional layout for storing binary logic values ​​(aval) and exception masks (bval) alternately, either element-wise or word-wise. This necessitates address retrieval interfaces that branch according to signal type, making implementation complex. Additionally, direct binary reads cannot efficiently utilize contiguous memory access, further reducing the performance of internal signal access in logic simulators. Therefore, improving the access performance and compatibility of internal signals in logic simulators is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a method, device, and medium for mixed access to signals inside a logic simulator, thereby improving the access performance and compatibility of signals inside the logic simulator.

[0005] According to a first aspect of the present invention, a method for mixed access to signals inside a logic simulator is provided, comprising:

[0006] Step S1: Obtain the handle of the signal to be accessed in the logic simulator;

[0007] Step S2: Based on the handle of the signal to be accessed, create a data encapsulation body containing read operation signals and write operation functions for the signal to be accessed through the Verilog program interface, and establish a Verilog program interface access channel.

[0008] Step S3: Dynamically detect whether the logic simulator provides an extended interface for obtaining memory addresses during runtime. If yes, proceed to step S4; otherwise, proceed to step S7.

[0009] Step S4: Call the memory address acquisition extension interface to obtain the physical memory address of the signal to be accessed, and determine whether the physical memory address of the signal to be accessed is valid. If it is valid, proceed to step S5; otherwise, proceed to step S7.

[0010] Step S5: Replace the read operation function in the data encapsulation body with the direct memory access operation function based on the physical memory address, and keep the write operation function executed through the Verilog program interface to establish a hybrid access channel and execute step S6.

[0011] Step S6: Access the signal to be accessed based on the hybrid access channel, and end the process;

[0012] Step S7: Access the signal to be accessed based on the Verilog program interface access channel, and end the process.

[0013] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.

[0014] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.

[0015] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the mixed access method, device, and medium for internal signals of a logic simulator provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It has at least the following beneficial effects:

[0016] This invention achieves adaptive access path selection by dynamically detecting whether the logic simulator provides a memory address acquisition extension interface at runtime. Only when the memory address acquisition extension interface exists and returns a valid physical memory address is the read operation switched to a direct memory access operation; otherwise, it automatically falls back to the Verilog program interface. This allows the same verification code to maintain both high performance and compatibility in different logic simulator environments without modification. Simultaneously, it employs a read-write separation strategy, where read operations directly connect to memory while write operations maintain the Verilog program interface. This bypasses the Verilog program interface call chain to eliminate read operation performance bottlenecks while ensuring that write operations are still processed by the logic simulator's event scheduling mechanism, fully maintaining the correctness of signal propagation semantics. Furthermore, the aforementioned path detection and switching are performed only once during the signal initialization phase, without adding any additional runtime judgment overhead to subsequent signal accesses. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating a method for mixed access to internal signals of a logic simulator provided in an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of the electronic device structure provided in an embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram of a computer-readable storage medium structure provided in an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This invention provides a method for mixed access to signals inside a logic simulator, which can be applied to scenarios such as application-specific integrated circuit (ASIC) design verification and field-programmable gate array (FPGA) logic simulation. Figure 1 As shown, the method includes:

[0023] Step S1: Obtain the handle of the signal to be accessed in the logic simulator.

[0024] It should be noted that the logic simulator assigns a unique signal handle to each register, net, array, and other signal within the design. This handle serves as a unified identifier for the simulation kernel to recognize the target signal. External verification programs can call the logic simulator's built-in query interface via the signal hierarchy path name to parse and obtain the handle of the corresponding signal to be accessed. If no matching handle is found, the signal to be accessed is determined to not exist, the access process is terminated, and an exception message is generated. Specifically, the logic simulator can be a digital logic simulator.

[0025] Step S2: Based on the handle of the signal to be accessed, create a data encapsulation body containing read operation signals and write operation functions for the signal to be accessed through the Verilog program interface, and establish a Verilog program interface access channel.

[0026] It should be noted that step 2 establishes a compatible fallback access channel, completing basic binding based on the industry-standard Verilog Programming Interface (VPI): using the handle of the signal to be accessed obtained in step S1 as input parameter, the three basic functions of the Verilog Programming Interface—attribute query, value reading, and value writing—are called, encapsulating the signal reading and writing logic into a unified data encapsulation body. This data encapsulation body provides a unified signal read / write call entry point, and the upper-layer verification code does not need to distinguish the underlying interaction method; it can complete signal access simply by calling the encapsulation body interface. At this stage, only the Verilog Programming Interface access channel is enabled by default, and all read / write operations interact with the logic simulator kernel through the Verilog Programming Interface, ensuring the cross-logic simulator universality of basic functions.

[0027] Step S3: Dynamically detect whether the logic simulator provides an extended interface for obtaining memory addresses during runtime. If yes, proceed to step S4; otherwise, proceed to step S7.

[0028] It should be noted that step S3 employs a runtime dynamic function retrieval mechanism to detect extended interfaces, without relying on pre-defined tool adaptation macros during the compilation phase, and without requiring the compilation of multiple versions of program binary files for different logic simulators. After program startup, the function entity corresponding to the extended interface is obtained by searching the memory address in the logic simulator's loaded library file using a dynamic symbol retrieval method. If the retrieval returns a null pointer, it means that the current logic simulator does not have open memory direct connection capability, and high-performance direct read optimization cannot be performed; the Verilog program interface access channel is directly used.

[0029] Step S4: Call the memory address acquisition extension interface to obtain the physical memory address of the signal to be accessed, and determine whether the physical memory address of the signal to be accessed is valid. If it is valid, proceed to step S5; otherwise, proceed to step S7.

[0030] It should be noted that the memory address acquisition extension interface is a private interface pre-configured by the logic simulator. It can parse signal handles and return the physical memory base address of the signal storage area. Address validity verification can include multiple layers of judgment logic: First, it checks whether the returned memory address is a zero empty address. An empty address means that the signal does not support direct memory connection (e.g., deleted after simulation optimization, composite structure signals, etc.). Second, it performs dual-channel numerical cross-verification, reading the current signal value through both the Verilog program interface and direct memory access, comparing whether the two sets of values ​​are consistent. If there is a discrepancy, the address resolution is determined to be abnormal, and the address is considered invalid. If any layer of verification fails, the direct connection optimization logic is abandoned, and the process falls back to the Verilog program interface access channel.

[0031] Step S5: Replace the read operation function in the data encapsulation body with the direct memory access operation function based on the physical memory address, and keep the write operation function executed through the Verilog program interface to establish a hybrid access channel, and then execute step S6.

[0032] It should be noted that step S5 employs a dual-channel design with read-write separation to balance access performance and simulation semantic consistency: the logic for reading the signal to be accessed is switched to direct memory access, bypassing the overhead of multi-layer function calls, data copying, and format conversion in the Verilog program interface, significantly improving the reading speed in large-scale signal sampling and waveform acquisition scenarios; the signal writing logic retains the standard Verilog program interface throughout execution, and the logic simulator scheduling kernel can fully capture signal value changes, normally completing level transmission, timing event triggering, and four-state logic synchronous updates, avoiding simulation timing errors, unknowns, and high-impedance state loss problems caused by directly rewriting memory. The function replacement process is only executed once during the signal initialization and binding phase, and does not require repeated processing during the simulation run phase, thus not increasing real-time access overhead. Moreover, the entire switching process is completely transparent to the upper-layer verification code, requiring no modification to the original test platform logic.

[0033] Step S6: Access the signal to be accessed based on the hybrid access channel, and end the process.

[0034] It should be noted that the hybrid access channel automatically distinguishes between read and write logic: when the external call signal read interface is used, a direct memory access operation is performed to quickly read the binary logic level data; when the external call signal write interface is used, the reserved Verilog program interface write function is automatically called to synchronously update the binary logic storage area and the exception mask storage area in the logic simulator kernel, taking into account both high-speed read performance and complete four-state simulation logic.

[0035] Step S7: Access the signal to be accessed based on the Verilog program interface access channel, and end the process.

[0036] It should be noted that when any of the following situations occur, such as missing expansion interfaces, invalid memory addresses, or address value verification failures, the system will automatically fall back to the Verilog program interface access channel. All signal reading and modification actions are performed through the standard Verilog program interface, fully complying with IEEE digital simulation standards and specifications, ensuring complete functionality and adaptability to general logic simulator environments without direct memory connection expansion capabilities.

[0037] The embodiments of the present invention can achieve fast direct memory read without offset, based on the unified dual-block storage structure built into the logic simulator: the binary logic data blocks of all signals are uniformly placed at the starting offset position of the storage structure, and the memory address acquisition extension interface directly returns the starting base address, without the need to distinguish between scalar, wide vector, and unpacked array signal types and calculate the memory offset separately; at the same time, the system matches the memory read logic of the corresponding byte length according to the actual bit width of the signal, further compressing the computational overhead of a single read operation.

[0038] As one embodiment, to support the fast memory read capability of the hybrid access channel, the logic simulator uses a dual-block storage structure to store the logic data of all signals, eliminating the offset calculation overhead during direct memory read from the underlying storage layout. The logic simulator splits the logic data of each signal into a binary logic value vector and an anomaly mask bit vector. The binary logic value vector stores the standard logic levels of the signal (0, 1), and the anomaly mask bit vector marks unknown or high-impedance abnormal states of the signal. The dual-block storage structure includes binary logic data blocks and anomaly mask data blocks. The binary logic data blocks store the binary logic value vectors, and the anomaly mask data blocks store the anomaly mask bit vectors. The binary logic data blocks are located at the starting address of the storage structure, and the anomaly mask data blocks are arranged continuously after the binary logic data blocks without alternating arrangement. This separate layout is the underlying foundation for achieving simplified addressing and high-speed batch reads of the memory address expansion interface.

[0039] As one embodiment, adapted sub-storage structures are set for different types and bit widths of signals. All sub-storage structures follow the dual-block storage layout and adhere to the unified rule of placing binary logic data blocks at offset 0.

[0040] For scalar and short vector signals with a bit width not exceeding 64 bits: a union substructure is adopted, in which the binary logic value fields of all substructures are located at the position with a structure offset of 0; the union is internally designed with multiple sets of sub-memory units with different bit widths, and the basic level can be read directly without distinguishing the signal bit width.

[0041] Wide vector signals with a bit width exceeding 64 bits are split into multiple standard word units for storage. The binary logic values ​​corresponding to all word units are arranged consecutively in a binary logic data block, and the mask data is uniformly placed at the end for easy vectorized batch reading.

[0042] The binary logic values ​​of all array elements of the unpacked array signal are arranged continuously in the order of array index. The exception mask of all elements is synchronously and centrally stored at the back. The read position of any array element can be linearly calculated through the base address and index, without the overhead of multi-level pointer dereferencing.

[0043] Based on the above unified storage design, the memory address acquisition extension interface only needs to return the starting base address of the storage structure, without distinguishing signal type or bit width and calculating memory offset separately, which simplifies the direct connection read logic and reduces runtime computation overhead.

[0044] As one embodiment, step S2 includes:

[0045] Step S21: Based on the handle of the signal to be accessed, read the signal value of the signal to be accessed and convert it into a form in which binary logic value and exception mask are stored alternately.

[0046] It should be noted that during the signal initialization and binding phase, the program relies on the unique signal handle obtained in step S1 to call the built-in value reading function of the Verilog program interface to obtain the original complete four-state logic data of the signal from the logic simulator kernel. The logic simulator kernel natively uses a block-based, continuous storage layout for binary logic data blocks and exception mask data blocks. However, the Verilog program interface stipulates that external interactions must use a standard transmission format that alternates between binary logic values ​​and exception masks to adapt to the interface's built-in data parsing and parameter verification logic. Therefore, step S21 requires format translation of the natively block-based data, disassembling and reorganizing the originally continuous binary logic data and mask data, and reorganizing them according to the rule of alternating single-segment binary logic values ​​and corresponding single-segment exception masks. This generates a signal value buffer that conforms to the Verilog sequence interface input specification, completely preserving the four logic state information of the signal: 0, 1, unknown, and high impedance, ensuring that subsequent standard interface read / write operations can completely recognize all four-state logic.

[0047] Step S22: Based on the handle of the signal to be accessed, create a data encapsulation containing read operation signals and write operation functions through the Verilog program interface, and establish a Verilog program interface access channel.

[0048] It should be noted that after the numerical format conversion is completed, the native read and write logic of the Verilog program interface is encapsulated and integrated using signal handles as the underlying identifier and alternating format values ​​as the data interaction carrier: For read operations, a standard read function adapted to alternating storage format is encapsulated. When the upper layer initiates a read request, this function calls the Verilog program interface to read the alternating format signal value, performs reverse format parsing, and outputs a readable standardized signal value to the upper layer; For write operations, a standard write function adapted to alternating storage format is encapsulated. After the upper layer sends the value to be written, this function first reassembles the upper layer input value into the alternating storage format required by the interface, and then calls the Verilog program interface to send it to the logic simulator kernel, synchronously updating the binary logic data block and exception mask data block inside the logic simulator, and triggering the simulation event scheduling and signal timing propagation process.

[0049] The alternating storage format of binary logic values ​​and exception masks used in steps S21 and S22 is only a temporary transmission format for external interaction of the Verilog program interface, not the native storage format of the logic simulator kernel. The underlying logic simulator still adopts the dual-block storage structure of this invention, with binary logic data blocks centrally placed at the front and exception mask data blocks placed entirely at the back. Standard interface access requires conversion between the two storage formats, which is the core reason for the format conversion overhead and low performance of pure Verilog program interface access. However, the direct memory read logic of the subsequent hybrid access channel of this invention directly operates on the native dual-block storage structure of the logic simulator, eliminating this format conversion step, thereby achieving a significant improvement in read performance.

[0050] After successfully obtaining a valid signal physical memory address and completing the read operation function replacement within the data encapsulation, proceed to step S6, where signal interaction is completed based on the read-write separation hybrid access channel. As one embodiment, step S6 includes:

[0051] Step S61: If a read operation needs to be performed on the access signal, proceed to step S62; if a write operation needs to be performed on the access signal, proceed to step S63.

[0052] Step S62: Call the direct memory access operation function in the data encapsulation body to perform a read operation on the signal to be accessed, and end the process.

[0053] It should be noted that this direct memory access operation function only completes the replacement once during the signal initialization and binding phase. There is no need for repeated adaptation or additional branch judgment overhead during runtime. The function completely bypasses the function call chain, data format conversion, and buffer copying process of the Verilog program interface. It directly operates on the native dual-block storage structure of the logic simulator kernel, and only reads the standard 0 and 1 level data in the binary logic data block. It is suitable for most verification scenarios that only require binary logic values, and significantly reduces performance loss.

[0054] Step S63: Call the write operation function in the data encapsulation body to perform a write operation on the access signal and end the process.

[0055] It should be noted that even though the hybrid access channel is currently enabled, the signal write operation still does not use the memory-to-write logic, and continues to reuse the write function based on the Verilog program interface. After the upper layer sends the write value, the data will be transmitted to the logic simulator kernel through the Verilog program interface, synchronously updating the binary logic data block and the exception mask data block. At the same time, the simulation event scheduling, signal propagation, timing calculation, and multi-drive conflict detection mechanism are fully triggered to avoid problems such as logic disorder, loss of X and Z abnormal states, and timing calculation errors caused by directly modifying memory to bypass the simulation scheduling, thus ensuring that the simulation behavior fully complies with the standard four-state logic specification.

[0056] As one embodiment, step S62 includes:

[0057] Step S621: Call the direct memory access operation function in the data encapsulation body to obtain the starting address of the binary value data block corresponding to the signal to be accessed as the physical memory address of the signal to be accessed.

[0058] It should be noted that, based on the unified dual-block storage layout at the bottom layer of the logic simulator, the binary logic data blocks of all signals are fixed at the position with an offset of 0 in the storage structure; the base address output by the memory address acquisition extension interface directly corresponds to the starting address of the binary logic data block, without the need to calculate offsets for different signal types such as scalars, wide vectors, and arrays. Step S621 only performs address extraction, without redundant operations such as format conversion and handle secondary verification, thus greatly reducing addressing overhead.

[0059] Step S622: Read the signal value of the signal to be accessed from the binary logic data block corresponding to the signal to be accessed based on the physical memory address of the signal to be accessed, and end the process.

[0060] It should be noted that, unlike the Verilog program interface which requires conversion of alternating storage formats, this step directly reads the simulation's native contiguous memory region, extracts only the binary logic value, and ignores the subsequent exception mask data block; simultaneously, it adaptively matches the optimal memory read granularity based on the actual signal bit width, eliminating runtime bit width judgment branch overhead. As one embodiment, in step S622, reading the signal value of the signal to be accessed from the binary logic data block corresponding to the signal to be accessed based on the physical memory address of the signal to be accessed includes:

[0061] Based on the memory read method corresponding to the signal bit width adaptation, all read operations directly read the binary logical data block based on the physical memory address of the signal to be accessed:

[0062] If the signal to be accessed is a unit scalar signal, a single byte of complete logical value is read at a time. This byte contains both binary logical value and exception mask information, and can be parsed to obtain a complete four-state logical value. This method is suitable for scalar scenarios such as single-bit ports and registers.

[0063] If the signal width to be accessed is 1 to 8 bits, the binary logic value is read in single-byte reads. A single byte of memory is read at a time, extracting only the binary logic value within the byte as the valid signal level; by default, there are no X or Z abnormal states.

[0064] If the signal width to be accessed is 9 to 16 bits, the binary logic value is read in two bytes. A single read of two bytes of continuous memory data directly extracts the complete binary logic vector without the need for segmentation and concatenation.

[0065] If the signal width to be accessed is 17 to 32 bits, the binary logic value is read in four bytes. A single four-byte read retrieves all binary logic values ​​at once, adapting to 32-bit data bus signals.

[0066] If the signal width to be accessed is 33 to 64 bits, then 32 bits of data are read in two separate steps and concatenated to obtain the complete signal value. Alternatively, two 32-bit segments of memory data are read in two separate steps, and then concatenated to obtain the complete 64-bit binary logic signal value.

[0067] If the signal to be accessed is a wide vector with a bit width greater than 64 bits, then iterate through and read 32-bit binary logic data in batches. Iterate through all 32-bit standard word units within the binary logic data block and read the binary logic data continuously in batches. This is suitable for scenarios with large-capacity address buses and long data vectors. The contiguous memory layout can make full use of CPU cache prefetching and SIMD vectorized reading capabilities to further improve batch reading efficiency.

[0068] The above-mentioned reading logic is implemented based on the dual-block storage structure. The layout of binary logical data blocks with a unified offset of 0 is the underlying foundation for achieving offset-free, high-speed direct reading with wide partitions. At the same time, through the read-write separation mechanism, performance optimization is performed only for read operations with extremely high access frequency, while low-frequency write operations retain the standard interface for execution. Without destroying the standard semantics of simulation, the 20% to 30% simulation performance loss caused by the traditional Verilog program interface is eliminated to the greatest extent.

[0069] As one embodiment, when the memory address acquisition extension interface is not found during runtime, or the acquired physical memory address is invalid, the process proceeds to step S7, which includes:

[0070] Step S71: If a read operation needs to be performed on the access signal, proceed to step S72; if a write operation needs to be performed on the access signal, proceed to step S73.

[0071] Step S72: Call the read operation function in the data encapsulation body to perform a read operation on the signal to be accessed, and end the process.

[0072] It should be noted that the read operation function is a standard read logic pre-encapsulated in step S2 and implemented based on the Verilog program interface. When the function executes, it uses the signal handle as input parameter to call the standard interface to read signal data from the logic simulator, obtaining the original values ​​in an alternating format of binary logic values ​​and exception masks. Then, it parses and restores the standard transmission format of the interface, integrating the signal values ​​containing complete 0, 1, unknown, and high-impedance four-state information, and returns them to the upper-layer verification program. The entire read process strictly follows the Verilog program interface specification, including handle validity verification, parameter checking, data copying, and format conversion, ensuring compatibility with all logic simulators that support the standard Verilog program interface and guaranteeing accurate and complete read results.

[0073] Step S73: Call the write operation function in the data encapsulation body to perform a write operation on the access signal and end the process.

[0074] It should be noted that this write operation function is also built on the standard Verilog program interface. After the upper layer sends the signal value to be written, the function first converts the input value into a binary logic value and an exception mask alternating storage format specified by the interface, and then calls the standard write interface to transmit the formatted data to the logic simulator kernel. After receiving the data, the logic simulator kernel will synchronously update the binary logic data block and the exception mask data block in the underlying dual-block storage structure, and at the same time fully trigger the simulation event scheduling mechanism to complete simulation behaviors such as signal level propagation, timing update, and driver conflict detection. There will be no simulation logic disorder caused by directly rewriting memory, ensuring that the four-state simulation semantics fully comply with industry standard requirements.

[0075] The access logic corresponding to step S7 serves as a fallback compatibility solution, relying entirely on the Verilog program interface to complete data interaction. It cannot bypass the interface layer to directly manipulate the native memory of the logic simulator. While this method is highly versatile, each access incurs overhead from multiple function calls, data copying, and format conversion. This can lead to significant simulation performance degradation in large-scale, high-frequency sampling scenarios. The hybrid access channel provided in step S6 of this invention avoids the format conversion overhead of read operations through a read-write separation mechanism, thereby balancing cross-logic simulator compatibility and simulation performance.

[0076] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0077] This invention achieves adaptive access path selection by dynamically detecting whether the logic simulator provides a memory address acquisition extension interface at runtime. Only when the memory address acquisition extension interface exists and returns a valid physical memory address is the read operation switched to a direct memory access operation; otherwise, it automatically falls back to the Verilog program interface. This allows the same verification code to maintain both high performance and compatibility in different logic simulator environments without modification. Simultaneously, a read-write separation strategy is adopted, where read operations directly connect to memory while write operations maintain the Verilog program interface. This bypasses the Verilog program interface call chain to eliminate read operation performance bottlenecks while ensuring that write operations are still processed through the logic simulator's event scheduling mechanism, fully maintaining the correctness of signal propagation semantics. Furthermore, the aforementioned path detection and switching are performed only once during the signal initialization phase, without adding any additional runtime judgment overhead to subsequent signal accesses.

[0078] This invention also provides an electronic device, such as... Figure 2 As shown, it includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the embodiments of the present invention.

[0079] For example, the electronic device may be a mobile electronic device or a non-mobile electronic device. Further, a mobile electronic device may be any one of a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA); a non-mobile electronic device includes any one of a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine.

[0080] This invention also provides a computer-readable storage medium, such as... Figure 3 As shown, computer-executable instructions are stored thereon, which are used to execute the methods described in the embodiments of the present invention.

[0081] Examples of computer-readable storage media include: computer read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), compact disc read-only memory (CD-ROM), flash memory, magnetic disk, optical disk, portable computer disk, hard disk and / or solid-state drive, etc.

[0082] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for mixed access to signals inside a logic simulator, characterized in that, include: Step S1: Obtain the handle of the signal to be accessed in the logic simulator; Step S2: Based on the handle of the signal to be accessed, create a data encapsulation body containing read operation signals and write operation functions for the signal to be accessed through the Verilog program interface, and establish a Verilog program interface access channel. Step S3: Dynamically detect whether the logic simulator provides an extended interface for obtaining memory addresses during runtime. If yes, proceed to step S4; otherwise, proceed to step S7. Step S4: Call the memory address acquisition extension interface to obtain the physical memory address of the signal to be accessed, and determine whether the physical memory address of the signal to be accessed is valid. If it is valid, proceed to step S5; otherwise, proceed to step S7. Step S5: Replace the read operation function in the data encapsulation body with the direct memory access operation function based on the physical memory address, and keep the write operation function executed through the Verilog program interface to establish a hybrid access channel and execute step S6. Step S6: Access the signal to be accessed based on the hybrid access channel, and end the process; Step S7: Access the signal to be accessed based on the Verilog program interface access channel, and end the process.

2. The method according to claim 1, characterized in that, The logic simulator uses a dual-block storage structure to store the logic data of all signals. The logic data of each signal is divided into a binary logic value vector and an anomaly mask bit vector. The binary logic value vector is used to store the standard logic levels of the signal (0, 1). The anomaly mask bit vector is used to mark the unknown or high-impedance abnormal states of the signal. The dual-block storage structure includes binary logic data blocks and anomaly mask data blocks. The binary logic data blocks are used to store the binary logic value vectors, and the anomaly mask data blocks are used to store the anomaly mask bit vectors. The binary logic data blocks are located at the starting address of the storage structure, and the anomaly mask data blocks are arranged continuously after the binary logic data blocks.

3. The method according to claim 2, characterized in that, For different types and bit widths of signals, appropriate sub-storage structures are set up, and all sub-storage structures follow the described dual-block storage layout: Signals with a bit width of no more than 64 bits adopt a union substructure, and the binary logic value fields of all substructures in the union are located at the position where the structure offset is 0. Wide vector signals with a bit width exceeding 64 bits are split into multiple standard word units for storage, and the binary logic values ​​corresponding to all word units are arranged in a continuous manner. The binary logic values ​​of all array elements of an unpacked array signal are arranged consecutively according to their array index order.

4. The method according to claim 2, characterized in that, Step S2 includes: Step S21: Based on the handle of the signal to be accessed, read the signal value of the signal to be accessed and convert it into a form in which binary logic value and exception mask are stored alternately; Step S22: Based on the handle of the signal to be accessed, create a data encapsulation containing read operation signals and write operation functions through the Verilog program interface, and establish a Verilog program interface access channel.

5. The method according to claim 3, characterized in that, Step S6 includes: Step S61: If a read operation needs to be performed on the access signal, then proceed to step S62; if a write operation needs to be performed on the access signal, then proceed to step S63. Step S62: Call the direct memory access operation function in the data encapsulation body to perform a read operation on the signal to be accessed, and end the process; Step S63: Call the write operation function in the data encapsulation body to perform a write operation on the access signal and end the process.

6. The method according to claim 5, characterized in that, Step S62 includes: Step S621: Call the direct memory access operation function in the data encapsulation body to obtain the starting address of the binary value data block corresponding to the signal to be accessed as the physical memory address of the signal to be accessed; Step S622: Read the signal value of the signal to be accessed from the binary logic data block corresponding to the signal to be accessed based on the physical memory address of the signal to be accessed, and end the process.

7. The method according to claim 6, characterized in that, In step S622, reading the signal value of the signal to be accessed from the binary logic data block corresponding to the signal to be accessed based on the physical memory address of the signal to be accessed includes: Based on the memory read method corresponding to the signal bit width adaptation, all read operations directly read the binary logical data block based on the physical memory address of the signal to be accessed: If the signal to be accessed is a unit scalar signal, then a single byte of complete logical value is read at a time. If the signal width to be accessed is 1 to 8 bits, then read the binary logic value in a single byte. If the signal width to be accessed is 9 to 16 bits, then read the binary logic value in two bytes. If the signal width to be accessed is 17 to 32 bits, then read the binary logic value in four bytes. If the signal width to be accessed is 33 to 64 bits, then read 32 bits of data in two separate steps and concatenate them to obtain the complete signal value; If the signal to be accessed is a wide vector with a bit width greater than 64 bits, then iterate through the data and read 32-bit binary logic data in batches.

8. The method according to claim 1, characterized in that, Step S7 includes: Step S71: If a read operation needs to be performed on the access signal, then proceed to step S72; if a write operation needs to be performed on the access signal, then proceed to step S73. Step S72: Call the read operation function in the data encapsulation body to perform a read operation on the access signal, and end the process; Step S73: Call the write operation function in the data encapsulation body to perform a write operation on the access signal and end the process.

9. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions that are executed by the at least one processor, the instructions being configured to perform the method as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method as described in any one of claims 1-8.

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