System and method for implementing jtag communication without ir decoding

Abstract

The present application relates to the field of integrated circuit test and embedded chip debugging technology, and particularly relates to a JTAG communication implementation method without IR decoding, comprising the following steps: S1, receiving a reset signal to make a JTAG state machine enter a Test-Logic-Reset state; S2, detecting a TMS pin level in the Test-Logic-Reset state, if the TMS pin level is low, jumping to a Run-Test / Idle state, otherwise maintaining the current state; S3, counting a TCK clock rising edge in the Run-Test / Idle state, the count value is recorded as C, and jumping to a SelectDR-Scan state when the TMS is high; S4, in the SelectDR-Scan state, if the TMS is high, returning to the Test-Logic-Reset, if the TMS is low, entering a Capture-DR state. The present application discards all IR related states in the standard JTAG protocol, simplifies the original 16 state machine into 9 effective states containing only the DR path, and does not need to perform scanning and decoding operations of the instruction register in the communication process, directly determines the access target by counting the TCK clock, which removes the IR decoding circuit on the one hand, and saves multiple IR state periods in the traditional JTAG on the other hand.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing and embedded chip debugging technology, and in particular to a JTAG communication implementation system and method that does not require IR decoding. Background Technology

[0002] JTAG, based on the IEEE 1149.1 standard, is a universal bus protocol for integrated circuit chip testing, embedded system debugging, and in-circuit programming. It relies on boundary scan technology to achieve non-intrusive measurement and control of chip pins and is widely used in chip development and mass production testing scenarios such as SoC, FPGA, and MCU.

[0003] The standard JTAG protocol is configured with five interfaces: TCK, TMS, TDI, TDO, and TRST, and is equipped with a complete state machine containing 16 states. Communication requires two independent stages: instruction register (IR) scanning and data register (DR) scanning. During interaction, debugging instructions are first written through IR scanning, and after hardware decoding, the system switches to DR scanning to transmit service data. The two sets of state transition logics, IR and DR, are independent of each other and executed sequentially.

[0004] Traditional JTAG communication relies on IR decoding to distinguish debugging functions. When changing instructions, the emulator needs to initiate an IR scan separately, and the hardware needs to add a dedicated decoding circuit to match the corresponding data path. The 16-state complete state machine has many jump branches and logic redundancy. IR shifting and decoding judgment consume a lot of TCK clocks, resulting in large hardware resource overhead of the chip JTAG controller, cumbersome host computer interaction process, and low bus transmission efficiency.

[0005] The existing standard JTAG suffers from drawbacks such as complex state machine logic and the need for communication to rely on IR scanning and decoding processes. This results in high hardware implementation costs, large interaction latency, and low communication efficiency. There is an urgent need to provide a JTAG communication scheme that can avoid IR decoding and simplify state machine logic. Summary of the Invention

[0006] The purpose of this invention is to address the aforementioned shortcomings in the prior art by proposing a JTAG communication implementation system and method that does not require IR decoding.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: a JTAG communication implementation method without IR decoding, comprising the following steps: S1. Receive a reset signal to cause the JTAG state machine to enter the Test-Logic-Reset state; S2. In Test-Logic-Reset state, detect the TMS pin level. If it is low, jump to Run-Test / Idle state; otherwise, maintain the current state. S3. In Run-Test / Idle state, count the rising edge of TCK clock, record the count value as C, and jump to SelectDR-Scan state when TMS is high. S4. In SelectDR-Scan state, if TMS is high, return to Test-Logic-Reset; if it is low, enter Capture-DR state. S5. In Capture-DR state, select the target register from the DR register group according to the count value C, and store the data to be transferred to the outside into the captured register; S6. In Shift-DR state, data is serially input through the TDI pin, the target DR register is shifted right bit by bit, and the shifted-out data is output through the TDO pin; S7. The shift is paused or jumped through the Exit1-DR, Pause-DR, and Exit2-DR states, and finally enters the Update-DR state. S8. In Update-DR state, update the corresponding DR register data to the boundary scan register or synchronization FIFO according to the count value C, and clear the counter to zero, i.e., C=0; The method skips all IR-related states during the entire communication process and does not perform any instruction decoding operations.

[0008] Preferably, the reset signal is a low-level active signal of the TRST pin, or a combination signal of four consecutive rising edges of TCK and a high level of TMS.

[0009] Preferably, the JTAG state machine contains only the following 9 states: Test-Logic-Reset, Run-Test / Idle, SelectDR-Scan, Capture-DR, Shift-DR, Exit1-DR, Pause-DR, Exit2-DR, and Update-DR; It does not include SelectIR-Scan, Capture-IR, Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, or Update-IR states.

[0010] Preferably, the counter described in step S3 only increments on each rising edge of TCK when the Run-Test / Idle state is in which TMS is low, i.e., C=C+1. When the state machine leaves this state, the count value C remains unchanged until it is cleared after entering the Update-DR state.

[0011] Preferably, the selection method of the target DR register in step S5 is as follows: the count value C is used as the address pointer to directly address the corresponding register in the DR register group, and the address mapping relationship is a predefined fixed mapping table.

[0012] Preferably, the number of shifts in the right shift operation in step S6 is equal to the corresponding bit width of the DR register, with one shift occurring on each rising edge of TCK. The data sequence output by TDO is a bit stream of the original least significant bit shifted out of the DR register sequentially. The shift logic is expressed as follows: ; Where w is the bit width of the DR register. This is the least significant bit of the DR register before the shift.

[0013] A JTAG communication system that does not require IR decoding includes: a JTAG physical interface, which includes at least TCK, TMS, TDI, TDO and TRST pins; A state machine control unit is used to execute the state transition logic as described in claim 1, and its state machine does not contain any IR-related states; The counter unit is used to count the rising edge of TCK in Run-Test / Idle state and output the count value C. The DR register group contains multiple data registers, which are addressed by the count value C. The data capture unit is used to write TDI or internal data to the selected DR register in Capture-DR state; The data update unit is used to output the contents of the selected DR register to the boundary scan register or the synchronization FIFO in Update-DR state; The shift control unit is used to control the selected DR register to shift right bit by bit in Shift-DR state and output the shifted-out data through TDO.

[0014] Preferably, the maximum count value M of the counter unit is a preset fixed value. When C > M, the state machine control unit automatically generates a reset signal, causing the state machine to jump to the Test-Logic-Reset state.

[0015] Preferably, each register in the DR register group has a unique number, which corresponds one-to-one with the count value C. The addressing logic is implemented using a combinational logic decoder, and the decoding output satisfies: ; If and only if ; Where N is the total number of DR registers, This is the chip select signal for the i-th register.

[0016] Preferably, the system does not include an instruction register and its decoding circuit. Data communication relies entirely on the count value C and the current state machine state to complete the control, without the need to execute an IR scan process.

[0017] The design scheme proposed in this invention has the following beneficial effects during application: 1. This invention eliminates all IR-related states in the standard JTAG protocol, simplifying the original 16-state machine to only 9 valid states containing the DR path. During communication, there is no need to perform instruction register scanning and decoding operations. The access target is determined directly by counting the TCK clock. This eliminates the IR decoding circuit, reducing chip area and power consumption. On the other hand, it saves multiple IR state cycles in traditional JTAG, significantly reducing the number of clock cycles required for a single data interaction and improving communication efficiency. 2. This invention uses the TCK clock count value directly as the access address of the DR register, eliminating the need for instruction encoding and decoding. The emulator only needs to stay in the Run-Test / Idle state for the required number of clock cycles to specify the target register. At the same time, this count value also determines the data transmission length during the shift stage. This design unifies address specification, length control, and data shifting into the same count value, simplifying the emulator's sending logic. The chip also does not need to maintain an additional instruction register, making communication more direct and efficient. 3. After each DR scan is completed, the present invention does not need to return to any IR state. It can stay in the Run-Test / Idle state or directly enter the next DR scan. The counter is automatically cleared to zero in each Update-DR state. The next round of communication starts counting from zero. The state machine can continuously execute multiple data reads and writes without resetting. For scenarios of batch transmission of debugging information or storage data, it avoids the overhead of repeated IR switching and state reset between each data in traditional JTAG, and ensures the smoothness of batch communication. Attached Figure Description

[0018] Figure 1 This is the JTAG state machine of the present invention; In the diagram: Test-Logic-Reset resets the test logic; Run-Test / Idle runs the test / idles; SelectDR-Scan selects the data register; Capture-DR captures the data register; Shift-DR shifts the data register; Exit1-DR exits the 1st data register; Pause-DR pauses the data register; Exit2-DR exits the 2nd data register; Update-DR updates the data register; SelectIR-Scan selects the instruction register; Capture-IR captures the instruction register; Shift-IR shifts the instruction register; Exit1-IR exits the 1st instruction register; Pause-IR pauses the instruction register; Exit2-IR exits the 2nd instruction register; Update-IR updates the instruction register. The states within the dashed boxes are those reserved by this invention, while those outside the dashed boxes are those discarded by this invention. Furthermore, in this invention, the SelectDR-Scan state will directly enter the Test-Logic-Reset state when TMS is 1 detected on the rising edge of TCK. Figure 2 This is a schematic diagram of the process of selecting the DR register in this invention; In the diagram: TCK rising edge count; Run-Test / Idle state; Write operation; Counter register; Value; Enable signal; Shift-DR state; TDI test data input port; Counter 1 equals 1; IDCODE chip identifier register; Counter 2 equals 2; BSR boundary scan register; Counter 3 equals 3; BYPASS bypass register; Counter 4 equals 4; Private instruction 1; Custom instruction 1; Counter m equals m; Private instruction n; Custom instruction n; Counter value; TDO test data output port. Detailed Implementation

[0019] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0020] Example 1 Reference Figures 1-2 A method for implementing JTAG communication without IR decoding includes the following steps: S1. Receive a reset signal to cause the JTAG state machine to enter the Test-Logic-Reset state; S2. In Test-Logic-Reset state, detect the TMS pin level. If it is low, jump to Run-Test / Idle state; otherwise, maintain the current state. S3. In Run-Test / Idle state, count the rising edge of TCK clock, record the count value as C, and jump to SelectDR-Scan state when TMS is high. S4. In SelectDR-Scan state, if TMS is high, return to Test-Logic-Reset; if it is low, enter Capture-DR state. S5. In Capture-DR state, select the target register from the DR register group according to the count value C, and store the data to be transferred to the outside into the captured register; S6. In Shift-DR state, data is serially input through the TDI pin, the target DR register is shifted right bit by bit, and the shifted-out data is output through the TDO pin; S7. The shift is paused or jumped through the Exit1-DR, Pause-DR, and Exit2-DR states, and finally enters the Update-DR state. S8. In Update-DR state, update the corresponding DR register data to the boundary scan register or synchronization FIFO according to the count value C, and clear the counter to zero, i.e., C=0; The method skips all IR-related states during the entire communication process and does not perform any instruction decoding operations.

[0021] Furthermore, the reset signal is either a low-level active signal on the TRST pin, or a combination of four consecutive rising edges of TCK and a high level on TMS.

[0022] Furthermore, the JTAG state machine contains only the following 9 states: Test-Logic-Reset, Run-Test / Idle, SelectDR-Scan, Capture-DR, Shift-DR, Exit1-DR, Pause-DR, Exit2-DR, and Update-DR; It does not include SelectIR-Scan, Capture-IR, Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, or Update-IR states.

[0023] Furthermore, in step S3, the counter only increments on each rising edge of TCK when the Run-Test / Idle state is in which TMS is low, i.e., C=C+1. When the state machine leaves this state, the count value C remains unchanged until it is cleared after entering the Update-DR state.

[0024] Furthermore, in step S5, the target DR register is selected by using the count value C as an address pointer to directly address the corresponding register in the DR register group, and the address mapping relationship is a predefined fixed mapping table.

[0025] Furthermore, in step S6, the number of shifts in the right shift operation is equal to the corresponding bit width of the DR register. The shift occurs once on each rising edge of TCK, and the data sequence output by TDO is a bit stream where the least significant bit of the original DR register is shifted out sequentially. The shift logic is represented as follows: ; Where w is the bit width of the DR register. This is the least significant bit of the DR register before the shift.

[0026] A JTAG communication system that does not require IR decoding includes: a JTAG physical interface, which includes at least TCK, TMS, TDI, TDO and TRST pins; A state machine control unit is used to execute the state transition logic as claimed in claim 1, and its state machine does not contain any IR-related states; The counter unit is used to count the rising edge of TCK in Run-Test / Idle state and output the count value C. The DR register group contains multiple data registers, which are addressed by the count value C. The data capture unit is used to write TDI or internal data to the selected DR register in Capture-DR state; The data update unit is used to output the contents of the selected DR register to the boundary scan register or the synchronization FIFO in Update-DR state; The shift control unit is used to control the selected DR register to shift right bit by bit in Shift-DR state and output the shifted-out data through TDO.

[0027] Furthermore, the maximum count value M of the counter unit is a preset fixed value. When C > M, the state machine control unit automatically generates a reset signal, causing the state machine to jump to the Test-Logic-Reset state.

[0028] Furthermore, each register in the DR register group has a unique number, which corresponds one-to-one with the count value C. The addressing logic is implemented using a combinational logic decoder, and the decoding output satisfies: ; If and only if ; Where N is the total number of DR registers, This is the chip select signal for the i-th register.

[0029] Furthermore, the system does not include an instruction register and its decoding circuit; data communication relies entirely on the count value C and the current state machine state to complete the control, without the need to execute an IR scan process.

[0030] Example 2 This embodiment provides a complete JTAG data communication process, as follows: Step 1: Reset and Initialization. The simulator initiates a reset in one of the following two ways: Method A: Pull the TRST pin low and hold it for at least 5 TCK cycles, and the JTAG state machine will directly enter the Test-Logic-Reset state; Method B: Apply four consecutive rising edges of TCK, and the TMS pin is high at each rising edge. The state machine will also enter the Test-Logic-Reset state. In Test-Logic-Reset state, all DR registers are asynchronously reset to their default values, all 0s or all 1s, depending on the specific chip design, and counter C is cleared to zero; Step 2: Enter Run-Test / Idle and start counting. When TMS is low on the next rising edge of TCK, the state machine jumps to the Run-Test / Idle state. In this state: If TMS remains low, the state machine remains in Run-Test / Idle and executes C=C+1 on each rising edge of TCK; In this embodiment, the simulator expects to transmit 8 bits of data, so it stays in the Run-Test / Idle state for 8 TCK cycles, making C=8; Step 3: Enter the DR scan path. When TMS is high on the next rising edge of TCK, the state machine jumps from Run-Test / Idle to SelectDR-Scan. Then TMS is pulled low, and the state machine enters Capture-DR. Step 4: Data capture. In Capture-DR state, the JTAG controller selects register number 8 from the DR register group based on the current count value C=8. This register contains response data to be sent to the emulator, such as chip ID or debug status word. The data is captured into the register's internal latch. Step 5: Data shift output, the state machine enters the Shift-DR state, and the simulator continuously drives C=8 clock cycles through TCK. In each cycle: The DR register is shifted one bit to the right. The least significant bit shifted out is output to the simulator via the TDO pin; New data input to the TDI pin is shifted into the most significant bit; The entire DR bit width has been transmitted via TDO; Step Six: State Transition and Update. The simulator pulls TMS high, and the state machine transitions from Shift-DR to Exit1-DR, then to Update-DR. In the Update-DR state: If this communication is a read operation, the data in the DR register will be updated in the boundary scan register or debug register; Counter C is cleared to prepare for the next communication; This concludes a complete JTAG communication session. No IR-related states were encountered during the entire process, therefore no instruction decoding was required.

[0031] Example 3 In this embodiment, the JTAG state machine is simplified to 9 states, and its transition logic is shown in the table below: The linkage mechanism between the counter and the state machine: The counting operation only occurs in the Run-Test / Idle state and when TMS is low, which ensures that the counting window is controllable and will not miscount the TCK clock in other states; Once the count value C is generated, it will be passed along with the state machine all the way to the Update-DR state. Intermediate states, such as Shift-DR and Pause-DR, do not change the value of C. In Update-DR state, the counter is cleared to ensure that the next communication starts counting from zero. If the count value C exceeds the preset maximum count value M (M=256 in this embodiment, corresponding to a maximum of 256 bits of data transmission), the state machine automatically generates an internal reset signal and jumps back to the Test-Logic-Reset state to prevent addressing errors caused by counter overflow. Timeout protection mechanism: In this embodiment, the maximum count value M and the TCK clock frequency and the system's maximum allowed communication timeout Relatedly, this embodiment sets , ,but: In the actual design, M is set to 1024. When C exceeds 1024, a reset is triggered to avoid communication hang-up.

[0032] Example 4 DR register group structure: In this embodiment, the DR register group contains N=16 registers, numbered from 0 to 15, each register having a bit width w=32 bits. The purpose of each register is allocated as follows: Addressing methods: In Capture-DR and Update-DR states, the count value C is directly fed into the combinational logic decoder as an address pointer. The decoder's input is C, and its output is a 16-bit chip select signal. to ,satisfy: If and only if ; The decoder is implemented using pure combinational logic with a delay of less than 2ns, ensuring that addressing is completed within the time window established after the rising edge of TCK. Data capture and update process: The simulator counts C=8 in Run-Test / Idle mode, and the target is the write data FIFO interface; When the state machine enters Capture-DR, the decoder selects register 8, but capture is not performed at this time, and write operations do not require data capture from JTAG; When the state machine enters Shift-DR, the simulator serially writes 32-bit data via TDI, shifting DR register 8 one bit to the right after each bit is written. After all 32 bits of data are written, the state machine enters Update-DR. At this time, the 32 bits of data in register 8 are updated in parallel to the write data FIFO, and the FIFO write pointer is incremented by 1. Reset counter C to zero.

[0033] Taking a single read operation as an example: The simulator counter C=1, the target is the debug status register; When entering Capture-DR, the decoder selects register 1, and the current value of register 1, such as the 32-bit debug state, is captured in parallel into the shift latch; Entering Shift-DR, the shift latch shifts out one by one over 32 TCK cycles and returns to the simulator via TDO; Upon entering Update-DR, counter C is cleared, while the contents of register 1 remain unchanged.

[0034] In this embodiment, the mapping relationship between register number and count value C is a fixed mapping table, which is burned into the chip's ROM during the production stage and cannot be changed, ensuring the protocol consistency between the emulator and the chip.

[0035] Example 5 System hardware architecture: This system includes the following hardware modules: JTAG physical interface: includes 5 standard pins: TCK (clock input), TMS (mode select), TDI (data input), TDO (data output), and TRST (reset input, optional). All signal levels are compatible with 3.3V or 1.8V LVCMOS standards. Clock Management Unit: Receives external TCK clock, performs edge detection on it, and generates rising and falling edge pulse signals for use by the state machine, counter, and shift logic. The maximum operating frequency of TCK is 20MHz. State machine control unit: consists of 9 state registers, 4-bit encoding. The system consists of a coding space with 99 valid and 7 invalid codes, and a combinational logic jump network. The state coding is as follows: Invalid codes (1001-1111) are constrained to return Test-Logic-Reset to prevent the state machine from locking up; Counter unit: 10-bit binary incrementing counter, maximum count value M=1024. In Run-Test / Idle state and when TMS is low, C=C+1 is executed on each rising edge of TCK, and the count value C[9:0] is output. DR register set: 16 32-bit registers, implemented using a register file structure, with dual ports (one write port and one read port) or single port (time division multiplexing). Decoder unit: Combinational logic decoder, which decodes the lower 4 bits (C[3:0]) of C[9:0] into a 16-bit chip select signal, and the higher 6 bits are used for out-of-bounds detection (a warning signal is generated when C is 16, but it can still work when C is greater than 15 in this system, and is only used for FIFO registers). Data capture and update unit: includes a parallel load latch and a parallel output driver. In Capture-DR state, it loads data from the DR register and in Update-DR state, it outputs the latch data to the target memory or FIFO. Shift control unit: Includes a 32-bit shift register, supports right shift operation, and performs a right shift once per rising edge of TCK in Shift-DR state; Example of working sequence: The following example uses 8-bit data reading to illustrate the timing of key signals: TRST is pulled low for 5 TCK cycles, resetting the state machine to Test-Logic-Reset; When TMS is pulled low, the state machine enters Run-Test / Idle, and the counter starts counting. For eight consecutive TCK cycles, TMS remains low, and the counter increments from 0 to 8. When TMS goes high, the state machine enters SelectDR-Scan. When TMS is pulled low, the state machine enters Capture-DR, the decoder selects register 8, and data is captured in parallel. When TMS is pulled low, the state machine enters Shift-DR. : 8 consecutive TCK cycles, 8 bits of data are serially output through TDO; When TMS goes high, the state machine enters Exit1-DR; When TMS goes high, the state machine enters Update-DR, data is updated to FIFO, and the counter is cleared. When TMS goes low, the state machine returns to Run-Test / Idle, preparing for the next communication; Verification of the beneficial effects of this system: Compared to traditional JTAG, this system omits the IR scan phase. Traditional JTAG requires entering seven IR-related states sequentially: SelectIR-Scan, Capture-IR, Shift-IR, Exit1-IR, and Update-IR. Taking reading 8 bits of data as an example, traditional JTAG requires approximately 5 (reset) + 8 (IR count) + 6 (IR state transition) + 8 (DR count) + 6 (DR state transition) = 33 TCK cycles, while this system only requires 5 (reset) + 8 (count) + 6 (DR state transition) = 19 TCK cycles, improving communication efficiency by approximately 42%. For debugging scenarios with frequent data transmission, the efficiency improvement is even more significant.

[0036] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for implementing JTAG communication without IR decoding, characterized in that, Includes the following steps: S1. Receive a reset signal to cause the JTAG state machine to enter the Test-Logic-Reset state; S2. In Test-Logic-Reset state, detect the TMS pin level. If it is low, jump to Run-Test / Idle state; otherwise, maintain the current state. S3. In Run-Test / Idle state, count the rising edge of TCK clock, record the count value as C, and jump to SelectDR-Scan state when TMS is high. S4. In SelectDR-Scan state, if TMS is high, return to Test-Logic-Reset; if it is low, enter Capture-DR state. S5. In Capture-DR state, select the target register from the DR register group according to the count value C, and store the data to be transferred to the outside into the captured register; S6. In Shift-DR state, data is serially input through the TDI pin, the target DR register is shifted right bit by bit, and the shifted-out data is output through the TDO pin; S7. The shift is paused or jumped through the Exit1-DR, Pause-DR, and Exit2-DR states, and finally enters the Update-DR state. S8. In Update-DR state, update the corresponding DR register data to the boundary scan register or synchronization FIFO according to the count value C, and clear the counter to zero, i.e., C=0; The method skips all IR-related states during the entire communication process and does not perform any instruction decoding operations.

2. The JTAG communication implementation method without IR decoding according to claim 1, characterized in that: The reset signal is a low-level active signal on the TRST pin, or a combination signal consisting of four consecutive rising edges of TCK and a high level of TMS.

3. The JTAG communication implementation method without IR decoding according to claim 1, characterized in that: The JTAG state machine contains only the following 9 states: Test-Logic-Reset, Run-Test / Idle, SelectDR-Scan, Capture-DR, Shift-DR, Exit1-DR, Pause-DR, Exit2-DR, and Update-DR. It does not include SelectIR-Scan, Capture-IR, Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, or Update-IR states.

4. The JTAG communication implementation method without IR decoding according to claim 1, characterized in that: The counter described in step S3 increments on each rising edge of TCK only when the Run-Test / Idle state is in which TMS is low, i.e., C=C+1. When the state machine leaves this state, the count value C remains unchanged until it is cleared after entering the Update-DR state.

5. The JTAG communication implementation method without IR decoding according to claim 1, characterized in that: The selection method for the target DR register in step S5 is as follows: the count value C is used as the address pointer to directly address the corresponding register in the DR register group, and the address mapping relationship is a predefined fixed mapping table.

6. The JTAG communication implementation method without IR decoding according to claim 1, characterized in that: The number of shifts in the right shift operation described in step S6 is equal to the corresponding bit width of the DR register. The shift occurs once on each rising edge of TCK. The data sequence output by TDO is a bit stream where the least significant bit of the original DR register is shifted out sequentially. The shift logic is expressed as follows: ； Where w is the bit width of the DR register. This is the least significant bit of the DR register before the shift.

7. A JTAG communication system that does not require IR decoding, characterized in that, include: The JTAG physical interface includes at least the TCK, TMS, TDI, TDO, and TRST pins; A state machine control unit is used to execute the state transition logic as described in claim 1, and its state machine does not contain any IR-related states; The counter unit is used to count the rising edge of TCK in the Run-Test / Idle state and output the count value C; The DR register group contains multiple data registers, which are addressed by the count value C. The data capture unit is used to write TDI or internal data to the selected DR register in Capture-DR state; The data update unit is used to output the contents of the selected DR register to the boundary scan register or the synchronization FIFO in Update-DR state; The shift control unit is used to control the selected DR register to shift right bit by bit in Shift-DR state and output the shifted-out data through TDO.

8. A JTAG communication system without IR decoding according to claim 7, characterized in that: The maximum count value M of the counter unit is a preset fixed value. When C > M, the state machine control unit automatically generates a reset signal, causing the state machine to jump to the Test-Logic-Reset state.

9. A JTAG communication system without IR decoding according to claim 7, characterized in that: Each register in the DR register group has a unique number, which corresponds one-to-one with the count value C. The addressing logic is implemented using a combinational logic decoder, and the decoding output satisfies: ； If and only if ; Where N is the total number of DR registers, This is the chip select signal for the i-th register.

10. A JTAG communication system without IR decoding according to claim 7, characterized in that: The system does not contain an instruction register or its decoding circuit. Data communication relies entirely on the count value C and the current state machine state to complete the control, without the need to perform an IR scan process.

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