Data transmission method and system based on virtual channel

Abstract

The application provides a data transmission method and system based on a virtual channel. The method comprises: obtaining transaction data for cross-chip transmission; classifying the transaction data according to the service type and / or data field attribute of the transaction data and assigning a corresponding virtual channel; encapsulating the corresponding transaction data based on the virtual channel to generate a data transmission unit carrying virtual channel identification information and sending the data transmission unit to a receiving end; the receiving end stores the data transmission units of different virtual channels in corresponding logical cache areas according to the virtual channel identification information and monitors cache state parameters; when a target virtual channel meets a preset flow control condition, generating flow control information and feeding back to the sending end, so that the sending end only adjusts the data transmission state of the target virtual channel while maintaining the data transmission of other virtual channels. The application effectively realizes the isolated transmission and accurate flow control of cross-chip transaction data in the multi-GPU chip interconnection scene, and improves the data transmission efficiency and stability between chips.

Description

Technical Field

[0001] This invention relates to the field of chip interconnect technology, and more specifically, to a data transmission method and system based on virtual channels. Background Technology With the development of artificial intelligence, massively parallel computing, and high-performance computing technologies, the computing power of a single chip is gradually becoming insufficient to meet the demands of complex computing tasks. To further improve computing performance, multiple processing chips typically work together through chip-to-chip (C2C) interconnect technology to achieve data exchange and resource sharing between different chips. In multi-GPU, multi-accelerator chip, and heterogeneous computing systems, the chip-to-chip interconnect links bear a large amount of data transmission related to computing tasks, and their transmission efficiency and stability directly affect the performance of the entire computing system.

[0002] Existing chip-to-chip interconnect systems typically include adapters located between the internal interfaces of computing chips and the physical interconnect links. These adapters perform functions such as data protocol conversion, data encapsulation, link transmission, and data parsing at the receiving end. Taking a multi-GPU chip collaborative computing scenario as an example, GPU chips generate a large number of cross-chip access transactions during the execution of computing tasks, including different types of data such as data read requests, read responses, data write requests, and write responses. Existing technologies typically use a unified data transmission channel to encapsulate and transmit these different types of data. That is, data of different service types are combined into data transmission units according to a preset format and sent to the target chip through a shared physical link.

[0003] like Figure 1 As shown, the typical data encapsulation process in the prior art is as follows: After data from different service channels (including write address channel AW, write data channel W, read address channel AR, read data channel R, and response channel B, etc.) enter the adaptation module, the arbitrator (ARB) selects data DA1 sequentially according to the preset scheduling strategy and sends it into each data slot inside the packer. The selected channel data DA1 is encapsulated to form a data transmission unit (Flit) containing mixed service type data. Data from different channels such as W, R, and AW are mixed and arranged in the same Flit and sent to the peer chip through a unified physical data path.

[0004] In the aforementioned transmission methods, since different types of data share the same data path and scheduling resources, a sudden surge in traffic or transmission congestion in one type of data can easily consume a large amount of link resources, thereby affecting the transmission efficiency of other types of data. Furthermore, existing inter-chip interconnect systems typically employ an overall flow control mechanism. When the receiving end's buffer resources are insufficient or the link becomes congested, it is often necessary to restrict the entire transmission link, affecting even data that is not congested, leading to reduced link utilization and increased data transmission latency.

[0005] Furthermore, existing data caching management methods typically allocate storage resources based on fixed data types or business modules, with different data types corresponding to fixed cache spaces. However, in actual operation, the proportion of data traffic generated by different computing tasks may change dynamically. Fixed allocation methods are difficult to adapt to different business load requirements, easily leading to problems such as insufficient cache space in some areas triggering frequent traffic limits, or some cache space remaining idle for extended periods, resulting in low storage resource utilization.

[0006] Therefore, existing chip interconnect systems still suffer from problems such as mutual interference in data transmission, coarse-grained congestion control, and insufficient utilization of cache resources in multi-service concurrent transmission scenarios, making it difficult to meet the requirements of high throughput, low latency, and stable data interaction in high-performance computing systems. Summary of the Invention

[0007] To address the problems of data interference, coarse-grained congestion control, and insufficient cache resource utilization caused by the sharing of transmission channels for different types of transaction data in existing chip interconnection systems, this invention provides a data transmission method based on virtual channels.

[0008] This invention identifies and classifies transaction data transmitted across chips by service type and / or data field attributes, and allocates corresponding virtual channels to transaction data of different service types and / or data field attributes based on the classification results. This allows different types of transaction data to be logically transmitted through different virtual channels. Furthermore, the transaction data is encapsulated based on its assigned virtual channel to generate a data transmission unit carrying virtual channel identification information. This enables the receiving end to identify data of different service types and / or data field attributes based on the virtual channel identification information, avoiding the mutual interference of data transmission caused by the mixed encapsulation of different types of transaction data in existing technologies.

[0009] Furthermore, at the receiving end, based on the virtual channel identification information carried by the data transmission unit, the present invention caches the data transmission units of different virtual channels into corresponding logical cache areas, and independently manages the data cache state corresponding to each virtual channel. When the data cache state of the target virtual channel meets the preset flow control conditions, flow control information is generated only for that target virtual channel and fed back to the sending end, so that the sending end only adjusts the data transmission state of the target virtual channel, while maintaining the data transmission of other virtual channels. Through the above method, fine-grained flow control for virtual channels is achieved, avoiding the problem of all data transmission being restricted due to congestion of a single service in the existing overall backpressure mechanism.

[0010] In addition, the present invention adopts a cache management method of physical sharing and logical isolation. The logical cache areas corresponding to different virtual channels are divided based on the virtual channel identification information, and the corresponding data cache status parameters are maintained respectively. While ensuring independent management and accurate flow control of different business data, the utilization efficiency of cache resources is improved.

[0011] Through the above technical solutions, this invention achieves data isolation transmission by packaging data transmission units into multiple virtual transmission channels and dividing cross-chip data transmission into data transmission units. Combined with a virtual channel binding precise backpressure mechanism, hierarchical data priority scheduling, and a shared memory classification storage architecture, it realizes local link rate limiting in congested scenarios and normal passage of non-congested services. At the same time, it optimizes the utilization rate of hardware storage resources, reduces memory resource waste, effectively reduces cross-chip transmission latency, and improves the overall transmission bandwidth and operational stability of C2C interconnect links. It can adapt to application scenarios of large-scale collaborative computing power interaction of multiple GPU chips.

[0012] In a first aspect, the present invention provides a data transmission method based on a virtual channel, characterized in that the method includes: Acquire transaction data transferred across chips; The transaction data is classified according to its business type and / or data field attributes, and virtual channels are allocated to the transaction data based on the classification results. Based on the virtual channel, the corresponding transaction data is encapsulated to generate a data transmission unit carrying virtual channel identification information, and then sent to the receiving end. The receiving end caches the data transmission units of different virtual channels into the corresponding logical cache areas according to the virtual channel identification information. The receiving end monitors the cache status parameters of each of the logical cache areas. When the cache status parameters corresponding to the target virtual channel meet the preset flow control conditions, it generates flow control information carrying the target virtual channel identification information and feeds it back to the sending end. The data transmission status of the target virtual channel is adjusted according to the flow control information, while maintaining the data transmission of other virtual channels.

[0013] Secondly, the present invention also provides a data transmission system based on a virtual channel, characterized in that the system includes: a transmitting end and a receiving end, the transmitting end including a transmitting end adapter and an encapsulation module, and the receiving end including a receiving end adapter; The transmitting adapter is used to acquire transaction data transmitted across chips; The sending adapter is also used to classify the transaction data according to the service type and / or data field attributes of the transaction data, and to allocate virtual channels to the transaction data based on the classification results; The encapsulation module is used to encapsulate the corresponding transaction data based on the virtual channel, generate a data transmission unit carrying virtual channel identification information, and send it to the receiving adapter. The receiving adapter is used to cache the data transmission units of different virtual channels into corresponding logical cache areas according to the virtual channel identification information. The receiving adapter is used to monitor the cache status parameters of each logical cache area. When the cache status parameters corresponding to the target virtual channel meet the preset flow control conditions, it generates flow control information carrying the target virtual channel identification information and feeds it back to the sending adapter. The transmitting adapter is also used to adjust the data transmission status of the target virtual channel according to the flow control information, and to maintain the data transmission of other virtual channels.

[0014] The present invention provides a data transmission method and system based on virtual channels: First, this invention classifies transaction data across chips based on the service type and / or data field attributes, and assigns corresponding virtual channels to different types of transaction data. This allows different transaction data to be scheduled and transmitted in logically isolated transmission paths. Existing technologies often use a unified channel to transmit various types of GPU chip data in a mixed manner, lacking a classification and scheduling mechanism. This invention encapsulates cross-chip data into data transmission units at the hardware layer and divides independent virtual channels based on data type. Simultaneously, by carrying virtual channel identification information in the data transmission units, the receiving end can identify the data source of different virtual channels, enabling independent management of different transaction data. This avoids data interference caused by the mixed encapsulation and shared scheduling of different types of transaction data in existing technologies, improving the efficiency of inter-chip link resource utilization.

[0015] Secondly, this invention configures corresponding transmission priorities for different virtual channels. When multiple virtual channels simultaneously have data transmission units waiting to be sent, arbitration scheduling is performed according to priority, ensuring that data transmission units for high-real-time and high-importance GPU chips are transmitted first, adapting to the business scenarios requiring GPU chip computing power collaboration and high-speed interaction. Simultaneously, the receiving end maintains the data buffer state corresponding to each virtual channel and generates flow control information carrying corresponding identification information based on the buffer state of the target virtual channel. This allows the sending end to adjust the data transmission state of the congested target virtual channel only, while maintaining the continued transmission of other virtual channels. Thus, the traditional overall flow control for the entire link is refined into virtual channel-level control, effectively avoiding the problem of a single blockage causing a complete blockage due to localized congestion.

[0016] Third, this invention adopts a physically shared, logically isolated cache management approach. The logical cache areas corresponding to each virtual channel are divided within the same shared storage space based on the virtual channel identifier information, and corresponding data cache status parameters are maintained separately. This breaks away from the traditional dedicated memory partition storage model, employing a combination of global shared storage space and data classification storage management. It achieves ordered storage by data type while simultaneously enabling shared storage resources. While ensuring independent caching and flow control for different business data, it also allows for shared utilization of storage resources among multiple virtual channels. This avoids the problems of insufficient or idle cache in some areas caused by traditional fixed cache partitioning, improving the utilization efficiency of internal chip storage resources, reducing waste of GPU chip hardware storage resources, and lowering hardware design costs.

[0017] Fourth, this invention further considers the propagation delay that exists during the process of flow control information being fed back from the receiving end to the sending end. Based on the propagation delay time and the data transmission rate of the target virtual channel, it calculates the amount of data that may continue to arrive before flow control takes effect, and reserves buffer space for the target virtual channel based on the amount of data in transit to determine reasonable flow control triggering conditions, ensuring that data arriving before the flow control information takes effect can still be buffered. Simultaneously, by setting a hysteresis interval between the backpressure start threshold and the backpressure release threshold, frequent switching of flow control states is avoided, improving system operational stability.

[0018] Fifth, this invention feeds back flow control information through a control channel independent of the data channel, avoiding the impact of data channel congestion on flow control information transmission and improving response timeliness under congestion conditions. Simultaneously, flow control information is transmitted in reverse order along the data transmission unit path from the sending end to the receiving end, allowing each intermediate link to continue receiving data using its own storage space after receiving flow control information, until the current storage space is full before continuing to the next level. This fully utilizes the storage resources of each intermediate link along the data transmission path, avoiding idle storage space due to premature termination of transmission and improving overall hardware resource utilization efficiency. Furthermore, this invention supports configuring and adjusting the number of virtual channels, service types and / or the mapping relationship between data field attributes and virtual channels, encapsulation strategies, priorities, and flow control parameters through a software configuration interface according to actual application needs. It is applicable to various GPU chip interconnect topologies such as direct interconnect, switching node interconnect, multi-hop, mesh, and ring interconnects, exhibiting good scalability and adaptability.

[0019] In summary, this invention effectively solves the problems of mutual interference of business data, excessive congestion propagation range, insufficient utilization of cache resources, and limited adaptability to complex topologies in existing inter-chip interconnection systems by combining technologies such as virtual channel isolated transmission, priority scheduling, channel-level precise flow control, shared cache management, and adaptive flow control optimization. It improves the efficiency, stability, and scalability of cross-chip data transmission in multi-GPU chip collaborative computing scenarios. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a typical data encapsulation diagram in existing technology; Figure 2 This is a flowchart of a data transmission method based on a virtual channel provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the direct interconnect topology between two GPU chips provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a one-to-many topology provided in an embodiment of the present invention, in which multiple GPU chips are interconnected through a switching node; Figure 5 This is a schematic diagram of a mesh topology for direct connection of multiple GPU chips provided in an embodiment of the present invention; Figure 6This is a schematic diagram of the Flit format provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the basic information in the Flit packet header provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of multiple write request data (AW) splicing and encapsulation provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of multiple write response data (B) splicing and encapsulation provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the hardware implementation of the transmitting end encapsulation control logic provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the hardware implementation of the arbitration method for the data transmission unit at the transmitting end provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of the hardware structure of the shared storage space of the receiving end provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of the step-by-step back pressure provided in an embodiment of the present invention; Figure 14 This is a schematic diagram illustrating the configuration of the virtual channel backpressure start threshold and backpressure release threshold provided in an embodiment of the present invention. Detailed Implementation

[0022] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Invention Overview As mentioned above, this invention provides a data transmission method and system based on virtual channels, which effectively realizes the virtual channel isolation transmission and precise flow control of cross-chip transaction data in multi-GPU chip interconnection scenarios. It solves the problems of mutual interference of business data, coarse congestion control granularity, and insufficient utilization of cache resources in the prior art, and improves the transmission efficiency and stability of the chip interconnection system.

[0024] Exemplary methods Figure 2This is a flowchart of a data transmission method based on a virtual channel provided by an embodiment of the present invention. The method is applied to C2C interconnection transmission of multiple GPU chips, and its topology includes any of the following: a direct interconnection topology between two GPU chips (i.e., a one-to-one direct interconnection topology), a one-to-many topology where multiple GPU chips are interconnected through a switch node, and a multi-hop topology. The multi-hop topology includes, but is not limited to, mesh topology and torus topology. In the multi-hop topology, at least one intermediate GPU chip node exists on the data transmission path to forward transaction data. The present invention can significantly improve data transmission efficiency and alleviate congestion in scenarios involving large amounts of transaction data transmission. In the one-to-many topology, the maximum number of GPU chips is determined by the number of interfaces of the switch node.

[0025] Figure 3 This is a schematic diagram of a direct interconnect topology between two GPU chips. (Example:) Figure 3 As shown, GPU0 and GPU1 are directly connected via their respective adapter hardware modules (hereinafter referred to as "adapters"), forming a point-to-point C2C interconnect link. In this topology, transaction data is classified, allocated virtual channels, and encapsulated at the sending end Adapter, and then directly transmitted to the receiving end Adapter via the data channel (physical link). The receiving end Adapter performs data parsing, caching, and forwarding to the target GPU chip. This topology is suitable for large-scale data interaction scenarios between two GPU chips and is the basic application form of this invention.

[0026] Figure 4 This is a schematic diagram of a one-to-many topology where multiple GPU chips are interconnected via a switching node. (Example:) Figure 4 As shown, GPU0, GPU1, and GPU2 are each connected to the same switching node through their respective adapters. Transaction data is forwarded between the GPU chips via the switching node. In this topology, due to the one-to-many data transmission requirement, the sending end needs to encapsulate transaction data destined for the same virtual channel into the same data transmission unit. The switching node determines the data forwarding path based on the destination information (Dst ID) in the data transmission unit header and routes the data to the target GPU chip. This topology is suitable for scenarios where multiple GPU chip clusters interact with data through a switching network.

[0027] Figure 5 This is a schematic diagram of a mesh topology where multiple GPU chips are directly connected. (Example:) Figure 5As shown, four GPU chips are arranged in a 2×2 grid. Each GPU chip is directly connected to its adjacent GPU chips through its own adapter, forming a mesh-like direct-connect network structure. Data from each GPU chip can be forwarded to the target GPU chip through intermediate GPU chip nodes. In this topology, since data may take one or more hops to reach the target GPU chip, the sending end needs to concatenate transaction data destined for the same virtual channel into the same data transmission unit when encapsulating data. The intermediate GPU chip nodes determine the data forwarding path based on the destination information (Dst ID) in the data transmission unit packet header and route the transaction data to the target GPU chip. This topology can also be extended to a ring structure, that is, by connecting the edge GPU chips correspondingly on the basis of the mesh topology to form a closed loop, so as to further balance network traffic.

[0028] Through the above-mentioned multiple topologies, this invention can flexibly adapt to different GPU chip cluster sizes and application scenarios, and has good scalability and versatility, ensuring efficient classification, scheduling and transmission of cross-chip data under different topologies.

[0029] Furthermore, in this invention, the sending end and the receiving end are symmetrically deployed using the same protocol stack.

[0030] Symmetrical deployment refers to GPU chips at both ends of an interconnect link being configured with identical hardware modules and protocol processing logic, each including complete adapters, encapsulation modules, arbitration modules, etc., thus possessing equivalent data transmission and reception capabilities. Based on this, either end of the interconnect link can act as a sender, performing transaction data classification, virtual channel allocation, encapsulation, and transmission operations, or as a receiver, performing transaction data reception, buffering, and parsing operations. Data transmission direction supports bidirectional reversibility. Through this symmetrical deployment method, any two GPU chips can establish an equal C2C interconnect relationship without distinguishing between master and slave devices, simplifying the system configuration process and improving the versatility and scalability of the interconnect solution, enabling it to flexibly adapt to various topologies such as direct interconnection, switching node interconnection, and multi-hop networking.

[0031] The following is combined with Figure 2 The specific steps of the data transmission method based on virtual channels provided in the embodiments of the present invention will be described in detail.

[0032] This embodiment includes the following steps: S101: Obtain transaction data transferred across chips.

[0033] This step, as the starting point of the entire data transmission process, mainly refers to the sending end (Tx) obtaining the cross-chip transaction data to be sent to the peer GPU chip (i.e., the receiving end, Rx).

[0034] S102: Classify the transaction data according to its business type and / or data field attributes, and allocate virtual channels to the transaction data based on the classification results.

[0035] Specifically, the adapter flexibly categorizes the received data according to its data type and software configuration. The transaction data includes access-type transaction data and interaction-type transaction data.

[0036] The access-type transaction data refers to the transaction data generated by data read and write operations between GPU chips. Its business types include at least one of read requests, read responses, write requests, write data, and write responses. As another classification method, for the convenience of transmission channel planning and arbitration, the business types of the access-type transaction data can also be divided into request-type data and response-type data according to requests and responses. The request-type data includes read requests and write requests, and the response-type data includes read responses and write responses.

[0037] The interactive transaction data refers to the transaction data generated by the control plane information exchange between GPU chips. Its business types include at least one of configuration data, synchronization data, control data, and message data. It should be noted that the interactive transaction data in this embodiment belongs to the transmission payload at the business layer; while the flow control information used to feedback the cache occupancy status and link congestion status belongs to the handshake control signal at the physical link layer. The two are fundamentally different in definition and function.

[0038] Furthermore, the transaction data typically carries multiple data field attributes. These data field attributes include at least one of the following: data packet header fields, address fields, and custom fields. The adapter is not limited to the above-mentioned business types; instead, it can be flexibly categorized according to specific domain segments of the transaction data. The categorization method can be flexibly configured according to actual application requirements.

[0039] It should be noted that in actual hardware design, the more refined the data types and the more categories of transactions, the more virtual channels (VCs) need to be allocated. Each additional virtual channel inevitably incurs additional hardware resource overhead, including but not limited to logical partitioning of shared cache space, independent linked list management logic, and complex multi-level arbitrator circuits. Therefore, in practical applications, a reasonable balance can be struck between the total number of categories and hardware resources based on business needs and hardware resource overhead, and the required classification methods and number of virtual channels can be flexibly configured through the software configuration interface.

[0040] S103: Based on the virtual channel, the corresponding transaction data is encapsulated to generate a data transmission unit carrying virtual channel identification information, and then sent to the receiving end.

[0041] Specifically, the virtual channel identification information is carried in the header of the data transmission unit; the header of the data transmission unit also carries destination information.

[0042] In this invention, the data transmission unit can be a Flit (Flow Control Unit). A Flit is the smallest independent unit for inter-chip data transmission, consisting of a header and a payload, such as... Figure 6 As shown, the packet header carries the control information required for data transmission, while the payload carries the specific transaction data content. At the sending end, the adapter encapsulates the transaction data into one or more Flits for transmission. Upon receiving a Flit, the receiving end parses the control information in the packet header, extracts the transaction data from the payload, and distributes it to the corresponding processing unit.

[0043] Because data transmission between GPU chips uses the Ethernet standard protocol, after removing the Ethernet header overhead, the adapter allows filling custom fields in the header with relevant transaction data information when assembling data transmission units. For example... Figure 7 As shown, the specific format of the packet header may include the following fields: Virtual Channel Identifier (VC Channel, 3 bits), used to identify the virtual channel to which the data transmission unit belongs; Packet Type, used to identify the service type of the transaction data carried by the data transmission unit; Priority, used to identify the transmission priority assigned to the data transmission unit; Frame Count, used to identify the number of payloads carried by the data transmission unit during packet concatenation; Destination GPU Chip ID (Dst ID), i.e., the destination information, used to identify the destination GPU chip of the data transmission unit; Source GPU Chip ID (Src ID), used to identify the source GPU chip that sent the data transmission unit; and EtherType, used to identify Ethernet protocol-related content. In addition, the packet header also includes a reserved field (rsv) for future feature expansion or custom purposes. Subsequent transmission and priority arbitration are based on the information in the packet header. The receiving adapter can identify the virtual channel, transaction data type, priority, and destination information of the data transmission unit by parsing the above fields in the packet header.

[0044] The receiving end is a peer GPU chip or a switching node; the peer GPU chip is the target GPU chip corresponding to the destination of the data transmission unit, or an intermediate GPU chip node. The destination information in the data transmission unit is also used by the switching node or the intermediate GPU chip node to determine the data forwarding path. Specifically, when the data transmission path includes a switching node or an intermediate node in a network of multiple directly connected GPU chips, the switching node or the intermediate GPU chip node routes the data transmission unit to the next-hop node or the final target GPU chip based on the destination information in the packet header. The relevant forwarding mechanism is described above. Figure 4 , Figure 5 The topology shown has been expanded and explained.

[0045] Furthermore, the step of encapsulating the corresponding transaction data based on the virtual channel, generating a data transmission unit carrying virtual channel identification information, and sending it to the receiving end specifically involves: encapsulating transaction data with the same virtual channel and the same destination into the same data transmission unit, and sending the data transmission unit to the corresponding receiving end according to the destination information.

[0046] It should be noted that the encapsulation strategy differs slightly under different topologies. In the interconnection mode of switching nodes or the many-to-many direct connection network mode, due to the one-to-many data transmission requirement, it is necessary to select transaction data with the same virtual channel and the same destination for packet assembly during encapsulation; in the mode of direct interconnection between two GPU chips, since the destination is the same, it is only necessary to encapsulate transaction data with the same virtual channel.

[0047] In practical applications, the read / write transaction data bit width of the GPU chip is usually mismatched with the transmission channel bit width. Therefore, the hardware circuit in the adapter needs to be encapsulated to splice multiple transaction data into the same data transmission unit for transmission, in order to improve data bandwidth utilization. Figure 8 and Figure 9 The single transmission bit width in the text represents the data width that the physical transmission channel (the data channel) can transmit in each cycle. If a single transaction exceeds this bit width, it will require multiple transmission cycles to complete the transmission, and the unfilled portion will generate blank padding data, resulting in wasted bandwidth.

[0048] For example, if the data transmission channel width is 1024 bits and the width of a single write address data is 1200 bits, transmitting a single write address data as a single data transmission unit would require two transmissions. The second transmission would contain a large amount of filler data, resulting in wasted bandwidth. By concatenating multiple transaction data from the same virtual channel and to the same destination into a single data transmission unit, the data from each transaction is arranged consecutively within the transmission cycle, effectively reducing the proportion of filler data and improving bandwidth utilization. Figure 8The diagram illustrates the concatenation and encapsulation of multiple write request data. By arranging three write request data (aw pload) consecutively after the packet header (flit header) and concatenating them into the same flit, the effective data in this flit is arranged continuously over three transmission cycles. The total data volume exactly fills or nearly fills an integer number of transmission cycles' width. Compared to the method where each data transmission unit carries only one write request data, this effectively reduces the proportion of padding data and improves bandwidth utilization. It should be noted that a flit is the basic unit of link-layer flow control; a flit can occupy multiple consecutive transmission cycles at the physical layer to complete transmission.

[0049] For transactional data types with small bit widths, such as write response data, if each data transmission unit only carries a single write response, it will still generate a large amount of padding data, resulting in wasted bandwidth. Therefore, write response data also needs to be encapsulated. For example... Figure 9 The diagram shows a concatenation and encapsulation of multiple write response data. The diagram exemplifies how three write response data (B pload) are arranged consecutively after the packet header and concatenated in the same data transmission unit. The total data volume is just close to filling the transmission bit width of one transmission cycle, effectively avoiding bandwidth waste caused by the small bit width of a single write response data.

[0050] During the encapsulation process, to prevent data transmission from being hindered due to waiting for encapsulation, this invention also implements encapsulation triggering through hardware control logic. Specifically, it includes the following transaction data encapsulation strategies: encapsulation is triggered when the number of transaction data in the data transmission unit to be encapsulated reaches a preset threshold; encapsulation is triggered when the waiting time of the data transmission unit to be encapsulated reaches a preset time threshold; encapsulation is triggered when an idle downstream link is detected; encapsulation is triggered when a data transmission unit to be encapsulated contains transaction data that needs to be sent first; and when a single transaction exceeds the capacity of a single data transmission unit, the transaction data is split and encapsulated in multiple data transmission units.

[0051] For example, carrying 4 transaction data in a single data transmission unit is an optimal example: (1) If three transaction data have already been stored in the current data transmission unit, the encapsulation and transmission will be triggered immediately after the arrival of the fourth transaction data; (2) If it is detected that the current data transmission unit contains transaction data that needs to be sent first, then without waiting to continue to assemble the packet, directly encapsulate and send it; (3) If the downstream link is detected to be idle, the encapsulation and transmission will be triggered as soon as there is a transaction in the current data transmission unit; (4) If the current data transmission unit has not been spliced ​​with 4 transaction data within the time window configured in the software, the current data transmission unit will be encapsulated and sent after the timeout.

[0052] like Figure 10 As shown, this invention incorporates multi-condition triggered Flit encapsulation control logic at the sending end. Specifically, the hardware circuit uses a data cache module (datamem) to store the transaction data to be encapsulated and a Flit information module (flitinfo) to record the status information of the Flit currently being assembled. The circuit monitors the packet assembly process in real time through several judgment conditions: when it detects that the current Flit has stored 3 data entries and the 4th data entry has arrived (inputvld&cnt==3), it immediately triggers the output of the Flit; when it identifies that the current Flit contains transaction data that needs to be sent first (highpriority_vld_arb), it can be output directly without waiting for the data to be fully collected; at the same time, the circuit introduces a timeout aging detection module (aging), if the expected number of data entries are not completed within the time window configured by the software, the current Flit will be forcibly encapsulated and sent after the timeout; in addition, a scanning module (scan) monitors the downstream link status, allowing the Flit to be output even if there is only 1 data entry when the downstream is idle. After the results of the above multiple conditions are uniformly aggregated, the control will send the Flit that has completed encapsulation or meets the pre-output conditions to the multi-chain buffer for subsequent transmission scheduling. Through this design, it ensures efficient packet assembly based on the optimal number of packets (e.g., 4 packets) to improve bandwidth utilization when data is sufficient, and avoids low-priority or sparse data occupying resources for a long time through flexible triggering mechanisms such as priority, timeout, and downstream idle, ensuring that data can be sent to the other end in a timely manner.

[0053] Furthermore, the sending end and the receiving end are connected via a single data channel, which can only transmit one data transmission unit at a time. Since there is only one actual physical transmission path, GPU chip data divided into different VCs must be arbitrated at the sending end before being sent to the receiving end.

[0054] The present invention also introduces a priority arbitration mechanism at the sending end to ensure the priority transmission of critical business data. The method further includes: configuring corresponding priorities for different virtual channels; when multiple virtual channels have data transmission units to be sent at the same time, arbitration is performed according to the priority of each virtual channel, and the data transmission units of the higher priority virtual channels are sent first through the data channel.

[0055] Regarding the details of the arbitration process, the specific steps for arbitrating based on the priority of each virtual channel are as follows: To strictly ensure the consistency of the physical link layer protocol and the integrity of the data, the arbitrator follows a "non-preemptive" transmission principle. That is, once the arbitration logic selects a data transmission unit (Flit) of a virtual channel to begin transmission, the arbitrator will forcibly maintain the transmission occupation state of that virtual channel until the data transmission unit (i.e., the complete Flit) is completed, without any interruption or transmission switching. Only after all current data transmission units have been transmitted will the arbitrator release the data channel and immediately initiate a new round of priority arbitration based on the latest priority status and queue status of each virtual channel to determine the next data transmission unit to be transmitted.

[0056] like Figure 11 As shown, the arbitrator is located at the transmitting end and is used to schedule multiple data transmission units to be transmitted in an orderly manner under the condition of a single physical data channel. The inputs vc0_data to vc3_data on the left side of the diagram represent data streams to be transmitted from four different virtual channels.

[0057] Specifically, each data transmission unit entering the arbitrator carries a header containing complete attribute information, primarily including the destination GPU chip ID (Dst ID), priority, data type, and the associated virtual channel identifier (VC Channel). Based on this rich attribute information, this embodiment employs a multi-level flexible arbitration architecture at the hardware level. As shown in the figure, the arbitration logic is divided into four parallel selection levels (multiplexer MUX groups), corresponding to four different arbitration strategies: the first level filters based on the virtual channel identifier (vc0~vc3); the second level filters based on the target device ID (Dst0~Dst3); the third level filters based on the priority identifier (Pri0~Pri3); and the fourth level filters based on the packet type (packet_type0~3). The selection results of these four levels are collectively output to the final arbitrator at the last level.

[0058] It should be noted that although the four different arbitration strategies mentioned above differ in physical path selection and reference attributes, the essence of the arbitration mechanism still uniformly follows the priority of each virtual channel for judgment. That is, whether using the destination GPU chip ID (Dst ID), packet type, or directly using the priority identifier as the first-level filtering condition, the final execution result of these strategies determines that a specific virtual channel (VC) is ultimately selected and granted the right to send. Therefore, Figure 11The multi-level arbitration mechanism shown is essentially a priority scheduling system that is flexibly mapped to different transaction attributes according to software configuration. Its core logic is still to ensure the priority transmission of critical business data under multi-VC competition by using pre-configured virtual channel priorities.

[0059] The arbitrator also includes a software control interface for interaction with the software layer. Through this reserved software interface, the effective status and weight of the arbitration strategies at each level can be flexibly configured or switched according to current business needs and network conditions. Simultaneously, to ensure the indivisibility of data transmission over the physical channel, the internal logic of the arbitrator is configured to follow a "non-preemptive" principle. That is, once the arbitration logic selects a data transmission unit (Flit) of a VC to initiate transmission, the arbitrator will maintain its current state and will not initiate any new round of arbitration until the complete Flit has been transmitted. This effectively avoids the risks of packet fragmentation and out-of-order delivery, ensuring the reliability and protocol consistency of the link layer transmission.

[0060] Specifically, the virtual channel allocated for the interactive transaction data is configured with a first priority, which is higher than the priority of the virtual channel allocated for the access transaction data, thereby ensuring that key control plane data such as configuration data, synchronization data, control data, and message data can obtain transmission resources first.

[0061] S104: The receiving end caches the data transmission units of different virtual channels into the corresponding logical cache areas according to the virtual channel identification information.

[0062] like Figure 12 As shown, the receiving end of a GPU chip is usually limited by hardware resources and is only configured with a common physical storage space to receive data transmitted from the other end. In order to overcome the problem of low resource utilization caused by the traditional fixed division of independent physical storage spaces according to virtual channels (that is, when the data traffic of VCO is large and the traffic of VC1 is small, it will lead to the idle waste of VC1 reserved space and at the same time exacerbate the congestion of VCO), the logical cache area physically belongs to the same shared storage space. The logical cache area corresponding to each virtual channel is logically divided in the shared storage space based on the virtual channel identification information, and the corresponding data cache status parameters are maintained respectively.

[0063] To achieve the above logical partitioning, the hardware circuitry of the receiving end includes a physically unified large-capacity storage space. To achieve independent isolation and orderly management of data from multiple virtual channels within a single storage space, the logical partitioning is implemented using linked lists: each virtual channel is allocated an independent linked list in the shared storage space. When the data transmission units (Flits) received by each virtual channel are stored in the shared storage space, they are not stored contiguously according to physical addresses. Instead, the data belonging to the same virtual channel are linked together end-to-end in the storage unit through pointer nodes of the corresponding linked list, thereby dynamically forming a logical buffer area dedicated to that virtual channel in the shared space.

[0064] Under this mechanism, the core function of the linked list is to connect the storage units of the same virtual channel in the shared storage space. The number of nodes currently connected in each linked list (i.e., the length of the linked list) represents the real-time capacity of the logical cache area corresponding to each virtual channel. It is important to emphasize that the length of the linked list is not fixed but dynamically changes according to the actual business traffic. It represents the actual space occupied by the virtual channel in the shared storage space at the current moment. Through this dynamic allocation mechanism of the linked list, the hardware does not need to allocate a fixed-size physical storage area for each VC, thereby significantly improving the overall utilization of cache resources and effectively avoiding the waste of hardware resources caused by one VC being idle while another VC is congested, as in traditional fixed partitioning schemes.

[0065] Furthermore, this invention introduces a software-configurable capacity control mechanism for each logical cache region, and the receiving end is equipped with a software configuration interface. For example... Figure 12 As shown in the labels VC0 Thd to VC3 Thd, the software can allocate the maximum space allowed to be occupied in the shared storage space for each virtual channel, i.e., the capacity of the logical cache area, based on the transaction load type currently running on the GPU chip, through the configuration interface. Through this linked list dynamic allocation combined with capacity control, the hardware supports elastic scheduling of the shared storage space: when an increase in data traffic is detected in a certain virtual channel (such as VC0), the logical cache area capacity of other virtual channels can be compressed through software configuration, dynamically allocating more shared storage resources to the high-load virtual channel. This significantly improves the utilization rate of the receiving end's storage space without increasing additional physical storage overhead, effectively alleviating data congestion problems in specific virtual channels.

[0066] S105: The receiving end monitors the cache status parameters of each of the logical cache areas. When the cache status parameters corresponding to the target virtual channel meet the preset flow control conditions, it generates flow control information carrying the target virtual channel identification information and feeds it back to the sending end.

[0067] When a virtual channel of the receiving GPU chip becomes congested, the sending end only needs to be notified to suspend the transmission of transaction data for that specific target virtual channel; while data in other virtual channels that are not congested can still be transmitted normally, thereby greatly improving the overall transmission efficiency and effectively avoiding the problem of global transmission interruption due to local congestion.

[0068] Regarding the transmission path of flow control information, the flow control information is fed back to the sending end through a control channel independent of the data channel. This control channel is directly transmitted and received by hardware logic and is used for dedicated line transmission of flow control signaling, without occupying the transmission bandwidth of the aforementioned transaction data.

[0069] Furthermore, to improve the overall utilization efficiency of the data transmission hardware, the step of feeding back the flow control information from the receiving end to the sending end includes: after the flow control information is generated by the logical buffer area corresponding to the target virtual channel at the receiving end, it is transmitted in reverse step by step along the path of data transmission unit from the sending end to the receiving end; after each intermediate link receives the flow control information, it continues to receive the data transmission unit of the target virtual channel using its own storage space; when the storage space of its own level reaches a preset state, it suspends the forwarding or processing of the data transmission unit of the target virtual channel in this link and continues to transmit the flow control information to the previous link; after the flow control information is transmitted back step by step through each intermediate link, it finally triggers the sending end to suspend the transmission of transaction data of the target virtual channel.

[0070] like Figure 13 The schematic diagram of step-by-step backpressure shown illustrates the specific hardware path for implementing virtual channel-level flow control based on the step-by-step backpressure mechanism in this embodiment of the invention.

[0071] In the data flow direction, read / write requests (read req / writereq) and read / write responses (read resp / write resp) issued by the sending end (Tx) cluster are first divided into channels by encapsulation modules belonging to different virtual channels (such as vc0_split to vc3_split), and then input into a multi-chain buffer for queue buffering. Finally, an arbiter (priority arb) selects a data transmission unit according to a preset strategy and sends it to the receiving end (Rx). At the hardware architecture level, flow control information, in the form of backpressure signals, is strictly transmitted back along the path of the data transmission unit from the sending end to the receiving end, level by level (from the receiving end back to the sending end via intermediate links).

[0072] The specific execution logic of this counter-pressure mechanism follows a bottom-up, hierarchical transmission process, specifically including: When the receiving GPU chip is unable to receive a specific virtual channel due to internal cache congestion (e.g., Figure 13 When data from the target virtual channel (vc3 channel shown) is received, the logical buffer area corresponding to the target virtual channel will first initiate a backpressure signal. This backpressure signal is transmitted upwards along the opposite path of the data flow to each intermediate stage (such as the multi-chain buffer at the receiving end). After receiving the backpressure signal, the intermediate stage will not immediately stop responding to the upstream data, but will continue to receive the data transmission units of the target virtual channel using the remaining storage space at this stage; only when the storage space at this stage is also filled, reaching the preset waterline or full load state, will the intermediate stage at this stage suspend the forwarding or processing of the target virtual channel's data at this stage, and continue to transmit the backpressure signal to the next intermediate stage.

[0073] Following this pattern, the backpressure signal is transmitted upwards through each intermediate stage, following this rule. Each intermediate stage first absorbs data using its own buffer, and then transmits the backpressure signal upwards only when the buffer is full. When the backpressure signal finally reaches the arbitrator and encapsulation module at the sending end, and their corresponding buffer space is exhausted, the sending end GPU chip will be triggered to pull the "Ready" signal of the VC3 channel low, thereby pausing the transmission of transaction data on the VC3 channel. Through this step-by-step transmission and layer-by-layer buffering backpressure mechanism, the system can maximize the utilization of the storage capacity of each link, blocking the transmission source only when absolutely necessary. At the same time, since backpressure is applied only to a single VC, data from other normal VCs can still continue to be transmitted, effectively avoiding significant fluctuations in global transmission performance caused by local congestion in a single channel.

[0074] Furthermore, the cache status parameters include the occupancy of the logical cache region, and the preset flow control conditions include the occupancy reaching the backpressure start threshold.

[0075] Since flow control information is typically fed back from the receiving end to the sending end, there is a certain propagation delay in the transmission of this flow control information in the inter-chip interconnect link. Before the flow control information reaches the sending end and takes effect, the sending end may still continue to send some data transmission units to the receiving end. Therefore, the receiving end needs to reserve buffer space in the logical buffer area of ​​the corresponding virtual channel to receive this part of the data in transit, in order to avoid buffer overflow caused by the delay in the backpressure taking effect.

[0076] To ensure that data arriving before the flow control information takes effect does not exceed the logical buffer area capacity and to achieve lossless transmission, this embodiment also introduces an in-transit data reservation mechanism. Based on software configuration parameters, the capacity of the corresponding logical buffer area and the backpressure start threshold are set for each virtual channel. The capacity of the logical buffer area is used to limit the maximum cache resources that the corresponding virtual channel is allowed to occupy in the shared storage space, and the backpressure start threshold is used to indicate the triggering condition for the corresponding virtual channel to enter the flow-limited state.

[0077] To achieve quantitative configuration and on-demand allocation of the reserved space, the amount of data in transit for each virtual channel is determined, and the data capacity available for actual caching of the corresponding virtual channel is adjusted based on the amount of data in transit.

[0078] Specifically, the propagation delay time of the flow control information from the receiving end to the sending end is obtained; Based on the propagation delay time and the data transmission rate of the target virtual channel, the number of data transmission units that can be transmitted within the propagation delay time is calculated as the amount of data in transit for the target virtual channel; based on the amount of data in transit, a corresponding buffer space is reserved for the logical buffer area corresponding to the target virtual channel; the capacity of the logical buffer area minus the size of the buffer space is used as the backpressure start threshold, so that the data transmission units arriving before the flow control information takes effect do not exceed the capacity of the logical buffer area.

[0079] Furthermore, to avoid frequent backpressure requests and frequent backpressure releases caused by fluctuations in cache usage near the critical state, this embodiment also configures a backpressure release threshold for each virtual channel. The backpressure release threshold is lower than the backpressure start threshold, and a preset interval is set between the two to form a hysteresis interval for traffic state switching.

[0080] Specifically, when the occupancy of the logical buffer area corresponding to the target virtual channel decreases below the backpressure release threshold, the receiving end generates flow control release information carrying the target virtual channel identification information and feeds it back to the sending end; the sending end resumes data transmission of the target virtual channel according to the flow control release information; wherein, the backpressure release threshold is lower than the backpressure start threshold, so as to form a hysteresis interval between the backpressure start threshold and the backpressure release threshold, and the buffer capacity corresponding to the hysteresis interval is greater than the buffer space corresponding to the amount of data in transit, thereby ensuring that the buffer occupancy after the backpressure is released will not immediately reach the backpressure start threshold again due to the data in transit or the data to be resumed, and avoiding frequent switching of flow control state.

[0081] Through the aforementioned backpressure threshold configuration based on virtual channels and the in-transit data reservation mechanism, each virtual channel can independently determine its cache protection space according to its own link transmission rate and traffic characteristics. This ensures the accuracy of backpressure control while avoiding storage resource waste caused by fixed reserved cache. Furthermore, by setting backpressure start and release thresholds with intervals, the additional control overhead caused by frequent flow control state switching can be reduced, improving the stability of inter-chip data transmission.

[0082] like Figure 14 As shown, the receiving end includes a shared storage space for multiple virtual channels. The data transmission units of different virtual channels are stored in the shared storage space based on the virtual channel identification information, and each maintains its corresponding cache status parameters.

[0083] Specifically, for each virtual channel, the software can independently configure the corresponding logical cache area capacity VC_Thd, backpressure start threshold VC_backpress_Thd, and backpressure release threshold VC_send_Thd. VC_Thd limits the maximum cache resources allowed for the corresponding virtual channel in the shared storage space. VC_backpress_Thd is lower than VC_Thd, forming a reserved buffer space to accommodate data transmission units that continue to arrive during the backpressure control information transmission and activation process, thereby preventing cache usage from exceeding the upper limit of the logical cache area capacity due to backpressure delays. VC_send_Thd is lower than VC_backpress_Thd, forming a hysteresis interval, ensuring that the cache usage decreases to a lower level before the backpressure state is released, thus avoiding repeated triggering and release of backpressure due to fluctuations in cache usage within a critical range. Furthermore, the buffer capacity corresponding to the hysteresis interval is greater than the buffer space corresponding to the amount of data in transit. This ensures that after the backpressure is released and data transmission is resumed, even if there is a flow control response delay and data transmission units continue to arrive in the link, the logical buffer area can still maintain sufficient buffer space. This prevents the buffer occupancy from quickly reaching VC_backpress_Thd again and triggering backpressure again, thereby improving the stability of flow control state switching.

[0084] Meanwhile, since different virtual channels carry different types of services, each virtual channel can be configured with different threshold parameters. For example, for virtual channels with high data traffic, the available cache resources can be increased by adjusting VC_Thd; for virtual channels with large data traffic fluctuations, the stability of traffic control can be improved by adjusting the interval between VC_backpress_Thd and VC_send_Thd. In this way, the shared storage space can be flexibly configured according to the data transmission characteristics of different virtual channels.

[0085] S106: Adjust the data transmission status of the target virtual channel according to the flow control information, and maintain the data transmission of other virtual channels.

[0086] In summary, this invention enables independent flow control for a single, specific virtual channel (VC), primarily based on the following technical foundations: First, at the data link layer, the data transmission unit (Flit) header explicitly carries virtual channel identification information, ensuring that each piece of data is strictly bound to a specific VC. Second, in the receiver's hardware architecture, although the shared storage space is physically shared by all VCs, a linked list mechanism achieves strict logical isolation based on the VC identifier, preventing interference between the buffer queue states of each VC. Finally, in conjunction with the aforementioned step-by-step backpressure mechanism, the flow control signal also carries a clear target VC identifier. During the reverse step-by-step transmission process, this signal precisely targets the gating logic and queue pointers in each intermediate stage that are only related to that specific VC. Therefore, the system can accurately identify and block the transmission behavior of a specific VC without affecting the transmission pipeline of other VCs, thus achieving microsecond-level, unidirectional, fine-grained local flow control.

[0087] In actual operation, the hardware parameters and strategies upon which the above steps depend can all be dynamically configured by software. The method further includes: dynamically configuring, either uniformly or individually, the number of virtual channels, the service type and / or mapping relationship between data field attributes and virtual channels, the encapsulation strategy of the data transmission unit, the priority of each virtual channel, the capacity of each logical cache area, and the preset flow control conditions of each logical cache area through a software configuration interface, based on data transmission requirements. Through this dynamic configuration, the present invention can dynamically optimize resource allocation and flow control strategies for cross-chip data transmission according to actual business load conditions.

[0088] Exemplary System Accordingly, this embodiment of the invention also provides a data transmission system based on a virtual channel. The system provided in this embodiment includes: a transmitting end and a receiving end; the transmitting end includes a transmitting end adapter and an encapsulation module; the receiving end includes a receiving end adapter. The transmitting adapter is used to acquire transaction data transmitted across chips; The sending adapter is also used to classify the transaction data according to the service type and / or data field attributes of the transaction data, and to allocate virtual channels to the transaction data based on the classification results; The encapsulation module is used to encapsulate the corresponding transaction data based on the virtual channel, generate a data transmission unit carrying virtual channel identification information, and send it to the receiving adapter. The receiving adapter is used to cache the data transmission units of different virtual channels into corresponding logical cache areas according to the virtual channel identification information. The receiving adapter is used to monitor the cache status parameters of each logical cache area. When the cache status parameters corresponding to the target virtual channel meet the preset flow control conditions, it generates flow control information carrying the target virtual channel identification information and feeds it back to the sending adapter. The transmitting adapter is also used to adjust the data transmission status of the target virtual channel according to the flow control information, and to maintain the data transmission of other virtual channels.

[0089] The transmitting end and the receiving end are connected through a single data channel, and the data channel can only transmit one data transmission unit at a time. The transmitting adapter also includes an arbitrator; The arbitrator is used to configure corresponding priorities for different virtual channels; The arbitrator is also used to arbitrate according to the priority of each virtual channel when multiple virtual channels have data transmission units to be sent at the same time, and to send the data transmission units of the higher priority virtual channels first through the data channel.

[0090] The arbitrator is also used to maintain the data transmission state of a virtual channel when the data transmission unit of a certain virtual channel is in the transmission state until the data transmission unit has finished transmitting, and to re-arbitrate according to the priority of each virtual channel after the transmission is completed.

[0091] The logical cache areas physically belong to the same shared storage space. The logical cache areas corresponding to each virtual channel are logically divided in the shared storage space based on the virtual channel identification information, and each maintains its corresponding data cache status parameters.

[0092] The logical partitioning is implemented using linked lists: a linked list is allocated to each virtual channel in the shared storage space, and the data transmission units of each virtual channel are connected in series through the corresponding linked lists to form the corresponding logical cache area.

[0093] The cache status parameters include the occupancy of the logical cache area, and the preset flow control conditions include the occupancy reaching the backpressure start threshold.

[0094] The receiver adapter is also used for: The propagation delay time of the flow control information from the receiving end to the sending end is obtained; Based on the propagation delay time and the data transmission rate of the target virtual channel, the number of data transmission units that can be transmitted within the propagation delay time is calculated, which is taken as the amount of data in transit of the target virtual channel. Based on the amount of data in transit, reserve corresponding buffer space for the logical cache area corresponding to the target virtual channel; The backpressure start threshold is set by subtracting the buffer space size from the capacity of the logical buffer area, so that the data transmission unit arriving before the flow control information takes effect does not exceed the capacity of the logical buffer area.

[0095] The receiving adapter is further configured to generate flow control release information carrying the target virtual channel identifier information and feed it back to the sending adapter when the occupancy of the logical buffer area corresponding to the target virtual channel is reduced to below the back pressure release threshold. The transmitting adapter is also used to restore data transmission of the target virtual channel based on the flow control release information; Wherein, the backpressure release threshold is lower than the backpressure start threshold, so as to form a hysteresis interval between the backpressure start threshold and the backpressure release threshold, and the cache capacity corresponding to the hysteresis interval is greater than the buffer space corresponding to the amount of data in transit.

[0096] The flow control information is fed back to the transmitting adapter through a control channel independent of the data channel.

[0097] The system also includes one or more intermediate links located between the transmitting adapter and the receiving adapter; The flow control information is generated by the logical buffer area corresponding to the target virtual channel of the receiving adapter and then transmitted in reverse order from the sending adapter to the receiving adapter along the path of the data transmission unit. Each intermediate link, upon receiving the flow control information, continues to receive the data transmission unit of the target virtual channel using its own storage space. When the storage space reaches a preset state, it suspends the forwarding or processing of the data transmission unit of the target virtual channel in this link and continues to transmit the flow control information to the next link. The flow control information is transmitted back through each intermediate link and finally triggers the sending adapter to suspend the transmission of transaction data for the target virtual channel.

[0098] The encapsulation module is used to encapsulate the transaction data according to the following encapsulation strategy: Encapsulation is triggered when the number of transaction data in the data transmission unit to be encapsulated reaches a preset threshold. Encapsulation is triggered when the waiting time of the data transmission unit to be encapsulated reaches a preset time threshold. Encapsulation is triggered when the downstream link is detected to be idle; Encapsulation is triggered when the data transmission unit to be encapsulated is detected to contain transaction data that needs to be sent first. When a single transaction exceeds the capacity of a single data transmission unit, the transaction data is split and encapsulated in multiple data transmission units.

[0099] The transaction data mentioned is access-type transaction data.

[0100] The business types for accessing transaction data include at least one of read requests, read responses, write requests, write data, and write responses.

[0101] The business types of the access-type transaction data include request-type data and response-type data; The request data includes read requests and write requests, and the response data includes read responses and write responses.

[0102] The transaction data also includes interactive transaction data, and the business types of the interactive transaction data include at least one of configuration data, synchronization data, control data, and message data; The arbitrator in the sending adapter is also used to configure a first priority for the virtual channel allocated for the interactive transaction data, the first priority being higher than the priority of the virtual channel allocated for the access transaction data.

[0103] The data field attributes include at least one of the following: data packet header field, address field, and custom field.

[0104] The virtual channel identification information is carried in the packet header of the data transmission unit; The header of the data transmission unit also carries destination information; The encapsulation module is also used to encapsulate transaction data with the same virtual channel and the same destination into the same data transmission unit, and send the data transmission unit to the corresponding receiving end according to the destination information.

[0105] The receiving end is a peer GPU chip or a switching node; The peer GPU chip is either the target GPU chip corresponding to the destination of the data transmission unit, or an intermediate GPU chip node. The destination information in the data transmission unit is also used to help the switching node or the intermediate GPU chip node determine the data forwarding path.

[0106] The system is applied to C2C interconnection and transmission of multiple GPU chips, and its topology includes any of the following: direct interconnection topology between two GPU chips, one-to-many topology of multiple GPU chips interconnected through switching nodes, and multi-hop topology.

[0107] The sending and receiving ends use the same protocol stack and are deployed symmetrically.

[0108] The sending end and the receiving end are also provided with software configuration interfaces, which are used to dynamically configure the number of virtual channels, service type and / or mapping relationship between data field attributes and virtual channels, encapsulation strategy, priority of each virtual channel, capacity of each logical buffer area and / or preset flow control conditions of each logical buffer area according to data transmission requirements.

[0109] It should be noted that although the operation of the data transmission method based on the virtual channel of the present invention is described in a specific order in the accompanying drawings, this does not require or imply that the operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0110] Furthermore, although several devices, units, or modules of a data transmission system based on virtual channels have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more modules described above can be embodied in a single module. Conversely, the features and functions of a single module described above can be further divided and embodied by multiple modules.

[0111] While the spirit and principles of the invention have been described with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined for benefit; such division is merely for ease of description. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0112] This invention provides: 1. A data transmission method based on a virtual channel, characterized in that the method includes: Acquire transaction data transferred across chips; The transaction data is classified according to its business type and / or data field attributes, and virtual channels are allocated to the transaction data based on the classification results. Based on the virtual channel, the corresponding transaction data is encapsulated to generate a data transmission unit carrying virtual channel identification information, and then sent to the receiving end. The receiving end caches the data transmission units of different virtual channels into the corresponding logical cache areas according to the virtual channel identification information. The receiving end monitors the cache status parameters of each of the logical cache areas. When the cache status parameters corresponding to the target virtual channel meet the preset flow control conditions, it generates flow control information carrying the target virtual channel identification information and feeds it back to the sending end. The data transmission status of the target virtual channel is adjusted according to the flow control information, while maintaining the data transmission of other virtual channels.

[0113] 2. The data transmission method based on a virtual channel according to item 1, characterized in that the sending end and the receiving end are connected through a single data channel, and the data channel can only transmit one data transmission unit at a time; The method further includes: Configure corresponding priorities for different virtual channels; When multiple virtual channels have data transmission units to be sent simultaneously, arbitration is performed according to the priority of each virtual channel, and the data transmission units of the higher-priority virtual channels are sent first through the data channel.

[0114] 3. The data transmission method based on virtual channels according to item 2, characterized in that the step of arbitrating according to the priority of each virtual channel specifically comprises: When a data transmission unit of a virtual channel is in the transmission state, the data transmission state of the virtual channel is maintained until the data transmission unit completes transmission, and arbitration is re-performed according to the priority of each virtual channel after transmission is completed.

[0115] 4. The data transmission method based on virtual channels as described in item 1, characterized in that the logical cache areas physically belong to the same shared storage space, and the logical cache areas corresponding to each virtual channel are logically divided in the shared storage space based on the virtual channel identification information, and respectively maintain the corresponding data cache status parameters.

[0116] 5. The data transmission method based on virtual channels according to item 4, characterized in that the logical partitioning is implemented by a linked list: a linked list is allocated for each virtual channel in the shared storage space, and the data transmission units of each virtual channel are connected in series through the corresponding linked list to form the corresponding logical cache area.

[0117] 6. The data transmission method based on a virtual channel according to item 4 or 5, wherein the cache status parameter includes the occupancy of the logical cache area, and the preset flow control condition includes the occupancy reaching the backpressure start threshold.

[0118] 7. The data transmission method based on a virtual channel according to item 6, characterized in that the method further includes: The propagation delay time of the flow control information from the receiving end to the sending end is obtained; Based on the propagation delay time and the data transmission rate of the target virtual channel, the number of data transmission units that can be transmitted within the propagation delay time is calculated, which is taken as the amount of data in transit of the target virtual channel. Based on the amount of data in transit, reserve corresponding buffer space for the logical cache area corresponding to the target virtual channel; The backpressure start threshold is set by subtracting the buffer space size from the capacity of the logical buffer area, so that the data transmission unit arriving before the flow control information takes effect does not exceed the capacity of the logical buffer area.

[0119] 8. The data transmission method based on a virtual channel according to item 7, characterized in that the method further includes: When the occupancy of the logical buffer area corresponding to the target virtual channel decreases to below the backpressure release threshold, the receiving end generates flow control release information carrying the target virtual channel identification information and feeds it back to the sending end; The sending end resumes data transmission of the target virtual channel based on the flow control release information; Wherein, the backpressure release threshold is lower than the backpressure start threshold, so as to form a hysteresis interval between the backpressure start threshold and the backpressure release threshold, and the cache capacity corresponding to the hysteresis interval is greater than the buffer space corresponding to the amount of data in transit.

[0120] 9. The data transmission method based on a virtual channel according to item 2, characterized in that the flow control information is fed back to the sending end through a control channel independent of the data channel.

[0121] 10. The data transmission method based on a virtual channel according to item 1, characterized in that the step of feeding back the flow control information from the receiving end to the sending end includes: The flow control information is generated by the logical buffer area corresponding to the target virtual channel at the receiving end, and then transmitted in reverse step by step along the path from the sending end to the receiving end through the data transmission unit. After receiving the flow control information, each intermediate link continues to receive the data transmission unit of the target virtual channel using its own storage space. When the storage space reaches a preset state, the forwarding or processing of the data transmission unit of the target virtual channel in this link is paused, and the flow control information is continued to be transmitted to the next link. The flow control information is transmitted back through each intermediate link and finally triggers the sending end to suspend the transmission of transaction data for the target virtual channel.

[0122] 11. The data transmission method based on a virtual channel according to item 1, characterized in that the step of encapsulating the corresponding transaction data based on the virtual channel, generating a data transmission unit carrying virtual channel identification information, and sending it to the receiving end further includes the encapsulation strategy of the transaction data: Encapsulation is triggered when the number of transaction data in the data transmission unit to be encapsulated reaches a preset threshold. Encapsulation is triggered when the waiting time of the data transmission unit to be encapsulated reaches a preset time threshold. Encapsulation is triggered when the downstream link is detected to be idle; Encapsulation is triggered when the data transmission unit to be encapsulated is detected to contain transaction data that needs to be sent first. When a single transaction exceeds the capacity of a single data transmission unit, the transaction data is split and encapsulated in multiple data transmission units.

[0123] 12. The data transmission method based on a virtual channel according to item 1, wherein the transaction data is access-type transaction data.

[0124] 13. The data transmission method based on a virtual channel according to item 12, wherein the service type of the access-type transaction data includes at least one of read request, read response, write request, write data, and write response.

[0125] 14. The data transmission method based on a virtual channel according to item 12, wherein the service types of the access-type transaction data include request-type data and response-type data; The request data includes read requests and write requests, and the response data includes read responses and write responses.

[0126] 15. The data transmission method based on a virtual channel according to any one of items 12-14, characterized in that the transaction data further includes interactive transaction data, and the service type of the interactive transaction data includes at least one of configuration data, synchronization data, control data, and message data; The virtual channel allocated for the interactive transaction data is configured with a first priority, which is higher than the priority of the virtual channel allocated for the access transaction data.

[0127] 16. The data transmission method based on a virtual channel according to item 1, wherein the data field attributes include at least one of a data packet header field, an address field, and a custom field.

[0128] 17. The data transmission method based on a virtual channel according to item 1, wherein the virtual channel identification information is carried in the packet header of the data transmission unit; The header of the data transmission unit also carries destination information; The specific steps for encapsulating the corresponding transaction data based on the virtual channel, generating a data transmission unit carrying virtual channel identification information, and sending it to the receiving end are as follows: Transaction data with the same virtual channel and the same destination are encapsulated into the same data transmission unit, and the data transmission unit is sent to the corresponding receiving end according to the destination information.

[0129] 18. The data transmission method based on a virtual channel according to item 17, wherein the receiving end is a peer GPU chip or a switching node; The peer GPU chip is either the target GPU chip corresponding to the destination of the data transmission unit, or an intermediate GPU chip node. The destination information in the data transmission unit is also used to help the switching node or the intermediate GPU chip node determine the data forwarding path.

[0130] 19. The data transmission method based on virtual channels according to item 1, characterized in that the method is applied to C2C interconnection transmission of multiple GPU chips, and its topology includes any one of the following: direct interconnection topology between two GPU chips, one-to-many topology of multiple GPU chips interconnected through switching nodes, and multi-hop topology.

[0131] 20. The data transmission method based on a virtual channel as described in item 1, characterized in that the sending end and the receiving end adopt the same protocol stack symmetrically deployed.

[0132] 21. The data transmission method based on virtual channels according to item 1, characterized in that the method further includes: dynamically configuring the number of virtual channels, service type and / or mapping relationship between data field attributes and virtual channels, encapsulation strategy, priority of each virtual channel, capacity of each logical cache area and / or preset flow control conditions of each logical cache area through a software configuration interface according to data transmission requirements.

[0133] 22. A data transmission system based on a virtual channel, characterized in that the system comprises: a transmitting end and a receiving end, the transmitting end comprising a transmitting end adapter and an encapsulation module, and the receiving end comprising a receiving end adapter; The transmitting adapter is used to acquire transaction data transmitted across chips; The sending adapter is also used to classify the transaction data according to the service type and / or data field attributes of the transaction data, and to allocate virtual channels to the transaction data based on the classification results; The encapsulation module is used to encapsulate the corresponding transaction data based on the virtual channel, generate a data transmission unit carrying virtual channel identification information, and send it to the receiving adapter. The receiving adapter is used to cache the data transmission units of different virtual channels into corresponding logical cache areas according to the virtual channel identification information. The receiving adapter is used to monitor the cache status parameters of each logical cache area. When the cache status parameters corresponding to the target virtual channel meet the preset flow control conditions, it generates flow control information carrying the target virtual channel identification information and feeds it back to the sending adapter. The transmitting adapter is also used to adjust the data transmission status of the target virtual channel according to the flow control information, and to maintain the data transmission of other virtual channels.

[0134] 23. The data transmission system based on a virtual channel according to item 22, characterized in that the transmitting end and the receiving end are connected through a single data channel, and the data channel can only transmit one data transmission unit at a time; The transmitting adapter also includes an arbitrator; The arbitrator is used to configure corresponding priorities for different virtual channels; The arbitrator is also used to arbitrate according to the priority of each virtual channel when multiple virtual channels have data transmission units to be sent at the same time, and to send the data transmission units of the higher priority virtual channels first through the data channel.

[0135] 24. The data transmission system based on virtual channels according to item 23, wherein the arbitrator is further configured to maintain the data transmission state of the virtual channel before the data transmission unit of a certain virtual channel is completed when the data transmission unit of a certain virtual channel is in the transmission state, and to re-arbitrate according to the priority of each virtual channel after the transmission is completed.

[0136] 25. The data transmission system based on virtual channels according to item 22, characterized in that the logical cache areas physically belong to the same shared storage space, and the logical cache areas corresponding to each virtual channel are logically divided in the shared storage space based on the virtual channel identification information, and respectively maintain the corresponding data cache status parameters.

[0137] 26. The data transmission system based on virtual channels according to item 25, characterized in that the logical partitioning is implemented by a linked list: a linked list is allocated for each virtual channel in the shared storage space, and the data transmission units of each virtual channel are connected in series through the corresponding linked list to form the corresponding logical cache area.

[0138] 27. The data transmission system based on a virtual channel according to item 25 or 26, wherein the cache status parameter includes the occupancy of the logical cache area, and the preset flow control condition includes the occupancy reaching the backpressure start threshold.

[0139] 28. The data transmission system based on a virtual channel according to claim 27, wherein the receiving adapter is further configured to: The propagation delay time of the flow control information from the receiving end to the sending end is obtained; Based on the propagation delay time and the data transmission rate of the target virtual channel, the number of data transmission units that can be transmitted within the propagation delay time is calculated, which is taken as the amount of data in transit of the target virtual channel. Based on the amount of data in transit, reserve corresponding buffer space for the logical cache area corresponding to the target virtual channel; The backpressure start threshold is set by subtracting the buffer space size from the capacity of the logical buffer area, so that the data transmission unit arriving before the flow control information takes effect does not exceed the capacity of the logical buffer area.

[0140] 29. The data transmission system based on a virtual channel according to item 28, wherein the receiving adapter is further configured to generate flow control release information carrying the identification information of the target virtual channel and feed it back to the sending adapter when the occupancy of the logical buffer area corresponding to the target virtual channel is reduced to below the back pressure release threshold; The transmitting adapter is also used to restore data transmission of the target virtual channel based on the flow control release information; Wherein, the backpressure release threshold is lower than the backpressure start threshold, so as to form a hysteresis interval between the backpressure start threshold and the backpressure release threshold, and the cache capacity corresponding to the hysteresis interval is greater than the buffer space corresponding to the amount of data in transit.

[0141] 30. The data transmission system based on a virtual channel according to claim 23, wherein the flow control information is fed back to the transmitting adapter through a control channel independent of the data channel.

[0142] 31. The data transmission system based on a virtual channel according to claim 22, characterized in that the system further includes one or more intermediate links located between the transmitting adapter and the receiving adapter; The flow control information is generated by the logical buffer area corresponding to the target virtual channel of the receiving adapter and then transmitted in reverse order from the sending adapter to the receiving adapter along the path of the data transmission unit. Each intermediate link, upon receiving the flow control information, continues to receive the data transmission unit of the target virtual channel using its own storage space. When the storage space reaches a preset state, it suspends the forwarding or processing of the data transmission unit of the target virtual channel in this link and continues to transmit the flow control information to the next link. The flow control information is transmitted back through each intermediate link and finally triggers the sending adapter to suspend the transmission of transaction data for the target virtual channel.

[0143] 32. The data transmission system based on a virtual channel according to claim 22, characterized in that the encapsulation module is configured to encapsulate the transaction data according to the following encapsulation strategy: Encapsulation is triggered when the number of transaction data in the data transmission unit to be encapsulated reaches a preset threshold. Encapsulation is triggered when the waiting time of the data transmission unit to be encapsulated reaches a preset time threshold. Encapsulation is triggered when the downstream link is detected to be idle; Encapsulation is triggered when the data transmission unit to be encapsulated is detected to contain transaction data that needs to be sent first. When a single transaction exceeds the capacity of a single data transmission unit, the transaction data is split and encapsulated in multiple data transmission units.

[0144] 33. The data transmission system based on a virtual channel according to item 22, wherein the transaction data is access-type transaction data.

[0145] 34. The data transmission system based on a virtual channel according to item 33, wherein the service type of the access-type transaction data includes at least one of read request, read response, write request, write data, and write response.

[0146] 35. The data transmission system based on a virtual channel according to item 33, wherein the service types of the access-type transaction data include request-type data and response-type data; The request data includes read requests and write requests, and the response data includes read responses and write responses.

[0147] 36. The data transmission system based on a virtual channel according to any one of items 33-35, characterized in that the transaction data further includes interactive transaction data, and the service type of the interactive transaction data includes at least one of configuration data, synchronization data, control data, and message data; The arbitrator in the sending adapter is also used to configure a first priority for the virtual channel allocated for the interactive transaction data, the first priority being higher than the priority of the virtual channel allocated for the access transaction data.

[0148] 37. The data transmission system based on a virtual channel according to claim 22, wherein the data field attributes include at least one of a data packet header field, an address field, and a custom field.

[0149] 38. The data transmission system based on a virtual channel according to claim 22, wherein the virtual channel identification information is carried in the packet header of the data transmission unit; The header of the data transmission unit also carries destination information; The encapsulation module is also used to encapsulate transaction data with the same virtual channel and the same destination into the same data transmission unit, and send the data transmission unit to the corresponding receiving end according to the destination information.

[0150] 39. The data transmission system based on a virtual channel according to item 38, wherein the receiving end is a peer GPU chip or a switching node; The peer GPU chip is either the target GPU chip corresponding to the destination of the data transmission unit, or an intermediate GPU chip node. The destination information in the data transmission unit is also used to help the switching node or the intermediate GPU chip node determine the data forwarding path.

[0151] 40. The data transmission system based on virtual channels according to item 22, characterized in that the system is applied to C2C interconnection transmission of multiple GPU chips, and its topology includes any of the following: direct interconnection topology between two GPU chips, one-to-many topology of multiple GPU chips interconnected through switching nodes, and multi-hop topology.

[0152] 41. The data transmission system based on a virtual channel according to item 22, characterized in that the sending end and the receiving end adopt the same protocol stack symmetrically deployed.

[0153] 42. The data transmission system based on virtual channels according to item 22, characterized in that the sending end and the receiving end are further provided with a software configuration interface, which is used to dynamically configure the number of virtual channels, service type and / or mapping relationship between data field attributes and virtual channels, encapsulation strategy, priority of each virtual channel, capacity of each logical buffer area and / or preset flow control conditions of each logical buffer area according to data transmission requirements.

Claims

1. A method of data transmission based on virtual lanes, characterized in that, The method includes: Acquire transaction data transferred across chips; The transaction data is classified according to its business type and / or data field attributes, and virtual channels are allocated to the transaction data based on the classification results. Based on the virtual channel, the corresponding transaction data is encapsulated to generate a data transmission unit carrying virtual channel identification information, and then sent to the receiving end. The receiving end caches the data transmission units of different virtual channels into the corresponding logical cache areas according to the virtual channel identification information. The receiving end monitors the cache status parameters of each of the logical cache areas. When the cache status parameters corresponding to the target virtual channel meet the preset flow control conditions, it generates flow control information carrying the target virtual channel identification information and feeds it back to the sending end. The data transmission status of the target virtual channel is adjusted according to the flow control information, while maintaining the data transmission of other virtual channels.

2. The virtual lane based data transfer method of claim 1, wherein, The transmitting end and the receiving end are connected through a single data channel, and the data channel can only transmit one data transmission unit at a time. The method further includes: Configure corresponding priorities for different virtual channels; When multiple virtual channels have data transmission units to be sent simultaneously, arbitration is performed according to the priority of each virtual channel, and the data transmission units of the higher-priority virtual channels are sent first through the data channel.

3. The virtual lane based data transfer method of claim 2, wherein, The specific steps for arbitration based on the priority of each virtual channel are as follows: When a data transmission unit of a virtual channel is in the transmission state, the data transmission state of the virtual channel is maintained until the data transmission unit completes transmission, and arbitration is re-performed according to the priority of each virtual channel after transmission is completed.

4. The virtual lane based data transfer method of claim 1, wherein, The logical cache areas physically belong to the same shared storage space. The logical cache areas corresponding to each virtual channel are logically divided in the shared storage space based on the virtual channel identification information, and each maintains its corresponding data cache status parameters.

5. The virtual lane based data transfer method of claim 4, wherein, The logical partitioning is implemented using linked lists: a linked list is allocated to each virtual channel in the shared storage space, and the data transmission units of each virtual channel are connected in series through the corresponding linked lists to form the corresponding logical cache area.

6. The virtual lane based data transfer method according to claim 4 or 5, wherein, The cache status parameters include the occupancy of the logical cache area, and the preset flow control conditions include the occupancy reaching the backpressure start threshold.

7. The virtual lane based data transfer method of claim 6, wherein, The method further includes: The propagation delay time of the flow control information from the receiving end to the sending end is obtained; Based on the propagation delay time and the data transmission rate of the target virtual channel, the number of data transmission units that can be transmitted within the propagation delay time is calculated, which is taken as the amount of data in transit of the target virtual channel. Based on the amount of data in transit, reserve corresponding buffer space for the logical cache area corresponding to the target virtual channel; The backpressure start threshold is set by subtracting the buffer space size from the capacity of the logical buffer area, so that the data transmission unit arriving before the flow control information takes effect does not exceed the capacity of the logical buffer area.

8. The virtual lane based data transfer method of claim 7, wherein, The method further includes: When the occupancy of the logical buffer area corresponding to the target virtual channel decreases to below the backpressure release threshold, the receiving end generates flow control release information carrying the target virtual channel identification information and feeds it back to the sending end; The sending end resumes data transmission of the target virtual channel based on the flow control release information; Wherein, the backpressure release threshold is lower than the backpressure start threshold, so as to form a hysteresis interval between the backpressure start threshold and the backpressure release threshold, and the cache capacity corresponding to the hysteresis interval is greater than the buffer space corresponding to the amount of data in transit.

9. The virtual lane based data transfer method of claim 2, wherein, The flow control information is fed back to the sending end through a control channel independent of the data channel.

10. A virtual lane based data transmission system, characterized by, The system includes a transmitter and a receiver. The transmitter includes a transmitter adapter and an encapsulation module, and the receiver includes a receiver adapter. The transmitting adapter is used to acquire transaction data transmitted across chips; The sending adapter is also used to classify the transaction data according to the service type and / or data field attributes of the transaction data, and to allocate virtual channels to the transaction data based on the classification results; The encapsulation module is used to encapsulate the corresponding transaction data based on the virtual channel, generate a data transmission unit carrying virtual channel identification information, and send it to the receiving adapter. The receiving adapter is used to cache the data transmission units of different virtual channels into corresponding logical cache areas according to the virtual channel identification information. The receiving adapter is used to monitor the cache status parameters of each logical cache area. When the cache status parameters corresponding to the target virtual channel meet the preset flow control conditions, it generates flow control information carrying the target virtual channel identification information and feeds it back to the sending adapter. The transmitting adapter is also used to adjust the data transmission status of the target virtual channel according to the flow control information, and to maintain the data transmission of other virtual channels.

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