Memory controller and queue scheduling method
Patent Information
- Application Number
- CN202611221212.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-12
- Publication Date
- 2026-11-03
AI Technical Summary
In the prior art, the memory controller of the system-on-chip uses a fixed polling method in the cross-clock domain path, which leads to queue congestion and makes it impossible to effectively perceive the actual cache amount of each channel. This results in the accumulation of packets on some channels, blocking the writing of packets on the DDR side and reducing the system bandwidth utilization.
The memory controller collects the cache count of each response channel in real time, and combines multi-level thresholds to divide channel priorities, thereby achieving dynamic adaptive hierarchical scheduling. High-load channels with the risk of cache overflow are prioritized for scheduling to avoid the response queue from being full.
It effectively alleviates the request flow pressure on the memory controller, reduces request latency, improves bandwidth utilization, reduces the probability of queue congestion, and optimizes overall transmission performance.
Smart Images
Figure CN123030532A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuits, and more particularly to a memory controller and a queue scheduling method. Background Technology
[0002] The System-on-Chip (SoC) integrates a DDR (Double Data Rate) controller and a Network-on-Chip (NoC) architecture. Since their clocks are asynchronous, a cross-clock domain path is needed to transmit CHI (Coherent Hub Interface) protocol response messages. The DDR controller uses a slow write clock, routing messages to multiple independent FIFO (First In First Out) response channels based on message type, and transmitting read / write pointers synchronously via Gray code. The NoC uses a fast read clock, outputting only a single response per cycle, relying on arbitration logic to select channels. Under fluctuating traffic, some channels are prone to rapid message accumulation. Existing solutions employ fixed-mask polling arbitration, determining scheduling based on queue eligibility, without considering the actual buffer size of each channel. If multiple channels contain messages, arbitration still strictly follows queue order, with each channel equally allocated scheduling slots. Even if a channel's message count is nearing its queue limit, it still needs to wait several cycles before receiving a poll. Therefore, the continuous writing of response messages will cause the cache of this channel to keep increasing until the queue is full, blocking the writing of messages on the DDR side, which will prolong the request processing process of the whole machine, further triggering request retransmission and reducing system bandwidth. Summary of the Invention
[0003] The purpose of this application is to provide a memory controller and a queue scheduling method that can solve the problem of queue congestion caused by the use of fixed polling in the prior art, alleviate the request flow pressure of the controller, reduce request latency, and improve bandwidth utilization.
[0004] To achieve the above objectives, embodiments of this application provide a memory controller for communicating with an on-chip interconnect network. The memory controller includes an interconnect high-speed interface module, a message generation module, a write module, and a read module, which are sequentially and communicatively connected. The high-speed interconnect interface module is used to receive data acquisition requests from the on-chip interconnect network; The message generation module is used to respond to the data acquisition request and generate a corresponding response message, which is output according to type. The write module includes at least two response channels, each of which is used to receive and cache the response message of the corresponding type. The write module collects the current cached quantity of each response channel in real time and synchronizes the current cached quantity to the read module. The read module has a preset cache threshold for each response channel. The read module determines the priority of each response channel based on the comparison result between the current cache quantity and the corresponding cache threshold, and outputs response messages to the on-chip interconnect network based on the priority of each response channel.
[0005] In this embodiment, the memory controller collects the actual cache quantity of each response channel in real time and dynamically classifies channel priorities based on the comparison between the actual cache quantity and the cache threshold. This enables hierarchical scheduling of response packets, prioritizing high-load channels with a risk of buffer overflow and preventing the problem of response queues becoming full and blocking packet transmission from the source. Compared with existing arbitration algorithms that rely solely on channel non-empty signals for fixed-order polling, this application can centrally schedule resources to quickly release backlogged packets in congested channels when a large number of response packets accumulate in some queues. This reduces the overall probability of memory controller blockage caused by single-channel buffer overflow, effectively alleviates congestion pressure on the memory controller's uplink request path, reduces latency losses from packet retransmission and request queuing, and improves the data bandwidth utilization between the on-chip interconnect network and the memory controller.
[0006] In one possible implementation, the cache threshold includes a quantity threshold and a variance threshold.
[0007] In this embodiment, the quantity threshold is used to determine whether there is an overflow risk in a single channel, the variance threshold is used to identify the situation where all channels are not overloaded but the load distribution between channels is extremely uneven, and the setting of the cache threshold can reduce the probability of channel blocking in the memory controller, balance the transmission pressure of each channel, and optimize the overall transmission bandwidth.
[0008] In one possible implementation, if the current cache count of all response channels is less than the specified count threshold, and the total cache variance of all response channels is less than the specified variance threshold, then all response channels are of low priority.
[0009] In this embodiment, when the number of caches for all response channels is less than the number threshold and the overall cache variance is less than the variance threshold, it is determined that the load on each channel is uniform and the overall pressure is low. All response channels are uniformly set to low priority and global round-robin scheduling is performed to ensure the fairness of scheduling of each response channel under the normal working condition of system load balancing, so that the response messages of each channel are output smoothly and orderly.
[0010] In one possible implementation, if the current cache count of all response channels is less than the specified threshold, and the total cache variance of all response channels is greater than or equal to the specified variance threshold, the response channel with a current cache count higher than the average cache count of all response channels is considered to have high priority.
[0011] In this embodiment, under the premise of light load where all channels have not reached the congestion threshold, the system identifies the multi-channel load imbalance by detecting the overall cache variance and prioritizes channels with a cache quantity higher than the average value, thereby enabling targeted priority scheduling. This allows for pre-processing before congestion occurs, preventing slight load imbalance from gradually deteriorating into severe backlog and reducing the probability of channel blockage.
[0012] In one possible implementation, if the current cache size of any response channel is greater than or equal to the stated threshold, that response channel is of high priority.
[0013] In this embodiment, when the number of buffers in any response channel reaches the threshold, it indicates that there are many messages in that channel and there is a risk of congestion. At this time, the channel is promoted to high priority, which can quickly schedule the response queue that is about to overflow, avoid the problem of a single channel queue being full and unable to receive new response messages, and improve the overall throughput of the memory controller.
[0014] In one possible implementation, the cache threshold is a capacity threshold. If any response channel carries a preset identifier and the current cache quantity of the response channel is greater than the capacity threshold, the response channel is of high priority. The preset identifier is used to indicate that the current response channel contains response messages that are sensitive to storage latency.
[0015] In this embodiment, an additional capacity threshold determination mechanism is set for special marked channels carrying delay-sensitive messages to provide differentiated protection for delay-sensitive services. When the buffer capacity of the channel is close to full, the scheduling priority is increased in a timely manner, which can avoid delay-sensitive response messages from timeout and retransmission due to scheduling lag, thereby improving the real-time transmission performance of critical services in the system.
[0016] In one possible implementation, the capacity threshold is determined based on the difference between the maximum buffer size of the response channel and a preset fixed value D, wherein the preset fixed value satisfies: 0≤D≤2.
[0017] In this embodiment of the application, the capacity threshold can determine the critical state when the channel is about to be fully loaded, thus enabling early prediction of overflow risk.
[0018] In one possible implementation, the read module has built-in queue scheduling logic, which is configured as follows: The target response channel is selected based on the priority of each response channel, the response message in the target response channel is read and output to the on-chip Internet of Things.
[0019] In this embodiment, the queue scheduling logic uses the real-time priority of each channel as the scheduling basis and dynamically selects the target response channel for message output. Compared with the traditional fixed-order mechanical polling method, this application realizes a dynamic and adaptive intelligent scheduling logic, which makes the scheduling behavior conform to the current channel load pressure distribution and improves the resource utilization of the memory controller.
[0020] In one possible implementation, the queue scheduling logic is specifically configured as follows: When at least one high-priority response channel exists, the target response channel is selected only from all high-priority response channels in a round-robin manner, the response message in the target response channel is read and output to the on-chip interconnect network; When all response channels are of low priority, the target response channel is selected from all low priority response channels in a round-robin manner, the response message in the target response channel is read and output to the on-chip interconnect network.
[0021] In this embodiment, when a high-priority channel exists, congestion is alleviated only by polling within the high-priority channel. Once all channels are lightly loaded, global equal polling is then performed. This mechanism ensures that queues that are about to be fully loaded are prioritized under congested conditions, improving channel congestion in multi-channel asynchronous response scenarios and increasing the resource utilization of the memory controller.
[0022] To achieve the above objectives, this application provides a queue scheduling method applied to a memory controller. The memory controller includes an interconnect high-speed interface module, a message generation module, a write module, and a read module. The write module includes at least two response channels, each of which is used to receive and buffer response messages of a corresponding type. The read module has a preset buffer threshold for each response channel. The method includes: The high-speed interconnect interface module receives data acquisition requests from the on-chip interconnect network. The message generation module responds to the data acquisition request by generating a corresponding response message, which is then output according to its type. The write module collects the current cache count for each response channel in real time and synchronizes the current cache count to the read module. The read module determines the priority of each response channel based on the comparison result between the current cache quantity and the corresponding cache threshold, and outputs a response message to the on-chip interconnect network based on the priority of each response channel.
[0023] In this embodiment, the memory controller collects the actual cache quantity of each response channel in real time and dynamically classifies channel priorities based on the comparison between the actual cache quantity and the cache threshold. This enables hierarchical scheduling of response packets, prioritizing high-load channels with a risk of buffer overflow and preventing the problem of response queues becoming full and blocking packet transmission from the source. Compared with existing arbitration algorithms that rely solely on channel non-empty signals for fixed-order polling, this application can centrally schedule resources to quickly release backlogged packets in congested channels when a large number of response packets accumulate in some queues. This reduces the overall probability of memory controller blockage caused by single-channel buffer overflow, effectively alleviates congestion pressure on the memory controller's uplink request path, reduces latency losses from packet retransmission and request queuing, and improves the data bandwidth utilization between the on-chip interconnect network and the memory controller. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of a cross-clock domain transmission architecture provided in the prior art; Figure 2 This is a flowchart of a cross-clock structure using polling arbitration with multiple request sources, provided in the prior art; Figure 3 This is a schematic diagram of partial channel congestion provided in existing technology; Figure 4 This is a schematic diagram of the structure of a memory controller provided in an embodiment of this application; Figure 5 This is a schematic diagram of the queue scheduling logic provided in an embodiment of this application; Figure 6 This is a queue scheduling method provided in an embodiment of this application; Figure 7 This is a queue scheduling method provided in an embodiment of this application; Figure 8 This is a queue scheduling method provided in an embodiment of this application; Figure 9 This is a queue scheduling method provided in an embodiment of this application; Figure 10 This is a flowchart of a queue scheduling method provided in an embodiment of this application. Detailed Implementation
[0025] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0026] See Figure 1 , Figure 1This is a schematic diagram of a cross-clock domain transmission architecture provided in existing technology. In current system-on-chip (SoC) designs, the clock frequency of the DDR controller and the clock frequency of the on-chip interconnect network are often designed asynchronously, belonging to different clock domains. When the DDR controller needs to send a response message back to the upstream on-chip interconnect network, a cross-clock domain transmission architecture must be used. This cross-clock domain transmission architecture includes write and read modules belonging to two asynchronous clock domains, such as... Figure 1 The right side of the image represents the write module, which operates in the write clock domain corresponding to the DDR controller. Figure 1 The left side of the image represents the read module, which operates in the read clock domain corresponding to the on-chip interconnect network. Since the on-chip interconnect network clock frequency is higher than the DDR controller clock, response messages need to be transmitted across domains from the slow write clock domain to the fast read clock domain. The process of transmitting response messages across clock domains is as follows: 1. After a request enters the DDR controller, it will generate a response message at different processing nodes according to the request type. These processing nodes are functional sub-modules that perform corresponding business processing and generate response messages for various requests sent from upstream. These include read transaction processing nodes and write transaction processing nodes. Specifically, after receiving a read request from upstream, the read transaction processing node accesses the external storage granules and reads the data, generating a read data response message. After receiving a write request from upstream, the write transaction processing node performs data writing operations on the external storage granules and generates a write data response message. 2. Response messages from different processing nodes enter the write module of the cross-clock domain structure through multiple response channels on the far right of the diagram. There are 5 channels in the diagram. In practice, different numbers of response channels can be enabled according to different controller design structures. 3. After the response message in each channel is parsed, it enters the corresponding storage information queue; 4. The queue generates a write pointer to indicate the status of the response messages stored under the current write clock. Whenever the DDR controller sends a response message, the pointer changes, and the change pattern conforms to Gray code. It is also synchronized to the read clock domain through two levels. 5. The read clock domain processing logic in the read module maintains a read pointer for each response channel. Whenever the arbitration logic decides to read a response message from that response channel, the pointer changes in accordance with Gray code and is synchronized across two levels to the write clock domain. 6. When the read and write pointers are different, it indicates that there are unsent response messages in the channel. At this time, multiple channels may be in a state where there are still response messages that have not been sent in each clock cycle. 7. When the high-speed interconnect interface module outputs a message, it will give a valid signal. At this time, the built-in polling arbitration logic in the read clock domain receives the FIFO non-empty signal of each channel and selects a single response channel from multiple channels with messages. 8. The successful arbitration response channel outputs a response message to the high-speed interconnect interface module according to the first-in-first-out rule, and sends it to the upstream on-chip interconnect network. At the same time, the read pointer changes, and the change is transmitted to the write module through two-level synchronization. The write module generates new space to store the newly generated response message of the DDR controller.
[0027] Because response messages are generated asynchronously across multiple nodes within the DDR controller, message backlog is possible across multiple response channels. Coupled with the upstream CHI protocol's credit flow control mechanism, scenarios with a large backlog of response messages on a single channel are easily encountered. Once the transmission link credit is restored, the arbitration logic needs to select one message from multiple backlogged response sources for transmission scheduling. Current technology relies solely on channel non-empty signals to perform fixed-order polling arbitration, failing to detect the actual message backlog on each channel. This can easily lead to some channels becoming queue-complete, resulting in a decrease in system bandwidth.
[0028] Most existing cross-clock architectures use algorithms that arbitrate through multiple request sources, with the following algorithm logic: Figure 2 As shown, Figure 2 This is a flowchart of a cross-clock structure using multiple request sources for arbitration, provided in the existing technology. The algorithm logic satisfies: 1. After the controller reset is completed, the arbitration logic starts to work. The request source indication signal starts from the least significant bit. For example, if there are a total of 5 channels, the signal width is request [4:0], and the current bit is request [0]. 2. Determine if there is a valid request in the current bit. A valid request means that the request signal of the corresponding channel is pulled high. If the request signal of the current bit is pulled high, then further determine if there is a request masking signal in the bit. The masking signal is an internal signal used by the arbitration to mark the channel selected in the previous clock cycle. In the first round of arbitration after the chip is reset, the masking signals of all channels will be cleared to zero and the level will be low. Therefore, if the initial current bit request [0] signal is pulled high and there is no masking signal, request [0] will win the arbitration directly and be the output result of this round. If the current bit request signal is not pulled high, it means that there is no message to be sent in the channel. Then skip the request source directly, switch the next bit to the new current bit, re-execute the request signal judgment, and loop until the channel that wins the arbitration is selected. 3. After successful arbitration, a masking signal for the current bit is generated, and the arbitration result for the current bit is output, proceeding to the next arbitration logic step; 4. If, in the next round, no other bit besides the current bit that is blocked has any requests, then the current bit will continue to be selected; otherwise, the next bit that is pulled up will become the current bit and arbitration will begin. 5. Make judgments according to step 2, and the overall logic will continue to loop.
[0029] In actual use, the number of response messages stored by each request source is different and the accumulation rate is different. According to the existing arbitration logic, if all 5 source requests [4:0] are high, but only request [1] has accumulated a number of response messages that are about to reach the limit, when using the existing arbitration logic, the arbitration will strictly allocate reading permissions in a fixed order and will not identify the difference in the amount of real-time cached messages in each channel. It will allocate equal scheduling clock cycles to requests [0] to [4], and will not tilt scheduling resources towards request [1] which is about to be full. It will not be able to quickly consume the response messages accumulated in request [1]. The continuously flowing new messages will continuously fill the FIFO queue of request [1], which will result in some channels being congested. For example, see Figure 3 , Figure 3 This is a schematic diagram of partial channel congestion provided in the prior art. At this time, a large number of unsent response messages are piled up in response channels 1 and 2. It is only every 5 clock cycles that a response message can be sent by this channel. During this period, the DDR controller may still return response messages from channel 1. At this time, because channel 1 has no position to receive, the subsequent transmission of response messages that do not belong to channel 1 will be blocked, thereby blocking the pipeline of the controller interface logic to process the requests sent from the upstream, resulting in an increase in the judgment of resending requests.
[0030] To address the problem of queue congestion caused by the inability of existing fixed polling arbitration mechanisms to perceive the actual load of each response channel, this application provides a memory controller that uses the real-time collection of the number of cached packets in each response channel as the basis for arbitration scheduling. Combined with multi-level thresholds to divide channel priorities, it achieves adaptive hierarchical polling arbitration, prioritizing the scheduling of high-load channels that are close to full load, thus relieving channel backlog pressure in advance and avoiding transmission blockage caused by queue fullness.
[0031] See Figure 4 , Figure 4 This is a schematic diagram of a memory controller provided in an embodiment of this application. The memory controller is a DDR controller used for communication with an on-chip interconnect network. The memory controller includes an interconnect high-speed interface module, a message generation module 20, a write module 30, and a read module 40, which are connected in sequence for communication. The high-speed interconnect interface module 10 is used to receive data acquisition requests from the on-chip interconnect network; Message generation module 20 is used to respond to data acquisition requests, generate corresponding response messages, and output response messages according to type. The write module 30 includes at least two response channels. Each response channel is used to receive and cache response messages of the corresponding type. The write module 30 collects the current cached quantity of each response channel in real time and synchronizes the current cached quantity to the read module 40. The read module 40 has a preset cache threshold for each response channel. The read module 40 determines the priority of each response channel based on the comparison between the current cache quantity and the corresponding cache threshold, and outputs response messages to the on-chip interconnect network based on the priority of each response channel.
[0032] For example, data acquisition requests are various service requests issued by the on-chip interconnect network to the DDR controller. The DDR controller receives these service requests through the high-speed interconnect interface module 10. These service requests include CHI transaction requests such as read data requests, write data requests, and consistency query requests. Response messages are feedback messages sent by the DDR controller to the upstream on-chip interconnect network after completing the corresponding data processing and storage interaction. These messages include read data responses, write completion responses, and consistency acknowledgment messages. After the message generation module 20 defines the transaction type according to the CHI protocol, it needs to add a type identifier to the generated response message. At this time, the message is output to the matching response channel in the write module 30 according to the transaction type to which the message belongs. For example, read data response messages are uniformly output to response channel 1, write completion response messages are uniformly output to response channel 2, and consistency acknowledgment messages are output to response channel 3, realizing the separate transmission of different service response messages.
[0033] The write module 30 includes n response channels, where n ≥ 2. The number of channels can be flexibly configured according to the service scale of the memory controller. Each response channel is internally configured with a FIFO (First In First Out) storage queue to buffer response messages of the same type, isolate the transmission process of different types of messages, and avoid message mixing interfering with arbitration scheduling. Each response channel maintains Gray code-encoded write and read pointers. Whenever the write module 30 writes a response message to the FIFO storage queue, the write pointer of the corresponding channel is updated synchronously according to the Gray code rules. Whenever the read module 40 reads a response message from the channel, the read pointer of the corresponding channel is updated synchronously according to the Gray code rules. Based on the pointer positions of the write and read pointers within the same channel, the current buffer quantity in the current FIFO queue is determined.
[0034] The read module 40 has a pre-configurable cache threshold, which can be pre-configured by the system to adapt to different business scenarios. This cache threshold corresponds one-to-one with each response channel. The read module 40 compares the real-time cached message count of a single response channel with the preset cache threshold for that channel, and distinguishes the scheduling priority of different response channels based on the comparison. Compared with the existing technology that relies solely on the non-empty signal of whether a channel has messages for fixed-order polling, this application dynamically divides priorities based on the comparison result of the channel's actual cached load and cache threshold. This can accurately identify response channels with queue overflow risk and set these channels to higher scheduling priority. Through this priority scheduling method, channels with excessive load can be cleared first.
[0035] In this embodiment, the memory controller collects the actual cache quantity of each response channel in real time and dynamically classifies channel priorities based on the comparison between the actual cache quantity and the cache threshold. This enables hierarchical scheduling of response packets, prioritizing high-load channels with a risk of buffer overflow and preventing the problem of response queues becoming full and blocking packet transmission from the source. Compared with existing arbitration algorithms that rely solely on channel non-empty signals for fixed-order polling, this application can centrally schedule resources to quickly release backlogged packets in congested channels when a large number of response packets accumulate in some queues. This reduces the overall probability of memory controller blockage caused by single-channel buffer overflow, effectively alleviates congestion pressure on the memory controller's uplink request path, reduces latency losses from packet retransmission and request queuing, and improves the data bandwidth utilization between the on-chip interconnect network and the memory controller.
[0036] Furthermore, the cache threshold includes a quantity threshold and a variance threshold.
[0037] For example, the quantity threshold is used to compare the current cache quantity of a single response channel to determine whether a single channel is experiencing packet backlog. The quantity threshold can be flexibly configured based on the total FIFO queue depth of each response channel. For instance, for a response channel carrying high-frequency read data response packets, the quantity threshold can be set to 70% of the corresponding total queue depth to identify channel overload in advance; conversely, for a response channel carrying low-frequency consistency response packets, the quantity threshold can be set to 85% of the corresponding total queue depth to fully utilize queue storage space and reduce idle hardware resources. The variance threshold is used to compare the overall variance calculation result of the cache quantity of all response channels to identify situations where all channels are not overloaded but the load distribution among channels is extremely uneven. The variance threshold can be customized based on the system's allowed range of load differences between channels. For example, when the system requires that the difference in the cached packet quantity of each channel should not be too large, the variance threshold can be set to a smaller value, and once the channel load dispersion exceeds the limit, balanced scheduling can be intervened in advance.
[0038] In this embodiment, the quantity threshold is used to determine whether there is an overflow risk in a single channel, the variance threshold is used to identify the situation where all channels are not overloaded but the load distribution between channels is extremely uneven, and the setting of the cache threshold can reduce the probability of channel blocking in the memory controller, balance the transmission pressure of each channel, and optimize the overall transmission bandwidth.
[0039] Furthermore, the cache threshold can also be a capacity threshold, which is determined based on the difference between the maximum cache size of the response channel and a preset fixed value D, where the preset fixed value satisfies: 0≤D≤2.
[0040] For example, the maximum buffer size of a response channel is the total depth of the FIFO queue, representing the maximum number of response messages that the channel can hold. Assuming the total depth of the FIFO queue for a response channel is 64, when the preset fixed value D is 1, the corresponding capacity threshold for that channel is 63. The preset fixed value is set to a range of 0 to 2 because the capacity threshold only applies to special response channels used for caching latency-sensitive messages. A reserved space of 0 to 2 maximizes the utilization of all storage resources of the response channel, avoiding large areas of idle queue space and saving hardware storage area.
[0041] It should be noted that the quantity threshold is set for regular business response channels, and is based solely on the total amount of real-time buffered messages in a single channel for overload judgment. It is generally set in the middle to later part of the total FIFO depth to identify regular congestion conditions where ordinary channels accumulate. The capacity threshold, on the other hand, is specifically matched for special-identification response channels carrying latency-sensitive messages. Its value is obtained by subtracting a fixed value from the total FIFO queue depth of the corresponding response channel. The warning position is closer to the queue full-load threshold, and the capacity threshold reserves less buffer space. It can trigger high-priority scheduling in advance before the FIFO is completely full, prioritizing the rapid output of latency-sensitive response messages and avoiding timeout retransmission issues caused by queue overflow for critical transactions.
[0042] In this embodiment of the application, the capacity threshold can determine the critical state when the channel is about to be fully loaded, thus enabling early prediction of overflow risk.
[0043] Further, see Figure 5 , Figure 5 This is a schematic diagram of the queue scheduling logic provided in the embodiments of this application. The embodiments of this application classify the real-time buffer quantity of each response channel based on the quantity threshold A, variance threshold B, and capacity threshold C, and divide different scheduling priorities according to the judgment results. There are the following four cases: 1) If the current cache count of all response channels is less than the count threshold A, and the total cache variance of all response channels is less than the variance threshold B, then all response channels are of low priority.
[0044] For example, see Figure 6 , Figure 6This application provides a queue scheduling method. In the figure, D1 to D5 correspond to 5 independent response channels. The squares filled with diagonal lines in each response channel represent the currently cached response messages, and the blank squares represent the remaining storage space of the FIFO queue. At this time, the current cache quantity of all 5 response channels is less than the quantity threshold A. Simultaneously, after calculating the total cache variance based on the cache quantity of the 5 response channels, it is determined that the total cache variance is less than the variance threshold B. Under this condition, there is no risk of FIFO queue overflow for any response channel. Therefore, the arbitration logic uniformly classifies all response channels as low priority and performs basic fixed-order round-robin scheduling. At this time, the response messages of each channel are read sequentially in the fixed order of D1→D2→D3→D4→D5. Each channel receives an equal scheduling opportunity according to a preset round-robin period, smoothly completing the orderly output of multi-channel response messages, adapting to the normal operating scenario of system load balancing.
[0045] In this embodiment, when the number of caches for all response channels is less than the number threshold and the overall cache variance is less than the variance threshold, it is determined that the load on each channel is uniform and the overall pressure is low. All response channels are uniformly set to low priority and global round-robin scheduling is performed to ensure the fairness of scheduling of each response channel under the normal working condition of system load balancing, so that the response messages of each channel are output smoothly and orderly.
[0046] 2) If the current cache count of all response channels is less than the count threshold A, and the total cache variance of all response channels is greater than or equal to the variance threshold B, the response channel with a current cache count higher than the average cache count of all response channels is of high priority.
[0047] For example, see Figure 7 , Figure 7 This application provides a queue scheduling method similar to Case 1, where the current cache counts of response channels D1-D5 have not reached the threshold A. However, there is a significant difference in the cached message counts among the five channels, and the calculated total cache variance is greater than or equal to the variance threshold B. In this case, the arbitration logic first calculates the average cache count of all channels, then selects D1 and D3 as response channels with current cache counts higher than the average. D1 and D3 are designated as high-priority channels, while D2, D4, and D5 are designated as low-priority channels. During scheduling, the arbitration logic prioritizes polling the high-priority channels in the order of D1→D3, prioritizing the consumption of response messages within channels with higher backlogs to proactively avoid subsequent load imbalance. Subsequent decisions are made only after the cache counts of D1 and D3 fall below the average.
[0048] In this embodiment, under the premise of light load where all channels have not reached the congestion threshold, the system identifies the multi-channel load imbalance by detecting the overall cache variance and prioritizes channels with a cache quantity higher than the average value, thereby enabling targeted priority scheduling. This allows for pre-processing before congestion occurs, preventing slight load imbalance from gradually deteriorating into severe backlog and reducing the probability of channel blockage.
[0049] 3) If the current cache count of any response channel is greater than or equal to the count threshold A, the response channel is of high priority.
[0050] For example, see Figure 8 , Figure 8 This application provides a queue scheduling method where the current cache counts of channels D1 and D3 both exceed the threshold A, posing an overflow risk. Therefore, D1 and D3 are classified as high-priority channels, while the cache counts of channels D2, D4, and D5 do not exceed the threshold A and are classified as low-priority channels. During scheduling, the arbitration logic prioritizes polling the high-priority channels, reading response messages sequentially in the order of D1→D3. This prioritizes consuming the messages accumulated in the high-load channels, quickly reducing the cache count of the two channels. Once the current cache counts of D1 and D3 fall below the threshold A, further judgment is made.
[0051] In this embodiment, when the number of buffers in any response channel reaches the threshold, it indicates that there are many messages in that channel and there is a risk of congestion. At this time, the channel is promoted to high priority, which can quickly schedule the response queue that is about to overflow, avoid the problem of a single channel queue being full and unable to receive new response messages, and improve the overall throughput of the memory controller.
[0052] 4) If any response channel carries a preset identifier and the current cache quantity of the response channel is greater than the capacity threshold C, the response channel is of high priority; wherein, the preset identifier is used to indicate that the current response channel contains response messages that are sensitive to storage latency.
[0053] For example, storage latency sensitivity means that this type of response message has strict constraints on transmission waiting time or transaction completion time. If it accumulates in the FIFO queue for a long time without being output in time, it is easy to trigger timeout, retransmission, and other conditions. For example, this type of response message can be a consistent acknowledgment message under the CHI protocol. See also Figure 9 , Figure 9This application provides a queue scheduling method where D3 is a special response channel carrying a preset identifier, specifically used to cache latency-sensitive response messages. The remaining channels D1, D2, D4, and D5 are ordinary service channels. When the current cache size of D3 is greater than the capacity threshold C, it means that the FIFO queue of this channel has very few empty slots and is about to reach its full capacity. At this time, the arbitration logic designates D3 as the highest priority channel, prioritizes polling and reading response messages in D3, releases the FIFO queue storage space, and avoids latency-sensitive messages accumulating until the queue is completely full, preventing the reception of new transactions. Subsequent judgments are made when the current cache size of D3 falls back to the capacity threshold C.
[0054] It should be noted that the channel scheduling priority corresponding to Case 4 is the highest priority in all operating conditions. At this time, even if the judgment conditions of Case 1, Case 2 or Case 3 are triggered at the same time, the system arbitration logic will prioritize the execution of the scheduling strategy corresponding to Case 4 and prioritize the output of the response message in the special identifier channel carrying the delay-sensitive message.
[0055] In this embodiment, an additional capacity threshold determination mechanism is set for special marked channels carrying delay-sensitive messages to provide differentiated protection for delay-sensitive services. When the buffer capacity of the channel is close to full, the scheduling priority is increased in a timely manner, which can avoid delay-sensitive response messages from timeout and retransmission due to scheduling lag, thereby improving the real-time transmission performance of critical services in the system.
[0056] Furthermore, the read module 40 has built-in queue scheduling logic, which is configured as follows: The target response channel is selected based on the priority of each response channel, the response message in the target response channel is read, and it is output to the on-chip interconnect network.
[0057] For example, the queue scheduling logic is a timing logic unit within the read module 40 that completes arbitration routing and message reading and distribution. It combines the quantity threshold, variance threshold, and capacity threshold configured in the registers to determine four operating conditions and assign a corresponding scheduling priority to each response channel. The target response channel is the response channel currently granted message reading permission, selected by the queue scheduling logic according to its priority. The queue scheduling logic follows a priority-to-lower-downward search order, prioritizing the search of high-priority channel groups and selecting a channel as the target response channel for this round. After selecting the target response channel, the queue scheduling logic reads a response message from the FIFO queue of that channel according to the first-in-first-out rule and outputs it to the upstream on-chip interconnect network. After this round of reading is completed, it re-traverses all channel priorities to update the target response channel for the next round.
[0058] In this embodiment, the queue scheduling logic uses the real-time priority of each channel as the scheduling basis and dynamically selects the target response channel for message output. Compared with the traditional fixed-order mechanical polling method, this application realizes a dynamic and adaptive intelligent scheduling logic, which makes the scheduling behavior conform to the current channel load pressure distribution and improves the resource utilization of the memory controller.
[0059] Furthermore, the queue scheduling logic is specifically configured as follows: When there is at least one high-priority response channel, the target response channel is selected only from all high-priority response channels in a round-robin manner, the response message in the target response channel is read and output to the on-chip interconnect network; When all response channels are of low priority, the target response channel is selected in a round-robin manner from all low-priority response channels, the response message in the target response channel is read and output to the on-chip interconnect network.
[0060] For example, scheduling resources will be tilted towards high-priority channel groups. Only when there are no high-priority channels in the system, i.e., when the load of all channels is stable, will the full-channel equal polling mode be activated to ensure the smooth parallel operation of multi-channel services. Taking case 2 as an example, D1 and D3 are classified as high-priority channels, and D2, D4, and D5 are low-priority channels. At this time, the system has high-priority channels. The queue scheduling logic only polls between D1 and D3 to select the target response channel. It continuously reads the response packets in the two channels according to the FIFO rule, gradually reducing the load difference between the channels, until the buffer count of D1 and D3 falls below the average value. The two channels are then converted to low priority. After there are no high-priority channels in the system, the scheduling logic switches to full-channel polling of D1, D2, D3, D4, and D5, and reads the packets of each channel for output in sequence.
[0061] In this embodiment, when a high-priority channel exists, congestion is alleviated only by polling within the high-priority channel. Once all channels are lightly loaded, global equal polling is then performed. This mechanism ensures that queues that are about to be fully loaded are prioritized under congested conditions, improving channel congestion in multi-channel asynchronous response scenarios and increasing the resource utilization of the memory controller.
[0062] See Figure 10 , Figure 10 This is a flowchart of a queue scheduling method provided in an embodiment of this application. The queue scheduling method is applied to a memory controller, which includes an interconnect high-speed interface module, a message generation module, a write module, and a read module. The write module includes at least two response channels, each used to receive and buffer response messages of a corresponding type. The read module has a preset buffer threshold for each response channel. The queue scheduling method includes: S1. Receive data acquisition requests from the on-chip interconnect network via the high-speed interconnect interface module; S2. The message generation module responds to the data acquisition request, generates the corresponding response message, and outputs the response message according to its type. S3. The write module collects the current cache count of each response channel in real time and synchronizes the current cache count to the read module. S4. The priority of each response channel is determined by the reading module based on the comparison result between the current cache quantity and the corresponding cache threshold, and the response message is output to the on-chip interconnection network based on the priority of each response channel.
[0063] It is worth noting that the working process of the queue scheduling method described in this application embodiment can refer to the working process of the memory controller described in the above embodiment, and will not be repeated here.
[0064] In this embodiment, the memory controller collects the actual cache quantity of each response channel in real time and dynamically classifies channel priorities based on the comparison between the actual cache quantity and the cache threshold. This enables hierarchical scheduling of response packets, prioritizing high-load channels with a risk of buffer overflow and preventing the problem of response queues becoming full and blocking packet transmission from the source. Compared with existing arbitration algorithms that rely solely on channel non-empty signals for fixed-order polling, this application can centrally schedule resources to quickly release backlogged packets in congested channels when a large number of response packets accumulate in some queues. This reduces the overall probability of memory controller blockage caused by single-channel buffer overflow, effectively alleviates congestion pressure on the memory controller's uplink request path, reduces latency losses from packet retransmission and request queuing, and improves the data bandwidth utilization between the on-chip interconnect network and the memory controller.
[0065] The above description is the preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.
Claims
1. A memory controller, characterized in that, For communicating with an on-chip interconnect network, the memory controller includes an interconnect high-speed interface module, a message generation module, a write module, and a read module that are sequentially connected in communication. The high-speed interconnect interface module is used to receive data acquisition requests from the on-chip interconnect network; The message generation module is used to respond to the data acquisition request and generate a corresponding response message, which is output according to type. The write module includes at least two response channels, each of which is used to receive and cache the response message of the corresponding type. The write module collects the current cached quantity of each response channel in real time and synchronizes the current cached quantity to the read module. The read module has a preset cache threshold for each response channel. The read module determines the priority of each response channel based on the comparison result between the current cache quantity and the corresponding cache threshold, and outputs response messages to the on-chip interconnect network based on the priority of each response channel.
2. The memory controller as described in claim 1, characterized in that, The cache thresholds include a quantity threshold and a variance threshold.
3. The memory controller as described in claim 2, characterized in that, If the current cache count of all response channels is less than the specified threshold, and the total cache variance of all response channels is less than the specified variance threshold, then all response channels are of low priority.
4. The memory controller as described in claim 2, characterized in that, If the current cache count of all response channels is less than the specified threshold, and the total cache variance of all response channels is greater than or equal to the specified variance threshold, the response channel with a current cache count higher than the average cache count of all response channels is considered to have high priority.
5. The memory controller as described in claim 2, characterized in that, If the current cache count of any response channel is greater than or equal to the specified threshold, that response channel is of high priority.
6. The memory controller as described in claim 1, characterized in that, The cache threshold is a capacity threshold. If any response channel carries a preset identifier and the current cache quantity of the response channel is greater than the capacity threshold, the response channel is of high priority. The preset identifier is used to indicate that the current response channel contains response messages that are sensitive to storage latency.
7. The memory controller as described in claim 6, characterized in that, The capacity threshold is determined based on the difference between the maximum buffer size of the response channel and a preset fixed value D, wherein the preset fixed value satisfies: 0≤D≤2.
8. The memory controller as described in any one of claims 1-7, characterized in that, The read module has built-in queue scheduling logic, which is configured as follows: The target response channel is selected based on the priority of each response channel, the response message in the target response channel is read and output to the on-chip Internet of Things.
9. The memory controller as described in claim 8, characterized in that, The queue scheduling logic is specifically configured as follows: When at least one high-priority response channel exists, the target response channel is selected only from all high-priority response channels in a round-robin manner, the response message in the target response channel is read and output to the on-chip interconnect network; When all response channels are of low priority, the target response channel is selected from all low priority response channels in a round-robin manner, the response message in the target response channel is read and output to the on-chip interconnect network.
10. A queue scheduling method, characterized in that, The method is applied to a memory controller, which includes an interconnect high-speed interface module, a message generation module, a write module, and a read module. The write module includes at least two response channels, each of which is used to receive and buffer response messages of a corresponding type. The read module has a preset buffer threshold for each response channel. The method includes: The high-speed interconnect interface module receives data acquisition requests from the on-chip interconnect network. The message generation module responds to the data acquisition request by generating a corresponding response message, which is then output according to its type. The write module collects the current cache count for each response channel in real time and synchronizes the current cache count to the read module. The read module determines the priority of each response channel based on the comparison result between the current cache quantity and the corresponding cache threshold, and outputs a response message to the on-chip interconnect network based on the priority of each response channel.