Display device and driving method thereof, timing controller

Abstract

Embodiments of the present application provide a display device and a driving method thereof, and a timing controller. The display device comprises a display panel, a source driving chip and a timing controller. The source driving chip is electrically connected with the display panel. The timing controller is electrically connected with the source driving chip and obtains a current refresh rate. In a case where the current refresh rate is a first refresh rate, the timing controller outputs a data signal to the source driving chip through a first number of output channels. In a case where the current refresh rate is a second refresh rate, the timing controller outputs the data signal to the source driving chip through a second number of output channels, and closes output channels other than the second number of output channels among the first number of output channels. The second refresh rate is less than the first refresh rate, and the second number of output channels is less than the first number of output channels. The technical solution of the present application reduces the power consumption of the display device in a low refresh rate working state.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and its driving method and timing controller. Background Technology

[0002] In traditional display devices, the timing controller (TCON) typically uses Mini-LVDS (Mini Low Voltage Differential Signaling) to transmit data to the source driver chip.

[0003] To meet the data bandwidth requirements of high refresh rates, timing controllers typically use a larger number of output channels to output data signals to the source driver chip. However, when the display device switches to a low refresh rate operating state, the timing controller still uses the same number of output channels to output data signals to the source driver chip as it does in the high refresh rate operating state. This operating mode increases the overall power consumption of the display device.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of this application is to provide a display device and its driving method and timing controller, which aim to reduce the power consumption of the display device in low refresh rate operation.

[0006] This application provides a display device, the display device comprising: a display panel; a source driver chip electrically connected to the display panel; and a timing controller electrically connected to the source driver chip and configured to acquire a current refresh rate, and, when the current refresh rate is a first refresh rate, output a data signal to the source driver chip through a first number of output channels, and, when the current refresh rate is a second refresh rate, output the data signal to the source driver chip through a second number of output channels, and disable the output channels of the first number of output channels other than the second number of output channels, wherein the second refresh rate is less than the first refresh rate, and the second number of channels is less than the first number of channels.

[0007] In the above-described display device, the timing controller is further configured to output a first level signal to the source driver chip before outputting the data signal to the source driver chip through the output channel of the first number of channels, so that the source driver chip is set to a receiving mode corresponding to the first number of channels, and to control the data formatting module of the timing controller to allocate the data signal to the output channel of the first number of channels.

[0008] In the above-described display device, the timing controller is further configured to output a second level signal to the source driver chip before outputting the data signal to the source driver chip through the output channel of the second channel number, so that the source driver chip is set to a receiving mode corresponding to the second channel number, and to control the data formatting module of the timing controller to allocate the data signal to the output channel of the second channel number.

[0009] In the above-mentioned display device, the timing controller is further configured to cut off the bias current of the output channels other than the output channels of the second number of channels in the first number of output channels, and control the output channels other than the output channels of the second number of output channels in the first number of output channels to output a low-level signal or be in a high-impedance state.

[0010] In the above-mentioned display device, the display device further includes an image scaling controller, which is used to control the display panel of the display device to perform a power-off operation, adjust the refresh rate of the display panel, and control the display panel to perform a power-on operation.

[0011] In the above-mentioned display device, the image scaling controller is electrically connected to the timing controller, and the image scaling controller is used to send a refresh rate signal to the timing controller.

[0012] In the aforementioned display device, the output channels of the second channel number include two ports, and each port includes three pairs of low-voltage differential signal channels; the output channels of the first channel number include two ports, and each port includes six pairs of low-voltage differential signal channels.

[0013] This application also provides a driving method for a display device, the driving method comprising: acquiring a current refresh rate; when the current refresh rate is a first refresh rate, outputting a data signal to a source driver chip of the display device through an output channel of a first number of channels; and when the current refresh rate is a second refresh rate, outputting the data signal to the source driver chip through an output channel of a second number of channels, and turning off the output channels of the first number of channels other than the output channels of the second number of channels; wherein the second refresh rate is less than the first refresh rate, and the second number of channels is less than the first number of channels.

[0014] In the above-described driving method for the display device, before outputting the data signal to the source driver chip through the output channel of the first number of channels, the driving method further includes: outputting a first level signal to the source driver chip, such that the source driver chip is set to a receiving mode corresponding to the first number of channels; and controlling the data formatting module of the timing controller of the display device to allocate the data signal to the output channel of the first number of channels.

[0015] In the above-described driving method for the display device, before outputting a data signal to the source driver chip through the output channel of the second channel number, the driving method further includes: outputting a second level signal to the source driver chip, so that the source driver chip is set to a receiving mode corresponding to the second channel number; and controlling the data formatting module of the timing controller of the display device to allocate the data signal to the output channel of the second channel number.

[0016] In the driving method of the above-mentioned display device, shutting down the output channels other than the output channels of the second number of channels in the first number of output channels includes: cutting off the bias current of the output channels other than the output channels of the second number of output channels in the first number of output channels; and controlling the output channels other than the output channels of the second number of output channels in the first number of output channels to output a low-level signal or be in a high-impedance state.

[0017] In the above-described driving method for the display device, before obtaining the current refresh rate, the driving method further includes: controlling the display panel of the display device to perform a power-off operation; adjusting the refresh rate of the display panel; and controlling the display panel to perform a power-on operation.

[0018] In the driving method of the above-mentioned display device, the output channel of the second channel number includes two ports, and each port includes three pairs of low-voltage differential signal channels, and the output channel of the first channel number includes two ports, and each port includes six pairs of low-voltage differential signal channels.

[0019] This application also provides a timing controller, the timing controller comprising: an acquisition module for acquiring the current refresh rate; and a control module for outputting a data signal through a first number of output channels when the current refresh rate is a first refresh rate, and outputting the data signal through a second number of output channels when the current refresh rate is a second refresh rate, and shutting down the output channels of the first number of output channels other than the second number of output channels; wherein the second refresh rate is less than the first refresh rate, and the second number of channels is less than the first number of channels.

[0020] In the aforementioned timing controller, the control module includes: a pin control unit, configured to output a first level signal when the current refresh rate is the first refresh rate, and to output a second level signal when the current refresh rate is the second refresh rate; and a mapping switching unit, configured to control the data formatting module of the timing controller to allocate the data signal to the output channel of the first number of channels when the current refresh rate is the first refresh rate, and to control the data formatting module to allocate the data signal to the output channel of the second number of channels when the current refresh rate is the second refresh rate.

[0021] In the timing controller described above, the control module further includes a channel shutdown unit, which is used to cut off the bias current of the output channels other than the output channels of the second number of channels when the current refresh rate is the second refresh rate, and control the output channels other than the output channels of the second number of channels to output a low-level signal or be in a high-impedance state.

[0022] In the aforementioned timing controller, the output channels of the second channel number include two ports, and each port includes three pairs of low-voltage differential signal channels; the output channels of the first channel number include two ports, and each port includes six pairs of low-voltage differential signal channels.

[0023] This application provides a display device and its driving method, as well as a timing controller. The timing controller acquires the current refresh rate. When the current refresh rate is a first refresh rate, it outputs data signals to the source driver chip through a first number of output channels. When the current refresh rate is a second refresh rate, it outputs data signals to the source driver chip through a second number of output channels and shuts down all output channels of the first number of output channels except for the second number of output channels. The second refresh rate is less than the first refresh rate, and the second number of channels is less than the first number of channels. This application's technical solution dynamically adjusts the number of output channels according to the current refresh rate. When the display device is in a low refresh rate operating state (second refresh rate), it reduces the number of operating output channels and completely shuts down idle output channels, preventing invalid signal flips from idle output channels. This reduces the power consumption of the timing controller's transmitting end and the source driver chip's receiving end, thereby reducing the overall power consumption of the display device in a low refresh rate operating state and meeting the display device's low power consumption requirements.

[0024] In the technical solution of this application, before the timing controller outputs a data signal to the source driver chip through the output channels of the first number of channels, it outputs a first-level signal to the source driver chip, setting the source driver chip to a receiving mode corresponding to the first number of channels, and controlling the data formatting module to distribute the data signal to the output channels of the first number of channels. Before the timing controller outputs a data signal to the source driver chip through the output channels of the second number of channels, it outputs a second-level signal to the source driver chip, setting the source driver chip to a receiving mode corresponding to the second number of channels, and controlling the data formatting module to distribute the data signal to the output channels of the second number of channels. This technical solution controls the receiving mode of the source driver chip by outputting different level signals, ensuring that the number of receiving channels of the source driver chip is consistent with the number of output channels of the timing controller. This guarantees accurate transmission of data signals between the timing controller and the source driver chip. Simultaneously, the data formatting module redistributes the data signal, ensuring complete mapping of the data signal under different numbers of channels and guaranteeing normal display of the display panel at different refresh rates.

[0025] In the technical solution of this application, the timing controller cuts off the bias current of the output channels other than the second number of output channels in the first number of output channels, and controls the output channels other than the second number of output channels in the first number of output channels to output a low-level signal or be in a high-impedance state. By cutting off the bias current of the idle output channels, the technical solution of this application physically stops the operation of the analog drive circuit and keeps the idle output channels in a low-level signal or high-impedance state, further eliminating unnecessary power consumption and improving the power reduction effect.

[0026] In the technical solution of this application, the image scaling controller controls the display panel of the display device to perform a power-off operation, adjust the refresh rate of the display panel, and control the display panel to perform a power-on operation. By performing power-off and power-on operations before and after adjusting the refresh rate, the image scaling controller avoids display abnormalities caused by directly switching the number of channels, ensuring the stability of the display device when switching between different refresh rates. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the display state of a traditional display device.

[0028] Figure 2 A schematic diagram of a display device provided for an embodiment of this application.

[0029] Figure 3 This is a schematic diagram illustrating a method for dynamically adjusting the number of output channels in a display device provided in an embodiment of this application.

[0030] Figure 4This is a schematic diagram illustrating the correspondence between the number of output channels and the refresh rate of a display device provided in an embodiment of this application. Detailed Implementation

[0031] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0032] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0033] The technical solutions of different embodiments of this application can be combined with each other.

[0034] The term "first level" can be, for example, a high level, and the term "second level" can be, for example, a low level. The first level and the second level of the same signal are relative. The first level of different signals can be equal or unequal, and the second level of different signals can be equal or unequal.

[0035] like Figure 1 As shown, traditional display devices typically have three display states with different refresh rates, ordered from lowest to highest: 60Hz, 120Hz, and 165Hz. In traditional display devices, the timing controller (TCON) usually uses Mini-LVDS (Mini Low Voltage Differential Signaling) to transmit data to the source driver chip (SDIC). To meet the data bandwidth requirements at high refresh rates, the timing controller (TCON) typically uses a large number of output channels to output data signals to the SDIC. However, when the display device switches to a low refresh rate operating state, the timing controller (TCON) still uses the same number of output channels to output data signals to the SDIC as in the high refresh rate operating state, which increases the overall power consumption of the display device. To solve the above technical problems, embodiments of this application provide a display device and its driving method, as well as a timing controller (TCON).

[0036] The display devices provided in the embodiments of this application may be, for example, liquid crystal display devices, organic light-emitting diode (OLED) display devices, mini light-emitting diode (Mini-LED) display devices, or micro light-emitting diode (Micro-LED) display devices. The embodiments of this application are described using liquid crystal display devices as an example.

[0037] like Figure 2 As shown, the display device provided in the embodiments of this application includes a display panel (DP), a timing controller (TCON), and multiple chip-on-film (COF) films. The display panel (DP) includes a gate-driver-on-array (GOA), multiple gate lines, multiple data lines, and multiple pixels. The gate-driver-on-array is electrically connected to the multiple gate lines and outputs gate drive signals to the gate lines to drive the multiple pixels line by line. Each pixel receives a data signal transmitted by the data lines under the control of its corresponding gate drive signal. The multiple data lines are electrically connected to a source driver chip (SDIC), which outputs data signals to the multiple pixels through the data lines to drive the multiple pixels to display an image. The timing controller (TCON) is electrically connected to the source driver chip (SDIC) and also electrically connected to the display panel (DP).

[0038] like Figure 2 As shown in the embodiments of this application, the display device includes eight flip-chip films, namely, a first flip-chip film COF1, a second flip-chip film COF2, a third flip-chip film COF3, a fourth flip-chip film COF4, a fifth flip-chip film COF5, a sixth flip-chip film COF6, a seventh flip-chip film COF7, and an eighth flip-chip film COF8. Each flip-chip film contains a source driver chip SDIC, which is electrically connected to the data line of the display panel DP and is used to output drive signals to the display panel DP. The timing controller TCON has a first mini-LVDS port A and a second mini-LVDS port B. The first mini-LVDS port A is electrically connected to the first flip-chip film COF1, the second flip-chip film COF2, the third flip-chip film COF3, and the fourth flip-chip film COF4 via wiring. The second mini low-voltage differential signal output port is electrically connected to the fifth flip-chip film COF5, the sixth flip-chip film COF6, the seventh flip-chip film COF7, and the eighth flip-chip film COF8 via wiring.

[0039] like Figure 3As shown, the display device provided in the embodiments of this application further includes an image scaling controller (SCL). The image scaling controller SCL is electrically connected to the timing controller TCON and is used to send refresh rate signals to the timing controller TCON. The image scaling controller SCL sends signals of different refresh rates to the timing controller TCON according to user selection or display content requirements. The timing controller TCON dynamically adjusts the number of output channels according to the received refresh rate signals to output corresponding data signals to the source driver chip SDIC.

[0040] The timing controller TCON obtains the current refresh rate by measuring the frequency of the vertical synchronization signal (Vsync), or by parsing configuration instructions from the integrated circuit bus (I2C) or serial peripheral interface (SPI) sent by the image scaling controller SCL. Specifically, the internal logic circuit of the timing controller TCON counts the pulse periods of the vertical synchronization signal and converts the count result into the current refresh rate; alternatively, the timing controller TCON reads the refresh rate parameter from the integrated circuit bus or serial peripheral interface configuration instructions sent by the image scaling controller SCL to obtain the current refresh rate. The timing controller TCON also adjusts the mini low-voltage differential signal output clock frequency according to the current refresh rate and the current number of output channels, so that the mini low-voltage differential signal output clock frequency matches the current refresh rate and the current number of output channels.

[0041] When the current refresh rate is the first refresh rate, the timing controller TCON outputs data signals to the source driver chip SDIC through the first number of output channels. When the current refresh rate is the second refresh rate, the timing controller TCON outputs data signals to the source driver chip SDIC through the second number of output channels, and shuts down all output channels except the second number of output channels out of the first number of output channels. Here, the second refresh rate is less than the first refresh rate, and the second number of channels is less than the first number of channels.

[0042] In embodiments of this application, the first refresh rate is 165Hz and the second refresh rate is 60Hz. The output channels of the second number of channels include two ports, and each port includes three pairs of low-voltage differential signal channels. The output channels of the first number of channels include two ports, and each port includes six pairs of low-voltage differential signal channels. In other embodiments, the first refresh rate, the second refresh rate, and the corresponding number of output channels can be adjusted according to the resolution and specifications of the display device.

[0043] like Figure 4As shown, when the refresh rate is 60Hz, the corresponding output channel includes two ports, and each port includes three pairs of low-voltage differential signal channels; when the refresh rate increases to 165Hz, the corresponding output channel includes two ports, and each port includes six pairs of low-voltage differential signal channels; when the refresh rate decreases back to 60Hz, the corresponding output channel includes two ports, and each port includes three pairs of low-voltage differential signal channels. The timing controller TCON adjusts the number of output channels in real time according to the change in the current refresh rate.

[0044] The source driver chip SDIC has a channel logarithmic selection (PAIRMODE) pin, which receives a level signal from the timing controller TCON to select the SDIC's receive mode. The SDIC's channel logarithmic selection pin is electrically connected to the TCON's general purpose input / output (GPIO) control pins via traces. Since switching the SDIC's receive channel mode requires resetting or re-initializing the SDIC, the timing controller TCON outputs a corresponding level signal to the SDIC's channel logarithmic selection pin via the GPIO control pins during the initialization phase when the display panel DP is powered on again. This ensures that the SDIC completes the receive mode setting during the initialization phase.

[0045] Before outputting data signals to the source driver chip SDIC through the output channels of the first channel number, the timing controller TCON outputs a first-level signal to the source driver chip SDIC. This sets the source driver chip SDIC to the receiving mode corresponding to the first channel number and controls the data formatter module of the timing controller TCON to distribute the data signals to the output channels of the first channel number. Specifically, when the timing controller TCON recognizes that the current refresh rate is 165Hz, the microcontroller (MCU) or logic circuit inside the timing controller TCON outputs a high level (i.e., the first-level signal) to the channel selection pin of the source driver chip SDIC through the general-purpose input / output control pin during the initialization phase when the display panel DP is powered on again. This sets the source driver chip SDIC to the receiving mode corresponding to the first channel number, i.e., a receiving mode with two ports, each including six pairs of low-voltage differential signal channels. The phase-locked loop (PLL) inside the timing controller TCON adjusts the mini low-voltage differential signal output clock frequency according to the pixel clock corresponding to 165Hz. Taking a QHD (Quad High Definition) resolution display device as an example, the total horizontal pixel count is 2720, the total vertical pixel count is 1490, the color depth is 8 bits, and the mini low-voltage differential signal output clock frequency is 669MHz. The data formatting module inside the timing controller TCON switches to the mapping logic of six pairs of low-voltage differential signal channels, evenly distributing the data signal to the six pairs of low-voltage differential signal channels. The timing controller TCON activates the physical layer (PHY) driver circuit of all mini low-voltage differential signal channels, outputting clock and data signals, and the display panel DP displays at a high refresh rate of 165Hz.

[0046] Before outputting data signals to the source driver chip SDIC through the output channels of the second channel number, the timing controller TCON outputs a second-level signal to the source driver chip SDIC. This sets the source driver chip SDIC to the receiving mode corresponding to the second channel number and controls the data formatting module of the timing controller TCON to distribute the data signals to the output channels of the second channel number. Specifically, when the timing controller TCON detects that the current refresh rate is 60Hz, during the initialization phase of the display panel DP power-on, the timing controller TCON outputs a low level (i.e., the second-level signal) to the channel selection pin of the source driver chip SDIC through the general purpose input / output control pin. This sets the source driver chip SDIC to the receiving mode corresponding to the second channel number, i.e., a receiving mode with two ports, each including three pairs of low-voltage differential signal channels. The phase-locked loop inside the timing controller TCON adjusts the mini low-voltage differential signal output clock frequency according to the pixel clock corresponding to 60Hz. As the number of output channels decreases from six pairs of low-voltage differential signal channels to three pairs, the data transmission rate requirement for each pair of low-voltage differential signal channels increases accordingly. However, since the overall refresh rate has been reduced to 60Hz, the calculated transmission frequency is 480MHz, which is lower than the 700MHz specification limit of the source driver chip SDIC. The data formatting module inside the timing controller TCON switches to the mapping logic of the three pairs of low-voltage differential signal channels, allocating the data signals to the 0th to 2nd pairs of low-voltage differential signal channels (LV(2:0)P / N) for transmission.

[0047] The timing controller TCON cuts off the bias current of all output channels except the second number of output channels in the first number of output channels, and controls the output channels except the second number of output channels to output a low-level signal or be in a high-impedance state. Specifically, the timing controller TCON shuts down the physical layer driving circuit of the 3rd to 5th pairs of low-voltage differential signal channels (LV(5:3)P / N) through its internal register, cuts off the bias current and related power supply of the 3rd to 5th pairs of low-voltage differential signal channels, and stops the toggling of the clock and data signals of the 3rd to 5th pairs of low-voltage differential signal channels, so that the 3rd to 5th pairs of low-voltage differential signal channels output a fixed low level or are in a high-impedance state. By reducing the data channel toggling by half and shutting down the analog driving circuit of the 3rd to 5th pairs of low-voltage differential signal channels, the power consumption of the transmitting end of the timing controller TCON and the receiving end of the source driver chip SDIC are reduced, meeting the power consumption reduction requirement in the 60Hz operating state.

[0048] The image scaling controller (SCL) controls the display panel (DP) of the display device to perform power-off operations, adjust the refresh rate of the DP, and control the DP to perform power-on operations. Since switching the receive channel mode of the source driver chip (SDIC) requires resetting or reinitializing the SDIC, the SCL first controls the DP to perform a power-off operation before adjusting the refresh rate, i.e., shutting down the power supply to the DP according to the power-off sequence. After the DP completes the power-off operation, the SCL adjusts the output video timing parameters, including the pixel clock and the vertical total pixels (V-total), to complete the refresh rate adjustment. After the refresh rate adjustment is complete, the SCL controls the DP to perform a power-on operation, i.e., re-energizing the DP according to the power-on sequence. After the DP completes the power-on operation, the timing controller (TCON) initializes according to the current refresh rate.

[0049] Embodiments of this application also provide a driving method for a display device. Since switching the receive channel mode of the source driver chip SDIC requires resetting or reinitializing the source driver chip SDIC, directly switching the number of output channels without a power-off operation can cause display abnormalities on the display panel DP. Therefore, before obtaining the current refresh rate, the image scaling controller SCL first controls the display panel DP to perform a power-off operation, that is, shutting down the power supply to each channel of the display panel DP according to the power-off sequence. After the display panel DP completes the power-off operation, the image scaling controller SCL adjusts the output video timing parameters, including the pixel clock and the total vertical pixel count, to complete the refresh rate adjustment. After the refresh rate adjustment is completed, the image scaling controller SCL controls the display panel DP to perform a power-on operation, that is, re-energizing the power supply to each channel of the display panel DP according to the power-on sequence.

[0050] After the display panel (DP) completes its power-on operation, the timing controller (TCON) acquires the current refresh rate. The timing controller (TCON) acquires the current refresh rate in one of two ways: either the internal logic circuitry of the timing controller (TCON) counts the pulse periods of the vertical synchronization signal and converts the count result into the current refresh rate; or the timing controller (TCON) reads the refresh rate parameter from the integrated circuit bus or serial peripheral interface configuration command sent by the image scaling controller (SCL) to obtain the current refresh rate.

[0051] With the current refresh rate at the first refresh rate (165Hz), before the timing controller TCON outputs data signals to the source driver chip SDIC through the output channels of the first number of channels, it outputs a first-level signal (i.e., a high level) to the channel selection pin of the source driver chip SDIC through the general-purpose input / output control pin. This sets the source driver chip SDIC to the receiving mode corresponding to the first number of channels, i.e., a receiving mode with two ports, each including six pairs of low-voltage differential signal channels. The timing controller TCON controls the data formatting module to switch to the mapping logic of the six pairs of low-voltage differential signal channels, evenly distributing the data signals to the output channels of the first number of channels, so that the data signals are fully mapped on the output channels of the first number of channels. After completing the above operations, the timing controller TCON outputs data signals to the source driver chip SDIC through the output channels of the first number of channels, and the display panel DP displays at a high refresh rate of 165Hz.

[0052] With the current refresh rate being the second refresh rate (60Hz), before outputting data signals to the source driver chip SDIC through the output channels of the second number of channels, the timing controller TCON outputs a second-level signal (i.e., low level) to the channel selection pin of the source driver chip SDIC through the general-purpose input / output control pin. This sets the source driver chip SDIC to the receiving mode corresponding to the second number of channels, i.e., a receiving mode with two ports, each including three pairs of low-voltage differential signal channels. The phase-locked loop inside the timing controller TCON adjusts the mini low-voltage differential signal output clock frequency to 480MHz according to the pixel clock corresponding to the second refresh rate, to match the output channels of the second number of channels and the second refresh rate. The timing controller TCON controls the data formatting module to switch to the mapping logic of the three pairs of low-voltage differential signal channels, allocating the data signals to the 0th to 2nd pairs of low-voltage differential signal channels (LV(2:0)P / N) for transmission. After completing the above operations, the timing controller TCON outputs data signals to the source driver chip SDIC through the second number of output channels, and shuts down the output channels of the first number of output channels except for the second number of output channels, namely the 3rd to 5th pairs of low-voltage differential signal channels (LV(5:3)P / N). Specifically, the timing controller TCON cuts off the bias current and related power supply of the 3rd to 5th pairs of low-voltage differential signal channels, and controls the 3rd to 5th pairs of low-voltage differential signal channels to output low-level signals or be in a high-impedance state, so as to stop the toggling of the clock signal and data signal of the 3rd to 5th pairs of low-voltage differential signal channels.

[0053] In embodiments of this application, the output channels of the second number of channels include two ports, and each port includes three pairs of low-voltage differential signal channels; the output channels of the first number of channels include two ports, and each port includes six pairs of low-voltage differential signal channels.

[0054] Embodiments of this application also provide a timing controller TCON. The timing controller TCON includes an acquisition module and a control module.

[0055] The acquisition module obtains the current refresh rate in one of two ways: either the internal logic circuit of the acquisition module counts the pulse periods of the vertical synchronization signal and converts the count result into the current refresh rate; or, the acquisition module reads the refresh rate parameter from the integrated circuit bus or serial peripheral interface configuration command sent by the image scaling controller SCL to obtain the current refresh rate. The acquisition module transmits the obtained current refresh rate to the control module, and the control module adjusts the number of output channels according to the current refresh rate.

[0056] The control module is electrically connected to the acquisition module and adjusts the number of output channels according to the current refresh rate transmitted by the acquisition module. When the current refresh rate is the first refresh rate (165Hz), the control module outputs data signals through the first number of output channels. When the current refresh rate is the second refresh rate (60Hz), the control module outputs data signals through the second number of output channels and shuts down all output channels except the second number of output channels out of the first number. The second refresh rate is less than the first refresh rate, and the second number of channels is less than the first number of channels.

[0057] The control module includes a pin control unit, a mapping switching unit, and a channel shutdown unit. The pin control unit is electrically connected to the general purpose input / output control pins of the timing controller TCON. When the current refresh rate is the first refresh rate (165Hz), the pin control unit outputs a first-level signal (i.e., high level) to the channel logarithmic selection pin of the source driver chip SDIC through the general purpose input / output control pin, so that the source driver chip SDIC is set to a two-port receiving mode with each port including six pairs of low-voltage differential signal channels; when the current refresh rate is the second refresh rate (60Hz), the pin control unit outputs a second-level signal (i.e., low level) to the channel logarithmic selection pin of the source driver chip SDIC through the general purpose input / output control pin, so that the source driver chip SDIC is set to a two-port receiving mode with each port including three pairs of low-voltage differential signal channels. The mapping switching unit is electrically connected to the data formatting module. When the current refresh rate is the first refresh rate (165Hz), the mapping switching unit sends a switching command to the data formatting module. The data formatting module switches to the mapping logic of six pairs of low-voltage differential signal channels, and distributes the data signal evenly to the output channels of the first number of channels. For example, the data signal is distributed to the 0th to the 5th pairs of low-voltage differential signal channels (LV(5:0)P / N) for transmission. When the current refresh rate is the second refresh rate (60Hz), the mapping switching unit sends a switching command to the data formatting module. The data formatting module switches to the mapping logic of three pairs of low-voltage differential signal channels, and distributes the data signal evenly to the output channels of the second number of channels. For example, the data signal is distributed to the 0th to the 2nd pairs of low-voltage differential signal channels (LV(2:0)P / N) for transmission. The channel shutdown unit is electrically connected to the physical layer drive circuit of the timing controller TCON. When the current refresh rate is the second refresh rate (60Hz), the channel shutdown unit sends a shutdown command to the physical layer drive circuit of the 3rd to 5th pairs of low-voltage differential signal channels (LV(5:3)P / N) through the internal register of the timing controller TCON. This cuts off the bias current and related power supply of the 3rd to 5th pairs of low-voltage differential signal channels, and controls the output of the 3rd to 5th pairs of low-voltage differential signal channels to be fixed low or in a high impedance state, so as to stop the toggling of the clock signal and data signal of the 3rd to 5th pairs of low-voltage differential signal channels.

[0058] In embodiments of this application, the output channels of the second number of channels include two ports, and each port includes three pairs of low-voltage differential signal channels; the output channels of the first number of channels include two ports, and each port includes six pairs of low-voltage differential signal channels.

[0059] This application provides a display device and its driving method, as well as a timing controller (TCON). The timing controller TCON acquires the current refresh rate. When the current refresh rate is a first refresh rate, it outputs data signals to the source driver chip (SDIC) through a first number of output channels. When the current refresh rate is a second refresh rate, it outputs data signals to the SDIC through a second number of output channels and shuts down all output channels except for the second number of output channels out of the first number. The second refresh rate is less than the first refresh rate, and the second number of channels is less than the first number of channels. This application's technical solution dynamically adjusts the number of output channels based on the current refresh rate. When the display device is operating at a second refresh rate, it reduces the number of output channels in operation and shuts down all output channels except for the second number of output channels out of the first number. This avoids invalid signal flipping from the shut-down output channels, reduces the power consumption of the timing controller TCON at the transmitter and the SDIC at the receiver, thereby reducing the overall power consumption of the display device at low refresh rates and meeting the display device's low power consumption requirements.

[0060] In the technical solution of this application, before the timing controller TCON outputs a data signal to the source driver chip SDIC through the output channel of the first channel number, it outputs a first level signal to the source driver chip SDIC, so that the source driver chip SDIC is set to the receiving mode corresponding to the first channel number, and controls the data formatting module to allocate the data signal to the output channel of the first channel number; before the timing controller TCON outputs a data signal to the source driver chip SDIC through the output channel of the second channel number, it outputs a second level signal to the source driver chip SDIC, so that the source driver chip SDIC is set to the receiving mode corresponding to the second channel number, and controls the data formatting module to allocate the data signal to the output channel of the second channel number. The technical solution of this application controls the receiving mode of the source driver chip SDIC by outputting different level signals to the source driver chip SDIC, so that the number of receiving channels of the source driver chip SDIC is consistent with the number of output channels of the timing controller TCON, ensuring the correct transmission of data signals between the timing controller TCON and the source driver chip SDIC. At the same time, the data signal is redistributed to the corresponding output channel through the data formatting module, ensuring the complete mapping of data signals under different numbers of output channels, and ensuring the normal display of the display panel DP at different refresh rates.

[0061] In the technical solution of this application, the timing controller TCON cuts off the bias current of the output channels other than the second number of output channels in the first number of output channels, and controls the output channels other than the second number of output channels in the first number of output channels to output a low-level signal or be in a high-impedance state. By cutting off the bias current of the aforementioned output channels, the technical solution of this application physically stops the operation of the analog drive circuit of the aforementioned output channels, and keeps the aforementioned output channels in a low-level signal or high-impedance state, further reducing power consumption.

[0062] In the technical solution of this application, the image scaling controller SCL controls the display panel DP of the display device to perform a power-off operation, adjust the refresh rate of the display panel DP, and control the display panel DP to perform a power-on operation. This technical solution, by having the image scaling controller SCL perform power-off and power-on operations before and after refresh rate adjustment, avoids display abnormalities caused by directly switching the number of output channels without a power-off operation, thus ensuring the stability of the display device when switching between different refresh rates.

[0063] Verification was conducted on a QHD 165Hz display device. Table 1 shows a comparison of the power consumption data of the timing controller TCON before and after adopting the dynamic adjustment method of this application in the QHD 60Hz operating state. The power consumption of the 3.3V power supply (VDD33) circuit of the timing controller TCON decreased from 0.8W to 0.6W, a reduction of 25%. Table 2 shows a comparison of the overall power consumption data. Under the ES8.0 standard on-condition (OC) test, the overall power consumption decreased from 3.08W to 2.81W, a reduction of 9%.

[0064] Table 1 Comparison of power consumption data for timing controllers

[0065] Table 2 Comparison of Overall Power Consumption Data

[0066] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, characterized in that, The display device includes: Display panel; Source driver chip, the source driver chip being electrically connected to the display panel; and A timing controller is electrically connected to the source driver chip and is used to acquire the current refresh rate. When the current refresh rate is a first refresh rate, the timing controller outputs a data signal to the source driver chip through a first number of output channels. When the current refresh rate is a second refresh rate, the timing controller outputs the data signal to the source driver chip through a second number of output channels and shuts down the output channels of the first number of output channels except for the second number of output channels. The second refresh rate is less than the first refresh rate, and the second number of channels is less than the first number of channels.

2. The display device according to claim 1, characterized in that, The timing controller is further configured to output a first level signal to the source driver chip before outputting the data signal to the source driver chip through the output channel of the first number of channels, so that the source driver chip is set to a receiving mode corresponding to the first number of channels, and to control the data formatting module of the timing controller to allocate the data signal to the output channel of the first number of channels.

3. The display device according to claim 1, characterized in that, The timing controller is further configured to output a second level signal to the source driver chip before outputting the data signal to the source driver chip through the output channel of the second channel number, so that the source driver chip is set to a receiving mode corresponding to the second channel number, and to control the data formatting module of the timing controller to allocate the data signal to the output channel of the second channel number.

4. The display device according to claim 1, characterized in that, The timing controller is also used to cut off the bias current of the output channels other than the output channels of the second number of channels in the first number of output channels, and to control the output channels other than the output channels of the second number of output channels in the first number of output channels to output a low-level signal or be in a high-impedance state.

5. The display device according to claim 1, characterized in that, The display device further includes an image scaling controller, which is used to control the display panel of the display device to perform a power-off operation, adjust the refresh rate of the display panel, and control the display panel to perform a power-on operation.

6. The display device according to claim 5, characterized in that, The image scaling controller is electrically connected to the timing controller, and the image scaling controller is used to send a refresh rate signal to the timing controller.

7. The display device according to claim 1, characterized in that, The output channels of the second channel number include two ports, and each port includes three pairs of low-voltage differential signal channels. The output channels of the first channel number include two ports, and each port includes six pairs of low-voltage differential signal channels.

8. A driving method for a display device, characterized in that, The driving method includes: Get the current refresh rate; When the current refresh rate is the first refresh rate, a data signal is output to the source driver chip of the display device through the output channel with the first number of channels; and When the current refresh rate is the second refresh rate, the data signal is output to the source driver chip through the output channel of the second number of channels, and the output channels of the first number of channels other than the output channel of the second number of channels are turned off; Wherein, the second refresh rate is less than the first refresh rate, and the second number of channels is less than the first number of channels.

9. The driving method for the display device according to claim 8, characterized in that, Before outputting the data signal to the source driver chip through the output channel of the first number of channels, the driving method further includes: Output a first-level signal to the source driver chip, thereby setting the source driver chip to a receiving mode corresponding to the first number of channels; and The data formatting module of the timing controller of the display device distributes the data signal to the output channel of the first channel number.

10. The driving method for the display device according to claim 8, characterized in that, Before outputting the data signal to the source driver chip through the output channel of the second channel number, the driving method further includes: Output a second-level signal to the source driver chip, causing the source driver chip to be set to a receiving mode corresponding to the second number of channels; and The data formatting module of the timing controller of the display device distributes the data signal to the output channel of the second channel number.

11. The driving method for the display device according to claim 8, characterized in that, The output channels that are closed in the first number of output channels, excluding the second number of output channels, include: Disconnect the bias current of the output channels other than the output channels of the second number of channels in the first number of output channels; and The output channels of the first number of output channels, excluding the output channels of the second number of output channels, output a low-level signal or are in a high-impedance state.

12. The driving method for the display device according to claim 8, characterized in that, Before obtaining the current refresh rate, the driving method further includes: Control the display panel of the display device to perform a power-off operation; Adjust the refresh rate of the display panel; and Control the display panel to perform a power-on operation.

13. The driving method for the display device according to claim 8, characterized in that, The output channels of the second channel number include two ports, and each port includes three pairs of low-voltage differential signal channels. The output channels of the first channel number include two ports, and each port includes six pairs of low-voltage differential signal channels.

14. A timing controller, characterized in that, The timing controller includes: The acquisition module is used to acquire the current refresh rate; and The control module is configured to output a data signal through a first number of output channels when the current refresh rate is a first refresh rate, and to output the data signal through a second number of output channels when the current refresh rate is a second refresh rate, and to close all output channels of the first number of output channels except for the second number of output channels. Wherein, the second refresh rate is less than the first refresh rate, and the second number of channels is less than the first number of channels.

15. The timing controller according to claim 14, characterized in that, The control module includes: A pin control unit, configured to output a first level signal when the current refresh rate is the first refresh rate, and to output a second level signal when the current refresh rate is the second refresh rate; and A mapping switching unit is configured to control the data formatting module of the timing controller to allocate the data signal to the output channel of the first number of channels when the current refresh rate is the first refresh rate, and to control the data formatting module to allocate the data signal to the output channel of the second number of channels when the current refresh rate is the second refresh rate.

16. The timing controller according to claim 15, characterized in that, The control module also includes: The channel shutdown unit is used to cut off the bias current of the output channels other than the output channels of the second number of channels when the current refresh rate is the second refresh rate, and to control the output channels other than the output channels of the first number of channels to output a low-level signal or be in a high-impedance state.

17. The timing controller according to claim 14, characterized in that, The output channels of the second channel number include two ports, and each port includes three pairs of low-voltage differential signal channels. The output channels of the first channel number include two ports, and each port includes six pairs of low-voltage differential signal channels.

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