A display device and a display method

Abstract

The application provides a display device and a display method. The display device comprises a system chip, a timing controller and a display panel. The display panel comprises a plurality of data lines, a plurality of pixels and a plurality of groups of gate lines. The system chip receives initial data to be displayed transmitted by an external device. The timing controller starts a frequency doubling function based on the initial data, detects a gray scale difference value of any two adjacent columns of data in the initial data, obtains target data according to the gray scale difference value and the to-be-filled gray scale information between the two adjacent columns of data, and transmits the target data to the pixels through the data lines for display. The timing controller starts the frequency doubling function based on the initial data and detects the gray scale difference value of the two adjacent columns of data, the target data is generated in combination with the to-be-filled gray scale information, the refresh rate of the display panel is improved, the filled data is dynamically adjusted according to the gray scale difference, picture distortion is avoided, and the display quality is maintained while the refresh rate is improved.

Description

[0001] This divisional application is a divisional application of Chinese patent application No. 202511521417.7, filed on October 22, 2025, entitled "A display device and display method". Technical Field

[0002] This application relates to the field of display technology, specifically to a display device and display method. Background Technology

[0003] Existing display panels based on the Dual Line Gate (DLG) architecture can be configured to achieve a refresh rate doubled. In display technology, a higher refresh rate can provide smoother visuals, especially in fast-moving scenes or high frame rate games. However, while DLG technology can generally achieve a doubled refresh rate increase, it is difficult to achieve higher multipliers (such as quadruple or hexaple). Furthermore, while higher multipliers can be achieved using data cloning technology (DCT), this can lead to image sharpening or distortion, affecting display quality. For example, in scenes with significant differences in grayscale between adjacent pixels, traditional methods struggle to maintain image quality while increasing the refresh rate. Summary of the Invention

[0004] This application provides a display device and display method, which have the advantages of improving the refresh rate of the display panel while avoiding image distortion and maintaining display quality.

[0005] This application provides a display device, including a system-on-a-chip, a timing controller, and a display panel, wherein the timing controller is connected to the system-on-a-chip and the display panel respectively; The display panel includes multiple data lines, multiple pixels and multiple sets of gate lines. Each data line is electrically connected to two columns of pixels located on both sides of the data line. Each row of pixels is electrically connected to a set of gate lines. Each set of gate lines includes two gate lines. The system-on-a-chip is configured to receive initial data to be displayed transmitted from an external device; The timing controller is configured as follows: Based on the initial data, the frequency multiplication function is enabled, and the grayscale difference between any two adjacent columns of data in the initial data is detected. The target data is obtained based on the grayscale difference and the grayscale information to be filled between the two adjacent columns of data, and the target data is transmitted to the pixel for display through the data line to improve the refresh rate of the display panel.

[0006] This application also provides a display method, using the display device described above, the method comprising: The frequency multiplication function is enabled based on the initial data to be displayed transmitted from the external device received by the system-on-a-chip, and the gray level difference between any two adjacent columns of data in the initial data is detected. Based on the grayscale difference and the grayscale information to be filled between the two adjacent columns of data, the target data is obtained, and the target data is transmitted to the pixels of the display panel for display through the data line of the display panel, so as to improve the refresh rate of the display panel.

[0007] In summary, the display device and display method provided in this application enable the frequency multiplication function based on initial data and detect the grayscale difference between two adjacent columns of data through a timing controller. The target data is generated by combining the grayscale information to be filled, thereby improving the refresh rate of the display panel. At the same time, the filling data is dynamically adjusted according to the grayscale difference to avoid image distortion. It has the advantage of maintaining display quality while improving the refresh rate. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is one of the schematic diagrams of a display device provided for an embodiment of this application.

[0010] Figure 2 This is a second schematic diagram of a display device provided for an embodiment of this application.

[0011] Figure 3 This is one of the schematic diagrams of the working scenario of the display device provided in the embodiments of this application.

[0012] Figure 4 This is a second schematic diagram of the working scenario of the display device provided in the embodiments of this application.

[0013] Figure 5 The third schematic diagram of the working scenario of the display device provided in the embodiments of this application.

[0014] Figure 6 The fourth schematic diagram of the working scenario of the display device provided in the embodiments of this application.

[0015] Figure 7 Fifth schematic diagram of the working scenario of the display device provided in the embodiments of this application.

[0016] Figure 8 A flowchart illustrating a display method provided for an embodiment of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0018] In the description of this application, the terms "first," "second," and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms "multiple" and similar words indicate two or more unless otherwise expressly defined. Embodiments of this application can be combined with each other.

[0019] This application provides a display device, which includes, but is not limited to, the following embodiments and combinations thereof.

[0020] In some embodiments, combined with Figure 1 and Figure 2 As shown, Figure 1 One of the schematic diagrams of a display device provided for an embodiment of this application; Figure 2 This is a second schematic diagram of a display device provided in an embodiment of this application. The display device may include a display panel, a timing controller, a source drive circuit, and a power management chip, etc. The display panel may include a pixel array, a gate drive circuit (GOA circuit), and a light-emitting controller, etc. The display panel provided in this embodiment may be, for example, an organic light-emitting diode (OLED) display panel; of course, the display panel may also be a Mini-LED display panel or a Micro-LED display panel. The display panel may also include a substrate, data lines configured to transmit data signals DATA, scan lines configured to transmit scan signals SCAN, power lines configured to transmit voltage VDD at the positive terminal of a power line or voltage VSS at the negative terminal of a power line, light-emitting control signal lines configured to transmit light-emitting control signals EM, a pixel array, an encapsulation layer, a polarizer, a color filter, etc.

[0021] The substrate can be, for example, a glass substrate, a flexible substrate (e.g., a polyimide substrate), etc. The pixel array is composed of multiple pixel units arranged in rows and columns, forming multiple pixel rows arranged along the row direction and multiple pixel columns arranged along the column direction. Each pixel row and each pixel column includes multiple pixel units, and each pixel unit includes multiple sub-pixels. Each sub-pixel includes a light-emitting device and pixel circuitry. For ease of description, pixel rows and pixel columns may be referred to as "rows" and "columns" thereafter. Taking an OLED display panel as an example, the pixel unit may include an organic light-emitting device and a pixel driving circuit. The pixel driving circuit may include a driving transistor configured to control the brightness of the corresponding organic light-emitting device in the display panel. In actual pixel units, the driving transistor may include, but is not limited to, low-temperature polycrystalline silicon (LTPS) and thin-film transistors (TFTs) of metal-oxide-semiconductor semiconductors. The TFT may employ a dual-gate structure, with the organic light-emitting device electrically connected to either the first or second electrode of the TFT. Organic light-emitting devices (OLEDs) can include an emissive layer, an electron transport layer, a hole transport layer, a cathode, and an anode. Different organic materials can emit light of different wavelengths to achieve full-color display. The encapsulation layer includes a multi-layer structure alternating between organic and inorganic materials. The gate driver on array (GOA) is mainly configured to drive the scanning of pixel rows. For example, the GOA circuit can include cascaded gate driver units, where each stage of the gate driver unit controls one or more pixel rows to achieve pixel selection. In some embodiments, the GOA can use single-sided or double-sided driving for multiple pixel rows. Single-sided driving can involve arranging gate driver units on only one side (such as the left or right side) and driving multiple pixel rows line by line through cascading. Double-sided driving can involve arranging driver units on both the left and right sides of the multiple pixel rows and driving multiple pixel rows line by line through the coordinated operation of both sides. The source driver circuit is configured to provide data signals to the pixel units. The timing controller is configured to receive externally input image data and synchronization signals and generate the signals required by the gate driver circuit and the source driver circuit. The power management chip is configured to provide the required operating voltage to various parts of the display panel. It should be noted that, Figure 2 This is an illustrative diagram, and the component connections shown are configured only to explain the functional logic of the display panel, not to limit the actual physical structure.

[0022] In one embodiment, such as Figure 1 and Figure 2As shown, the display device 100 includes a system-on-a-chip (SoC) 101, a timing controller 102, and a display panel 103. The timing controller 102 is connected to both the SoC 101 and the display panel 102. The display panel 103 includes multiple data lines, multiple pixels, and multiple sets of gate lines. Each data line is electrically connected to two columns of pixels located on both sides of the data line, and each row of pixels is electrically connected to a set of gate lines. Each set of gate lines includes two gate lines. The SoC 101 is configured to receive initial data to be displayed transmitted from an external device. The timing controller 102 is configured to: enable a frequency multiplication function based on the initial data; detect the grayscale difference between any two adjacent columns of data in the initial data; obtain target data based on the grayscale difference and the grayscale information to be filled between the two adjacent columns of data; and transmit the target data to the pixels for display via the data lines to improve the refresh rate of the display panel.

[0023] In this embodiment, the display panel can be implemented based on a dual-line gate (DLG) architecture to facilitate quadruple or hexaple frequency multiplication. Specifically, as an example, the DLG architecture can be configured such that each row of pixels is connected to two gate lines from a set of gate lines, with adjacent columns of pixels sharing a single data line. For instance, a set of gate lines may include a first gate line and a second gate line. The first gate line, electrically connected to the pixels in the same row, is electrically connected to the pixels in the odd-numbered columns of that row, while the second gate line is electrically connected to the pixels in the even-numbered columns of that row. The first and second gate lines are configured to sequentially output gate drive signals. This connection method enables the frequency multiplication function of the display panel.

[0024] The quadruple refresh rate function refers to achieving a display capability four times that of the original refresh rate through dual data expansion in both horizontal and vertical directions. This can be achieved using a combination of time-division multiplexing and parallel driving. Gray-scale difference detection refers to the quantification and analysis of the brightness difference between two adjacent columns of pixel data, which can be implemented through a comparator circuit or a digital signal processor. Gray-scale information to be filled refers to supplementary display data generated based on the characteristics of the original data, which can be generated using interpolation algorithms or pattern prediction methods. Target data refers to the complete display signal after integrating the original data and supplementary data, which can be implemented through a data buffer and a signal synthesis module.

[0025] Specifically, after the initial data received by the system-on-a-chip 101 is transmitted to the timing controller 102, the quadruple frequency processing module of the display panel is first activated. This module determines whether a transition grayscale value needs to be inserted by comparing the grayscale differences between adjacent data columns in the horizontal dimension. When a large difference is detected, an intermediate grayscale value is automatically calculated as fill data; when the difference is small, the grayscale data values ​​of adjacent columns are reused. In the vertical dimension, the row scan speed is doubled by simultaneously driving two sets of gate lines. Through the synergy of horizontal interpolation and vertical acceleration, the original data is expanded into a quadruple frequency signal and output to the display panel. The timing controller 102 can be referred to as Tcon IC.

[0026] As an example, by examining the grayscale difference between two adjacent columns of data, the system can intelligently choose between adaptive interpolation or copy interpolation to process intermediate data. For instance, when the grayscale difference is greater than 128, adaptive interpolation calculates an intermediate value based on the grayscale difference between the two adjacent columns as fill data, avoiding sharpening when the brightness difference between the two columns is large. When the grayscale difference is less than 128, copy interpolation uses either of the two grayscale values ​​from the two adjacent columns as fill data, avoiding sharpening when the brightness difference between the two columns is small. This dynamic selection process effectively balances image quality and refresh rate improvement.

[0027] The six-fold refresh rate function can be achieved by coordinating data interpolation and drive signal processing to increase the refresh rate to six times the original value. Specifically, this can be achieved by using a timing controller to perform step-by-step interpolation and superposition processing on the horizontal and vertical data. The grayscale difference between two adjacent columns of data can be the brightness information of the left and right adjacent columns of pixels in the same row. This can be detected by scanning each row sequentially by reading the arrangement order of pixels in the initial data. The grayscale information to be filled can be intermediate transition data generated based on the original grayscale values ​​of two adjacent columns. This can be generated by calculating the average value or selecting the original value, and configured to fill the gaps between the original data to increase data density. The target data can be a data stream with higher resolution and refresh rate formed after interpolation processing. This can be achieved by arranging the original data and the filled data in a specific timing sequence and then transmitting them to the display panel.

[0028] The system-on-a-chip (SoC), acting as the data processing hub, can be implemented using a SoC with integrated video decoding capabilities, responsible for receiving and temporarily storing external input signals. The timing controller includes a grayscale analysis module that generates transition values ​​by comparing the brightness differences between adjacent pixels, for example, by using an arithmetic logic unit to calculate the average value of adjacent grayscale levels. The display panel's wiring structure uses an interleaved connection method, with each data line serving two columns of pixel units, specifically implemented using a matrix wiring process. The gate drive circuit is configured in a synchronous trigger mode, for example, using parallel drive transistors to simultaneously activate two scan lines.

[0029] Specifically, after the initial data is transmitted to the timing controller via the system-on-a-chip (SoC), the grayscale analysis module scans the pixel values ​​of adjacent data columns row by row. When a grayscale difference is detected between two data columns, a transition grayscale value is calculated and inserted between them. For example, for adjacent columns with grayscale values ​​of 120 and 180, two transition values ​​of 150 and 160 can be inserted to form a smooth gradient. When the reconstructed target data is transmitted via the data line, it is combined with synchronously triggered dual-gate line drive, enabling more pixel rows to be refreshed in a single data write. This synergy between data processing and drive timing allows more frames to be refreshed per unit time. The timing controller 102 can be referred to as Tcon IC.

[0030] As an example, combined Figure 6 As shown, by examining the grayscale difference between two adjacent columns of data, the system can intelligently select either adaptive copying, averaging, or copying plus averaging to process intermediate data. For example, after the initial data is received, the six-fold frequency multiplication function is activated. The timing controller first analyzes the grayscale values ​​of two adjacent columns in the horizontal direction, detecting that the grayscale value of the first column is A and the grayscale value of the second column is B, and then generates two columns of fill data C and D. The fill data can be calculated based on the average or mixed value of A and B, for example, C=(A+B) / 2, D=A or B. Next, in the vertical direction, the original data is divided into three parts, and each part is interpolated in conjunction with the fill data to form the vertically expanded data. The horizontally and vertically processed data are superimposed to generate the final target data, which is then transmitted to the pixels via data lines. Simultaneously, two gate lines in a set of gate lines are driven synchronously, allowing two rows of pixels to be refreshed simultaneously in a single scan, thereby improving the refresh rate in both the horizontal and vertical dimensions. This intelligent selection process effectively balances image quality and refresh rate improvement.

[0031] This application incorporates an intelligent data processing mechanism at the hardware driver level, retaining the efficiency advantages of parallel driving while avoiding image distortion caused by simple interpolation through grayscale difference analysis. This hardware-software collaborative working mode overcomes the limitations of single-dimensional optimization. Thus, this application can significantly improve the screen refresh rate while maintaining the original data characteristics, making it particularly suitable for display scenarios with high dynamic contrast, such as game scenes. By dynamically adjusting the fill grayscale values, it effectively suppresses image tearing during high-speed refresh while maintaining the natural smoothness of color transitions. This solution improves hardware driver efficiency while compensating for potential image quality loss due to frequency multiplication through data optimization.

[0032] In one embodiment, Figure 3 One of the schematic diagrams illustrating the working scenario of the display device provided in the embodiments of this application is shown below. Figure 3As shown, the grayscale difference between two adjacent columns of data includes a first grayscale value and a second grayscale value. The timing controller is further configured to calculate a target grayscale value based on the grayscale difference between the two adjacent columns of data when the grayscale difference is greater than a preset threshold, and use the target grayscale value as the grayscale information to be filled. The target grayscale value is located between the first and second grayscale values. Alternatively, the target grayscale value is greater than the smaller of the first and second grayscale values, but less than the larger of the first and second grayscale values. The grayscale difference characterizes the degree of brightness difference between two adjacent columns of pixel data. Specifically, it can be achieved by subtracting the two columns of grayscale data using an absolute value calculation method and taking the absolute value. This difference is configured to determine the severity of the transition at the edge of the image. The preset threshold is a pre-set critical value used to distinguish between smooth areas and high-contrast areas of the image. It can be set to a fixed value based on experimental data or experience, for example, 10% of the total grayscale range. The target grayscale value refers to the transition value between the original two grayscale values. Specifically, it can be achieved by using an arithmetic logic unit to perform a weighted average operation on the first grayscale value and the second grayscale value, for example, by adding the two values ​​and then dividing by two.

[0033] Specifically, when the difference in grayscale between two adjacent columns exceeds a preset threshold, it indicates the presence of a clear boundary between light and dark areas. At this point, new fill data is generated and inserted between the original data by calculating the intermediate transition value between the two grayscale values. For example, when displaying a black-and-white boundary line, if adjacent columns in the original data are grayscale levels 0 and 255 respectively, inserting a grayscale value of 128 can create a gradient effect at the boundary. This process is completed in real-time by the timing controller's data processing module. The fill data and the original data together constitute the target data stream, which is transmitted to the pixel array via data lines.

[0034] As an example, the preset threshold can be 128. A checking mechanism can be added to the timing controller 102 to detect the data given in each frame when the fourth harmonic is enabled. When the grayscale difference between two adjacent columns of data is detected to be greater than 128, the intermediate data adopts the aforementioned adaptive interpolation method. This can avoid sharpening when the brightness difference between two adjacent columns of data is large.

[0035] This application achieves more natural image transitions while maintaining a high refresh rate by dynamically calculating intermediate grayscale values. For example, existing technologies produce a sense of discontinuity when displaying the edges of fast-moving objects, while the transition grayscale generated by this solution effectively eliminates visual discontinuity. Thus, this application can automatically generate smooth transition data even when there are significant differences in grayscale between adjacent pixels, avoiding image distortion caused by simple data copying. Especially when displaying high-speed motion scenes or high-contrast images, this technology effectively eliminates edge jaggedness and improves display quality in dynamic scenes.

[0036] In one embodiment, such as Figure 5As shown, the target grayscale value is the average grayscale value of the first grayscale value and the second grayscale value.

[0037] The target grayscale value refers to the median value obtained by mathematically equalizing the grayscale values ​​of two adjacent columns of pixels. Specifically, it can be achieved by summing the first and second grayscale values ​​using an arithmetic mean algorithm and then dividing by two. This feature is configured to generate a smoother intermediate grayscale when there is a large difference in grayscale between adjacent pixels, thus avoiding obvious brightness jumps in the image. The average grayscale value refers to the median value generated by linear interpolation. Specifically, it can be obtained by adding the two grayscale values ​​and dividing by two. For example, when the grayscale values ​​of two adjacent columns are 100 and 200, 150 is calculated as the fill grayscale. This method can effectively reduce the contrast difference between adjacent pixels and avoid jagged edges caused by abrupt changes in grayscale.

[0038] Specifically, when the grayscale difference between two adjacent columns of data exceeds a preset threshold, the timing controller averages the grayscale values ​​of the two columns. For example, when the first grayscale value is 120 and the second grayscale value is 180, the average of the sum of 300 (150) is used as the grayscale to be filled. This calculation process can be completed within the logic circuit of the timing controller, and the generated intermediate grayscale data is inserted between the original data columns to form the target data. During data transmission, the original data and the inserted data are output alternately in chronological order, doubling the amount of data transmitted in each display cycle, thereby increasing the refresh rate.

[0039] This application uses the average value of adjacent gray levels as fill data to improve the refresh rate while maintaining the continuity of gray levels in the image. Existing methods that directly copy gray level values ​​can produce visual artifacts in high-contrast areas, while the averaging method in this solution effectively eliminates such artifacts, resulting in smoother motion graphics. Thus, this application effectively avoids image edge sharpening distortion when achieving a quadruple refresh rate display, especially when displaying fast-moving images, as the intermediate data generated by the gray level averaging algorithm significantly reduces the brightness difference between adjacent pixels. When the displayed content contains gradient colors or complex textures, this technical solution ensures a natural transition between the inserted gray level data and the original data, thereby maintaining image detail. In high-dynamic scenarios such as games or video playback, this solution can improve the refresh rate while maintaining image quality, solving the problem of balancing refresh rate improvement and image quality maintenance in existing technologies.

[0040] In one embodiment, such as Figure 3 As shown, the gray level difference between two adjacent columns of data includes a first gray level value and a second gray level value; the timing controller 102 is also configured to determine the gray level information to be filled based on the first gray level value and the second gray level value when the gray level difference is less than a preset threshold.

[0041] Here, grayscale difference refers to the difference in brightness levels between two adjacent columns of pixel data. It can be calculated by comparing the grayscale values ​​of adjacent columns of pixels and is configured to determine the degree of brightness variation in adjacent areas of the image. The preset threshold is a pre-defined critical value for grayscale difference, which can be set using a fixed value or a dynamically adjusted algorithm. It is configured to distinguish whether the aforementioned adaptive data interpolation processing needs to be performed. Grayscale information to be filled refers to supplementary data inserted between two adjacent columns of data. It can be generated by directly reusing the grayscale values ​​of adjacent columns and is configured to maintain the original image features in low-difference areas.

[0042] Specifically, when the grayscale difference between two adjacent columns of pixels does not reach a preset threshold, it indicates that the brightness change in that area of ​​the image is gradual, and the original grayscale value of one column is directly selected as the intermediate fill data. For example, when displaying a gradient background, the grayscale value difference between adjacent columns is small, and reusing the data from adjacent columns can avoid artifacts caused by interpolation calculations. The timing controller alternately transmits the original data and the reused data to the pixel array via data lines, reducing the amount of data processing while maintaining a smooth image transition.

[0043] As an example, the preset threshold can be 128 (the intermediate gray level between 0-255 gray levels). When the timing controller 102 is enabled with the fourth frequency multiplication, it detects the data given in each frame. When the gray level difference between two adjacent columns of data is detected to be less than 128, the intermediate data is copied to obtain the fill gray level. At this time, the sharpening situation when the brightness difference between two adjacent columns of data is small can be avoided.

[0044] This application directly reuses the original grayscale values ​​in low-difference areas, avoiding errors introduced by interpolation algorithms and reducing computational complexity. Existing technologies cannot differentiate grayscale variations and uniformly employ interpolation. This solution uses a preset threshold to classify and process difference areas, effectively balancing image quality and processing efficiency. Thus, by reusing original data in low-grayscale difference areas, this application maintains image edge sharpness while reducing processing latency caused by interpolation calculations. In achieving a fourfold refresh rate increase, it avoids image blurring or noise issues that may result from simple interpolation, while also reducing the demand on hardware computing resources.

[0045] In one embodiment, the frequency multiplication function is a quadruple frequency multiplication function; the grayscale information to be filled is a column; the target grayscale value is one; the timing controller is further configured to use a target grayscale value as the grayscale information to be filled; or, use either the first grayscale value or the second grayscale value as a column of grayscale information to be filled.

[0046] Among them, the grayscale information to be filled refers to the supplementary data inserted between two adjacent columns of data. Specifically, it can be generated by directly reusing the grayscale values ​​of adjacent columns, and configured to maintain the original image features in low-difference areas.

[0047] Specifically, the original grayscale value of one column can be directly selected as the intermediate fill data. For example, when displaying a gradient background, the difference in grayscale values ​​between adjacent columns is small. In this case, reusing the data from adjacent columns can avoid artifacts caused by interpolation calculations. The timing controller alternately transmits the original data and the reused data to the pixel array via data lines, reducing the amount of data processing while maintaining a smooth image transition.

[0048] This application directly reuses the original grayscale values ​​in low-difference areas, avoiding errors introduced by interpolation algorithms and reducing computational complexity. Existing technologies cannot differentiate grayscale variations and uniformly employ interpolation. This solution uses a preset threshold to classify and process difference areas, effectively balancing image quality and processing efficiency. Thus, by reusing original data in low-grayscale difference areas, this application maintains image edge sharpness while reducing processing latency caused by interpolation calculations. In achieving a fourfold refresh rate increase, it avoids image blurring or noise issues that may result from simple interpolation, while also reducing the demand on hardware computing resources.

[0049] In one embodiment, the target data includes lateral target data; the initial resolution of the initial data is M1×N1, and the initial refresh rate is R1; the target resolution of the target data is M2×N2, and the target refresh rate is R2; the timing controller 102 is further configured to simultaneously send gate drive signals to two gate lines in a set of gate lines in the lateral direction to simultaneously drive the pixels connected to the two gate lines; wherein, N1=2N2, R2=2R1.

[0050] The horizontal direction refers to the direction of the horizontally arranged pixel rows in the display panel. This can be achieved by adjusting the timing of the gate drive signals, so that two lines in the same group of gate lines are activated simultaneously. Simultaneously driving two gate lines means controlling the pixels connected by two gate lines in a single scan operation. This can be achieved using time-division multiplexing or signal superposition, thereby reducing the number of horizontal scans. The relationship between the initial resolution and the target resolution is that the number of horizontal pixels is reduced to half of the original resolution. This can be achieved by merging the data transmission paths of two adjacent columns of pixels. The relationship between the initial refresh rate and the target refresh rate is that the refresh rate is increased to twice the original refresh rate. This can be achieved by shortening the single scan cycle.

[0051] Specifically, during the lateral driving process, two lines from a set of gate lines are activated simultaneously, allowing a row of pixels that would normally require two scans to be completed in a single scan. For example, when the initial resolution is 3840×2160 and the initial refresh rate is 60Hz, the target resolution can be adjusted to 3840×1080, increasing the target refresh rate to 120Hz. By driving two gate lines simultaneously, the 2160 rows of pixels that would normally require line-by-line scanning are compressed into 1080 scan operations, with each scan covering two rows of pixels, thus doubling the refresh rate while halving the number of pixels in the lateral direction.

[0052] As an example, the horizontal orientation is the same as DLG, and two lines are opened simultaneously, with the resolution halved and the refresh rate doubled.

[0053] This application, by merging drive signals in the horizontal direction, eliminates the limitation of vertical scanning mechanisms on refresh rate improvement. Existing technologies that simply copy or interpolate data can lead to image sharpening or distortion. This solution, however, adjusts the horizontal drive timing to reduce the number of scans while maintaining the original data distribution, thus avoiding a decrease in image quality. In this way, this application doubles the refresh rate while halving the horizontal resolution, solving the problem that existing DLG technologies cannot break through the double-frequency limitation. Simultaneously, since it does not rely on data interpolation or copying, it avoids image distortion caused by algorithm errors, achieving a balance between higher refresh rate and image quality.

[0054] In one embodiment, the target data includes longitudinal target data; The timing controller is also configured to obtain longitudinal target data in the longitudinal direction based on half of the initial data and the grayscale information to be filled, so that M1 = 2M2 and R2 = 2R1.

[0055] Among them, vertical target data refers to display data reconstructed from pixel data in the vertical direction. Specifically, it can be achieved by processing the original resolution data using a vertical interpolation algorithm. For example, in the vertical dimension, grayscale difference calculation is performed on the pixel data of two adjacent rows to generate the intermediate row data.

[0056] Half of the initial data refers to the amount of data after the vertical resolution is halved. Specifically, this can be achieved by extracting pixel data from odd or even rows of the original resolution at intervals. For example, in a 1080P resolution, 540 rows of valid data can be selected for processing.

[0057] The grayscale information to be filled refers to the transition grayscale data between two adjacent rows of pixels in the vertical direction. Specifically, it can be achieved by calculating the grayscale difference between adjacent rows to generate an intermediate value. For example, when the grayscale difference between two rows exceeds the threshold, the average value is inserted.

[0058] Specifically, during the vertical display driving process, the timing controller first halves the vertical resolution of the received raw image data, retaining only half of the effective rows. Then, transition rows calculated from grayscale differences are inserted between adjacent rows to form the complete vertical target data. For example, in a raw resolution of 2160 rows, by calculating the grayscale relationship between 1080 pairs of adjacent rows, a transition row is inserted between each pair, ultimately forming 2160 rows of vertical target data. This data processing method doubles the number of effective driving rows in the vertical direction of the display panel while maintaining the same data bandwidth requirements.

[0059] As an example, in this case, only half of the original data is transmitted to the timing controller vertically, while the other half is calculated by the timing controller. With the vertical data now reduced to half, the resolution is also reduced to half, thus doubling the refresh rate.

[0060] This application achieves vertical frequency multiplication through vertical data reconstruction. Existing technologies still employ line-by-line scanning in the vertical direction, while this solution, by inserting transitional grayscale data in the vertical dimension, enables a single scan to drive two rows of pixels, breaking through the limitations of traditional vertical scan rates. Thus, this application achieves decoupled control of resolution and refresh rate in vertical display driving, allowing the display device to effectively improve the vertical refresh rate through intelligent grayscale interpolation algorithms while maintaining the original data bandwidth. This solution solves the problem of vertical detail loss caused by simple horizontal frequency multiplication, maintaining vertical image continuity in moving images and avoiding vertical ghosting caused by traditional data duplication.

[0061] In one embodiment, such as Figure 1 As shown; the timing controller is also configured to overlay the horizontal target data and the vertical target data to obtain the target data, so that M1 = 2M2, N1 = 2N2, and R2 = 4R1.

[0062] The horizontal target data refers to the data used to increase the refresh rate in the horizontal direction by simultaneously driving two gate lines. This can be achieved by sending gate drive signals in parallel, activating the left and right columns of data in the same row of pixels simultaneously. The vertical target data refers to the data generated vertically based on the initial data and the grayscale information to be filled. This can be achieved by interpolation or copying adjacent grayscale values ​​to supplement vertical pixel information. Overlay processing refers to integrating the horizontally and vertically processed data. This can be achieved using data fusion algorithms or signal overlay circuits to ensure that the refresh rate improvement effects in the horizontal and vertical directions are combined.

[0063] Specifically, during the horizontal driving process, the timing controller simultaneously sends signals to two gate lines in a set, causing the data of the left and right columns of the same row of pixels to be written at the same time. During the vertical driving process, intermediate grayscale data is generated through interpolation or duplication to supplement the pixel information in the vertical direction. Subsequently, the horizontally and vertically processed data are merged into complete target data through an overlay algorithm, which halves the original resolution in both the horizontal and vertical directions, while increasing the refresh rate to four times.

[0064] As an example, assume M1 is 3840, N1 is 2160, and R1 is 60Hz; a display panel with an original resolution of 3840×2160 (4K) and a refresh rate of 60Hz. Applying the method described in this application, the process is as follows: Horizontal processing: Two rows are opened simultaneously, halving the vertical resolution to 3840×1080. This step increases the refresh rate to 120Hz. Vertical processing: The timing controller only receives data from 1920 rows (half of the original 3840). For the remaining 1920 rows, the timing controller performs calculations based on the received data. Data processing: Assuming the grayscale difference between columns 100 and 101 is 150 (greater than 128), the system will use adaptive interpolation to process the data between these two columns to avoid sharpening. Between columns 200 and 201, the grayscale difference is 80 (less than 128). The system will then use copy interpolation to process the data between these two columns to maintain a smooth image. Final result: Display resolution becomes 1920×1080 (Full HD). Refresh rate is increased to 240Hz (60Hz × 2 × 2). That is, M2 is 1920, N2 is 1080, and R1 is 240Hz. Image quality is optimized, avoiding sharpening or distortion issues that may result from simple frequency multiplication.

[0065] This application optimizes data writing efficiency in both horizontal and vertical directions by superimposing horizontal and vertical processing, avoiding the distortion risk caused by single-direction interpolation and achieving a fourfold increase in refresh rate. Thus, this application solves the problem that existing technologies cannot break through the two-fold limit. Through the coordinated processing of horizontal and vertical data, it significantly improves the dynamic response capability of the display panel while maintaining image quality, making it particularly suitable for the display needs of high frame rate games or fast-moving scenes.

[0066] In one embodiment, the frequency multiplication function is a six-fold frequency multiplication function; the grayscale information to be filled consists of two columns; there are two target grayscale values; the timing controller is further configured to use the two target grayscale values ​​as two columns of grayscale information to be filled; or, to use one of the two target grayscale values ​​as the average grayscale value of the first grayscale value and the second grayscale value, and the other as the first grayscale value or the second grayscale value.

[0067] The six-fold refresh rate function can be achieved by coordinating data interpolation and drive signal processing to increase the refresh rate to six times the original value. Specifically, this can be achieved by using a timing controller to perform step-by-step interpolation and superposition processing on the horizontal and vertical data. The grayscale difference between two adjacent columns of data can be the brightness information of the left and right adjacent columns of pixels in the same row. This can be detected by scanning each row sequentially by reading the arrangement order of pixels in the initial data. The grayscale information to be filled can be intermediate transition data generated based on the original grayscale values ​​of two adjacent columns. This can be generated by calculating the average value or selecting the original value, and configured to fill the gaps between the original data to increase data density. The target data can be a data stream with higher resolution and refresh rate formed after interpolation processing. This can be achieved by arranging the original data and the filled data in a specific timing sequence and then transmitting them to the display panel.

[0068] The system-on-a-chip (SoC), acting as the data processing hub, can be implemented using a SoC with integrated video decoding capabilities, responsible for receiving and temporarily storing external input signals. The timing controller includes a grayscale analysis module that generates transition values ​​by comparing the brightness differences between adjacent pixels, for example, by using an arithmetic logic unit to calculate the average value of adjacent grayscale levels. The display panel's wiring structure uses an interleaved connection method, with each data line serving two columns of pixel units, specifically implemented using a matrix wiring process. The gate drive circuit is configured in a synchronous trigger mode, for example, using parallel drive transistors to simultaneously activate two scan lines.

[0069] Specifically, after the initial data is transmitted to the timing controller via the system-on-a-chip (SoC), the grayscale analysis module scans the pixel values ​​of adjacent data columns row by row. When a grayscale difference is detected between two data columns, a transition grayscale value is calculated and inserted between them. For example, for adjacent columns with grayscale values ​​of 120 and 180, two transition values ​​of 150 and 160 can be inserted to form a smooth gradient. When the reconstructed target data is transmitted via the data line, it is combined with synchronously triggered dual-gate line drive, enabling more pixel rows to be refreshed in a single data write. This synergy between data processing and drive timing allows more frames to be refreshed per unit time. The timing controller 102 can be referred to as Tcon IC.

[0070] As an example, combined Figure 3As shown, by examining the grayscale difference between two adjacent columns of data, the system can intelligently select either adaptive copying, averaging, or copying plus averaging to process intermediate data. For example, after the initial data is received, the six-fold frequency multiplication function is activated. The timing controller first analyzes the grayscale values ​​of two adjacent columns in the horizontal direction, detecting that the grayscale value of the first column is A and the grayscale value of the second column is B, and then generates two columns of fill data C and D. The fill data can be calculated based on the average or mixed value of A and B, for example, C=(A+B) / 2, D=A or B. Next, in the vertical direction, the original data is divided into three parts, and each part is interpolated in conjunction with the fill data to form the vertically expanded data. The horizontally and vertically processed data are superimposed to generate the final target data, which is then transmitted to the pixels via data lines. Simultaneously, two gate lines in a set of gate lines are driven synchronously, allowing two rows of pixels to be refreshed simultaneously in a single scan, thereby improving the refresh rate in both the horizontal and vertical dimensions. This intelligent selection process effectively balances image quality and refresh rate improvement.

[0071] The grayscale value can be a numerical representation of the pixel's display brightness, specifically implemented using 8-bit or 10-bit binary data, and configured to quantify different color or brightness levels. The average grayscale value can be the intermediate value obtained by arithmetically averaging two grayscale values. This can be achieved in real-time calculation of adjacent columns of data by the timing controller's built-in processing unit, and configured to generate smooth transitions in grayscale information between adjacent pixels. The first or second grayscale value can be an unmodified grayscale value from the original input data, specifically implemented by retaining the original data through a data caching module, and configured to maintain the original display characteristics of some pixels.

[0072] Specifically, during the grayscale value processing of two adjacent columns of pixels, the timing controller first acquires the first grayscale value and the second grayscale value. Then, the processing unit generates the average grayscale value of the two as one of the data to be filled, while simultaneously selecting and retaining one of the original grayscale values ​​as the other data to be filled. For example, an average grayscale value column and an original first grayscale value column are inserted between the first and second columns, or an average grayscale value column and an original second grayscale value column are inserted between the two columns. By alternately using the average grayscale value and the original grayscale value for filling, the data density is increased to improve the refresh rate, while avoiding the image blurring or sharpening problems caused by relying entirely on interpolation.

[0073] As an example, this content can be combined Figure 3This understanding allows for the intelligent selection of adaptive copying and averaging methods to process intermediate data. For example, when the grayscale value of a pixel on the left side of a row is A and the grayscale value on the right side is B, a fill grayscale value of A or B is generated by copying A or B, and a fill grayscale value of (A+B) / 2 is generated by performing an operation on (A+B) / 2. These two fill values ​​are inserted between the original data to form the target data, enabling the data lines to drive pixels at a higher frequency during transmission while maintaining a natural grayscale transition between adjacent areas.

[0074] This application uses a hybrid approach, combining average grayscale values ​​and original grayscale values, to increase the amount of data while retaining some of the original grayscale information. This allows for smooth transitions in high refresh rates while maintaining clarity in critical areas. Thus, this application effectively balances the image quality loss caused by data interpolation while achieving a six-fold increase in refresh rate. By selectively retaining original grayscale values, it reduces image distortion caused by complete reliance on interpolation, while the insertion of some average grayscale values ​​ensures natural transitions between adjacent pixels, thereby balancing display smoothness and image fidelity in high refresh rate scenarios.

[0075] In one embodiment, the target data includes horizontal target data; the initial resolution of the initial data is M1×N1, and the initial refresh rate is R1; the target resolution of the target data is M2×N2, and the target refresh rate is R2.

[0076] The timing controller is also configured to simultaneously send gate drive signals to two gate lines in a set of gate lines in the lateral direction to simultaneously drive the pixels connected to the two gate lines; wherein, N1 = 2N2, R2 = 2R1.

[0077] The horizontal direction can refer to the direction of horizontally arranged pixel rows in the display panel. This can be achieved by adjusting the timing of the gate drive signals, so that two lines in the same group of gate lines are activated simultaneously. Simultaneously driving two gate lines can be achieved by controlling the pixels connected to the two gate lines in a single scan operation. This can be implemented using time-division multiplexing or signal superposition, thereby reducing the number of horizontal scans. The relationship between the initial resolution and the target resolution is that the number of horizontal pixels is reduced to half of the original resolution. This can be achieved by merging the data transmission paths of adjacent columns of pixels. The relationship between the initial refresh rate and the target refresh rate is that the refresh rate is increased to twice the original refresh rate. This can be achieved by shortening the single scan cycle.

[0078] The horizontal target data can be extended data generated through horizontal interpolation or data replication. Specifically, it can be achieved by interpolating the grayscale values ​​of two adjacent columns of pixels, configured to extend the image resolution in the horizontal direction. The initial resolution can be the number of rows and columns of pixels in the original input image, specifically obtained by the video signal analysis module, configured to characterize the information density of the original image. The target resolution can be the number of rows and columns of pixels in the image actually displayed on the panel after processing, specifically adjusted through the gate line grouping driving method, configured to match the physical structure of the display panel. Simultaneously driving two gate lines can be achieved by applying an enable signal to two gate lines in the same group within the same clock cycle, specifically implemented using a parallel driving circuit, configured to double the number of pixel rows covered in a single line scan operation.

[0079] Specifically, during the lateral driving process, two lines from a set of gate lines are activated simultaneously, allowing a row of pixels that would normally require two scans to be completed in a single scan. For example, when the initial resolution is 3840×2160 and the initial refresh rate is 60Hz, the target resolution can be adjusted to 3840×1080, increasing the target refresh rate to 120Hz. By driving two gate lines simultaneously, the 2160 rows of pixels that would normally require line-by-line scanning are compressed into 1080 scan operations, with each scan covering two rows of pixels, thus doubling the refresh rate while halving the number of pixels in the lateral direction.

[0080] As an example, the horizontal orientation is the same as DLG, and two lines are opened simultaneously, with the resolution halved and the refresh rate doubled.

[0081] This application, by merging drive signals in the horizontal direction, eliminates the limitation of vertical scanning mechanisms on refresh rate improvement. Existing technologies that simply copy or interpolate data can lead to image sharpening or distortion. This solution, however, adjusts the horizontal drive timing to reduce the number of scans while maintaining the original data distribution, thus avoiding a decrease in image quality. In this way, this application doubles the refresh rate while halving the horizontal resolution, solving the problem that existing DLG technologies cannot break through the double-frequency limitation. Simultaneously, since it does not rely on data interpolation or copying, it avoids image distortion caused by algorithm errors, achieving a balance between higher refresh rate and image quality.

[0082] In one embodiment, the target data includes longitudinal target data; the timing controller is further configured to obtain longitudinal target data in the longitudinal direction based on one-third of the initial data and grayscale information to be filled, such that M1 = 3M2 and R2 = 3R1.

[0083] The vertical direction can refer to the data processing method in the vertical direction of the display panel. Specifically, a time-division driving method can be used to divide the original data into multiple sub-parts for processing. By adjusting the data distribution and coordinating the timing control signals, the driving efficiency of the vertical pixels can be optimized.

[0084] The initial data can be the raw image data to be displayed transmitted from an external device. Specifically, it can be received and parsed through video bandwidth protocols or high-definition multimedia protocols, serving as the basic input for generating the target data.

[0085] The grayscale information to be filled can be intermediate data generated based on the grayscale difference between two adjacent columns of data. Specifically, it can be generated using an interpolation algorithm or a copying algorithm, and is configured to supplement the transition information between the original data to maintain the smoothness of the image.

[0086] Vertical target data can be the final output data formed after vertical processing. Specifically, it can be achieved by reducing the vertical resolution to one-third of the original data and increasing the refresh rate to three times, thereby optimizing signal transmission efficiency while maintaining image quality.

[0087] Specifically, during vertical processing, the timing controller divides the raw data into three sub-parts along the vertical direction, with each sub-part corresponding to a row of pixels in the vertical target data. By combining one-third of the raw data with the grayscale information to be filled, vertical target data containing a complete grayscale distribution is generated. During the driving process, the timing controller uses a time-division driving method to sequentially activate the pixel rows corresponding to different sub-parts, increasing the actual refresh rate of each row of pixels to three times that of the original data. This method balances the need for increased refresh rate and preservation of image detail while reducing vertical resolution by dynamically adjusting the data allocation ratio.

[0088] As an example, in this case, only 1 / 3 of the original data is transmitted to the timing controller vertically, while the other 1 / 3 is calculated by the timing controller. With the vertical data reduced to 1 / 3, the resolution becomes 1 / 3 of its original value, thus increasing the refresh rate to three times its original value.

[0089] This application decouples vertical resolution and refresh rate by introducing a data partitioning and filling mechanism in the vertical direction, enabling an independent three-fold increase in the vertical refresh rate. Simultaneously, by dynamically generating the grayscale information to be filled, it avoids the image sharpening or detail loss issues caused by simply reducing resolution. Thus, this application achieves a three-fold increase in the vertical refresh rate, which, combined with a two-fold increase in the horizontal refresh rate, ultimately achieves a six-fold increase. This solution overcomes the limitations of traditional DLG technology on the vertical refresh rate while maintaining smooth image transitions, making it particularly suitable for scenarios requiring high dynamic response speeds, such as rendering fast-moving scenes or playing high-frame-rate videos.

[0090] In one embodiment, the timing controller is further configured to overlay the lateral target data and the longitudinal target data to obtain target data such that M1 = 3M2, N1 = 2N2, and R2 = 6R1.

[0091] The horizontal target data can be compressed horizontally by merging adjacent column pixel data. This can be achieved by simultaneously driving two sets of gate lines, which reduces the horizontal pixel density but doubles the refresh rate. The vertical target data can be extended vertically by interpolation algorithms, specifically by inserting calculated grayscale values ​​in the vertical direction. This method improves the vertical scanning speed while maintaining vertical display quality. The overlay processing can fuse the horizontally compressed and vertically extended data, specifically using a pixel matrix recombination algorithm. This spatial data reconstruction achieves simultaneous optimization of resolution and refresh rate.

[0092] Specifically, in the horizontal processing stage, two sets of gate lines are synchronously activated, allowing two rows of pixels to receive data simultaneously. At this point, the original horizontal pixel column count is compressed to half, but the refresh rate doubles. In the vertical processing stage, every three rows of original pixel data are recalculated into one row of target data, and two rows of interpolated data are inserted, reducing the vertical resolution to one-third but tripling the refresh rate. When the horizontal compression and vertical expansion processing modes are combined, the overall refresh rate is increased sixfold through the product effect of the two processing modes, while maintaining effective display information.

[0093] As an example, assume M1 is 3840, N1 is 2160, and R1 is 60Hz; a display panel with an original resolution of 3840×2160 (4K) and a refresh rate of 60Hz. Applying the method described in this application, the process is as follows: Horizontal processing: Two rows are opened simultaneously, halving the vertical resolution to 3840×1080. This step increases the refresh rate to 120Hz. Vertical processing: The timing controller only receives data from 1280 columns (one-third of the original 3840). For the remaining 2560 columns, the timing controller performs column-wise calculations based on the received data. Data processing: For copying: For example, column 2 data is copied from column 1, and column 3 is copied from column 4. For averaging: For example, column 2 and column 3 data are obtained by averaging column 1 and column 4. For copying with averaging: For example, column 1 data is first copied to column 2, and then the average of column 2 and column 4 is taken to obtain column 3 data. Final result: Display resolution becomes 1280×1080 (Full HD). Refresh rate is increased to 240Hz (60Hz × 2 × 3). That is, M2 is 1280, N2 is 1080, and R1 is 360Hz. Picture quality is optimized, avoiding sharpening or distortion issues that may be caused by simple frequency multiplication.

[0094] This application overcomes the single-dimensional frequency multiplication limitation by coordinating horizontal and vertical processing while maintaining image integrity. Existing technologies, using simple data copying, lead to edge sharpening, while this solution effectively avoids image distortion through grayscale interpolation. Thus, without altering the physical structure of the display panel, this application achieves a six-fold refresh rate breakthrough through coordinated optimization of data reconstruction and driving timing. This solution solves the technical bottleneck of traditional dual-line scanning technology, which struggles to overcome the two-fold frequency multiplication limitation. It significantly reduces motion blur in fast-moving scene displays while avoiding signal integrity issues caused by simply increasing the scanning frequency. In one embodiment, such as... Figure 1 As shown; the system-on-a-chip 101 and the timing controller 102 are connected via a video bandwidth protocol interface or a high-definition multimedia protocol interface; the system-on-a-chip 101 is also configured to transmit initial data to the timing controller 102 via a video bandwidth protocol or a high-definition multimedia protocol.

[0095] Among them, the video bandwidth protocol interface refers to the physical connection interface that supports high-bandwidth video signal transmission. Specifically, it can be implemented using the V-by-One protocol interface, which improves data transmission rate through a multi-channel differential signal transmission mechanism. The high-definition multimedia protocol interface refers to the standardized interface that supports high-resolution audio and video stream transmission. Specifically, it can be implemented using the HDMI protocol interface, which achieves high-speed serial data transmission through TMDS encoding technology.

[0096] Specifically, when the system-on-chip 101 establishes a physical connection with the timing controller via the video bandwidth protocol interface, it uses an embedded clock synchronization mechanism to package and transmit the initial data. When using a high-definition multimedia protocol interface, the timing controller obtains the initial data by parsing the encoded data packets in the TMDS channel. For example, in the HDMI protocol, RGB color component data is transmitted through three independent channels. Both interfaces achieve low-latency transmission of high-resolution image data between chips by reducing the number of signal lines and increasing the single-line transmission rate.

[0097] This application employs a video bandwidth protocol or high-definition multimedia protocol interface. Through a dynamic channel allocation mechanism and efficient encoding methods, it achieves more than double the effective bandwidth increase within the same physical interface size, while simultaneously being compatible with data formats of different resolutions and color depths. Thus, this application solves the problem of limited high refresh rate data transmission in existing display devices due to insufficient interface bandwidth, enabling the timing controller to fully receive the four times the data volume required for the quadruple refresh rate function, while avoiding screen tearing or partial refresh delays caused by insufficient interface speed.

[0098] In one embodiment, the timing controller is further configured to digitize the target data to obtain digitized target data.

[0099] Digital processing can be understood as a signal format conversion function, which can analyze and process the received VBO or HDMI signals and convert them into digital (P2P) signals that the display panel can recognize and transmit them.

[0100] In one embodiment, the external device includes at least a computer host; the system-on-a-chip establishes a connection with the computer host via wired or wireless means.

[0101] In this embodiment, the system-on-a-chip 101 establishes a signal connection with the computer host via wired or wireless means to ensure stable transmission of external signals.

[0102] As an example, such as Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 As shown, Figure 3 This is one of the schematic diagrams of the working scenario of the display device provided in the embodiments of this application. Figure 4 This is a second schematic diagram of the working scenario of the display device provided in the embodiments of this application. Figure 5 The third schematic diagram of the working scenario of the display device provided in the embodiments of this application. Figure 6 The fourth schematic diagram of the working scenario of the display device provided in the embodiments of this application. Figure 7This is the fifth schematic diagram of the working scenario of the display device provided in the embodiments of this application. The system-on-a-chip 101 can be a SOC. The timing controller 102 can be a Tcon IC, abbreviated as Tcon. The display panel 103 can be a Cell. The SOC processes the signals from the computer host and sends them to the Tcon, usually using VBO or HDMI signal protocols. The Tcon processes and converts the VBO or HDMI signals from the SOC into P2P signals and sends them to the Cell to achieve the display effect. The display device of this application can achieve a four-fold frequency multiplication display effect, which can be called DLG Pro frequency multiplication technology. A checking mechanism is added to the Tcon IC to detect the data given in each frame when the four-fold frequency multiplication is enabled. Specifically, interpolation checks are performed on the gray levels of two adjacent columns of data. When the gray level difference between two adjacent columns of data is detected to be greater than 128, the intermediate data is processed by interpolation. When the gray level difference between two adjacent columns of data is less than 128, the intermediate data is processed by copying. Horizontally, it is the same as DLG, opening two rows simultaneously, halving the resolution, and doubling the refresh rate. Vertically, only half of the original data is transmitted to Tcon, with the other half calculated by Tcon. In this way, both horizontal and vertical refresh rates are doubled, achieving a 4x multiplier effect. When enabling a 6x multiplier, the horizontal direction is the same as DLG, with two lines open simultaneously, halving the resolution and doubling the refresh rate. Vertically, only one-third of the original data is transmitted to Tcon, with the other two-thirds calculated by Tcon. With the vertical data now at one-third and the resolution at one-third, the refresh rate can be tripled. Multiplying the horizontal and vertical data, 2 × 3 = 6, thus achieving a 6x multiplier. The vertical data transmission method is as follows... Figure 6 As shown.

[0103] Figure 8 A schematic diagram of the display method provided in the embodiments of this application; as shown Figure 8 As shown, the display method, using the aforementioned display device, includes: Step 801: Based on the initial data to be displayed transmitted from the external device received by the system-on-a-chip, enable the frequency multiplication function and detect the grayscale difference between any two adjacent columns of data in the initial data.

[0104] Step 802: Based on the grayscale difference and the grayscale information to be filled between two adjacent columns of data, the target data is obtained, and the target data is transmitted to the pixels of the display panel for display through the data cable of the display panel to improve the refresh rate of the display panel.

[0105] The quadruple refresh rate function refers to making the display refresh rate four times that of the original data through data interpolation and timing control. Specifically, it can be achieved by combining grayscale difference detection with dynamic interpolation algorithm, which is configured to break through the performance limitations of traditional double refresh rate technology.

[0106] Grayscale difference refers to the brightness difference between two adjacent columns of pixel data. It can be calculated by comparing the grayscale values ​​of the two columns of pixels. It is configured to determine whether an intermediate grayscale value needs to be inserted to avoid image distortion. Grayscale information to be filled refers to the transition data inserted between two adjacent columns of data. It can be generated by averaging the adjacent grayscale values ​​or by directly copying one column of data. It is configured to maintain image smoothness when the refresh rate is increased.

[0107] Data line transmission refers to transmitting processed target data to pixel units through the conductive lines of the display panel. Specifically, it can be implemented using time-division multiplexing or parallel transmission technology, configured to complete the rapid transmission of high-resolution data under limited hardware resources.

[0108] Specifically, after the system-on-a-chip (SoC) receives the initial data, the quadruple refresh rate function is activated. The timing controller calculates the grayscale difference between every two columns of adjacent pixel data. If the difference exceeds a preset threshold, a transitional grayscale value between the two columns is generated; if the difference is below the threshold, one column of data is directly reused as filler information. After processing, the target data is transmitted to the pixel unit via data lines. Simultaneously, the gate drive signal synchronously controls two sets of gate lines, driving both rows of pixels simultaneously, thereby achieving a cumulative increase in refresh rate in both the horizontal and vertical dimensions.

[0109] In some specific implementations, the grayscale difference threshold can be set to 10% of the grayscale range. For example, when the grayscale values ​​of two adjacent columns of data are 120 and 140 respectively, if the difference exceeds the threshold, 130 is inserted as a transition value. Data line transmission can adopt a dual-channel parallel mode, for example, splitting the original data into odd and even columns for separate transmission to match the data throughput requirements after quadruple frequency processing.

[0110] This application combines grayscale difference detection with dynamic interpolation to simultaneously optimize data both horizontally and vertically, achieving a fourfold increase in refresh rate while avoiding image sharpening. Traditional methods use fixed copying or averaging algorithms during interpolation, while this solution dynamically selects the interpolation strategy based on grayscale differences, effectively reducing distortion in transition areas. Thus, this application solves the problem that existing display technologies cannot exceed the double-frequency limit and that interpolation algorithms cause image distortion, achieving a fourfold increase in refresh rate while maintaining the original resolution, making it particularly suitable for display scenarios with fast-moving images. The dynamic generation mechanism of transition grayscale values ​​avoids blurring or jagged edges on large areas of color blocks, ensuring stable image quality at high refresh rates.

[0111] In one embodiment, the grayscale difference between two adjacent columns of data includes a first grayscale value and a second grayscale value; the method further includes: When the gray level difference is greater than the preset threshold, the target gray level value is calculated based on the gray level difference between two adjacent columns of data, and the target gray level value is used as the gray level information to be filled; wherein, the target gray level value is located between the first gray level value and the second gray level value.

[0112] Here, grayscale difference refers to the degree of brightness difference between two adjacent columns of pixel data. It is calculated by comparing the absolute difference in grayscale values ​​between the two columns of pixels and is configured to determine the contrast variation in adjacent areas of the image. Preset threshold is a pre-defined critical value used to distinguish the complexity of image details. It is determined experimentally to identify the optimal segmentation point for different display panels and is configured to dynamically select an interpolation strategy. Target grayscale value is the intermediate brightness value generated by the algorithm. It can be calculated using an arithmetic mean or weighted average method to find the median value between two adjacent columns of grayscale values ​​and is configured to create a smooth transition between adjacent high-contrast areas.

[0113] Specifically, when the grayscale difference between two adjacent columns exceeds a preset threshold, data interpolation is performed by dynamically calculating intermediate grayscale values. The process includes: first, scanning the input image data column by column and calculating the grayscale difference between each pair of adjacent columns in real time; when the difference exceeds a preset threshold, an interpolation algorithm is immediately triggered to generate intermediate grayscale data; then, the original data and interpolated data are alternately output to the display panel according to a predetermined time sequence. This dynamic interpolation mechanism can automatically insert transitional grayscale levels in high-contrast areas, avoiding edge sharpening caused by directly copying adjacent data, while maintaining signal transmission efficiency by optimizing the data filling method.

[0114] This application introduces a dynamic grayscale interpolation mechanism, which automatically selects the optimal interpolation strategy based on the actual screen content. This effectively eliminates image distortion while achieving a 4x refresh rate, making it particularly suitable for displaying fast-moving scenes or complex textures. Thus, this application effectively solves the display distortion problem caused by existing refresh rate technologies in high-contrast scenes. Through an intelligent grayscale interpolation algorithm, it maintains smooth image transitions while increasing the refresh rate, enabling fast-moving scenes to still present a natural and smooth visual effect in 4x refresh rate mode, significantly improving the display quality of dynamic images.

[0115] In one embodiment, the grayscale difference between two adjacent columns of data includes a first grayscale value and a second grayscale value; the method further includes: When the gray level difference is less than a preset threshold, the gray level information to be filled is determined based on the first gray level value and the second gray level value.

[0116] In one embodiment, the frequency doubling function is a quadruple frequency doubling function; the grayscale information to be filled is a column; the target grayscale value is one; the method further includes: Use a target grayscale value as the grayscale information to be filled; or, use either the first grayscale value or the second grayscale value as a column of grayscale information to be filled.

[0117] In one embodiment, the target data includes horizontal target data; the initial resolution of the initial data is M1×N1, and the initial refresh rate is R1; the target resolution of the target data is M2×N2, and the target refresh rate is R2; the method further includes: In the horizontal direction, gate drive signals are simultaneously sent to two gate lines in a set of gate lines in the display panel to drive the pixels connected to the two gate lines simultaneously; where N1 = 2N2 and R2 = 2R1.

[0118] In one embodiment, the target data includes longitudinal target data; the method further includes: In the vertical direction, the vertical target data is obtained based on half of the initial data and the grayscale information to be filled, so that M1 = 2M2 and R2 = 2R1.

[0119] In one embodiment, the method further includes: The horizontal and vertical target data are overlaid to obtain the target data, such that M1 = 2M2, N1 = 2N2, and R2 = 4R1.

[0120] In one embodiment, the frequency multiplication function is a sixth frequency multiplication function; the grayscale information to be filled is one column; the target grayscale value is one; the method further includes: the grayscale information to be filled is two columns; the target grayscale value is two; the method further includes: Use two target grayscale values ​​as two columns of grayscale information to be filled; or, use one of the two target grayscale values ​​as the average grayscale value of the first grayscale value and the second grayscale value, and the other as the first grayscale value or the second grayscale value.

[0121] In one embodiment, the target data includes horizontal target data; the initial resolution of the initial data is M1×N1, and the initial refresh rate is R1; the target resolution of the target data is M2×N2, and the target refresh rate is R2; the method further includes: In the lateral direction, gate drive signals are sent simultaneously to two gate lines in a set of gate lines to drive the pixels connected to the two gate lines at the same time; where N1 = 2N2 and R2 = 2R1.

[0122] In one embodiment, the target data includes longitudinal target data; the method further includes: In the vertical direction, the target vertical data is obtained based on one-third of the initial data and the grayscale information to be filled, so that M1 = 3M2 and R2 = 3R1.

[0123] In one embodiment, the method further includes: The horizontal and vertical target data are overlaid to obtain the target data, such that M1 = 3M2, N1 = 2N2, and R2 = 6R1.

[0124] For details of the above display method, please refer to the specific description in the relevant embodiments of the aforementioned display device, which will not be repeated here.

[0125] The display device and display method provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only configured to help understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display device, characterized in that, It includes a system-on-a-chip, a timing controller, and a display panel, wherein the timing controller is connected to the system-on-a-chip and the display panel respectively; The display panel includes multiple data lines, multiple pixels and multiple sets of gate lines. Each data line is electrically connected to two columns of pixels located on both sides of the data line. Each row of pixels is electrically connected to a set of gate lines. Each set of gate lines includes two gate lines. The system-on-a-chip is configured to receive initial data to be displayed transmitted from an external device; the initial data includes the grayscale difference between any two adjacent columns of data. The timing controller is configured to enable the frequency multiplication function based on the initial data, and to determine the target data based on the gray level difference and the gray level values ​​corresponding to the adjacent two columns of data to obtain the gray level information to be filled; the gray level information to be filled is the average value of the gray level values ​​corresponding to the adjacent two columns of data or any one of the gray level values ​​corresponding to the adjacent two columns of data. The display panel is configured to receive and display the target data transmitted by the timing controller through the data line, thereby improving the refresh rate.

2. The display device according to claim 1, characterized in that, The frequency multiplication function is a quadruple frequency multiplication function; the grayscale information to be filled is a column; the target grayscale value is one; The timing controller is further configured to use one of the target grayscale values ​​as the grayscale information to be filled; or, to use either one of the grayscale values ​​corresponding to two adjacent columns of data as a column of grayscale information to be filled.

3. The display device according to claim 2, characterized in that, The target data includes gate line scan direction target data; the initial resolution of the initial data is M1×N1, and the initial refresh rate is R1; the target resolution of the target data is M2×N2, and the target refresh rate is R2. The timing controller is further configured to simultaneously send gate drive signals to two of the gate lines in a set of gate lines in the gate line scanning direction, so as to simultaneously drive the pixels connected to the two gate lines; wherein, N1 = 2N2, R2 = 2R1.

4. The display device according to claim 3, characterized in that, The target data includes target data in the data line scanning direction; The timing controller is further configured to obtain target data in the data line scanning direction based on half of the initial data and the grayscale information to be filled, such that M1 = 2M2 and R2 = 2R1.

5. The display device according to claim 4, characterized in that, The timing controller is further configured to superimpose the target data in the gate line scan direction and the target data in the data line scan direction to obtain the target data, such that M1 = 2M2, N1 = 2N2, and R2 = 4R1.

6. The display device according to claim 1, characterized in that, The frequency multiplication function is a six-fold frequency multiplication function; the grayscale information to be filled consists of two columns; the target grayscale value is two; The timing controller is further configured to use the two target grayscale values ​​as two columns of grayscale information to be filled; or, to use one of the two target grayscale values ​​as the average grayscale value of the grayscale values ​​corresponding to the two adjacent columns of data, and the other as any one of the grayscale values ​​corresponding to the two adjacent columns of data.

7. The display device according to claim 6, characterized in that, The target data includes gate line scan direction target data; the initial resolution of the initial data is M1×N1, and the initial refresh rate is R1; the target resolution of the target data is M2×N2, and the target refresh rate is R2. The timing controller is further configured to simultaneously send gate drive signals to two of the gate lines in a set of gate lines in the gate line scanning direction, so as to simultaneously drive the pixels connected to the two gate lines; wherein, N1 = 2N2, R2 = 2R1.

8. The display device according to claim 7, characterized in that, The target data includes target data in the data line scanning direction; The timing controller is further configured to obtain target data in the data line scanning direction based on one-third of the initial data and the grayscale information to be filled, so that M1 = 3M2 and R2 = 3R1.

9. The display device according to claim 8, characterized in that, The timing controller is further configured to superimpose the target data in the gate line scan direction and the target data in the data line scan direction to obtain the target data, such that M1 = 3M2, N1 = 2N2, and R2 = 6R1.

10. The display device according to claim 1, characterized in that, The system-on-a-chip is connected to the timing controller via a video bandwidth protocol interface or a high-definition multimedia protocol interface. The system-on-a-chip is further configured to transmit the initial data to the timing controller using the video bandwidth protocol or the high-definition multimedia protocol.

11. A display method, characterized in that, The method of using the display device according to any one of claims 1-10 includes: The frequency multiplication function is enabled based on the initial data to be displayed transmitted from the external device received by the system-on-a-chip, and the gray level difference between any two adjacent columns of data in the initial data is detected. The grayscale information to be filled is obtained based on the grayscale values ​​corresponding to the two adjacent columns of data. The grayscale information to be filled is the average value of the grayscale values ​​corresponding to the two adjacent columns of data or any one of the grayscale values ​​corresponding to the two adjacent columns of data. The target data is obtained based on the grayscale difference and the grayscale information to be filled, and the target data is transmitted to the pixels of the display panel for display through the data line of the display panel to improve the refresh rate of the display panel.

12. The display method according to claim 11, characterized in that, The frequency doubling function is a quadruple frequency doubling function; the grayscale information to be filled is a column; the target grayscale value is one; the method further includes: Use one of the target grayscale values ​​as the grayscale information to be filled; or, use any one of the grayscale values ​​corresponding to the two adjacent columns of data as a column of grayscale information to be filled.

13. The display method according to claim 12, characterized in that, The target data includes horizontal target data; the initial resolution of the initial data is M1×N1, and the initial refresh rate is R1; the target resolution of the target data is M2×N2, and the target refresh rate is R2. The method further includes: In the gate line scanning direction, gate drive signals are simultaneously sent to two of the gate lines in a set of gate lines in the display panel to simultaneously drive the pixels connected to the two gate lines; wherein, N1 = 2N2, R2 = 2R1.

14. The display method according to claim 13, characterized in that, The target data includes gate line scan direction target data; the method further includes: In the gate line scanning direction, the target data for the gate line scanning direction is obtained based on half of the initial data and the grayscale information to be filled, so that M1 = 2M2 and R2 = 2R1.

15. The display method according to claim 14, characterized in that, The method further includes: The target data in the data line scanning direction and the target data in the gate line scanning direction are superimposed to obtain the target data, such that M1 = 2M2, N1 = 2N2, and R2 = 4R1.

16. The display method according to claim 11, characterized in that, The frequency multiplication function is a six-fold frequency multiplication function; the grayscale information to be filled consists of two columns; The target grayscale value is two; The method further includes: the grayscale information to be filled consists of two columns; the target grayscale values ​​are two; the method further includes: The two target grayscale values ​​are used as two columns of grayscale information to be filled; or, one of the two target grayscale values ​​is the average grayscale value of the grayscale values ​​corresponding to the two adjacent columns of data, and the other is any one of the grayscale values ​​corresponding to the two adjacent columns of data.

17. The display method according to claim 16, characterized in that, The target data includes target data in the data line scanning direction; the initial resolution of the initial data is M1×N1, and the initial refresh rate is R1; the target resolution of the target data is M2×N2, and the target refresh rate is R2. The method further includes: In the data line scanning direction, gate drive signals are simultaneously sent to two of the gate lines in a set of gate lines to simultaneously drive the pixels connected to the two gate lines; where N1 = 2N2 and R2 = 2R1.

18. The display method according to claim 17, characterized in that, The target data includes gate line scan direction target data; the method further includes: In the gate line scanning direction, the target data for the gate line scanning direction is obtained based on one-third of the initial data and the grayscale information to be filled, so that M1 = 3M2 and R2 = 3R1.

19. The display method according to claim 18, characterized in that, The method further includes: The target data in the data line scanning direction and the target data in the gate line scanning direction are superimposed to obtain the target data, such that M1 = 3M2, N1 = 2N2, and R2 = 6R1.

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