Pixel driving circuit, display driving method and display panel

Abstract

The application discloses a pixel driving circuit, a display driving method and a display panel, and belongs to the technical field of display. The pixel driving circuit comprises a first transistor, a fourth transistor and a flicker optimization unit connected between the second electrode of the fourth transistor and a target control signal line. The flicker optimization unit can reduce the potential difference between the first electrode and the second electrode of the fourth transistor in the light-emitting stage, thereby reducing the leakage current of the fourth transistor, inhibiting the drift of the gate potential of the first transistor in the light-emitting stage, ensuring the stability of the driving current flowing into the light-emitting unit, keeping the light-emitting brightness of the light-emitting unit relatively stable in the light-emitting stage, effectively inhibiting the picture flicker phenomenon when the display panel is in a low-frequency driving scene, thereby reducing the overall power consumption of the display panel while improving the picture quality and user visual experience of the display panel in the low-frequency driving scene.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel driving circuit, a display driving method, and a display panel. Background Technology

[0002] In low-frequency driving scenarios, the display panel has a lower display refresh rate, which can effectively reduce the overall power consumption of the display panel.

[0003] However, in low-frequency driving scenarios, traditional display panels are prone to screen flicker that is perceptible to the human eye, which seriously affects the image quality and user visual experience of traditional display panels in low-frequency driving scenarios.

[0004] Therefore, how to effectively suppress screen flicker in low-frequency driving scenarios, thereby improving screen quality and user visual experience in low-frequency driving scenarios, is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] A pixel driving circuit, a display driving method, and a display panel are provided to solve the above-mentioned technical problems.

[0006] In a first aspect, a pixel driving circuit is provided for driving a light-emitting unit in a display panel to emit light, comprising: a first transistor, a fourth transistor, and a flicker optimization unit; The first terminal of the first transistor is connected to the gate voltage line, the second terminal of the first transistor is connected to the light-emitting unit, the gate of the first transistor is connected to the data voltage line and the first terminal of the fourth transistor, the second terminal of the fourth transistor is connected to the reset voltage line, and the fourth transistor is connected to the first scan line. The flicker optimization unit is connected to the second electrode of the fourth transistor and is used to reduce the potential difference between the first and second electrodes of the fourth transistor during the light emission phase.

[0007] Secondly, embodiments of this application also provide a display driving method for driving a pixel driving circuit as described above, comprising: during a reset phase and a data writing phase, outputting a first scan signal to the pixel driving circuit via a first scan line, the first scan signal having pulses corresponding to the reset phase and the data writing phase; and during a light emission phase, outputting a target signal to the pixel driving circuit via a target signal line, the target signal having pulses corresponding to the light emission phase in the driving cycle of the pixel driving circuit.

[0008] Thirdly, embodiments of this application also provide a display panel, including the pixel driving circuit and the light-emitting unit as described above; the pixel driving circuit is used to drive the light-emitting unit to emit light.

[0009] The pixel driving circuit in this application includes a first transistor, a fourth transistor, and a flicker optimization unit connected between the second electrode of the fourth transistor and the target control signal line. The flicker optimization unit can reduce the potential difference between the first and second electrodes of the fourth transistor during the light-emitting stage, thereby reducing the leakage current through the fourth transistor, suppressing the gate potential drift of the first transistor during the light-emitting stage, ensuring the stability of the driving current flowing into the light-emitting unit, and making the light-emitting brightness of the light-emitting unit relatively stable during the light-emitting stage. It can effectively suppress screen flicker when the display panel is in a low-frequency driving scenario, thereby reducing the overall power consumption of the display panel and improving the screen quality and user visual experience of the display panel in a low-frequency driving scenario. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0012] Figure 1 One of the circuit structure diagrams of the pixel driving circuit provided in the exemplary embodiments of this disclosure; Figure 2 Simulated waveforms of the potentials at points Q and P in a pixel driving circuit provided as an exemplary embodiment of this disclosure; Figure 3 A second schematic diagram of the circuit structure of the pixel driving circuit provided in an exemplary embodiment of this disclosure; Figure 4 The signal timing diagram is provided for an exemplary embodiment of the pixel driving circuit of this disclosure.

[0013] Figure label: 100: Pixel driving circuit; 11: Flash optimization unit; T1: First transistor; T2: Second transistor; T5: Fifth transistor; T4: Fourth transistor; Cst: Storage capacitor; VDD: Positive power supply voltage; DATA: Data voltage; VSS: Negative power supply voltage; VI2: Reset voltage; T9: Ninth transistor; EM1: Light emission control signal; SCAN1: First scan signal; SCAN2: Second scan signal; SCAN3: Third scan signal; VI3: Anode reset voltage; EM2: Anode reset signal. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0015] In the embodiments of this application, "at least one" refers to one or more; "multiple" refers to two or more. In the description of this application, the terms "first," "second," "third," etc., are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance, nor should they be construed as indicating or implying order.

[0016] References such as “one embodiment” or “some embodiments” as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the terms “comprising,” “including,” “having,” and variations thereof, as used in this specification, mean “including, but not limited to,” unless otherwise specifically emphasized.

[0017] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0018] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0019] It should be noted that LTPS (Low Temperature Poly-Silicon) transistors have been widely used in various display panels due to their advantages such as high carrier mobility, strong driving capability, and ease of achieving high resolution and narrow bezels.

[0020] For Organic Light-Emitting Diode (OLED) display panels, since OLED devices are current-driven devices, the luminous brightness of an OLED device is directly proportional to the magnitude of the driving current flowing through it. Therefore, the core function of the pixel driving circuit in an OLED display panel is to convert the externally input data voltage into a stable and precise driving current to power the OLED device for light emission, and to maintain the driving current constant throughout the entire light emission phase of the OLED device, thereby keeping the luminous brightness of the OLED device constant.

[0021] The pixel driving circuit in an OLED display panel typically includes electronic components such as a driving transistor (Drive TFT), a data writing transistor, a reset transistor, a light-emitting control transistor, and a memory circuit. Among these, the driving transistor, data writing transistor, reset transistor, and light-emitting control transistor can all be LTPS transistors. The driving transistor is the core of the pixel driving circuit; its gate potential determines the magnitude of the driving current flowing through the OLED device. The data writing transistor is responsible for introducing the externally input data voltage into the pixel driving circuit during the writing phase. The reset transistor is responsible for resetting the potential of relevant nodes in the pixel driving circuit at the beginning of each display frame cycle to clear any residual charge from the previous display frame cycle. The light-emitting control transistor, controlled by the light-emitting control (EM) signal, is responsible for conducting the current path of the OLED device during the light-emitting phase. The memory circuit is used to maintain the gate potential of the driving transistor during the light-emitting phase.

[0022] In conventional driving scenarios, display panels operate at a relatively high refresh rate (typically no less than 60Hz). The fluctuations in OLED device brightness are not easily perceptible to the human eye due to the short duration of a single display frame cycle. However, in low-frequency driving scenarios, the display panel operates at a lower refresh rate (typically no more than 30Hz). The duration of a single display frame cycle is significantly extended, and the cumulative effect of gate potential drift in the driving transistors over time intensifies. This leads to greater fluctuations in OLED device brightness, eventually exceeding the visual fusion threshold of the human eye, resulting in visible screen flicker. This severely impacts the image quality and user experience in low-frequency display modes.

[0023] Therefore, how to effectively suppress screen flicker in low-frequency driving scenarios, thereby improving screen quality and user visual experience in low-frequency driving scenarios, is a technical problem that urgently needs to be solved in this field.

[0024] In response, this application provides a pixel driving circuit. Figure 1 This is one of the circuit structure diagrams of a pixel driving circuit provided in an exemplary embodiment of this disclosure. Please refer to... Figure 1A pixel driving circuit 100 is used to drive the light-emitting unit in the display panel to emit light, including: a first transistor T1, a fourth transistor T4 and a flicker optimization unit 11.

[0025] The first terminal of the first transistor T1 is connected to the power supply voltage line, the second terminal of the first transistor T1 is connected to the light-emitting unit, the gate of the first transistor T1 is connected to the data voltage DATA line and the first terminal of the fourth transistor T4, the second terminal of the fourth transistor T4 is connected to the reset voltage VI2 line, and the fourth transistor T4 is connected to the first scan line.

[0026] The flicker optimization unit 11 is connected to the second electrode of the fourth transistor T4 and is used to reduce the potential difference between the first and second electrodes of the fourth transistor T4 during the light emission stage.

[0027] Specifically, in this embodiment, the light-emitting unit refers to a self-emissive device in the display panel driven by the pixel driving circuit 100. As an example, the light-emitting unit can be an organic light-emitting diode (OLED) device; as another example, the light-emitting unit can also be a current-driven self-emissive device such as a quantum dot light-emitting diode (QLED) device or a mini light-emitting diode (Mini-LED) device. This embodiment does not limit the specific type of the light-emitting unit, as long as the luminous intensity of the light-emitting unit is related to the magnitude of the driving current flowing through it. The light-emitting unit in this embodiment typically includes an anode and a cathode.

[0028] It should be noted that in this embodiment, the first and second terminals of the transistor refer to one of the source and the other of the drain, respectively. As an example, if the first terminal of the transistor is the source, the second terminal is the drain; as another example, if the first terminal of the transistor is the drain, the second terminal is the source. This embodiment does not limit the specific source or drain that the first and second terminals of the transistor correspond to.

[0029] It should be noted that the transistors in this embodiment can be either P-type or N-type transistors, and the specific transistor type is not limited in this embodiment.

[0030] As an example, the transistors in this embodiment can all be low-temperature polycrystalline silicon transistors.

[0031] In this embodiment, the first transistor T1 is the driving transistor in the pixel driving circuit 100. The gate potential of the first transistor T1 determines the magnitude of the driving current flowing through the light-emitting unit, and thus determines the light emission brightness of the light-emitting unit.

[0032] In this embodiment, the first terminal of the first transistor T1 is connected to the power supply voltage line to receive the gate voltage provided by the power supply voltage line; the second terminal of the first transistor T1 is connected to one end of the light-emitting unit to provide driving current to the light-emitting unit when the first transistor T1 is turned on; the gate of the first transistor T1 is connected to the data voltage DATA line to receive the data voltage DATA provided by the data voltage DATA line; the gate of the first transistor T1 is also connected to the first terminal of the fourth transistor T4 to receive the reset voltage VI2 provided by the reset voltage VI2 line through the fourth transistor T4; the other end of the light-emitting unit is connected to the power supply line.

[0033] In this embodiment, point Q is located between the gate of the first transistor T1 and the first electrode of the fourth transistor T4. Since point Q, the gate of the first transistor T1, and the first electrode of the fourth transistor T4 are connected in series on the same signal line, the gate potential of the first transistor T1, the first electrode potential of the fourth transistor T4, and the potential of point Q are all the same.

[0034] It should be noted that in this embodiment, the power supply voltage line is used to provide a gate voltage to the first terminal of the first transistor T1, wherein the gate voltage can be a positive power supply voltage VDD; the data voltage DATA line is used to provide a data voltage DATA to the gate of the first transistor T1, the magnitude of which is positively correlated with the conduction degree between the first and second terminals of the first transistor T1, and thus positively correlated with the magnitude of the driving current flowing to the light-emitting unit through the first and second terminals of the first transistor T1; the reset voltage VI2 line is used to provide a reset voltage VI2 to the gate of the first transistor T1 through the fourth transistor T4 to reset the gate potential of the first transistor T1. The power supply line is used to provide a negative power supply voltage VSS to the light-emitting unit. In this embodiment, the specific values ​​of the gate voltage, data voltage DATA, and reset voltage VI2 are not limited, and can be configured according to the transistor type and required driving logic in the pixel driving circuit 100.

[0035] In this embodiment, the fourth transistor T4 is used to transmit the reset voltage VI2 provided by the reset voltage VI2 line to the gate of the first transistor T1 in response to the first scan signal SCAN1 transmitted by the first scan line during the driving cycle of the pixel driving circuit 100, so as to reset the gate potential of the first transistor T1. The first terminal of the fourth transistor T4 is connected to the gate of the first transistor T1, the second terminal of the fourth transistor T4 is connected to the reset voltage VI2 line, and the gate of the fourth transistor T4 is connected to the first scan line. In this embodiment, the node where the second terminal of the fourth transistor T4 is located is called point P. It can be understood that the potential difference between the first and second terminals of the fourth transistor T4 is the potential difference between point Q and point P.

[0036] It should be noted that the first scan signal SCAN1 transmitted by the first scan line has pulses. Under the action of the pulses in the first scan signal SCAN1, the first and second terminals of the fourth transistor T4 are turned on, and the potentials at point Q and point P tend to be equal. After the pulses in the first scan signal SCAN1 end, the first and second terminals of the fourth transistor T4 are turned off. In this embodiment, the timing of the pulses in the first scan signal SCAN1 is not specifically limited.

[0037] It should be noted that the driving cycle in this embodiment refers to the time period corresponding to the pixel driving circuit 100 completing one drive of the light-emitting unit. It can be understood that the driving cycle of the pixel driving circuit 100 specifically corresponds to the display frame cycle of the display panel.

[0038] One driving cycle of the pixel driving circuit 100 includes a reset phase, a write phase, and a light emission phase. The reset phase refers to the initial stage of a driving cycle where the potential of relevant nodes (e.g., Q-points) in the pixel driving circuit 100 is reset to clear any residual charge from the previous driving cycle. During the reset phase, the pulse in the first scan signal SCAN1 turns on the first and second terminals of the fourth transistor T4. The reset voltage VI2 provided by the reset voltage VI2 line resets the gate potential of the first transistor T1 through the fifth transistor T5, point P, the fourth transistor T4, and point Q. At this time, the potentials of point Q and point P are approximately equal, both close to the potential of the reset voltage VI2. During the reset phase, the potential difference between the first and second terminals of the fourth transistor T4 approaches zero.

[0039] The data writing phase refers to the stage in which the data voltage DATA provided by the data voltage DATA line is written into the pixel driving circuit 100 to determine the luminous intensity of the light-emitting unit. During the data writing phase, the data voltage DATA provided by the data voltage DATA line is written to point Q. At this time, the potential of point Q is adjusted to an operating potential determined by the data voltage DATA and the threshold voltage of the first transistor T1. It can be understood that after the data writing phase ends, the potential of point Q (i.e., the gate potential of the first transistor T1) is removed from the reset potential established in the reset phase and is at the operating potential.

[0040] The light-emitting stage refers to the stage in which the pixel driving circuit 100 drives the light-emitting unit to emit light. Figure 2 This is a simulation waveform diagram of the potential at points Q and P in the pixel driving circuit 100 provided in an exemplary embodiment of this disclosure. During the light-emitting phase, the fourth transistor T4 is in the off state, and the first transistor T1 is turned on under the control of its gate potential (i.e., the potential at point Q). The driving current generated by the first transistor T1 is injected into the light-emitting unit through the first and second terminals of the first transistor T1 to drive the light-emitting unit to emit light. During the light-emitting phase, the potential at point P gradually rises from the potential of the reset voltage VI2, and the potential difference between point Q and point P increases, that is, the potential difference between the source and drain of the fourth transistor T4 increases.

[0041] Although LTPS transistors have advantages such as high carrier mobility and strong driving capability, their threshold voltage has a large dispersion, and there is still a certain leakage current in the off state. Therefore, the increased potential difference between the source and drain of the fourth transistor T4 leads to a significant increase in the leakage current between the source and drain of the fourth transistor T4, which in turn causes the potential at the Q point to rise continuously.

[0042] Since the gate potential of the first transistor T1 is the same as the potential of the Q point, the gate potential of the first transistor T1 continuously drifts within one display frame cycle due to the potential difference between the source and drain of the fourth transistor T4. This causes dynamic changes in the driving current input to the OLED device, which ultimately manifests as continuous fluctuations in the luminous brightness of the OLED device within one display frame cycle.

[0043] It should be noted that the reset phase, data writing phase, and light emission phase described above are merely exemplary time-series divisions of a driving cycle. It is understood that a driving cycle may include one light emission phase or multiple light emission phases spaced apart; correspondingly, a driving cycle may also include one or more reset phases and data writing phases. This embodiment does not limit the specific number, duration, or timing division of each phase included in a driving cycle, as long as the target signal has a pulse corresponding to the light emission phase, enabling the flicker optimization unit 11 to reduce the potential difference between the first and second electrodes of the fourth transistor T4 during the light emission phase.

[0044] In this embodiment, the flicker optimization unit 11 applies an action to the second electrode (i.e., point P) of the fourth transistor T4 during the light-emitting phase, causing the potential of the second electrode of the fourth transistor T4 to change in a direction approaching the potential of the first electrode (i.e., point Q potential), thereby reducing the potential difference between the first and second electrodes of the fourth transistor T4 during the light-emitting phase. This embodiment does not limit the specific implementation method of the flicker optimization unit 11 in reducing the aforementioned potential difference, as long as the flicker optimization unit 11 can reduce the potential difference between the first and second electrodes of the fourth transistor T4 during the light-emitting phase based on the pulse in the target signal corresponding to the light-emitting phase.

[0045] Understandably, during the light-emitting phase, the fourth transistor T4 is in the off state. At this time, the potential at point Q needs to be maintained at the operating potential so that a stable driving current flows between the first and second terminals of the first transistor T1. The leakage path at point Q points points to point P via the fourth transistor T4, which is in the off state. Since the fourth transistor T4 still has a certain leakage current in the off state, and this leakage current increases with the increase of the potential difference between the first and second terminals of the fourth transistor T4 (i.e., the potential difference between point Q and point P), in this embodiment, the flicker optimization unit 11 connected between the second terminal of the fourth transistor T4 and the target control signal line reduces the potential difference between the first and second terminals of the fourth transistor T4 during the light-emitting phase, thereby reducing the leakage current through the fourth transistor T4, suppressing the potential drift of point Q during the light-emitting phase, and thus keeping the gate potential of the first transistor T1 relatively stable during the light-emitting phase, so that the driving current flowing through the light-emitting unit remains relatively constant, and finally keeping the luminous brightness of the light-emitting unit relatively stable during the light-emitting phase.

[0046] The pixel driving circuit in this embodiment includes a first transistor, a fourth transistor, and a flicker optimization unit connected between the second electrode of the fourth transistor and the target control signal line. The flicker optimization unit can reduce the potential difference between the first and second electrodes of the fourth transistor during the light-emitting stage, thereby reducing the leakage current through the fourth transistor, suppressing the gate potential drift of the first transistor during the light-emitting stage, ensuring the stability of the driving current flowing into the light-emitting unit, and making the light-emitting brightness of the light-emitting unit relatively stable during the light-emitting stage. It can effectively suppress screen flicker when the display panel is in a low-frequency driving scenario, thereby reducing the overall power consumption of the display panel and improving the screen quality and user visual experience of the display panel in a low-frequency driving scenario.

[0047] In some embodiments, the flicker optimization unit 11 is connected between the second electrode of the fourth transistor T4 and the target control signal line, which is used to transmit the target signal.

[0048] The target signal has a pulse corresponding to the light emission phase in the driving cycle of the pixel driving circuit 100, which causes the flicker optimization unit 11 to reduce the potential difference between the first and second electrodes of the fourth transistor T4 during the light emission phase based on the pulse.

[0049] Specifically, in this embodiment, the target control signal line is used to transmit a target signal; wherein, the target signal has a pulse corresponding to the light emission stage in the driving cycle of the pixel driving circuit 100, which means that in terms of timing, the rising edge / falling edge of the target signal pulse is located at the start time of the light emission stage, and the falling edge / rising edge of the target signal pulse is located at the end time of the light emission stage.

[0050] In this embodiment, the flicker optimization unit 11 connected between the second electrode of the fourth transistor T4 and the target control signal line utilizes the pulse in the target signal corresponding to the light emission stage to reduce the potential difference between the first and second electrodes of the fourth transistor T4 during the light emission stage. This reduces the leakage current through the fourth transistor T4, suppresses the potential drift of the Q point during the light emission stage, and thus keeps the gate potential of the first transistor T1 relatively stable during the light emission stage. This keeps the driving current flowing through the light emission unit relatively constant, and ultimately keeps the luminous brightness of the light emission unit relatively stable during the light emission stage.

[0051] Please refer to Figure 1 In some embodiments, the flicker optimization unit 11 includes a ninth transistor T9; the gate of the ninth transistor T9 is connected to the target control signal line, the first terminal of the ninth transistor T9 is connected to the second terminal of the fourth transistor T4, and the second terminal of the ninth transistor T9 is floating.

[0052] The potential of the second electrode of the ninth transistor T9 is positively correlated with the potential of the gate of the ninth transistor T9.

[0053] Specifically, the ninth transistor T9 in this embodiment can be a thin-film transistor. The ninth transistor T9 in this embodiment can be either a P-type transistor or an N-type transistor; the specific transistor type of the ninth transistor T9 is not limited in this embodiment. As an example, the ninth transistor T9 can be a low-temperature polysilicon transistor, and the ninth transistor T9 can be fabricated together with the other transistors in the pixel driving circuit 100 using the same process to simplify the fabrication process of the pixel driving circuit 100.

[0054] In this embodiment, the gate of the ninth transistor T9 is connected to the target control signal line to receive the target signal transmitted by the target control signal line; the first terminal of the ninth transistor T9 is connected to the second terminal of the fourth transistor T4, that is, the first terminal of the ninth transistor T9 is connected to point P; the second terminal of the ninth transistor T9 is floating.

[0055] It should be noted that in this embodiment, the second terminal of the ninth transistor T9 is floating, meaning that the second terminal of the ninth transistor T9 is not electrically connected to other signal lines, voltage lines, or circuit nodes with fixed potentials; that is, the second terminal of the ninth transistor T9 is in a floating state. Because the second terminal of the ninth transistor T9 is floating, no actual current path is formed between the first terminal (i.e., point P) and the second terminal of the ninth transistor T9. This prevents the introduction of an additional leakage path to point P other than the fourth transistor T4, thus avoiding any adverse impact on the potential maintenance capability of point P and even point Q due to the introduction of the flicker optimization unit 11.

[0056] It should be noted that in this embodiment, the potential of the second electrode of the ninth transistor T9 is positively correlated with the potential of the gate of the ninth transistor T9. This means that when the second electrode of the ninth transistor T9 is floating, as the potential of the target signal received by the gate of the ninth transistor T9 changes, the potential of the second electrode of the ninth transistor T9 in the floating state will change in the same direction through the coupling effect between the gate and the second electrode of the ninth transistor T9.

[0057] Please refer to Figure 2There is a parasitic capacitance between the gate and the first electrode of the ninth transistor T9. Since the target signal has a pulse corresponding to the light-emitting stage, the edge of the pulse in the target signal will cause a potential jump in the gate of the ninth transistor T9 when the pixel driving circuit 100 enters the light-emitting stage. At the instant the potential of the gate of the ninth transistor T9 jumps, the potential jump of the gate of the ninth transistor T9 will couple to the first electrode (i.e., point P) of the ninth transistor T9 via the parasitic capacitance between the gate and the first electrode, thereby pulling the potential of point P towards a potential closer to point Q, and thus reducing the potential difference between the first and second electrodes of the fourth transistor T4 (i.e., between point Q and point P) during the light-emitting stage.

[0058] For example, when all transistors in the pixel driving circuit 100 are P-type transistors, after the reset phase and data writing phase are completed, the pixel driving circuit 100 enters the light-emitting phase. At this time, the pulse in the target signal corresponding to the light-emitting phase jumps to a low potential, and the potential of the gate of the ninth transistor T9 is pulled down accordingly. This potential jump is coupled to point P through the parasitic capacitance between the gate of the ninth transistor T9 and the first electrode, so that the potential of point P is pulled down at the beginning of the light-emitting phase, reducing the potential difference between point P and point Q. This reduces the leakage current flowing from point Q to point P through the fourth transistor T4 which is in the off state, suppresses the drift of the potential of point Q (i.e., the gate potential of the first transistor T1) in the light-emitting phase, and finally keeps the light-emitting brightness of the light-emitting unit relatively stable in the light-emitting phase.

[0059] It should be noted that in this embodiment, the parasitic capacitance between the gate and the first electrode of the ninth transistor T9 can be adjusted by designing the channel width-to-length ratio (W / L). This, in turn, adjusts the change in the potential at point P caused by the pulse in the target signal coupling to point P via the ninth transistor T9, thereby flexibly adjusting the potential difference between point Q and point P during the light-emitting stage. As an example, the channel width-to-length ratio of the ninth transistor T9 can be designed according to the required reduction in the potential difference between point Q and point P during the light-emitting stage, so that the potential at point P during the light-emitting stage matches the potential at point Q.

[0060] It is understood that in this embodiment, the second electrode of the ninth transistor T9 is floating, and there is no need to arrange additional traces to connect the second electrode of the ninth transistor T9 to other signal lines, voltage lines or circuit nodes. Therefore, it is beneficial to save the layout space of the pixel driving circuit 100.

[0061] In some embodiments, the pixel driving circuit includes: an inorganic layer and a gate metal layer stacked along the thickness direction of the pixel driving circuit, the inorganic layer including wiring, the gate metal layer including a target control signal line, and a ninth transistor T9 formed at the intersection of the wiring and the target control signal line along the thickness direction of the pixel driving circuit.

[0062] It should be noted that the ninth transistor T9 in this embodiment can be laid out in a way that saves layout space. As an example, the traces connected to point P in the pixel driving circuit 100 can be formed by traces of the polysilicon layer, and the traces of the target control signal line can be formed by traces of the gate metal layer. By making the traces of the polysilicon layer and the traces of the gate metal layer overlap, the ninth transistor T9 can be formed at the overlap, thereby realizing the flicker optimization unit 11 while saving the layout space of the pixel driving circuit 100 to the greatest extent.

[0063] The flicker optimization unit in this embodiment includes a ninth transistor. The gate of the ninth transistor receives the target signal. The first electrode of the ninth transistor is connected to the second electrode of the fourth transistor. The second electrode of the ninth transistor is floating. It can utilize the parasitic capacitance between the gate and the first electrode of the ninth transistor to couple the potential jump of the pulse corresponding to the light emission stage in the target signal to point P. This reduces the potential difference between the first and second electrodes of the fourth transistor during the light emission stage. The floating second electrode of the ninth transistor does not introduce an additional leakage path to point P. Under the premise of using a single transistor, simple circuit structure, and not occupying too much layout space, it can effectively reduce the leakage current through the fourth transistor during the light emission stage and suppress the drift of the gate potential of the first transistor. Thus, it can effectively suppress screen flicker in low-frequency driving scenarios and improve the screen quality and user visual experience of the display panel in low-frequency driving scenarios.

[0064] Figure 3 This is a second schematic diagram of the circuit structure of the pixel driving circuit provided in an exemplary embodiment of this disclosure. Please refer to... Figure 3 In some embodiments, the flicker optimization unit 11 includes a first capacitor connected between the target control signal line and the second terminal of the fourth transistor T4; wherein the potential of the first terminal of the first capacitor is positively correlated with the potential of the second terminal of the first capacitor.

[0065] Specifically, the flicker optimization unit 11 in this embodiment includes a first capacitor, the first terminal of which is connected to the target control signal line and is used to receive the target signal transmitted by the target control signal line; the second terminal of the first capacitor is connected to the second terminal of the fourth transistor T4, that is, the second terminal of the first capacitor is connected to point P.

[0066] It should be noted that the first capacitor in this embodiment can be a discrete capacitor or a capacitor formed between different metal layers in the pixel driving circuit 100. The specific implementation of the first capacitor is not limited in this embodiment. As an example, the first capacitor can be formed by the overlapping areas of different metal layers in the layout of the pixel driving circuit 100, thereby simplifying the manufacturing process of the pixel driving circuit 100 and saving layout space.

[0067] It should be noted that in this embodiment, the potential of the first electrode of the first capacitor is positively correlated with the potential of the second electrode of the first capacitor. This means that, based on the charge coupling between the two plates of the capacitor, as the potential of the target signal received by the first electrode of the first capacitor changes, the potential of the second electrode of the first capacitor (i.e., point P) will change in the same direction through the coupling effect of the first capacitor. That is, when the potential of the first electrode of the first capacitor increases, the potential of the second electrode of the first capacitor changes in the direction of increasing; when the potential of the first electrode of the first capacitor decreases, the potential of the second electrode of the first capacitor changes in the direction of decreasing.

[0068] Please refer to Figure 2 Since the target signal has a pulse corresponding to the light-emitting stage, when the pixel driving circuit 100 enters the light-emitting stage, the edge of the pulse in the target signal will cause a potential jump at the first terminal of the first capacitor. At the instant the potential jumps at the first terminal of the first capacitor, the potential jump at the first terminal of the first capacitor will be coupled to the second terminal of the first capacitor (i.e., point P) through the first capacitor, thereby pulling the potential at point P towards the potential of point Q, and thus reducing the potential difference between the first and second terminals of the fourth transistor T4 (i.e., between point Q and point P) during the light-emitting stage.

[0069] For example, when all transistors in the pixel driving circuit 100 are P-type transistors, after the reset phase and data writing phase are completed, the pixel driving circuit 100 enters the light-emitting phase. At this time, the pulse in the target signal corresponding to the light-emitting phase jumps to a low potential, and the potential of the first terminal of the first capacitor is pulled down accordingly. This potential jump is coupled to point P through the first capacitor, so that the potential of point P is pulled down at the beginning of the light-emitting phase, reducing the potential difference between point P and point Q. This reduces the leakage current flowing from point Q to point P through the fourth transistor T4 which is in the off state, suppresses the drift of the potential of point Q (i.e., the gate potential of the first transistor T1) in the light-emitting phase, and finally keeps the light-emitting brightness of the light-emitting unit relatively stable in the light-emitting phase.

[0070] It should be noted that in this embodiment, the change in the potential at point P caused by the pulse in the target signal being coupled to point P via the first capacitor can be adjusted by designing the capacitance value of the first capacitor, thereby flexibly adjusting the potential difference between point Q and point P during the light-emitting stage. As an example, the capacitance value of the first capacitor can be designed according to the required reduction in the potential difference between point Q and point P during the light-emitting stage, so that the potential at point P during the light-emitting stage matches the potential at point Q.

[0071] The flicker optimization unit in this embodiment includes a first capacitor connected between the target control signal line and the second electrode of the fourth transistor. Utilizing the capacitive coupling effect of the first capacitor, the potential jump of the pulse corresponding to the light-emitting stage in the target signal is coupled to point P. This reduces the potential difference between the first and second electrodes of the fourth transistor during the light-emitting stage. Under the premise of a simple circuit structure and ease of layout implementation, this effectively reduces the leakage current through the fourth transistor during the light-emitting stage and suppresses the drift of the gate potential of the first transistor. Therefore, it effectively suppresses screen flicker in low-frequency driving scenarios, improving the image quality and user visual experience of the display panel in low-frequency driving scenarios.

[0072] Please refer to Figure 1 and Figure 3 In some embodiments, the target control signal line is the light emission control signal EM1 line, and the target signal is the light emission control signal EM1 used to control the light emission of the light emission unit.

[0073] Specifically, in this embodiment, the light emission control signal EM1 line is a signal line used to transmit the light emission control signal EM1 to the pixel driving circuit 100; the light emission control signal EM1 refers to a signal used to control the light emission process of the light emission unit.

[0074] It should be noted that the light emission control signal EM1 has pulses corresponding to the light emission stage. When the pixel driving circuit 100 enters the light emission stage, the pulses in the light emission control signal EM1 can turn on the current path between the light emission unit and the first transistor T1, thereby driving current to flow into the light emission unit through the first and second terminals of the first transistor T1, and the light emission unit emits light during the light emission stage. Outside the light emission stage, the pulses in the light emission control signal EM1 end, the current path between the light emission unit and the first transistor T1 is turned off, and the light emission unit does not emit light.

[0075] Since the timing of the pulses in the light emission control signal EM1 corresponds to the light emission stage, in this embodiment, the light emission control signal EM1 line is multiplexed as the target control signal line, and the light emission control signal EM1 is multiplexed as the target signal. That is, the flicker optimization unit 11 directly receives the light emission control signal EM1 transmitted by the light emission control signal EM1 line, and based on the pulses in the light emission control signal EM1 that correspond to the light emission stage, reduces the potential difference between the first and second electrodes of the fourth transistor T4 during the light emission stage.

[0076] In this embodiment, the light emission control signal line is multiplexed as the target control signal line, and the light emission control signal is multiplexed as the target signal. By utilizing the characteristic that the timing of the pulses in the light emission control signal corresponds to the timing of the light emission stage in the driving cycle, the flicker optimization unit can reduce the potential difference between the first and second electrodes of the fourth transistor during the light emission stage based on the light emission control signal. This allows flicker optimization to be achieved without the need for additional target control signal lines and signal generation circuits, further simplifying the signal wiring and structure of the pixel driving circuit and saving layout space.

[0077] It should be noted that the target signal in this embodiment may not be the light emission control signal EM1; the target signal only needs to contain pulses corresponding to the light emission stage.

[0078] Figure 4 The signal timing diagram is provided for an exemplary embodiment of the pixel driving circuit of this disclosure. Please refer to... Figure 4 In some embodiments, the driving cycle further includes a reset phase and a data writing phase, which are sequentially arranged in time; the first scan signal SCAN1 transmitted by the first scan line has pulses corresponding to the reset phase and the data writing phase.

[0079] Specifically, in this embodiment, a driving cycle includes a reset phase, a data writing phase, and a light emission phase arranged sequentially in time. That is, within one driving cycle, the pixel driving circuit 100 first enters the reset phase to reset the potential of the relevant nodes, then enters the data writing phase to write the data voltage DATA, and finally enters the light emission phase to drive the light-emitting unit to emit light. The specific meaning of each of the above phases can be found in the relevant descriptions in the foregoing embodiments, and will not be repeated here.

[0080] It should be noted that in this embodiment, the first scan signal SCAN1 has pulses corresponding to the reset phase and the data writing phase. This means that, in terms of timing, the rising edge / falling edge of the pulse of the first scan signal SCAN1 is located at the start time of the reset phase, and the falling edge / rising edge of the pulse of the first scan signal SCAN1 is located at the end time of the data writing phase.

[0081] Since the gate of the fourth transistor T4 is connected to the first scan line, the fourth transistor T4 is controlled by the first scan signal SCAN1: During the reset phase, the pulse in the first scan signal SCAN1 corresponding to the reset phase turns on the first and second terminals of the fourth transistor T4, and the reset voltage VI2 provided by the reset voltage VI2 line is transmitted to point Q through the fourth transistor T4. At this time, the potential of point Q and the potential of point P tend to be equal. During the data writing phase, the pulse in the first scan signal SCAN1 corresponding to the data writing phase turns on the first and second terminals of the fourth transistor T4 again, so that the potential of point Q and the potential of point P also tend to be equal during the data writing phase.

[0082] It should be noted that in this embodiment, by making the pulse in the first scan signal SCAN1 correspond to the reset stage and the data writing stage, the fourth transistor T4 can be turned on in both the reset and data writing stages, so that the potential of point P tends to be equal to the potential of point Q in both the reset and data writing stages. Therefore, when the pixel driving circuit 100 is about to enter the light-emitting stage, the potential of point P and the potential of point Q are close, providing good initial conditions for the flicker optimization unit 11 to further reduce the potential difference between point P and point Q in the light-emitting stage. After the data writing stage ends and the pixel driving circuit 100 enters the light-emitting stage, the pulse in the first scan signal SCAN1 ends, the first and second terminals of the fourth transistor T4 are turned off, and point P is subsequently disconnected from point Q.

[0083] The driving cycle in this embodiment includes a reset phase, a data writing phase, and a light emission phase arranged sequentially in time. The first scan signal has pulses corresponding to the reset phase and the data writing phase, so that the fourth transistor is turned on in both the reset phase and the data writing phase. The potential of point P tends to be equal to that of point Q in both the reset phase and the data writing phase. This makes the potentials of point P and point Q close before the pixel driving circuit enters the light emission phase, providing a good initial condition for the flicker optimization unit to further reduce the potential difference between the first and second electrodes of the fourth transistor in the light emission phase, which is beneficial to further improve the stability of the light emission brightness of the light emission unit in the light emission phase.

[0084] Please refer to Figure 1 and Figure 3 In some embodiments, it further includes: a fifth transistor T5; the first terminal of the fifth transistor T5 is connected to the second terminal of the fourth transistor T4, the second terminal of the fifth transistor T5 is connected to the reset voltage VI2 line, and the gate of the fifth transistor T5 is connected to the second scan line; wherein, the second scan signal SCAN2 transmitted by the second scan line has a pulse corresponding to the reset phase.

[0085] Specifically, in this embodiment, the fifth transistor T5 can be a thin-film transistor, and its transistor type can be the same as the other transistors in the pixel driving circuit 100. As can be seen from the previous embodiments, the first terminal of the fourth transistor T4 is connected to point Q, and the second terminal is connected to point P; the first terminal of the fifth transistor T5 is connected to point P, and the second terminal is connected to the reset voltage VI2 line. Thus, the fifth transistor T5, point P, and the fourth transistor T4 are connected in series between the reset voltage VI2 line and point Q. That is, the reset voltage VI2 provided by the reset voltage VI2 line is transmitted sequentially through the fifth transistor T5, point P, and the fourth transistor T4 to point Q, thereby resetting the potential of the gate of the first transistor T1. In this embodiment, the fourth transistor T4 and the fifth transistor T5 together constitute a dual-gate transistor structure for resetting the potential of the gate of the first transistor T1, and point P is the intermediate node of this dual-gate transistor structure.

[0086] It should be noted that in this embodiment, the second scan signal SCAN2 has a pulse corresponding to the reset phase. This means that, in terms of timing, the rising / falling edge of the pulse in the second scan signal SCAN2 is located at the start of the reset phase, and the falling / rising edge of the pulse in the second scan signal SCAN2 is located at the end of the reset phase. Since the gate of the fifth transistor T5 is connected to the second scan line, during the reset phase, the pulse in the second scan signal SCAN2 corresponding to the reset phase turns on the first and second terminals of the fifth transistor T5.

[0087] It should be noted that, as in the aforementioned embodiment, during the reset phase, the pulse in the first scan signal SCAN1 corresponding to the reset phase turns on the first and second terminals of the fourth transistor T4; simultaneously, in this embodiment, the pulse in the second scan signal SCAN2 corresponding to the reset phase turns on the first and second terminals of the fifth transistor T5. Therefore, during the reset phase, both the fourth transistor T4 and the fifth transistor T5 are in the on state, and the reset voltage VI2 is transmitted sequentially through the fifth transistor T5, point P, and the fourth transistor T4 to point Q, causing the potentials of both point Q and point P to be reset to a level close to the reset voltage VI2, meaning that during the reset phase, the potentials of point Q and point P tend to be equal.

[0088] Outside the reset phase, the pulse in the second scan signal SCAN2 ends, and the first and second terminals of the fifth transistor T5 are turned off, thereby disconnecting point P from the reset voltage VI2 line. It can be understood that during the light-emitting phase, both the fourth transistor T4 and the fifth transistor T5 are in the off state. Point P is located between the off-state fourth transistor T4 and the off-state fifth transistor T5. Therefore, the leakage path at point Q is the only path from the fourth transistor T4 to point P. In this embodiment, the flicker optimization unit 11 can effectively suppress leakage current through this unique leakage path by reducing the potential difference between the first and second terminals of the fourth transistor T4 during the light-emitting phase.

[0089] The pixel driving circuit in this embodiment also includes a fifth transistor. The fifth transistor and the fourth transistor together form a dual-gate transistor structure to reset the potential of the gate of the first transistor. This allows the reset voltage to be transmitted sequentially through the fifth transistor, point P, and the fourth transistor to point Q. During the light-emitting stage, both the fourth and fifth transistors are turned off, causing the leakage path at point Q to converge into a single path pointing to point P via the fourth transistor. This improves the reliability of resetting the gate potential of the first transistor. In conjunction with the flicker optimization unit, it reduces the potential difference between the first and second electrodes of the fourth transistor during the light-emitting stage, effectively suppressing the leakage current through this single leakage path. This further improves the stability of the light-emitting unit's brightness in low-frequency driving scenarios.

[0090] In some embodiments, the pixel driving circuit 100 further includes: an eighth transistor; the first terminal of the eighth transistor is connected to the second terminal of the fourth transistor T4, the second terminal of the eighth transistor is connected to the second terminal of the first transistor T1 and the light-emitting unit, and the gate of the eighth transistor is connected to the third scan line.

[0091] Among them, the third scan signal SCAN3 transmitted by the third scan line has a pulse corresponding to the data writing stage.

[0092] Specifically, in this embodiment, the eighth transistor can be a thin-film transistor, and its transistor type can be the same as the other transistors in the pixel driving circuit 100. In this embodiment, the first terminal of the eighth transistor is connected to the second terminal (i.e., point P) of the fourth transistor T4, the second terminal of the eighth transistor is connected to the second terminal of the first transistor T1 and the light-emitting unit, and the gate of the eighth transistor is connected to the third scan line.

[0093] It should be noted that in this embodiment, the third scan signal SCAN3 has pulses corresponding to the data writing stage. This means that, in terms of timing, the rising / falling edge of the pulse in the third scan signal SCAN3 is located at the start time of the data writing stage, and the falling / rising edge of the pulse in the third scan signal SCAN3 is located at the end time of the data writing stage. Since the gate of the eighth transistor is connected to the third scan line, during the data writing stage, the pulse in the third scan signal SCAN3 corresponding to the data writing stage turns on the first and second terminals of the eighth transistor; outside the data writing stage, when the pulse in the third scan signal SCAN3 ends, the first and second terminals of the eighth transistor are turned off.

[0094] In this embodiment, the eighth transistor is turned on during the data writing phase, connecting the second terminal of the fourth transistor T4 (i.e., point P) with the second terminal of the first transistor T1 and the light-emitting unit. This provides a corresponding current path for the pixel driving circuit 100 during the data writing phase, facilitating the data voltage DATA writing and threshold compensation process. During the light-emitting phase, the pulse in the third scan signal SCAN3 ends, and the connection between the first and second terminals of the eighth transistor is turned off. This prevents additional connection between point P and the second terminal of the first transistor T1 and the light-emitting unit via the eighth transistor during the light-emitting phase, thus avoiding introducing an additional leakage path for point P during the light-emitting phase.

[0095] The pixel driving circuit in this embodiment also includes an eighth transistor. The eighth transistor is turned on during the data writing stage to connect the second terminal of the fourth transistor with the second terminal of the first transistor and the light-emitting unit, thereby providing a current path for data voltage writing and threshold compensation. It is turned off during the light-emitting stage to avoid introducing an additional leakage path to point P. This can improve the data writing and threshold compensation functions of the pixel driving circuit while ensuring the stability of the potential of point P during the light-emitting stage, thereby further improving the stability of the light-emitting unit's brightness in conjunction with the flicker optimization unit.

[0096] In some embodiments, the pixel driving circuit 100 further includes: a second transistor T2 and a storage capacitor Cst; the first terminal of the second transistor T2 is connected to the data voltage DATA line, the second terminal of the second transistor T2 is connected to the first terminal of the storage capacitor Cst and the gate of the first transistor T1, the gate of the second transistor T2 is connected to the third scan line, and the other terminal of the storage capacitor Cst is connected to the power supply voltage line.

[0097] Specifically, in this embodiment, the second transistor T2 can be a thin-film transistor, and its transistor type can be the same as the other transistors in the pixel driving circuit 100; the storage capacitor Cst in this embodiment can be a discrete capacitor or it can be composed of capacitors formed between different metal layers in the pixel driving circuit 100. In this embodiment, the second transistor T2 is a data writing transistor in the pixel driving circuit 100, used to write the data voltage DATA provided by the data voltage DATA line to the gate (i.e., Q point) of the first transistor T1 during the data writing stage.

[0098] It should be noted that in this embodiment, the gate of the second transistor T2 is connected to the third scan line, and the third scan signal SCAN3 has a pulse corresponding to the data writing stage. Therefore, during the data writing stage, the pulse in the third scan signal SCAN3 corresponding to the data writing stage turns on the first and second terminals of the second transistor T2, and the data voltage DATA provided by the data voltage DATA line is written to point Q through the second transistor T2; outside the data writing stage, when the pulse in the third scan signal SCAN3 ends, the first and second terminals of the second transistor T2 are turned off, thereby disconnecting point Q from the data voltage DATA line.

[0099] As can be seen from the foregoing embodiments, in this embodiment, the gates of the second transistor T2 and the eighth transistor are both connected to the third scan line. That is, the third scan signal SCAN3 simultaneously controls the second transistor T2 and the eighth transistor to be turned on during the data writing stage, so that the data writing process of the second transistor T2 and the current path provided by the eighth transistor are synchronized during the data writing stage, which helps to simplify the scanning signal wiring of the pixel driving circuit 100.

[0100] In this embodiment, the storage capacitor Cst is connected between point Q and the power supply voltage line. During the data writing phase, the potential of point Q is adjusted to the operating potential determined by the data voltage DATA and the threshold voltage of the first transistor T1, and the storage capacitor Cst stores the potential of point Q. After the data writing phase ends and the pixel driving circuit 100 enters the light-emitting phase, the storage capacitor Cst is used to maintain the potential of point Q (i.e., the gate potential of the first transistor T1), so that the first transistor T1 outputs a relatively stable driving current during the light-emitting phase.

[0101] It is understandable that although the storage capacitor Cst can maintain the potential of point Q, during the light-emitting phase, leakage current will still be generated from point Q to point P through the fourth transistor T4, which is in the off state, thus causing the potential of point Q to drift. In this embodiment, by reducing the potential difference between the first and second electrodes of the fourth transistor T4 during the light-emitting phase through the flicker optimization unit 11, the aforementioned leakage current can be reduced, thereby further improving the stability of the potential of point Q during the light-emitting phase in conjunction with the storage capacitor Cst.

[0102] The pixel driving circuit in this embodiment also includes a second transistor and a storage capacitor. The second transistor is turned on during the data writing phase to write the data voltage to the gate of the first transistor. The storage capacitor is connected between the gate of the first transistor and the power supply voltage line to maintain the gate potential of the first transistor during the light emission phase. The gates of both the second transistor and the eighth transistor are connected to the third scan line and are synchronously controlled by the third scan signal. This can improve the data writing and potential maintenance functions of the pixel driving circuit, simplify the scan signal wiring, and, in conjunction with the flicker optimization unit, further enhance the stability of the gate potential of the first transistor and the brightness of the light emission unit during the light emission phase.

[0103] In some embodiments, the pixel driving circuit 100 further includes: a sixth transistor; the first terminal of the sixth transistor is connected to the second terminal of the first transistor T1, the second terminal of the sixth transistor is connected to the light-emitting unit, and the gate of the sixth transistor is connected to the light-emitting control signal EM1 line.

[0104] Specifically, the sixth transistor in this embodiment can be a thin-film transistor, and its transistor type can be the same as the other transistors in the pixel driving circuit 100.

[0105] As in the aforementioned embodiment, the light-emitting control signal EM1 has pulses corresponding to the light-emitting stage. Therefore, during the light-emitting stage, the pulses in the light-emitting control signal EM1 corresponding to the light-emitting stage turn on the first and second terminals of the sixth transistor, and the driving current is injected into the light-emitting unit through the first transistor T1 and the sixth transistor to drive the light-emitting unit to emit light; outside the light-emitting stage, the pulses in the light-emitting control signal EM1 end, and the first and second terminals of the sixth transistor turn off. Even if the first transistor T1 is still in the on state under the action of its gate potential, the driving current generated by the first transistor T1 cannot be injected into the light-emitting unit through the sixth transistor, and the light-emitting unit does not emit light.

[0106] The pixel driving circuit in this embodiment also includes a sixth transistor. The sixth transistor, as a light-emitting control transistor, conducts the current path between the first transistor and the light-emitting unit during the light-emitting stage under the control of the light-emitting control signal. This not only improves the light-emitting control function of the pixel driving circuit, but also provides a basis for multiplexing the light-emitting control signal as the target signal. This is beneficial to reduce the potential difference between the first and second electrodes of the fourth transistor during the light-emitting stage without the need to set an additional target control signal line.

[0107] In some embodiments, the pixel driving circuit 100 further includes: a seventh transistor; the first terminal of the seventh transistor is connected to the second terminal of the sixth transistor and the light-emitting unit, the second terminal of the seventh transistor is connected to the anode reset voltage VI3 line, and the gate of the seventh transistor is connected to the anode reset signal EM2 line.

[0108] Specifically, the seventh transistor in this embodiment can be a thin-film transistor, and its transistor type can be the same as the other transistors in the pixel driving circuit 100. In this embodiment, the seventh transistor is used to reset the potential of the anode of the light-emitting unit.

[0109] It should be noted that in this embodiment, the anode reset voltage line VI3 is used to provide the anode reset voltage VI3 to the second terminal of the seventh transistor; the anode reset signal line EM2 is used to transmit the anode reset signal EM2 to the gate of the seventh transistor. It is understood that the anode of the light-emitting unit has parasitic capacitance. The driving voltage of the previous light-emitting stage and the light-emitting current flowing through the light-emitting unit will accumulate residual charge on the anode of the light-emitting unit. If this residual charge is not removed, in subsequent light-emitting processes, the anode of the light-emitting unit will carry the residual charge from the previous light-emitting stage into the new light-emitting state, which may cause brightness fluctuations, ghosting, and afterimages.

[0110] Therefore, in this embodiment, the seventh transistor is used to reset the potential of the anode of the light-emitting unit before the light-emitting unit is lit, in response to the anode reset signal EM2 transmitted via the anode reset signal EM2 line. Specifically, when the anode reset signal EM2 turns on the first and second terminals of the seventh transistor, the anode reset voltage VI3 provided by the anode reset voltage VI3 line is injected into the anode of the light-emitting unit via the seventh transistor, resetting the potential of the anode of the light-emitting unit to the anode reset voltage VI3, thereby clearing the residual charge accumulated on the anode of the light-emitting unit and improving the aforementioned phenomena such as brightness fluctuations, ghosting, and afterimages; while when the anode reset signal EM2 turns off the first and second terminals of the seventh transistor, the anode of the light-emitting unit is disconnected from the anode reset voltage VI3 line to avoid the anode reset voltage VI3 interfering with the light-emitting process of the light-emitting unit.

[0111] It should be noted that the reset of the anode of the light-emitting unit by the seventh transistor in this embodiment, and the reset of the gate (i.e., Q point) of the first transistor T1 by the aforementioned fourth transistor T4 and fifth transistor T5, are reset processes performed on different nodes in the pixel driving circuit 100. The object reset by the seventh transistor is the anode of the light-emitting unit, while the objects reset by the fourth transistor T4 and fifth transistor T5 are the gate of the first transistor T1, and the two are independent of each other.

[0112] The pixel driving circuit in this embodiment also includes a seventh transistor. In response to the anode reset signal, the seventh transistor injects the anode reset voltage into the anode of the light-emitting unit to reset the potential of the anode of the light-emitting unit. This can clear the residual charge accumulated on the anode of the light-emitting unit. Thus, based on the flicker optimization unit suppressing the gate potential drift of the first transistor, it further improves the brightness fluctuation, ghosting and afterimage phenomena caused by the accumulation of residual charge on the anode of the light-emitting unit, thereby improving the display quality of the display panel.

[0113] Based on the above embodiments, this application also provides a display driving method for driving a pixel driving circuit as described above, comprising: during a reset phase and a data writing phase, outputting a first scan signal to the pixel driving circuit through a first scan line, the first scan signal having pulses corresponding to the reset phase and the data writing phase; and during a light emission phase, outputting a target signal to the pixel driving circuit through a target signal line, the target signal having pulses corresponding to the light emission phase in the driving cycle of the pixel driving circuit.

[0114] In this embodiment, a driving cycle of the pixel driving circuit includes a reset phase, a data writing phase, and a light emission phase arranged sequentially in time. During the reset and data writing phases, a first scan signal with pulses corresponding to the reset and data writing phases is output to the pixel driving circuit via a first scan line. During the light emission phase, a target signal with pulses corresponding to the light emission phase in the driving cycle of the pixel driving circuit is output to the pixel driving circuit via a target signal line. The pulses in the target signal corresponding to the light emission phase can be used to reduce the potential difference between the first and second electrodes of the fourth transistor during the light emission phase, thereby reducing the leakage current through the fourth transistor and suppressing the Q-point. The potential drift during the light-emitting phase allows the gate potential of the first transistor to remain relatively stable during the light-emitting phase, and also allows the driving current flowing through the light-emitting unit to remain relatively constant. Ultimately, this keeps the brightness of the light-emitting unit relatively stable during the light-emitting phase, allowing the fourth transistor to conduct during both the reset and data writing phases. The potential at point P tends to be equal to the potential at point Q during the reset and data writing phases. This makes the potentials at point P and point Q close before the pixel driving circuit enters the light-emitting phase, providing good initial conditions for the flicker optimization unit to further reduce the potential difference between the first and second electrodes of the fourth transistor during the light-emitting phase, which is beneficial to further improving the stability of the brightness of the light-emitting unit during the light-emitting phase.

[0115] Based on the above embodiments, this application also provides a display panel, which includes a pixel driving circuit 100 as described in any of the above embodiments and a light-emitting unit; the pixel driving circuit 100 is used to drive the light-emitting unit to emit light.

[0116] Specifically, the display panel in this embodiment may include a plurality of light-emitting units arranged in an array and a plurality of pixel driving circuits 100 corresponding to each light-emitting unit. Each pixel driving circuit 100 is used to drive its corresponding light-emitting unit to emit light. The specific structure, connection relationship and working principle of the pixel driving circuit 100 can be found in the relevant description in any of the foregoing embodiments, and will not be repeated here.

[0117] It should be noted that the display panel in this embodiment can be applied to electronic devices with display functions such as televisions, monitors, laptops, tablets, mobile phones, and wearable devices, and this embodiment does not limit it.

[0118] The display panel in this embodiment includes the aforementioned pixel driving circuit and light-emitting unit. Since the pixel driving circuit can utilize the flicker optimization unit to reduce the potential difference between the first and second electrodes of the fourth transistor during the light-emitting stage based on the pulse in the target signal corresponding to the light-emitting stage, thereby reducing the leakage current through the fourth transistor and suppressing the drift of the gate potential of the first transistor, the light-emitting unit's brightness remains relatively stable during the light-emitting stage. Therefore, the display panel can effectively suppress screen flicker in low-frequency driving scenarios, thereby reducing the overall power consumption of the display panel while improving the screen quality and user visual experience of the display panel in low-frequency driving scenarios.

[0119] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0120] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A pixel driving circuit for driving light-emitting units in a display panel to emit light, characterized in that, include: The first transistor, the fourth transistor, and the scintillation optimization unit; The first terminal of the first transistor is connected to the power supply voltage line, the second terminal of the first transistor is connected to the light-emitting unit, the gate of the first transistor is connected to the data voltage line and the first terminal of the fourth transistor, the second terminal of the fourth transistor is connected to the reset voltage line, and the fourth transistor is connected to the first scan line. The flicker optimization unit is connected to the second electrode of the fourth transistor and is used to reduce the potential difference between the first and second electrodes of the fourth transistor during the light emission phase.

2. The pixel driving circuit according to claim 1, characterized in that, The flicker optimization unit is connected between the second electrode of the fourth transistor and the target control signal line, which is used to transmit the target signal. The target signal has a pulse that corresponds to the light-emitting phase in the driving cycle of the pixel driving circuit.

3. The pixel driving circuit according to claim 2, characterized in that, The scintillation optimization unit includes a ninth transistor; The gate of the ninth transistor is connected to the target control signal line, the first terminal of the ninth transistor is connected to the second terminal of the fourth transistor, and the second terminal of the ninth transistor is floating. The potential of the second electrode of the ninth transistor is positively correlated with the potential of the gate of the ninth transistor.

4. The pixel driving circuit according to claim 3, characterized in that, include: An inorganic layer and a gate metal layer are stacked along the thickness direction of the pixel driving circuit. The inorganic layer includes a trace, and the gate metal layer includes the target control signal line. The ninth transistor is formed at the intersection of the trace and the target control signal line in the thickness direction of the pixel driving circuit.

5. The pixel driving circuit according to claim 2, characterized in that, The flicker optimization unit includes a first capacitor connected between the target control signal line and the second electrode of the fourth transistor; The potential of the first terminal of the first capacitor is positively correlated with the potential of the second terminal of the first capacitor.

6. The pixel driving circuit according to claim 2, characterized in that, The target control signal line is a light emission control signal line, and the target signal is a light emission control signal used to control the light emission of the light emission unit.

7. The pixel driving circuit according to any one of claims 2 to 6, characterized in that, The driving cycle also includes a reset phase and a data writing phase, and the reset phase, the data writing phase and the light emission phase are arranged sequentially in time. The first scan signal transmitted by the first scan line has pulses corresponding to the reset phase and the data writing phase.

8. The pixel driving circuit according to claim 7, characterized in that, Also includes: The fifth transistor; The first terminal of the fifth transistor is connected to the second terminal of the fourth transistor, the second terminal of the fifth transistor is connected to the reset voltage line, and the gate of the fifth transistor is connected to the second scan line. The second scan signal transmitted by the second scan line has a pulse corresponding to the reset phase.

9. The pixel driving circuit according to claim 8, characterized in that, Also includes: Second transistor and storage capacitor; The first terminal of the second transistor is connected to the data voltage line, the second terminal of the second transistor is connected to one terminal of the storage capacitor and the gate of the first transistor, the gate of the second transistor is connected to the third scan line, the other terminal of the storage capacitor is connected to the power supply voltage line, and the third scan signal transmitted by the third scan line has a pulse corresponding to the data writing stage.

10. A display driving method for driving a pixel driving circuit as described in any one of claims 7 to 9, characterized in that, include: During the reset and data writing phases, a first scan signal is output to the pixel driving circuit via a first scan line. This first scan signal has pulses corresponding to the reset and data writing phases, and... During the light-emitting phase, a target signal is output to the pixel driving circuit through the target signal line. The target signal has a pulse corresponding to the light-emitting phase in the driving cycle of the pixel driving circuit.

11. A display panel, characterized in that, It includes a pixel driving circuit as described in any one of claims 1 to 9 and a light-emitting unit; the pixel driving circuit is used to drive the light-emitting unit.

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