Instruction-level programming control device and pipeline synchronous programming method for resistive random access memory

Abstract

The application discloses a kind of resistive random access memory instruction level programming control device, pipeline synchronous programming method and compiler instruction rearrangement and scheduling method.The device includes processor and resistive random access memory execution unit, and processor instruction set contains programming instruction, start verification instruction and read-back result instruction;Programming instruction is uniform programming instruction, hardware hosting instruction is returned immediately after being launched without blocking processor;Hardware handshake signal line is provided between instruction launch unit and execution unit, and according to the state signal of execution unit, subsequent hardware hosting instruction is kept in pipeline launch slot when execution unit is busy, and read-back result instruction is kept in pipeline launch slot when verification data is not ready.Execution unit responds to hardware hosting instruction, and the pre-configuration signal in configuration register is latched, and hardware state machine is independently generated physical timing signal according to the pre-configuration signal of latching and is applied to resistive random access memory array.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit and computer architecture technology, and more specifically, to an instruction-level programming control device and a pipelined synchronous programming method for resistive random access memory. Background Technology

[0002] In traditional memory designs (such as SRAM, DRAM, or conventional non-volatile memory), the processor typically sends programming commands to the controller via memory-mapped I / O. The processor then uses software to continuously poll the controller's status register to confirm whether the operation is complete. This "command-polling-wait" interaction works effectively because write operations to conventional memory are relatively fast and have a relatively predictable time consumption, and the overhead of software polling is within an acceptable range.

[0003] However, with the rise of RRAM (Resistive Random Access Memory) technology, RRAM is not only used as a high-density non-volatile storage medium, but also widely used as a weight carrier in neural network computing in-memory (CIM) arrays. Unlike SRAM or DRAM, RRAM programming is essentially a simulated physical process. The duration of its physical timing parameters, such as pulse width and voltage amplitude, is typically on the order of tens of nanoseconds to microseconds, much longer than the clock cycle of modern processors, and the actual time consumption of a single programming operation is uncertain. If the traditional "command-polling-wait" strategy is directly adopted, the processor needs to spend tens or even hundreds of times more cycles than the normal instruction execution time during each RRAM programming operation to poll the status register, resulting in a serious waste of processor computing resources. If the physical timing is directly controlled by the processor software, it is difficult to guarantee the nanosecond-level pulse accuracy required by the processor pipeline due to execution jitter and interrupt response latency. In in-memory computing scenarios, accurate writing of weights requires multiple Program-Verify iteration loops. If the traditional peripheral control architecture is still used in each iteration, it will have to go through a long path of "sending programming commands → polling and waiting for programming to complete → sending verification commands → polling and waiting for verification to complete → reading results → software judgment", which results in extremely low efficiency of weight update.

[0004] Therefore, how to eliminate the processor's wasted computing cycles caused by software polling while retaining the processor's high-level control flexibility over RRAM programming operations has become an urgent technical problem to be solved. Summary of the Invention

[0005] This specification provides an instruction-level programming control device and a pipelined synchronous programming method for resistive random access memory (RRAM) to overcome at least one technical problem existing in related technologies.

[0006] According to a first aspect of the embodiments of this specification, an instruction-level programming control device for a resistive random access memory is provided, comprising: A processor includes an instruction fetch unit, an instruction dispatch unit, and pipeline control logic; The resistive random access memory execution unit includes a hardware state machine, configuration registers, latches, and a physical array interface, and is connected to the processor; The processor's instruction set includes hardware-managed instructions for controlling the programming of resistive random access memory (RRAM). These hardware-managed instructions include programming instructions, start verification instructions, and readback result instructions. The programming instructions are unified programming instructions, which, through a mode selection signal in the configuration register, determine whether to execute a SET operation to set the memory cell to a low-resistance state, a RESET operation to set it to a high-resistance state, or a FORM operation to initially activate it. The hardware-managed instructions return immediately after being issued without blocking the processor, which continues to issue and execute non-hardware-managed instructions without blocking. A hardware handshake signal line is provided between the instruction issuing unit and the resistive random access memory (RRAM) execution unit. The hardware handshake signal line is used to transmit the status signal of the RRAM execution unit to the instruction issuing unit. The status signal includes a first status signal indicating whether the RRAM execution unit is in a busy state and a second status signal indicating whether the verification data is ready. The resistive random access memory execution unit is configured to: in response to the hardware managed instruction issued by the processor, the latch latches the pre-configuration signal in the configuration register, and the hardware state machine autonomously generates physical timing signals based on the latched pre-configuration signal and applies them to the resistive random access memory array through the physical array interface; The instruction issuing unit is configured to: hold subsequent hardware-managed instructions in the pipeline issuing slot when the resistive random access memory execution unit is in a busy state, based on the status signal transmitted by the hardware handshake signal line, and hold the readback result instruction in the pipeline issuing slot when the second status signal indicates that the data is not ready.

[0007] In some optional implementations, the configuration register is used to store software pre-configuration signals, including operating voltage adjustment values, multi-stage pulse width time parameters, row and column selection addresses, multiple sampling averaging times, and programming mode selection. The configuration register has a system bus interface for connecting to the processor to receive the pre-configuration signal written by the processor via non-hardware managed instructions; The latch is used to latch the pre-configuration signal in the configuration register when the hardware managed instruction is received, and the hardware state machine generates dynamic physical timing signals based on the latched pre-configuration signal; The output of the configuration register is sampled and held by the latch. After the hardware-managed instruction triggers the latch, the output value of the latch no longer changes with subsequent changes to the configuration register.

[0008] In some alternative implementations, the hardware state machine includes unified state transition control logic, which includes an idle state, a first waiting state for waiting for the analog voltage to stabilize, and a second waiting state for applying a programming pulse or a sampling pulse. The configuration register contains multiple pulse width time parameter storage areas, with different storage areas corresponding to different instruction modes. The hardware state machine selects different pulse width time parameters from the configuration register under different instruction modes to control the duration of the first waiting state and the second waiting state.

[0009] In some optional implementations, the resistive random access memory execution unit further includes an analog-to-digital conversion processing module and a read-only register; The analog-to-digital conversion processing module is connected to the physical array interface and is used to read the analog data of the resistive random access memory array. The analog-to-digital conversion processing module includes an accumulation averaging unit and a bit width conversion unit. The accumulation averaging unit is used to accumulate multiple sampled data in multiple cycles according to the number of averaging calculations pre-configured in the configuration register. The bit width conversion unit is used to perform mean calculation and bit width conversion on the accumulation result. The read-only register is used to store the digital result processed by the analog-to-digital conversion module and to output the second status signal.

[0010] According to a second aspect of the embodiments of this specification, a pipelined synchronous programming method for resistive random access memory is provided, comprising the steps of: The programming instructions are sent from the processor to the resistive random access memory execution unit. After the programming instructions are sent, the processor immediately returns and continues to send subsequent instructions. In response to the issuance of the programming instruction, the hardware state machine of the resistive random access memory execution unit enters a busy state, latches the pre-configuration parameters in the configuration register, and autonomously generates physical timing signals according to the latched pre-configuration parameters to perform programming operations on the resistive random access memory array. While the hardware state machine is in the busy state, when the processor is preparing to issue a boot verification instruction in the pipeline, the boot verification instruction is blocked in the pipeline according to the hardware handshake protocol. After the programming operation is completed, the hardware state machine exits the busy state and pulls up the ready signal. The processor receives the ready signal, releases the block on the start verification instruction, and sends the start verification instruction to the resistive random access memory execution unit. After the start verification command is issued, the processor immediately returns and continues to issue subsequent commands. In response to the issuance of the start verification command, the hardware state machine re-enters the busy state, reads the analog data of the resistive random access memory array, converts it into digital results, and stores them in a read-only register. While the digital result is being stored in the read-only register, the processor detects that the digital result is not yet ready when it is preparing to issue a readback instruction in the pipeline, and blocks the readback instruction in the pipeline. Once the digital result is ready, the blocking of the readback result instruction is released, and the digital result is written back from the read-only register to the processor's target register.

[0011] In some optional implementations, the step of blocking the startup verification command in the pipeline specifically includes: The processor's instruction issuing unit detects the ready signal fed back by the resistive random access memory execution unit; If the ready signal is low, the instruction issuing unit holds the start verification instruction in the pipeline issuing slot until the ready signal becomes high, then releases the block and issues the start verification instruction to the resistive random access memory execution unit. The step of blocking the readback result instruction in the pipeline includes: The processor's instruction issuing unit detects the data ready signal fed back by the resistive random access memory execution unit; If the data ready signal is low, the instruction issuing unit holds the readback result instruction in the pipeline issuing slot until the data ready signal becomes high, then unblocks and writes the digital result from the read-only register back to the processor's target register; During the period when the start verification instruction or the readback result instruction is blocked in the pipeline launch slot, the non-hardware managed instructions already issued by the processor continue to be executed without being blocked.

[0012] In some optional implementations, the step of pre-configuring parameters in the latch configuration register includes: The pre-configured parameters include operating voltage adjustment value, pulse width time parameter, row and column selection address, number of samplings, and programming mode selection; The pre-configured parameters are pre-written into the configuration register by the processor using non-hardware managed instructions; When the hardware state machine receives the programming instruction or the start verification instruction, it latches the pre-configuration parameters and generates dynamic physical timing signals based on the latched pre-configuration parameters. After latching is complete, the processor modifies the configuration register using non-hardware managed instructions to prepare for the next operation without affecting the currently executing operation.

[0013] In some optional implementations, the step of reading the analog data from the resistive random access memory array and converting it into a digital result to be stored in a read-only register includes: The analog-to-digital conversion processing module of the resistive random access memory execution unit controls the hardware state machine to apply sampling pulses multiple times according to the averaging mode and averaging number pre-configured in the configuration register. After performing multi-cycle accumulation averaging and bit width conversion processing on the read analog data, the resulting digital result is stored in the read-only register, and the data ready signal is pulled high.

[0014] In some optional implementations, the software uses the programming instructions, the start verification instructions, and the readback result instructions as operation primitives, and implements various programming processes through instruction combination and process arrangement; The various programming processes include at least one of progressive pulse programming, multi-bit programming, adaptive programming, and batch array programming. The progressive pulse programming process includes the following steps: setting an initial voltage value, a voltage increment step size, and a target resistance value; writing the current voltage value as a pre-configuration parameter into the configuration register; issuing the programming instruction; issuing the start verification instruction; issuing the read-back result instruction to read the verification result back to the processor's general-purpose register; comparing the verification result with the target resistance value; if the target resistance value is not reached, increasing the current voltage value by one voltage increment step size and writing the updated current voltage value into the configuration register, repeating the above steps; if the target resistance value is reached, exiting the loop. The multi-bit programming process includes the following steps: setting multiple target resistance thresholds and sorting them according to resistance order; selecting a target resistance threshold as the current target value in sequence according to the sorted order; for each current target value, repeating the following sub-steps until the current target value is reached: writing the pre-configuration parameters corresponding to the current target value into the configuration register, issuing the programming instruction, issuing the start verification instruction, issuing the readback result instruction, and determining whether the current target value has been reached based on the readback verification result; after programming all target resistance thresholds in sequence, programming a single resistive variable memory cell to multiple discrete resistance states; The adaptive programming process includes the following steps: 1) Sending the programming instruction to perform a programming operation on the target unit; 2) Sending the start verification instruction and the readback result instruction to read back the actual resistance value of the target unit; 3) Calculating the deviation between the actual resistance value and the target resistance value; 4) If the actual resistance value is lower than the target resistance value, updating the configuration register to select the RESET operation mode and writing the corresponding pulse parameters into the configuration register, and resending the programming instruction to perform the RESET operation; 5) If the actual resistance value is higher than the target resistance value, updating the configuration register to select the SET operation mode and writing the corresponding pulse parameters into the configuration register, and resending the programming instruction to perform the SET operation; 6) Repeating the above steps until the actual resistance value reaches the target resistance value. The batch array programming process includes the following steps: looping through the row and column address registers, sequentially writing the row and column selection addresses and programming parameters of different units as pre-configuration parameters into the configuration register, issuing the programming instructions, and sequentially performing programming operations on multiple units.

[0015] According to a third aspect of the embodiments of this specification, a compiler instruction reordering and scheduling method for managed instructions of resistive random access memory (RRAM) is provided, comprising the steps of: Data dependency analysis is performed on the instructions in the program, and the instructions are divided into two categories: the first category of dependent instructions that depend on the results of resistive random access memory (RRAM) operations and the second category of unrelated instructions that do not depend on the results of RRAM operations. Identify consecutive hardware managed instruction pairs, the hardware managed instructions including programming instructions, startup verification instructions and readback result instructions, the consecutive hardware managed instruction pairs including programming instructions and startup verification instructions, or startup verification instructions and readback result instructions; Insert the second type of irrelevant instruction between the consecutive hardware managed instruction pairs, so that the processor issues and executes the second type of irrelevant instruction without blocking before the subsequent hardware managed instruction triggers pipeline blockage; When multiple resistive random access memory (RRAM) cells need to be programmed, the data dependency between the programming instructions of the first cell and the configuration instructions of the second cell is identified. If the configuration instructions of the second cell do not depend on the programming result of the first cell, the configuration instructions of the second cell are scheduled after the programming instructions of the first cell and before the start verification instructions of the first cell, so that during the execution of the programming instructions of the first cell, the processor issues and executes the configuration instructions of the second cell without blocking. For an iterative loop containing programming instructions, start verification instructions, and readback result instructions, data dependency analysis is performed on the instructions between adjacent iterations to identify whether the parameter configuration instruction of the (i+1)th iteration depends on the verification result returned by the readback result instruction of the i-th iteration. If the parameter configuration instruction of the (i+1)th iteration does not depend on the verification result of the i-th iteration, then the parameter configuration instruction of the (i+1)th iteration is moved forward to be executed after the programming instruction or the start verification instruction of the i-th iteration, so that the parameter preparation of the (i+1)th iteration and the verification result judgment of the i-th iteration overlap in time.

[0016] The beneficial effects of the embodiments in this specification are as follows: In the technical solution of this application, the processor's programming control of the resistive random access memory does not adopt the traditional software polling and waiting method. Instead, the processor issues a hardware-managed instruction and immediately returns to continue executing subsequent instructions. The latch of the resistive random access memory execution unit latches the pre-configuration signal in the configuration register at the moment the instruction is triggered. The hardware state machine autonomously generates physical timing signals based on the latched pre-configuration signals and applies them to the resistive random access memory array. Only when the execution unit is busy or the verification data is not ready is the hardware handshake signal line triggered by the instruction issuing unit to keep the subsequent hardware-managed instructions in the pipeline issuing slot. Since the blocking control is automatically triggered and deactivated by the physical timing signals driven by the hardware state machine based on the latched pre-configured parameters, this scheme can enable the processor to execute non-hardware managed instructions without blocking while waiting for the resistive random access memory to simulate physical operations, while ensuring the integrity of the programming verification closed loop. This is equivalent to transforming the waiting overhead of repeated software queries to the status register in traditional schemes into instruction pipeline pauses controlled by the hardware handshake protocol. Furthermore, the hardware state machine uses a unified state transition framework to reuse different pulse width parameters in different instruction modes. After latching, the processor can modify the configuration register in advance to prepare for the next operation, thereby effectively eliminating the processor computation cycle waste caused by software polling, avoiding the decrease in timing accuracy caused by pipeline execution jitter and interrupt response delay, and achieving efficient synchronization between uncertain delay physical operations and deterministic digital pipelines. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments or related technologies of this specification, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1This is a microarchitecture block diagram of the instruction-level programming control device for the resistive random access memory in the embodiments of this application; Figure 2 This is an instruction timing diagram provided in a non-blocking scenario according to an embodiment of this application; Figure 3 This is an instruction timing diagram provided in an embodiment of the present application for a busy and blocked execution unit scenario; Figure 4 This application provides an instruction timing diagram for a data-not-ready blocking scenario in an embodiment of the present application. Figure 5 This application provides an instruction timing diagram for a multi-bank interleaved programming scenario. Figure 6 This is an instruction timing diagram provided for an embodiment of the present application in a non-blocking scenario of a complete Program-Verify loop. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the embodiments of this application.

[0020] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another.

[0021] The following is a detailed description of the scheme of this application based on the accompanying drawings, such as... Figure 1 As shown in the figure, this diagram illustrates the microarchitecture block diagram of the hardware architecture of this application. The hardware architecture of this scheme includes a processor (containing an instruction fetch unit, an instruction issue unit, and pipeline control logic) and a resistive random access memory (RRAM) execution unit connected to the processor (containing a hardware state machine (FSM), a configuration register (RRAMCFG), a latch, and a physical array interface (RRAMCTL)). The processor's instruction set includes hardware-managed instructions for controlling RRAM programming. These hardware-managed instructions include programming instructions, start verification instructions, and read-back result instructions. The programming instructions are unified programming instructions, which determine whether to execute a SET, RESET, or FORM operation through a mode selection signal in the configuration register. After the hardware-managed instructions are issued, they return immediately without blocking the processor, allowing the processor to continue issuing and executing non-hardware-managed instructions without blocking. A hardware handshake signal line is provided between the instruction issue unit and the RRAM execution unit. Figure 1The direct_cfg path and stall signal are used to transmit the status signals of the execution unit to the instruction issue unit. The status signals include a first status signal indicating whether the execution unit is busy and a second status signal indicating whether the verification data is ready. The resistive random access memory (RRAM) execution unit is configured to respond to the pre-configuration signal in the hardware managed instruction latch configuration register issued by the processor and autonomously generate physical timing signals. The instruction issue unit is configured to hold subsequent hardware managed instructions in the pipeline issue slot when the execution unit is busy, based on the status signals transmitted by the hardware handshake signal line, and hold the readback result instruction in the pipeline issue slot when the second status signal indicates that the data is not ready.

[0022] like Figure 1 As further shown, this architecture embodies the "dual-path separation" design concept of the present application. Figure 1 The diagram illustrates three data paths. The first is the `normal_cfg` path, where data enters the RRAMCFG (configuration register) from the Bus via the `normal_cfg` signal. This corresponds to the configuration register interface where the processor writes pre-configuration parameters via the system bus (e.g., the APB bus). The second is the `direct_cfg` path, where data directly connects to the FSM (hardware state machine) from the Issue unit via the `direct_cfg` signal. Simultaneously, the FSM feeds back its status to the Issue unit via the `stall` signal. This corresponds to the instruction issue unit directly connected to the processor, including the instruction control interface with Req / Ready handshake signals. The third is the `latchcfg` path, where data connects to the Latch from the RRAMCFG via the `latchcfg` signal. This corresponds to the latching mechanism that latches the pre-configuration signals in the configuration register at the moment the instruction is triggered. This separation of the three paths allows for complete decoupling of software pre-configuration from hardware execution, providing a physical basis for subsequent configuration modifications after latching without affecting the current operation. Figure 1 As can be seen, the RRAM execution unit contains four core modules: RRAMCFG (configuration register, storing voltage adjustment values, pulse width timing parameters, row and column selection addresses, sampling counts, and programming mode selection), Latch (latch that latches the parameters in the configuration register at the moment of instruction triggering), FSM (hardware state machine, which autonomously generates physical timing signals according to the fixed flow framework of IDLE→WAIT_CYCLE1→WAIT_CYCLE2→IDLE), and RRAMCTL (physical array interface, including word line enable signal line wl_en, bit line driver circuit, and analog-to-digital conversion data read path). RRAMCTL is ultimately connected to RRAMArray (RRAM memory array), forming a complete control chain from instruction issuance to physical operation completion.

[0023] In the embodiments of this specification, a processor can refer to the core component of an integrated circuit or system-on-a-chip responsible for executing program instructions. Internally, it includes an instruction fetch unit, an instruction issue unit, and pipeline control logic. The fetch unit is responsible for reading instructions from the instruction cache or memory. The issue unit is a functional module in the processor pipeline responsible for dispatching and distributing decoded instructions; it selects the instruction to be executed from the instruction queue and sends it to the corresponding execution unit. The pipeline control logic can be understood as the control circuit in the processor responsible for managing the flow and scheduling of instructions between different pipeline stages. It can schedule and coordinate the issuance and execution of instructions based on the feedback status of each execution unit.

[0024] A resistive random access memory (RRAM) execution unit can refer to an independent functional unit integrated into the processor pipeline, specifically responsible for performing programming and verification read operations related to the RRAM array. This execution unit sits alongside the scalar ALU and vector arithmetic units in the processor pipeline, receiving instruction dispatches from the instruction issuer. Internally, this execution unit comprises four components: a hardware state machine (FSM), a configuration register (RRAMCFG), a latch, and a physical array interface (RRAMCTL). The hardware state machine can be understood as a dedicated finite state machine controller responsible for autonomously taking over control upon receiving hardware-managed instructions and generating precise physical timing signals according to a pre-defined state transition sequence. The configuration register can refer to a set of registers that can be read and written by the processor via the system bus (such as the APB bus). It is used to temporarily store various control parameters pre-written by the processor, including but not limited to operating voltage adjustment values, pulse width timing parameters, row and column selection addresses, multiple sampling averaging counts, and programming mode selections. A latch is a storage unit within a hardware state machine. It copies and freezes all parameters in the configuration register at the moment an instruction is triggered, ensuring that the parameters are not affected by subsequent CPU modifications during operation. Regarding the sample-and-hold relationship between the latch and the configuration register, in this scheme, the output of the configuration register is connected to the input of the latch. When the hardware-managed instruction triggers the latch signal, the latch samples the current value output by the configuration register and stores it at its output. After latching, even if the contents of the configuration register change due to subsequent software modifications, the latch's output value will not change, thus achieving the sample-and-hold function. This mechanism ensures that the parameters used by the hardware state machine during physical operations are snapshot values ​​at the time of latching, unaffected by subsequent software operations, providing a low-level circuit guarantee for complete decoupling between "software pre-configuration" and "hardware execution." The physical array interface can refer to the driver and sampling circuit interface that connects to the RRAM memory array. It can include word line enable signal lines, bit line driver circuits, and analog-to-digital conversion data read paths. It is used to convert the timing control signals generated by the hardware state machine into actual voltage waveforms applied to the RRAM array, and to transmit the analog current or voltage signals returned by the array to the analog-to-digital conversion processing module.

[0025] This execution unit connects to the processor through two sets of interfaces, one of which is the configuration register interface ( Figure 1 The first is the `normal_cfg` path, which connects to the processor's system bus (such as the APB bus) and is used to receive software pre-configuration parameters written by the processor via regular instructions. The second is the instruction control interface (…). Figure 1The `direct_cfg` path directly connects to the processor's instruction dispatch unit, containing Req / Ready handshake signals to receive hardware-managed instructions and provide execution status feedback. This dual-interface design decouples software pre-configuration from hardware execution, providing a theoretical basis for subsequent configuration modifications after latching without affecting the current operation.

[0026] Hardware-managed instructions refer to a special type of instruction in the processor instruction set, distinct from traditional arithmetic logic instructions, memory access instructions, or branch instructions. The characteristic of hardware-managed instructions is that they are not directly executed by the processor pipeline; instead, they act as triggers, transferring execution control to the hardware state machine within the resistive random access memory (RRAM) execution unit, which then autonomously completes the entire physical operation. Specifically, the hardware-managed instructions in this application may include at least three: a unified programming instruction (assembler mnemonic: RRAM_PROG), a startup verification instruction (assembler mnemonic: RRAM_VERIFY_START), and a read-back instruction (RRAM_VERIFY_READ). The unified programming instruction can determine the specific operation type triggered this time, i.e., SET, RESET, or FORM, through a mode selection signal pre-written in the configuration register. The startup verification instruction triggers the RRAM execution unit to begin reading analog data from the RRAM array and performing analog-to-digital conversion and averaging, returning immediately after being issued. The readback instruction is used to write the digital result obtained from the verification operation from the internal read-only register of the RRAM execution unit back to the processor's general-purpose register. When it is executed, it checks the status of the data ready signal. If the data is not ready, it is blocked in the pipeline.

[0027] All hardware-managed instructions return immediately after issuance without blocking the processor. In other words, once the instruction issuer dispatches a hardware-managed instruction to the RRAM execution unit and completes the handshake, the instruction is considered issued. The processor pipeline does not halt the fetching, decoding, and issuance of subsequent instructions because that instruction has not yet completed execution. The processor can continue to issue and execute non-hardware-managed instructions (such as arithmetic and logical operation instructions, memory access instructions, branch instructions, etc.) without blocking. This non-blocking issue characteristic allows the processor to continue performing useful calculations even while waiting for the RRAM to simulate physical operations to complete, typically within tens of nanoseconds to microseconds, thus significantly improving processor utilization.

[0028] Hardware handshake signal lines refer to the physical signal lines between the processor instruction issuing unit and the RRAM execution unit specifically used to transmit status and control information. Figure 1The stall signal line points from the FSM to the Issue. This is distinct from the processor's internal general-purpose data bus or control bus; it is a set of low-latency, point-to-point dedicated signal paths. This hardware handshake signal line transmits at least two types of status signals. The first status signal (corresponding to the ro_pro_ready signal in the specific implementation) indicates whether the RRAM execution unit is currently busy. When the RRAM execution unit is in the process of executing a hardware-managed instruction (i.e., the hardware state machine is not in an IDLE state), this first status signal is set low, indicating "busy" or "not ready". When the RRAM execution unit is in an idle state, this signal is set high, indicating "ready". The second status signal (corresponding to the ro_verify_ready signal in the specific implementation) indicates whether the verification data is ready for readback. When the ADC sampling and averaging operation triggered by the start verification instruction has not yet completed, this second status signal is set low; when the verification operation is completed and the digital result has been written to the read-only register, this signal is set high.

[0029] One of the configuration features of the RRAM execution unit is its "instruction-triggered latching" capability. When the processor issues a hardware-managed instruction to the RRAM execution unit, the unit does not immediately begin executing physical operations. Instead, it first performs a critical action the instant the instruction is received: copying and latching all pre-configuration signals currently stored in the configuration register into an internal latch. This latching action... Figure 1 This is manifested as a data path flowing from RRAMCFG to the Latch via the latchcfg signal. The timing of this latching action is crucial; it occurs at the moment the instruction handshake is successful, specifically at the boundary moment when the hardware state machine transitions from the IDLE state to the WAIT_CYCLE1 state. Once latching is complete, all subsequent physical timing operations executed by the hardware state machine are based on the parameter values ​​in the latch, rather than on the real-time values ​​of the configuration register. This means that the configuration register can be freely modified by the processor after latching to prepare for the next operation, while the hardware state machine still executes the current operation completely according to the parameter values ​​at the time of latching, without interference between the two. After latching, the hardware state machine takes over control and autonomously generates physical timing signals according to a pre-defined unified state transition framework. These physical timing signals may include, but are not limited to: high and low level changes of the word line enable signal (wl_en), the application and removal of bit line voltages, and precise timing of pulse widths.

[0030] The instruction issuing unit selectively controls the issuance of hardware-managed instructions based on the state of the hardware handshake signal lines. Specifically, when the instruction issuing unit is ready to issue a hardware-managed instruction, it first checks the level of the first status signal. If this signal is low, it indicates that the RRAM execution unit is currently busy, and the instruction issuing unit will not send the new hardware-managed instruction to the RRAM execution unit, but will hold it in the pipeline issue slot until the first status signal goes high. Once the first status signal is detected to be high, the pipeline immediately unblocks, and the instruction is issued to the RRAM execution unit. When the instruction issuing unit is ready to issue a read-back result instruction, in addition to checking the first status signal, it also needs to check the level of the second status signal. If the second status signal is low, it indicates that the verification data is not yet ready, and the read-back result instruction is also held in the pipeline issue slot until the second status signal goes high. Once the data is ready, the block is released, and the instruction issuing unit issues the read-back result instruction to the RRAM execution unit, which then writes the digital result in the read-only register back to the processor's designated general-purpose register. The advantage of this "selective blocking" mechanism is that blocking only occurs in scenarios where there is a real data dependency or resource conflict, namely "issuing the next hardware-managed instruction but the execution unit is busy" and "reading back the result but the data is not yet ready". The processor is completely unaffected by any blocking when executing non-hardware-managed instructions and can run at full speed.

[0031] To explain in detail the complete process of the above-mentioned pipelined synchronous programming method and its timing behavior in different scenarios, such as Figures 2 to 6 As shown, these timing diagrams illustrate the detailed timing performance of the core mechanism of the technical solution in this application under various working scenarios.

[0032] Figure 2This diagram illustrates the instruction timing in a non-blocking scenario. From top to bottom, it includes the Instruction line (instruction sequence), the RRAM State line (RRAM execution unit state), and the Stall line (blocked state). The Instruction line shows the instruction sequence as follows: CFG (configuration register write) → RRAM_PROG (programming instruction) → ADD → SUB → MUL (non-hardware managed instruction) → CFG → RRAM_VERIFY_START (start verification instruction) → ADD → ADD → RRAM_VERIFY_READ (read back result instruction) → BLT (conditional branch). After RRAM_PROG is issued, the processor immediately executes irrelevant instructions such as ADD, SUB, and MUL. Observing the RRAM State line reveals a blank free gap after the PROG region ends before entering the VERIFY region; similarly, a blank free gap follows after the VERIFY region before entering the READ region. This indicates that RRAM_PROG is completed before RRAM_VERIFY_START is issued, and RRAM_VERIFY_START does not need to wait during issuance. Meanwhile, VERIFY is completed before RRAM_VERIFY_READ is issued, and RRAM_VERIFY_READ does not need to wait during issuance. Therefore, the Stall action is empty, and the pipeline never blocks throughout the entire process. This corresponds to the basic rule of non-blocking issue where the processor does not block and returns immediately after all hardware-managed instructions are issued.

[0033] Figure 3 This diagram illustrates the instruction timing under a busy and blocked execution unit scenario. It also includes Instruction lines, RRAM State lines, and Stall lines. The Instruction lines show the instruction sequence as follows: CFG→RRAM_PROG→ADD→RRAM_VERIFY_START→ADD→ADD→RRAM_VERIFY_READ→BLT. and Figure 2The difference lies in the execution of only one ADD instruction after RRAM_PROG is issued, before the processor attempts to issue RRAM_VERIFY_START. Observing the RRAM State line reveals that when the RRAM_VERIFY_START instruction appears in the Instruction line, the RRAM State line shows that the PROG region is not yet finished, with no free gap. The Stall line displays a STALL flag at the corresponding position of RRAM_VERIFY_START, and the RRAM_VERIFY_START instruction block is widened (indicating that the instruction was held in the issue slot for several clock cycles). When PROG completes, Stall is released, RRAM_VERIFY_START is issued, and VERIFY begins. Subsequently, when RRAM_VERIFY_READ is issued, VERIFY has already completed, so there is no second Stall. This corresponds to blocking condition 1: when the RRAM execution unit is processing a hardware managed instruction (in a busy state), if the processor attempts to issue the next hardware managed instruction, the RRAM execution unit refuses to handshake, triggering the pipeline to block (Stall) the subsequent hardware managed instruction. Once the current operation is completed, the pipeline automatically unblocks.

[0034] Figure 4 This diagram illustrates the instruction timing under a data-not-ready blocking scenario. It also includes Instruction lines, RRAM State lines, and Stall lines. The Instruction lines show the instruction sequence as follows: CFG→RRAM_VERIFY_START→ADD→RRAM_VERIFY_READ→BLT. Observing the RRAM State line, we find that when the RRAM_VERIFY_READ instruction appears in the Instruction line, the RRAM State line shows that the VERIFY region has not yet ended, and the data is not yet ready. The Stall line displays the STALL flag at the corresponding position of RRAM_VERIFY_READ, and the RRAM_VERIFY_READ instruction block is widened. After VERIFY is completed (the hardware state machine completes ADC sampling, accumulation, averaging, and bit width conversion, stores the result in the read-only register, and pulls the ro_verify_ready signal high), Stall is released, RRAM_VERIFY_READ is issued, READ is completed, and the data is written back to the general-purpose register. This corresponds to blocking condition 2: when the processor issues a read-back instruction, if the hardware verification operation has not yet been completed (the data ready signal is not high), the instruction is blocked in the pipeline until the data is ready, at which point it is automatically unblocked and the result is written back to the processor register.

[0035] Figure 5This diagram illustrates the instruction timing in a multi-bank interleaved programming scenario. The diagram includes Instruction rows, Bank A / B / C / D State rows (the RRAM states of the four independent banks), and Stall rows. The Instruction rows show the instruction sequence as follows: CFG_A→PROG→CFG_B→PROG→CFG_C→PROG→CFG_D→PROG→CFG_A→V_START→CFG_B→V_START→CFG_C→V_START→CFG_D→V_START→V_READ_A→V_READ_B→V_READ_C→V_READ_D→BLT. Observing the State lines of Bank A / B / C / D, it can be seen that PROG A / B / C / D are issued back-to-back—different banks are independent of each other; while one bank is executing a PROG, the configuration instructions (CFG) of another bank can be issued and executed. The Stall line shows three STALLs: V_START_A was issued when Bank A's PROG was not yet complete (a brief Stall occurred); V_START_B was issued when Bank B's PROG was not yet complete (a brief Stall occurred); V_READ_D was issued when Bank D's VERIFY was not yet complete (a Stall occurred). V_START_C / D has no Stall (because sufficient time has passed, and PROG C / D has already completed); V_READ_A / B / C has no Stall (the corresponding VERIFY has already completed). This corresponds to point 3 of the compiler instruction reordering and scheduling method: when multiple RRAM units need to be programmed, the compiler interweaves the configuration instructions and hardware-managed instructions of different units. During the execution of the hardware-managed instructions of the first unit, the processor can execute the configuration instructions of the second unit, so that the hardware-managed instructions can be unblocked and the programming instructions of the next unit can be issued immediately, realizing the software pipelinedization of multi-unit programming.

[0036] Figure 6 This diagram illustrates the instruction timing of the complete Program-Verify loop in a non-blocking scenario. The diagram includes Instruction lines, RRAM State lines, and Stall lines. The Instruction lines show the instruction sequence as follows: CFG→CFG→RRAM_PROG→ADD→ADD→ADD→ADD→ADD→CFG→RRAM_VERIFY_START→ADD→ADD→ADD→ADD→RRAM_VERIFY_READ→BLT. Observing the RRAM State line, we can see that there is a significant idle gap after the PROG region ends, before entering the VERIFY region; similarly, there is a significant idle gap after the VERIFY region ends, before entering the READ region. The Stall line is empty, and the pipeline never blocks throughout the entire process. This corresponds to automatically completing the waiting and synchronization through a hardware blocking mechanism, compressing a complete iteration into: The instruction sequence is a linear sequence of four instructions: RRAM_PROG→RRAM_VERIFY_START→RRAM_VERIFY_READ→BLT, without any closed-loop iterative timing compression mechanism that requires no polling or waiting code in between.

[0037] comprehensive Figures 2 to 6 Time series analysis, Figure 2 and Figure 6 It demonstrates the ideal working state without obstruction. Figure 3 and Figure 4 The triggering and release processes of two blocking conditions (execution unit busy blocking and data not ready blocking) are shown respectively; Figure 5 The study demonstrates the optimization effect of compiler instruction reordering in multi-bank scenarios. The five timing diagrams together form a complete timing map from basic mechanisms to advanced optimizations.

[0038] The following section uses a complete SET operation as an example to explain in more detail the actual execution flow of the above architecture and method.

[0039] During the configuration phase (software pre-configuration), the processor writes pre-configuration parameters to the configuration register via the system bus (APB interface): word line / bit line address of the target unit (reg_wlgrp_sel, reg_bl_sel, etc.); SET operation mode configuration (reg_rram_mode=1 represents PRO mode, reg_rram_pro_mode=1 represents SET); voltage adjustment value (reg_pro_din_vwl, reg_pro_din_vbl); pulse width timing parameters (reg_ana_set_wait_cycle, reg_ana_set_cycle).

[0040] During the trigger phase (instruction issuance), the processor issues the RRAM_PROG unified programming instruction (at this time, the configuration register has been selected in SET mode). After the instruction is issued, it returns immediately, triggering the start signal of the execution unit (reg_start is pulled high).

[0041] During the takeover and execution phase (hardware state machine takeover), the state machine detects the start pulse (start_pls), immediately latches the row and column addresses, voltage adjustment values, and pulse duration parameters in the configuration register, and then enters the WAIT_CYCLE1 state. In this phase, the latched address and voltage configuration are passed to the RRAM array, and the processor waits for the analog voltage to stabilize. The waiting time is determined by the latched reg_ana_set_wait_cycle parameter. Because the latching occurs at the moment of instruction triggering, the processor can safely modify the configuration register afterwards to prepare for the next operation. After WAIT_CYCLE1 ends, the state machine automatically enters the WAIT_CYCLE2 state. At this time, the word line enable signal (wl_en) is pulled high, officially applying the SET programming pulse to the RRAM cell. The pulse duration is determined by reg_ana_set_cycle.

[0042] During the selective blocking and synchronization phase, while the state machine is in a non-IDLE (busy) state, the execution unit keeps the Ready signal (ro_pro_ready) to the processor low. At this time, the processor does not block and can continue to issue non-hardware managed instructions. Blocking is triggered only in the following two situations: when the processor attempts to issue the next hardware managed instruction, the instruction issuer blocks the hardware managed instruction in the pipeline slot because it has not received the Ready signal; when the processor issues an RRAM_VERIFY_READ instruction, if the data ready signal (ro_verify_ready) is not pulled high, the instruction is also blocked in the pipeline.

[0043] During the completion and recovery phase, after WAIT_CYCLE2 ends, the state machine pulls the wl_en signal low, returns to the IDLE state, and pulls the ro_pro_ready signal high. The processor pipeline detects the Ready signal going high, immediately unblocks, and issues the next hardware-managed instruction that was previously blocked to the RRAM execution unit.

[0044] Regarding the splitting and special mechanism of the VERIFY instruction, the RRAM_VERIFY_START instruction returns immediately after being issued. When the state machine enters the WAIT_CYCLE2 stage, if the averaging mode is configured, the wl_en signal will be pulled high and low multiple times for sampling. After the analog data output by the array is sampled by the ADC, the hardware automatically performs bit width conversion and averaging (i.e., summing the digital values ​​of multiple samples and dividing by the number of samples to obtain the average result), and the final result is written to the read-only register (ro_verify_avg_data), and the data ready signal (ro_verify_ready) is pulled high. When the RRAM_VERIFY_READ instruction is executed, if the ro_verify_ready signal is not pulled high, the instruction is blocked in the pipeline. Once the data is ready, the block is released, and the hardware writes the value of ro_verify_avg_data back to the general-purpose register specified in the processor instruction.

[0045] In a traditional polling architecture, the pseudo-assembly code for one Program-Verify loop is as follows: ; After adopting the hardware managed instruction architecture of this application, the code is extremely concise and polling-free: ; As can be seen, the technical solution of this application can completely eliminate the polling loop of WAIT_SET and WAIT_VERIFY, and allow a large number of irrelevant numerical instructions to be inserted between hardware managed instructions to mask the delay, and the execution efficiency reaches the theoretical limit of the hardware.

[0046] Based on the technical solutions described above, this specification also provides some specific implementation schemes, which are described below.

[0047] In an optional embodiment, the programming instruction can be a unified programming instruction, which determines whether to perform a SET operation to set the memory cell to a low-impedance state, a RESET operation to set it to a high-impedance state, or an initial activation FORM operation through the mode selection signal in the configuration register.

[0048] In the embodiments described in this specification, the programming instructions embody the abstraction level of hardware-managed instructions and employ a unified encoding method. That is, all programming operations, whether SET, RESET, or FORM, share the same instruction code (RRAM_PROG). The specific distinction between operation types depends entirely on the mode selection signal pre-written in the configuration register. Specifically, the configuration register may contain two key mode control fields: the reg_rram_mode field and the reg_rram_pro_mode field. When reg_rram_mode is set to 1 (indicating PRO mode) and reg_rram_pro_mode is set to 1, the SET operation is executed. When reg_rram_mode is set to 1 and reg_rram_pro_mode is set to 0, the RESET operation is executed. When reg_rram_mode is set to other values ​​(indicating FORM mode), the FORM operation is executed. This design allows for extremely concise instruction encoding while providing software with flexible programming mode selection capabilities. That is, the software only needs to modify the mode selection signal in the configuration register using regular instructions before issuing the programming instruction to switch between different programming operation types within the same code logic. The practical significance of this design lies in the fact that, in an adaptive programming strategy, the software can dynamically select the programming direction for the next iteration based on the verification readback results. Throughout the process, the encoding of the programming instructions remains unchanged, and only the contents of the configuration registers change, thus achieving a flexible architecture with stable instruction encoding and dynamically configurable operation types.

[0049] In an optional embodiment, the configuration register stores software pre-configuration signals, including operating voltage adjustment values, multi-stage pulse width timing parameters, row and column selection addresses, multiple sampling averaging counts, and programming mode selection. The configuration register has a system bus interface for connecting to the processor to receive the pre-configuration signals written by the processor via non-hardware managed instructions. The hardware state machine includes a latch for latching the pre-configuration signals in the configuration register when triggered by a hardware managed instruction. The hardware state machine generates dynamic physical timing signals based on the latched pre-configuration signals. The output of the configuration register is sampled and held via the latch; after the hardware managed instruction triggers the latch, the output value of the latch no longer changes with subsequent changes to the configuration register.

[0050] In the embodiments described in this specification, the configuration register is a set of registers in the RRAM execution unit that can be accessed via the system bus, specifically used to store various control parameters pre-written by the processor. The specific contents of these software pre-configuration signals may include: operating voltage adjustment values ​​(word line voltage adjustment values ​​reg_pro_din_vwl and bit line voltage adjustment values ​​reg_pro_din_vbl), used to adjust the voltage amplitude applied to the word lines and bit lines of the RRAM cell; multi-stage pulse width timing parameters (reg_ana_set_wait_cycle and reg_ana_set_cycle related to SET operation, reg_ana_reset_wait_cycle and reg_ana_reset_cycle related to RESET operation, and reg_ana_form_wait_cycle and reg_an related to FORM operation). The `a_form_cycle` and `reg_ana_vrfy_wait_cycle` and `reg_ana_vrfy_cycle` related to the VERIFY operation control the duration of the hardware state machine in different operating modes and states, respectively. The row and column selection addresses (`reg_wlgrp_sel` and `reg_bl_sel`) specify the position of the specific RRAM cell in the array for this operation. The multiple sampling averaging count configures the number of ADC sampling repetitions during verification operations. The programming mode selection (`reg_rram_mode` and `reg_rram_pro_mode`) determines whether the programming instruction executes a SET, RESET, or FORM operation. The configuration register has a system bus interface connected to the processor's APB bus, allowing the processor to write to the configuration register using regular non-hardware managed instructions. The hardware state machine of the RRAM execution unit contains latches; when the hardware state machine detects a start pulse, it instantly copies and latches all relevant parameters in the configuration register into the latches. The basic function of a latch is to transmit the signal value from the input terminal to the output terminal while the trigger signal is valid, and to isolate the input terminal from the output terminal after the trigger signal is invalidated, with the output terminal retaining the value at the instant the trigger signal was invalidated. In this application, when the hardware state machine transitions from the IDLE state to the WAIT_CYCLE1 state, the latch's trigger signal becomes valid, and all pre-configured signals currently stored in the configuration register are sampled and held to the latch's output terminal. After sampling and holding, the latch's output terminal is isolated from the input terminal. Therefore, even if the processor subsequently modifies the contents of the configuration register through non-hardware managed instructions, the latch's output value will not change. After latching, the processor can safely modify the configuration register to prepare for the next operation, while the hardware state machine still executes the current operation completely according to the original parameter values ​​in the latch.

[0051] In an optional embodiment, the hardware state machine includes unified state transition control logic, which includes an idle state, a first waiting state for the analog voltage to stabilize, and a second waiting state for applying a programming pulse or a sampling pulse. The configuration register includes multiple pulse width time parameter storage areas, with different storage areas corresponding to different instruction modes. The hardware state machine selects different pulse width time parameters from the configuration register under different instruction modes to control the duration of the first waiting state and the second waiting state.

[0052] In the embodiments described in this specification, the hardware state machine inside the RRAM execution unit adopts a unified state transition framework to execute different types of hardware managed instructions. This state transition framework is a fixed flow structure, specifically a loop of IDLE (idle state) → WAIT_CYCLE1 (first waiting state) → WAIT_CYCLE2 (second waiting state) → IDLE (idle state). The IDLE state is the default state of the state machine, indicating that the RRAM execution unit is currently idle and can receive new hardware managed instructions; in this state, the first state signal is high. The WAIT_CYCLE1 state is the first waiting state, its function being to wait for the analog circuit voltage to stabilize before applying a programming pulse or sampling pulse. When the state machine receives a start pulse from the IDLE state, it first enters the WAIT_CYCLE1 state; the duration of this state is controlled by the latched wait time parameter. The WAIT_CYCLE2 state is the second waiting state, its function being to formally apply the programming pulse or sampling pulse. When WAIT_CYCLE1 ends, the state machine automatically enters the WAIT_CYCLE2 state; the duration of this state is controlled by the latched pulse width parameter. The configuration register contains multiple storage areas for pulse width timing parameters. Different storage areas correspond to different instruction modes: SET operation corresponds to `reg_ana_set_wait_cycle` and `reg_ana_set_cycle`; RESET operation corresponds to `reg_ana_reset_wait_cycle` and `reg_ana_reset_cycle`; FORM operation corresponds to `reg_ana_form_wait_cycle` and `reg_ana_form_cycle`; and VERIFY operation corresponds to `reg_ana_vrfy_wait_cycle` and `reg_ana_vrfy_cycle`. When the hardware state machine executes in different instruction modes, it selects the corresponding storage area parameters from the configuration register to control the duration of each state. This unified state transition framework, combined with a parameter reuse mechanism, makes the state machine logic extremely concise; the only difference is that the duration parameters of each state come from different configuration register storage areas.

[0053] In an optional embodiment, the resistive random access memory (RRAM) execution unit further includes an analog-to-digital conversion (ADC) processing module and a read-only register. The ADC processing module is connected to the physical array interface and is used to read analog data from the RRAM array. The ADC processing module includes an averaging unit and a bit-width conversion unit. The averaging unit is used to perform multi-cycle averaging on multiple sampled data according to the number of averaging operations pre-configured in the configuration register. The bit-width conversion unit is used to perform mean calculation (e.g., divide the accumulated value by the number of samplings to obtain the average value of multiple samples) and bit-width conversion on the accumulated result. The read-only register is used to store the digital result processed by the ADC processing module and output the second status signal.

[0054] In the embodiments described in this specification, the RRAM execution unit also integrates an analog-to-digital conversion (ADC) processing module and a read-only register to support analog-to-digital conversion and data storage for verification operations. The ADC processing module connects to the physical array interface and its function is to convert the analog current or voltage signals returned by the RRAM array into digital values ​​during the execution of the verification instruction. This module contains two sub-units: an averaging unit and a bit-width conversion unit. When the averaging mode is pre-configured in the configuration register, the hardware state machine will repeatedly pull the word line enable signal high and low in the WAIT_CYCLE2 state. Each time the signal is pulled high, it reads analog data from the RRAM array once. The ADC performs analog-to-digital conversion on each read data, and the averaging unit successively accumulates these multiple sampled digital values. The number of accumulations is determined by the averaging count parameter pre-configured in the configuration register. Averaging through multiple samples effectively reduces the impact of noise and interference in a single sample, improving the accuracy of the verification read. After completing multi-cycle accumulation, the bit-width conversion unit performs an averaging operation on the accumulated result, dividing the accumulated value by the number of samples to obtain the averaged digital value (the average value can be calculated using fixed-point division, shift averaging, or other mathematical operations; the specific implementation method can be flexibly chosen according to different design requirements). Simultaneously, it adjusts the bit width to convert the original bit width of the ADC output into a format matching the bit width of the processor register. The read-only register stores the final digital result processed by the analog-to-digital conversion module. It is read-only to the processor and its contents can only be read into a general-purpose register via a read-back instruction. This read-only register also outputs a second status signal (ro_verify_ready). This signal is low when the verification operation is in progress and the digital result has not yet been generated; it is pulled high when the verification operation is complete and the digital result has been written to the read-only register.

[0055] In an optional embodiment, the step of blocking the boot verification instruction in the pipeline may include: the processor's instruction issuing unit detecting the ready signal fed back by the resistive random access memory (RRAM) execution unit; if the ready signal is low, the instruction issuing unit holding the boot verification instruction in the pipeline slot until the ready signal becomes high, then unblocking and issuing the boot verification instruction to the RRAM execution unit; the step of blocking the readback result instruction in the pipeline includes: the processor's instruction issuing unit detecting the data ready signal fed back by the RRAM execution unit; if the data ready signal is low, the instruction issuing unit holding the readback result instruction in the pipeline slot until the data ready signal becomes high, then unblocking and writing the digital result from the read-only register back to the processor's target register; wherein, during the period when the boot verification instruction or the readback result instruction is blocked in the pipeline slot, the non-hardware managed instructions already issued by the processor continue to be executed without being blocked.

[0056] In the embodiments of this specification, the selective pipeline blocking mechanism mentioned above is implemented in the following specific ways. For blocking of the start verification instruction, when the instruction issuing unit is ready to issue the start verification instruction (RRAM_VERIFY_START), it first detects the first status signal (i.e., the ready signal ro_pro_ready) fed back by the RRAM execution unit. If this signal is high, it indicates that the RRAM execution unit is in an idle state, and the start verification instruction is normally issued to the RRAM execution unit. If this signal is low, it indicates that the RRAM execution unit is in a busy state (executing the previous programming instruction), and the instruction issuing unit holds the start verification instruction in the pipeline issuing slot, not passing it downstream, and the pipeline pauses at this issuing slot. The instruction issuing unit continues to monitor the first status signal until it becomes high, then immediately unblocks and issues the start verification instruction to the RRAM execution unit. For blocking of the read-back result instruction, when the instruction issuing unit is ready to issue the read-back result instruction (RRAM_VERIFY_READ), it first detects the second status signal (i.e., the data ready signal ro_verify_ready). If the signal is high, it indicates that the verification data is ready, and the readback result instruction is normally issued to the RRAM execution unit. The execution unit writes the digital result in the read-only register back to the target general-purpose register specified by the processor. If the signal is low, it indicates that the verification data is not yet ready, and the instruction issuer holds the readback result instruction in the pipeline issue slot, continuously monitoring the second state signal until it goes high to release the blockage. An important characteristic during the period when the start verification instruction or readback result instruction is blocked in the pipeline issue slot is that non-hardware managed instructions that have already been issued and are in the execution phase are unaffected and can continue to execute until completion. This is because pipeline blocking only occurs at the issue stage (i.e., the queue position between instruction fetch and issue), and instructions already in the execution phase are not affected by issue stage pauses. This characteristic in this scheme contrasts with the traditional software polling method, where the processor is completely occupied during the polling loop and cannot perform any other calculations.

[0057] In an optional embodiment, the step of latching the pre-configuration parameters in the configuration register may include: the pre-configuration parameters may include an operating voltage adjustment value, a pulse width time parameter, a row and column selection address, a sampling count, and a programming mode selection; the pre-configuration parameters are pre-written into the configuration register by the processor using non-hardware managed instructions; when the hardware state machine receives the programming instruction or the start verification instruction, it latches the pre-configuration parameters and generates dynamic physical timing signals based on the latched pre-configuration parameters; after latching, the processor modifies the configuration register using non-hardware managed instructions to prepare for the next operation without affecting the currently executing operation.

[0058] In the embodiments of this specification, the specific content of the pre-configuration parameters in the latch configuration register may include the operating voltage adjustment value, multi-stage pulse width time parameter, row and column selection address, number of multiple sampling averaging times, and programming mode selection. The values ​​of these parameters are calculated and determined by the software at runtime according to the current programming strategy. The software writes these parameters into the configuration register through a non-hardware managed instruction (i.e., the conventional store instruction STORE). This write operation is completed through the system bus and is completed through a separate instruction control interface, which is separate from the issuance of hardware managed instructions. The two are physically separate. When the hardware state machine receives a programming instruction or a start verification instruction, it first performs a latching action. When a start pulse is detected, before entering the WAIT_CYCLE1 state, it copies all relevant parameters in the configuration register into the internal latch. The latching action occurs at the moment of instruction triggering and requires a very short time (nanosecond level), which does not affect the timing of subsequent physical operations. After latching is completed, the hardware state machine generates dynamic physical timing signals based on the parameters in the latch. During this process, even if the contents of the configuration register are modified by the software, it will not affect the values ​​in the latch, and therefore will not affect the currently executed operation. During the physical operations performed by the hardware state machine, software can safely modify parameters in the configuration registers via non-hardware managed instructions, achieving overlap between computation and execution and further reducing iteration gaps. Taking ISPP incremental programming as an example, the assembly code is as follows: ISPP_LOOP: STORE [REG_PRO_DIN_VWL], R3 # Configure the current voltage RRAM_PROG # Issue programming command, latch voltage V ADD R3, R3, R4 # Immediately increment the voltage (in preparation for the next iteration) RRAM_VERIFY_START # Verify the current operation RRAM_VERIFY_READ R2 BLT R2, R5, ISPP_LOOP In the code above, the ADD instruction completes the voltage increment during the execution of RRAM_PROG, while the current programming operation still uses the latched old voltage value, thus achieving an overlap between calculation and execution.

[0059] In an optional embodiment, the step of reading the analog data of the resistive random access memory array and converting it into a digital result and storing it in a read-only register may include: the analog-to-digital conversion processing module of the resistive random access memory execution unit controls the hardware state machine to apply sampling pulses multiple times according to the averaging mode and averaging number pre-configured in the configuration register, performs multi-cycle accumulation averaging and bit width conversion processing on the read analog data, stores the obtained digital result in the read-only register, and pulls up the data ready signal.

[0060] In the embodiments of this specification, the analog data reading and conversion during the execution of the start verification instruction is specifically implemented as follows. After the start verification instruction is sent to the RRAM execution unit, the hardware state machine enters a unified state transition framework. In the WAIT_CYCLE1 stage, it waits for the analog voltage to stabilize before entering the WAIT_CYCLE2 stage. In the WAIT_CYCLE2 stage, the hardware state machine determines the sampling behavior based on the pre-configured averaging mode in the configuration register. If the averaging mode is disabled (averaging count is 1), the state machine only pulls the word line enable signal high once to read a set of analog data, which is then directly stored in the read-only register after ADC conversion. If the averaging mode is enabled (averaging count N>1), the state machine executes N sampling cycles, that is, it pulls wl_en high each time to read analog data, converts it to a digital value via the ADC, accumulates it using the accumulator averaging unit, and then pulls wl_en low. After repeating N times, the averaging unit obtains the accumulated value S = Σ(ADC_i) (i = 1 to N). The bit-width conversion unit performs an averaging operation (e.g., dividing the accumulated value S by the number of samples N to obtain the average value = S / N) and performs bit-width conversion to obtain the final digital result. The final digital result is stored in a read-only register. After storage, the RRAM execution unit pulls up the second status signal to notify the instruction issuing unit that the verification data is ready. This multi-cycle averaging mechanism can effectively reduce the impact of random noise in a single ADC sampling. For example, when the averaging is performed 8 times, the variance of random noise can be reduced to 1 / 8 of the original, significantly improving the signal-to-noise ratio of the verification readout.

[0061] In an optional embodiment, the software uses the programming instructions, the start verification instructions, and the readback result instructions as operation primitives to implement multiple programming processes through instruction combination and process arrangement; the multiple programming processes include at least one of progressive pulse programming process, multi-bit programming process, adaptive programming process, and batch array programming process.

[0062] In the embodiments described in this specification, hardware-managed instructions (RRAM_PROG, RRAM_VERIFY_START, RRAM_VERIFY_READ) constitute the operational primitives for RRAM programming operations. Based on these basic hardware-managed operations, software can implement various complex programming flows through flexible instruction combinations and process arrangement.

[0063] The Progressive Pulse Programming (ISPP) process may include the following steps: setting an initial voltage value, a voltage increment step size, and a target resistance value; writing the current voltage value as a pre-configuration parameter into the configuration register; issuing the programming instruction; issuing the start verification instruction; issuing the read-back result instruction to read the verification result back to the processor's general-purpose register; comparing the verification result with the target resistance value; if the target resistance value is not reached, increasing the current voltage value by the voltage increment step size and writing the updated current voltage value into the configuration register, repeating the above steps; if the target resistance value is reached, exiting the loop. The following is an example of assembly code for a progressive pulse programming process implemented based on hardware managed instructions: # ISPP programming flow: Increment the voltage in each iteration until the target resistance value is reached. LI R3, INIT_VOLTAGE # Initial voltage LI R4, VOLTAGE_STEP # Voltage increment step size LI R5, TARGET_VAL # Target resistance value LI R6, MAX_VOLTAGE # Voltage limit ISPP_LOOP: STORE [REG_PRO_DIN_VWL], R3 # Pre-configured voltage trimming register RRAM_PROG # Issue unified programming instructions and return immediately. RRAM_VERIFY_START # Sends the start verification command, automatically blocking until PROG completes, and returns immediately after sending. RRAM_VERIFY_READ R2 # Issues a readback command. If the data is not ready, it blocks; once ready, it reads back to R2. BGE R2, R5, ISPP_DONE # Exit if target is met ADD R3, R3, R4 # Voltage increment BLT R3, R6, ISPP_LOOP # Continue iteration if not exceeding the limit ISPP_DONE: ... # Programming complete This example demonstrates how software can build complex ISPP programming strategies based on basic hardware-managed operations. High-level logic such as voltage increment (ADD R3, R3, R4), compliance checks (BGE R2, R5, ISPP_DONE), and over-limit protection (BLT R3, R6, ISPP_LOOP) is entirely software-controlled, while the precise timing of each programming pulse and the ADC sampling for verification are guaranteed by a hardware state machine. A hardware blocking mechanism ensures a strict timing order for programming and verification in each iteration; that is, RRAM_VERIFY_START automatically waits for RRAM_PROG to complete before execution.

[0064] The Multi-bit Programming (MLC) process may include the following steps: setting multiple target resistance thresholds and sorting them according to resistance order; selecting a target resistance threshold as the current target value in sequence according to the sorted order; for each current target value, repeating the following sub-steps until the current target value is reached: writing the pre-configuration parameters corresponding to the current target value into the configuration register, issuing the programming instruction, issuing the start verification instruction, issuing the readback result instruction, and determining whether the current target value has been reached based on the readback verification result; after programming all target resistance thresholds in sequence, programming a single RRAM cell to multiple discrete resistance states. Multi-bit programming utilizes the physical characteristic that RRAM cells can store multiple levels of resistance states. The software sets multiple target resistance thresholds and sequentially executes multiple rounds of Program-Verify loops on the same cell. The software is responsible for threshold management and state transition logic, while the hardware is responsible for precise pulse application and verification reading at each step.

[0065] The adaptive programming process may include the following steps: issuing the programming instruction to perform a programming operation on the target unit; issuing the start verification instruction and the readback result instruction to read back the actual resistance value of the target unit; calculating the deviation between the actual resistance value and the target resistance value; if the actual resistance value is lower than the target resistance value, updating the configuration register to select the RESET operation mode and writing the corresponding pulse parameters into the configuration register, and re-issuing the programming instruction to perform the RESET operation; if the actual resistance value is higher than the target resistance value, updating the configuration register to select the SET operation mode and writing the corresponding pulse parameters into the configuration register, and re-issuing the programming instruction to perform the SET operation; repeating the above steps until the actual resistance value reaches the target resistance value. The core of the adaptive programming process lies in "bidirectional approximation," that is, when the actual resistance value read back from the verification is higher than the target resistance value, the SET operation is performed to decrease the resistance value, and when the actual resistance value is lower than the target resistance value, the RESET operation is performed to increase the resistance value. This bidirectional approximation strategy can converge to the target resistance value more quickly, and is especially suitable for scenarios requiring high-precision weighted quantization.

[0066] The batch array programming process may include the following steps: looping through the row and column address registers, sequentially writing the row and column selection addresses and programming parameters of different cells as pre-configuration parameters into the configuration register, issuing the programming instructions, and sequentially performing programming operations on multiple cells. Batch array programming is one of the most basic programming processes. The software loops through the row and column address registers, updates the row and column selection addresses in the configuration register in each loop, and then issues hardware-managed instructions. The hardware state machine performs programming operations on the selected RRAM cells according to the new addresses. This is suitable for scenarios where data is written in batches to an RRAM array.

[0067] In an optional embodiment, when multiple resistive random access memory (RRAM) cells need to be programmed, the method further includes the following steps: during the execution of the programming instructions for the first cell by the hardware state machine, the processor non-blockingly issues and executes the configuration instructions for the second cell, writing the pre-configuration parameters of the second cell into the configuration register; after the programming instructions for the first cell are executed, the processor immediately issues the programming instructions for the second cell, triggering the hardware state machine to perform a programming operation on the second cell.

[0068] In the embodiments of this specification, when multiple RRAM cells need to be programmed, the software can utilize the non-blocking issue feature of this application to achieve software pipelined multi-cell programming. For programming tasks of cells A and B, the compiler can insert the address / voltage preparation and register write instructions of cell B between RRAM_PROG, RRAM_VERIFY_START, and RRAM_VERIFY_READ of cell A. This rearrangement is safe because the hardware state machine latches the value of the current configuration register the moment it receives the hardware-managed instruction, and subsequent modifications to the configuration register will not affect the operation being executed. Since the hardware-managed instruction does not block the processor after issuance, the processor no longer idles while waiting for RRAM simulation operations, thus completing the data preparation of cell B. After the verification of cell A is completed, the programming of cell B can begin immediately, realizing software pipelined multi-cell programming. The specific comparison of the assembly code before and after optimization is as follows: Before optimization (naive sequential execution): # Unit A Programming STORE [REG_ADDR], ADDR_A STORE [REG_VOLTAGE], V_A RRAM_PROG # Issue programming instructions RRAM_VERIFY_START # Blocks if PROG is not complete, returns immediately after launch. RRAM_VERIFY_READ R2 # Block if data is not ready BLT R2, TARGET, RETRY_A # Unit B Programming STORE [REG_ADDR], ADDR_B STORE [REG_VOLTAGE], V_B RRAM_PROG RRAM_VERIFY_START RRAM_VERIFY_READ R2 BLT R2, TARGET, RETRY_B After optimization (after compiler reordering): # Unit A Configuration and Triggering STORE [REG_ADDR], ADDR_A STORE [REG_VOLTAGE], V_A RRAM_PROG # Triggers A cell programming, returns immediately after emit. # ------------ The following instructions are issued and executed normally by the processor without blocking during PROG execution in RRAM ------------ LI R10, ADDR_B # Prepare address for cell B (irrelevant instruction) LI R11, V_B # Prepare voltage for cell B (irrelevant instruction) ADD R7, R7, R8 # Other irrelevant calculations # ------------ The following command may trigger a stop (if Unit A's PROG process has not yet completed) ------------ RRAM_VERIFY_START # Triggers cell A verification, returns immediately after transmission # ------------ The following instructions are issued and executed normally by the processor without blocking during the VERIFY operation in RRAM ------------ STORE [REG_ADDR], R10 # Pre-write the address of cell B to the configuration register STORE [REG_VOLTAGE], R11 # Pre-write the B cell voltage to the configuration register # ------------ The following command may trigger a Stall (if the Verify data in cell A is not yet ready) ------------ RRAM_VERIFY_READ R2 # Blocks if data is not ready, then reads back cell A to verify the result once ready. BLT R2, TARGET, RETRY_A # Unit B configuration has been completed in advance, trigger directly RRAM_PROG # Immediately trigger B-cell programming In an optional embodiment, a compiler instruction reordering and scheduling method for hardware managed instructions of resistive random access memory (RRAM) may include the following steps: performing data dependency analysis on instructions in the program, classifying instructions into a first type of dependent instructions that depend on the results of RRAM operations and a second type of unrelated instructions that do not depend on the results of RRAM operations; identifying consecutive hardware managed instruction pairs, wherein the hardware managed instructions include programming instructions, boot verification instructions, and read-back result instructions, and the consecutive hardware managed instruction pairs include programming instructions and boot verification instructions, or boot verification instructions and read-back result instructions; inserting the second type of unrelated instructions between the consecutive hardware managed instruction pairs, so that the processor issues and executes the second type of unrelated instructions without blocking before subsequent hardware managed instructions trigger pipeline blocking; when multiple RRAM cells need to be programmed, identifying the data dependency relationship between the programming instructions of the first cell and the configuration instructions of the second cell, if the second cell's... If the configuration instruction does not depend on the programming result of the first unit, then the configuration instruction of the second unit is scheduled after the programming instruction of the first unit and before the start verification instruction of the first unit, so that during the execution of the programming instruction of the first unit, the processor issues and executes the configuration instruction of the second unit without blocking. For an iterative loop containing programming instructions, start verification instructions, and readback result instructions, data dependency analysis is performed on the instructions between adjacent iterations to identify whether the parameter configuration instruction of the (i+1)th iteration depends on the verification result returned by the readback result instruction of the i-th iteration. If the parameter configuration instruction of the (i+1)th iteration does not depend on the verification result of the i-th iteration, then the parameter configuration instruction of the (i+1)th iteration is moved forward to be executed after the programming instruction or the start verification instruction of the i-th iteration, so that the parameter preparation of the (i+1)th iteration and the verification result judgment of the i-th iteration overlap in time.

[0069] In the embodiments of this specification, to maximize processor utilization while waiting for RRAM emulation operations, this application further proposes a compiler-level instruction reordering and scheduling method. This compiler optimization method is based on the hardware-provided "non-blocking issue" and "latching mechanism". The compiler's first task is to perform data dependency analysis, scanning each instruction in the program to identify whether it depends on the result of an RRAM operation. For example, the RRAM_VERIFY_READ instruction writes the verification result back to the general-purpose register R2. Subsequent BLT R2, TARGET, and LOOP instructions depend on the value in R2 to determine whether to continue the loop. Therefore, the BLT instruction is an instruction that depends on the result of an RRAM operation, while instructions that do not depend on the result of an RRAM operation are irrelevant instructions, such as loading immediate values ​​(LI), register addition (ADD), and storage instructions (STORE) that write addresses and voltages to the configuration register. The compiler's second task is to identify consecutive hardware managed instruction pairs, such as a programming instruction followed by a start verification instruction, or a start verification instruction followed by a read-back instruction, which constitute consecutive hardware managed instruction pairs. For these two types of instruction pairs, the compiler inserts as many irrelevant instructions as possible between the two managed instructions. Since hardware-managed instructions do not block the processor after being issued, these irrelevant instructions can be issued and executed normally by the processor before subsequent hardware-managed instructions trigger Stall, thus utilizing the waiting time of the simulation operation to complete useful computations. The compiler's third task is the pipelined scheduling of multi-unit programming. That is, when a program needs to program multiple RRAM units, the compiler identifies the data dependency between the programming instructions of the first unit and the configuration instructions of the second unit. If the configuration instructions of the second unit do not depend on the programming result of the first unit, the compiler schedules the configuration instructions of the second unit after the programming instructions of the first unit and before the start verification instructions of the first unit, so that the processor executes the configuration instructions of the second unit without blocking while the programming instructions of the first unit are executed by the hardware state machine. The compiler's fourth task is loop unrolling and iteration overlap. For iterative loops containing programming instructions, start-up verification instructions, and result readback instructions, the compiler performs data dependency analysis on instructions between adjacent iterations. If the parameter configuration instructions of the (i+1)th iteration do not depend on the verification result of the i-th iteration, the compiler can move these configuration instructions forward to execute after the programming instructions or start-up verification instructions of the i-th iteration. This allows the parameter preparation of the (i+1)th iteration to overlap with the verification result judgment of the i-th iteration, further compressing the iteration gap. Through the combined application of these four compiler optimization techniques, the processor no longer idles while waiting for RRAM emulation operations, achieving a significant improvement in overall system throughput.

[0070] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An instruction-level programming control device for a resistive random access memory, characterized in that, include: A processor includes an instruction fetch unit, an instruction dispatch unit, and pipeline control logic; The resistive random access memory execution unit includes a hardware state machine, configuration registers, latches, and a physical array interface, and is connected to the processor; The processor's instruction set includes hardware-managed instructions for controlling the programming of resistive random access memory (RRAM). These hardware-managed instructions include programming instructions, start verification instructions, and readback result instructions. The programming instructions are unified programming instructions, which, through a mode selection signal in the configuration register, determine whether to execute a SET operation to set the memory cell to a low-resistance state, a RESET operation to set it to a high-resistance state, or a FORM operation to initially activate it. The hardware-managed instructions return immediately after being issued without blocking the processor, which continues to issue and execute non-hardware-managed instructions without blocking. A hardware handshake signal line is provided between the instruction issuing unit and the resistive random access memory (RRAM) execution unit. The hardware handshake signal line is used to transmit the status signal of the RRAM execution unit to the instruction issuing unit. The status signal includes a first status signal indicating whether the RRAM execution unit is in a busy state and a second status signal indicating whether the verification data is ready. The resistive random access memory execution unit is configured to: in response to the hardware managed instruction issued by the processor, the latch latches the pre-configuration signal in the configuration register, and the hardware state machine autonomously generates physical timing signals based on the latched pre-configuration signal and applies them to the resistive random access memory array through the physical array interface; The instruction issuing unit is configured to: hold subsequent hardware-managed instructions in the pipeline issuing slot when the resistive random access memory execution unit is in a busy state, based on the status signal transmitted by the hardware handshake signal line, and hold the readback result instruction in the pipeline issuing slot when the second status signal indicates that the data is not ready.

2. The instruction-level programming control device for resistive random access memory as described in claim 1, characterized in that, The configuration register is used to store software pre-configuration signals, which include operating voltage adjustment value, multi-stage pulse width time parameter, row and column selection address, number of multiple sampling averaging times, and programming mode selection. The configuration register has a system bus interface for connecting to the processor to receive the pre-configuration signal written by the processor via non-hardware managed instructions; The latch is used to latch the pre-configuration signal in the configuration register when the hardware managed instruction is received, and the hardware state machine generates dynamic physical timing signals based on the latched pre-configuration signal; The output of the configuration register is sampled and held by the latch. After the hardware-managed instruction triggers the latch, the output value of the latch no longer changes with subsequent changes to the configuration register.

3. The instruction-level programming control device for resistive random access memory as described in claim 1, characterized in that, The hardware state machine includes unified state transition control logic, which includes an idle state, a first waiting state for waiting for the analog voltage to stabilize, and a second waiting state for applying a programming pulse or a sampling pulse. The configuration register contains multiple pulse width time parameter storage areas, with different storage areas corresponding to different instruction modes. The hardware state machine selects different pulse width time parameters from the configuration register under different instruction modes to control the duration of the first waiting state and the second waiting state.

4. The instruction-level programming control device for resistive random access memory as described in claim 1, characterized in that, The resistive random access memory execution unit also includes an analog-to-digital conversion processing module and a read-only register; The analog-to-digital conversion processing module is connected to the physical array interface and is used to read the analog data of the resistive random access memory array. The analog-to-digital conversion processing module includes an accumulation averaging unit and a bit width conversion unit. The accumulation averaging unit is used to accumulate multiple sampled data in multiple cycles according to the number of averaging calculations pre-configured in the configuration register. The bit width conversion unit is used to perform mean calculation and bit width conversion on the accumulation result. The read-only register is used to store the digital result processed by the analog-to-digital conversion module and to output the second status signal.

5. A pipelined synchronous programming method for resistive random access memory, characterized in that, Including the following steps: The programming instructions are sent from the processor to the resistive random access memory execution unit. After the programming instructions are sent, the processor immediately returns and continues to send subsequent instructions. In response to the issuance of the programming instruction, the hardware state machine of the resistive random access memory execution unit enters a busy state, latches the pre-configuration parameters in the configuration register, and autonomously generates physical timing signals according to the latched pre-configuration parameters to perform programming operations on the resistive random access memory array. While the hardware state machine is in the busy state, when the processor is preparing to issue a boot verification instruction in the pipeline, the boot verification instruction is blocked in the pipeline according to the hardware handshake protocol. After the programming operation is completed, the hardware state machine exits the busy state and pulls up the ready signal. The processor receives the ready signal, releases the block on the start verification instruction, and sends the start verification instruction to the resistive random access memory execution unit. After the start verification command is issued, the processor immediately returns and continues to issue subsequent commands. In response to the issuance of the start verification command, the hardware state machine re-enters the busy state, reads the analog data of the resistive random access memory array, converts it into digital results, and stores them in a read-only register. While the digital result is being stored in the read-only register, the processor detects that the digital result is not yet ready when it is preparing to issue a readback instruction in the pipeline, and blocks the readback instruction in the pipeline. Once the digital result is ready, the blocking of the readback result instruction is released, and the digital result is written back from the read-only register to the processor's target register.

6. The pipelined synchronous programming method for resistive random access memory as described in claim 5, characterized in that, The step of blocking the startup verification command in the pipeline specifically includes: The processor's instruction issuing unit detects the ready signal fed back by the resistive random access memory execution unit; If the ready signal is low, the instruction issuing unit holds the start verification instruction in the pipeline issuing slot until the ready signal becomes high, then releases the block and issues the start verification instruction to the resistive random access memory execution unit. The step of blocking the readback result instruction in the pipeline includes: The processor's instruction issuing unit detects the data ready signal fed back by the resistive random access memory execution unit; If the data ready signal is low, the instruction issuing unit holds the readback result instruction in the pipeline issuing slot until the data ready signal becomes high, then unblocks and writes the digital result from the read-only register back to the processor's target register; During the period when the start verification instruction or the readback result instruction is blocked in the pipeline launch slot, the non-hardware managed instructions already issued by the processor continue to be executed without being blocked.

7. The pipelined synchronous programming method for resistive random access memory as described in claim 5, characterized in that, The steps for pre-configuring parameters in the latch configuration register include: The pre-configured parameters include operating voltage adjustment value, pulse width time parameter, row and column selection address, number of samplings, and programming mode selection; The pre-configured parameters are pre-written into the configuration register by the processor using non-hardware managed instructions; When the hardware state machine receives the programming instruction or the start verification instruction, it latches the pre-configuration parameters and generates dynamic physical timing signals based on the latched pre-configuration parameters. After latching is complete, the processor modifies the configuration register using non-hardware managed instructions to prepare for the next operation without affecting the currently executing operation.

8. The pipelined synchronous programming method for resistive random access memory as described in claim 5, characterized in that, The step of reading the analog data from the resistive random access memory array and converting it into a digital result to be stored in a read-only register includes: The analog-to-digital conversion processing module of the resistive random access memory execution unit controls the hardware state machine to apply sampling pulses multiple times according to the averaging mode and averaging number pre-configured in the configuration register. After performing multi-cycle accumulation averaging and bit width conversion processing on the read analog data, the resulting digital result is stored in the read-only register, and the data ready signal is pulled high.

9. The pipelined synchronous programming method for resistive random access memory as described in claim 5, characterized in that, The software uses the programming instructions, the startup verification instructions, and the readback result instructions as operation primitives, and implements various programming processes through instruction combination and process arrangement; The various programming processes include at least one of progressive pulse programming, multi-bit programming, adaptive programming, and batch array programming. The progressive pulse programming process includes the following steps: setting the initial voltage value, voltage increment step size, and target resistance value; Write the current voltage value as a pre-configured parameter into the configuration register; issue the programming instruction; issue the start verification instruction; issue the read-back result instruction to read the verification result back into the processor's general-purpose register; compare the verification result with the target resistance value; if the target resistance value is not reached, increment the current voltage value by the voltage increment step and write the updated current voltage value into the configuration register, repeating the above steps; if the target resistance value is reached, exit the loop. The multi-bit programming process includes the following steps: setting multiple target resistance thresholds and sorting them according to resistance order; selecting a target resistance threshold as the current target value in sequence according to the sorted order; for each current target value, repeating the following sub-steps until the current target value is reached: writing the pre-configuration parameters corresponding to the current target value into the configuration register, issuing the programming instruction, issuing the start verification instruction, issuing the readback result instruction, and determining whether the current target value has been reached based on the readback verification result; After programming all target resistance thresholds in sequence, a single resistive variable memory cell is programmed into multiple discrete resistive states. The adaptive programming process includes the steps of: issuing the programming instructions to perform programming operations on the target unit; The start verification command and the readback result command are transmitted to read back the actual resistance value of the target unit; Calculate the deviation between the actual resistance value and the target resistance value; If the actual resistance value is lower than the target resistance value, the configuration register is updated to select the RESET operation mode and the corresponding pulse parameters are written into the configuration register. The programming instruction is then re-issued to execute the RESET operation. If the actual resistance value is higher than the target resistance value, the configuration register is updated to select the SET operation mode and the corresponding pulse parameters are written into the configuration register. The programming instruction is then re-issued to execute the SET operation. The above steps are repeated until the actual resistance value reaches the target resistance value. The batch array programming process includes the following steps: looping through the row and column address registers, sequentially writing the row and column selection addresses and programming parameters of different units as pre-configuration parameters into the configuration register, issuing the programming instructions, and sequentially performing programming operations on multiple units.

10. A compiler instruction reordering and scheduling method for managed instructions of resistive random access memory (RRAM), characterized in that, Including the following steps: Data dependency analysis is performed on the instructions in the program, and the instructions are divided into two categories: the first category of dependent instructions that depend on the results of resistive random access memory (RRAM) operations and the second category of unrelated instructions that do not depend on the results of RRAM operations. Identify consecutive hardware managed instruction pairs, the hardware managed instructions including programming instructions, startup verification instructions and readback result instructions, the consecutive hardware managed instruction pairs including programming instructions and startup verification instructions, or startup verification instructions and readback result instructions; Insert the second type of irrelevant instruction between the consecutive hardware managed instruction pairs, so that the processor issues and executes the second type of irrelevant instruction without blocking before the subsequent hardware managed instruction triggers pipeline blockage; When multiple resistive random access memory (RRAM) cells need to be programmed, the data dependency between the programming instructions of the first cell and the configuration instructions of the second cell is identified. If the configuration instructions of the second cell do not depend on the programming result of the first cell, the configuration instructions of the second cell are scheduled after the programming instructions of the first cell and before the start verification instructions of the first cell, so that during the execution of the programming instructions of the first cell, the processor issues and executes the configuration instructions of the second cell without blocking. For an iterative loop containing programming instructions, start verification instructions, and readback result instructions, data dependency analysis is performed on the instructions between adjacent iterations to identify whether the parameter configuration instruction of the (i+1)th iteration depends on the verification result returned by the readback result instruction of the i-th iteration. If the parameter configuration instruction of the (i+1)th iteration does not depend on the verification result of the i-th iteration, then the parameter configuration instruction of the (i+1)th iteration is moved forward to be executed after the programming instruction or the start verification instruction of the i-th iteration, so that the parameter preparation of the (i+1)th iteration and the verification result judgment of the i-th iteration overlap in time.

Images