Boost synchronous tube soft turn-on control circuit of bidirectional buck-boost converter

Abstract

The application discloses a Boost synchronous tube soft opening control circuit of a bidirectional Buck-Boost converter, and belongs to the technical field of power electronic control. The circuit comprises a direction detection reset unit, a reference voltage generation unit, a slope signal generation unit, a comparison unit and a logic synthesis unit. When a direction control signal Dir is flipped, the direction detection reset unit outputs a reset pulse, so that the reference voltage Vref is reset and slowly rises with constant current charging; the Vref and a period slope signal ramp are compared by the comparison unit to generate a pulse signal SR1 with an increasing pulse width; after being inverted, the PWM_Boost is compared with the SR1 by the logic synthesis unit to output a Boost synchronous tube driving signal, so that the conduction duty cycle of the synchronous tube gradually increases. The application realizes soft opening of the Boost synchronous tube when the power flow direction is switched, eliminates the risk of circuit lock caused by the mismatch between the control and the power state, is suitable for both Boost and Buck modes, has a simple structure and a smooth switching process.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic converter control, and specifically relates to a soft turn-on control circuit for the Boost synchronous rectifier of a bidirectional Buck-Boost converter. Background Art

[0002] The bidirectional four-switch Buck-Boost converter can realize bidirectional power transmission, can operate in Buck mode or Boost mode according to the relationship between input and output voltages, and is widely used in scenarios requiring bidirectional energy flow such as energy storage systems and new energy power supplies.

[0003] Figure 6 It is a prior-art bidirectional four-switch Buck-Boost control circuit, which includes a four-switch Buck-Boost step-up / step-down power circuit composed of power transistors Q1 to Q4 and a power inductor L1; RA is a current detection resistor when energy is transferred from B to A, and RB is a current detection resistor when energy is transferred from A to B; CS2 is a current detection signal when energy is transferred from B to A, and CS3 is a current detection signal when energy is transferred from A to B.

[0004] The working logic of the prior art is: When energy is transferred from A to B, the CS3 signal is used to control the output current. Q1 and Q2 form the upper and lower transistors of the Buck circuit, and Q3 and Q4 form the upper and lower transistors of the Boost circuit. If VA>VB, the Buck circuit operates, Q1 and Q2 are switched alternately, Q4 is permanently turned on, and Q3 is normally turned off; if VA<VB, the Boost circuit operates, Q3 and Q4 are switched alternately, Q1 is permanently turned on, and Q2 is normally turned off; if VA=VB, the Buck-Boost circuit operates, Q1 and Q2, as well as Q3 and Q4 are switched alternately.

[0005] When energy is transferred from B to A, the CS2 signal is used to control the output current. Q1 and Q2 form the upper and lower transistors of the Boost circuit, and Q3 and Q4 form the upper and lower transistors of the Buck circuit. If VA<VB, the Buck circuit operates, Q3 and Q4 are switched alternately, Q1 is permanently turned on, and Q2 is normally turned off; if VA>VB, the Boost circuit operates, Q1 and Q2 are switched alternately, Q4 is permanently turned on, and Q3 is normally turned off; if VA=VB, the Buck-Boost circuit operates, Q1 and Q2, as well as Q3 and Q4 are switched alternately.

[0006] Figures 7-9 It shows the normal power flow switching process of the prior art: Figure 7Operating principle 1 during normal operation: VA < VB, Dir is low, power flows from B to A, B is Vin, and A is Vout; at this time, Vin > Vout, the circuit operates in Buck mode, Vcomp is in the Buck interval, and the CS2 signal is used to control the output current; Q1 and Q2 form the upper and lower switches of the Boost circuit, and Q3 and Q4 form the upper and lower switches of the Buck circuit; since the circuit operates in Buck mode, Q3 and Q4 are switched alternately, Q1 is permanently on, and Q2 is permanently off.

[0007] Figure 8 Operating principle 2 during normal operation: VA < VB, Dir goes high, the power flow direction switches to from A to B, A is Vin, and B is Vout; at this time, Vin < Vout, but since Vcomp is still in the Buck interval, the operating state of the system remains Buck, the output voltage drops, the inductor current continues to become negative, Vcomp rapidly rises to the Boost region, the inductor current becomes positive, and the CS3 signal is used to control the output current; Q1 and Q2 form the upper and lower switches of the Buck circuit, and Q3 and Q4 form the upper and lower switches of the Boost circuit; since the circuit operates in Buck mode, Q1 and Q2 are switched alternately, Q4 is permanently on, and Q3 is permanently off. In this phase, the operating mode does not match the state of the input and output voltages, which is the most prone to problems.

[0008] Figure 9 Operating principle 3 during normal operation: VA < VB, Dir goes high, power flows from A to B, A is Vin, and B is Vout; at this time, Vin < Vout, Vcomp has entered the Boost interval, the system is in Boost mode, the output is stabilized at the set value, the inductor current maintains positive balance, and the CS3 signal is used to control the output current; Q1 and Q2 form the upper and lower switches of the Buck circuit, and Q3 and Q4 form the upper and lower switches of the Boost circuit; since the circuit operates in Boost mode, Q3 and Q4 are switched alternately, Q1 is permanently on, and Q2 is permanently off.

[0009] However, the prior art has obvious defects: during the transient of power flow direction switching, the update of the loop compensation voltage Vcomp lags behind the inversion of the Dir direction signal, which causes a mismatch between the control mode and the actual power state; especially under the current-limited constant current operating condition, the reverse current will cause the current detection signal to exceed the current limiting threshold, the error amplifier clamps Vcomp at the minimum value, which cannot rise with the voltage loop to switch to the Boost mode, and eventually mode lockout occurs.

[0010] Figures 10-12 shows the abnormal operating condition of the prior art: Figure 10Operating waveform 1 in abnormal state: VA<VB, Dir is low, power flows from B to A, B is Vin, A is Vout, CS2=ilimit, the circuit operates in constant current mode, and Vcomp is controlled by CS2; at this time, Vin>Vout, the circuit operates in Buck mode, Vcomp is in the Buck interval, and the CS2 signal achieves constant current by controlling Vcomp; Q1 and Q2 form the high-side and low-side switches of the Boost circuit, and Q3 and Q4 form the high-side and low-side switches of the Buck circuit; since the circuit operates in Buck mode, Q3 and Q4 are alternately switched, Q1 is permanently on, and Q2 is permanently off.

[0011] Figure 11 Operating waveform 2 in abnormal state: VA<VB, Dir goes high, B is Vin, A is Vout; at this time, Vin<Vout, but the circuit still operates in Buck mode, Vcomp is in the Buck interval, Vout continues to supply energy to Vin through the body diode of the power transistor, the inductor current becomes more negative, the CS2 signal further rises, Vcomp is pulled to the minimum, and the system is locked in Buck mode; Q1 and Q2 form the high-side and low-side switches of the Buck circuit, and Q3 and Q4 form the high-side and low-side switches of the Boost circuit; since the circuit operates in Buck mode, Q1 and Q2 are alternately switched, Q4 is permanently on, and Q3 is permanently off; Vout is continuously pulled low until Vout=Vin.

[0012] Figure 12 Operating waveform 3 in abnormal state: VA<VB, Dir goes high, B is Vin, A is Vout; at this time, Vin>=Vout, the circuit still operates in Buck mode, Vcomp is in the Buck interval; since Vout<Vin, the output can no longer transfer energy to the input, so the inductor current rises and the CS2 voltage drops; when the CS2 voltage drops below ilimit, Vcomp is released and taken over by the voltage loop; Vcomp rises rapidly, both the inductor current and the input voltage increase rapidly, and finally the system returns to Boost mode, at which time Vin<Vout; Q1 and Q2 form the high-side and low-side switches of the Buck circuit, and Q3 and Q4 form the high-side and low-side switches of the Boost circuit; since the circuit operates in Boost mode, Q3 and Q4 are alternately switched, Q1 is permanently on, and Q2 is permanently off.

[0013] It can be seen that in the process of power flow switching of the existing bidirectional Buck-Boost converter, the mode switching speed of the control stage is faster than the response speed of the power stage and the loop, which causes mismatch between the control logic and the actual power state, and in severe cases, mode lockup occurs, resulting in output abnormality. The existing solutions lack progressive turn-on control for the Boost synchronous transistor, and cannot suppress the reverse current spike and mode lockup phenomenon during the switching transient. Summary of the Invention

[0014] To address the issue in existing bidirectional four-switch Buck-Boost converters where the loop compensation voltage update lags behind the direction signal flip during power direction switching, leading to a mismatch between the control mode and power state, especially under constant current conditions where reverse current causes Vcomp to be clamped and mode lock-up, this application designs a soft-turn-on control circuit for the Boost synchronous transistor in a bidirectional Buck-Boost converter. This circuit gradually increases the duty cycle of the Boost synchronous transistor during direction switching, suppressing reverse current spikes and achieving a smooth transition of power direction, thus avoiding lock-up anomalies.

[0015] A soft-turn-on control circuit for the Boost synchronous transistor of a bidirectional Buck-Boost converter includes a direction detection and reset unit, a reference voltage generation unit, a ramp signal generation unit, a comparison unit, and a logic synthesis unit. The input terminal of the direction detection and reset unit is connected to the direction control signal Dir, and the output terminal is connected to the reset control terminal of the reference voltage generation unit, which is used to output a reset pulse when the Dir signal level flips. The reference voltage generation unit includes a first current source, a first energy storage capacitor, and a first reset switch. One end of the first current source is connected to the power supply voltage Vcc, and the other end is connected to the upper end of the first energy storage capacitor, while the lower end of the first energy storage capacitor is grounded. The first current source is used to charge the first energy storage capacitor with a constant current to generate a reference voltage Vref that rises slowly over time. The first reset switch is turned on in response to the reset pulse to discharge and reset the first energy storage capacitor, causing Vref to rise again from a 0 level. The ramp signal generation unit includes a second current source, a second energy storage capacitor, and a second reset switch. One end of the second current source is connected to the power supply voltage Vcc, and the other end is connected to the upper end of the second energy storage capacitor, while the lower end of the second energy storage capacitor is grounded. The second current source is used to charge the second energy storage capacitor with a constant current to generate a periodically rising ramp signal. The second reset switch is used to turn on during each switching cycle to discharge and reset the second energy storage capacitor. The non-inverting input of the comparator is connected to Vref, the inverting input is connected to ramp, and the output is a pulse signal SR1; the conduction pulse width of SR1 gradually increases as Vref increases. The logic synthesis unit connects SR1 and the Boost lower transistor main drive signal PWM_Boost, inverts PWM_Boost and performs an AND operation with SR1 to output the Boost synchronous transistor drive signal Boost_TG. During the soft turn-on phase, the conduction width of Boost_TG is limited by SR1, and during the steady-state phase, the conduction width of Boost_TG is determined by the inverted signal of PWM_Boost.

[0016] Preferably, the direction detection and reset unit includes a delay unit and an XOR gate; one path of the Dir signal is directly connected to the first input terminal of the XOR gate, and the other path is delayed by the delay unit and then connected to the second input terminal of the XOR gate; the output terminal of the XOR gate is connected to the control electrode of the first reset switch transistor; when the Dir signal level flips, the XOR gate outputs a reset pulse that matches the delay duration of the delay unit.

[0017] Preferably, the reference voltage generation unit further includes a first clamping diode, wherein the highest level of Vref is clamped at the power supply voltage Vcc by the first clamping diode; the ramp signal generation unit further includes a second clamping diode, wherein the highest level of ramp is clamped at Vcc-0.3V by the second clamping diode.

[0018] Preferably, the ramp signal generation unit further includes an inverter and an RS flip-flop; Boost_TG is connected to the set terminal of the RS flip-flop, SR1 is connected to the reset terminal of the RS flip-flop via the inverter, and the output terminal of the RS flip-flop is connected to the control electrode of the second reset switch; the rising edge of Boost_TG in each switching cycle sets the RS flip-flop, the second reset switch is turned off, and ramp starts charging; the falling edge of SR1 triggers the RS flip-flop to reset, and the second reset switch is turned on to reset the ramp signal.

[0019] Preferably, the logic synthesis unit is an AND gate with an inverting input; PWM_Boost is connected to the inverting input of the AND gate, and SR1 is connected to the non-inverting input of the AND gate; the conduction width of Boost_TG is the smaller value between the conduction width of SR1 and the low-level width of PWM_Boost.

[0020] Preferably, the control circuit is applied to a four-switch bidirectional Buck-Boost power topology; the four-switch bidirectional Buck-Boost power topology includes a Buck bridge arm, a Boost bridge arm, and a power inductor, wherein the upper transistor of the Boost bridge arm is a Boost synchronous transistor; the driving terminal of the Boost synchronous transistor is connected to Boost_TG.

[0021] Preferably, when the converter operates in Boost mode, PWM_Boost is a periodic square wave signal; during the soft-turn-on phase, the conduction width of Boost_TG is determined by SR1 and gradually increases; when Vref is higher than the highest level of ramp, SR1 remains at a constant high level, and the conduction width of Boost_TG is determined by the inversion of PWM_Boost, and the circuit enters steady-state operation.

[0022] Preferably, when the converter is operating in Buck mode, PWM_Boost remains at a constant low level; the conduction width of Boost_TG is consistent with the conduction width of SR1, and gradually increases as Vref increases; when Vref is higher than the highest level of ramp, SR1 remains at a constant high level, and the Boost synchronous transistor enters the fully conducting state.

[0023] Preferably, when the power flow direction of the bidirectional Buck-Boost converter switches and the Dir signal level flips, the direction detection and reset unit outputs a reset pulse to reset Vref and gradually increase it again. The duty cycle of the Boost synchronous tube gradually increases, suppressing reverse current spikes and avoiding mode lock-up caused by the current loop clamping of the loop compensation voltage.

[0024] The advantages and effects of this application are as follows: 1. The soft-turn-on control circuit of the Boost synchronous tube in the bidirectional Buck-Boost converter designed in this application triggers the reference voltage reset when the Dir signal flips through the direction detection reset unit. With constant current charging, Vref is slowly increased, thereby gradually increasing the duty cycle of the Boost synchronous tube. This avoids the reverse current spike caused by the synchronous tube suddenly turning on, and solves the circuit lock-up problem caused by the mismatch between control and power state from the root. 2. The soft-turn-on control circuit of the Boost synchronous tube of the bidirectional Buck-Boost converter designed in this application generates control pulses with increasing pulse width by comparing the reference voltage with the periodic ramp. The slope of the conduction width change is determined by the parameters of the current source and the energy storage capacitor. It has high control accuracy and flexible parameter adjustment, and can be adapted to converters of different power levels. 3. The soft-start control circuit of the Boost synchronous tube of the bidirectional Buck-Boost converter designed in this application inverts the PWM_Boost and performs an AND operation with SR1 through the logic synthesis unit. During the soft-start stage, SR1 automatically limits the conduction width. During the steady-state stage, SR1 remains high and does not affect the normal control of the original main PWM. The mode switching is seamless and has strong compatibility. 4. The soft-turn-on control circuit for the Boost synchronous tube of the bidirectional Buck-Boost converter designed in this application is compatible with both Boost and Buck operating modes. It can achieve soft-turn-on effect in both directions of bidirectional power transmission switching scenarios, has a wide range of applications, and the circuit structure is implemented entirely with analog devices, without the need for digital control, resulting in low cost and high reliability.

[0025] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the preferred embodiments of this application are described in detail below with reference to the accompanying drawings.

[0026] The above and other objects, advantages and features of this application will become more apparent to those skilled in the art from the following detailed description of specific embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In all drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0028] Figure 1 This is a schematic diagram of the Boost synchronous transistor soft-turn-on control circuit according to an embodiment of the present invention; Figure 2 This is a waveform diagram of soft-enable operation in Boost mode according to an embodiment of the present invention; Figure 3 This is a waveform diagram of soft-start operation in Buck mode according to an embodiment of the present invention; Figure 4 This is a simplified topology diagram of the bidirectional Buck-Boost power stage used in an embodiment of the present invention; Figure 5 This is a waveform diagram of the power flow direction switching transient in an embodiment of the present invention; Figure 6 This is a schematic diagram of a bidirectional four-switch Buck-boost control circuit in the prior art. Figure 7 The waveform 1 is the working waveform when the existing technology is working normally (B flows to A, Buck steady-state mode). Figure 8 The working waveform 2 (mode mismatch transition stage after Dir flip) is the working waveform when the existing technology is working normally. Figure 9 The waveform 3 is the working waveform when the existing technology is working normally (A flows to B, Boost steady-state mode). Figure 10 Waveform 1 for abnormal operating conditions of existing technology (constant current Buck mode). Figure 11Waveform 2 for abnormal operating conditions of existing technology (mode lock-up stage after Dir flip). Figure 12 Waveform 3 for abnormal operating conditions of existing technology (recovery from locked state to Boost mode). Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. In the following description, specific details such as specific configurations and components are provided merely to help fully understand the embodiments of this application. Therefore, those skilled in the art should understand that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. In addition, for clarity and brevity, descriptions of known functions and structures are omitted in the embodiments.

[0030] It should be understood that the phrase "an embodiment" or "this embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "an embodiment" or "this embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0031] Furthermore, reference numerals and / or letters may be repeated in different examples within this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0032] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist simultaneously. The term " / and" in this article describes another type of relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " in this article generally indicates that the related objects before and after it are in an "or" relationship.

[0033] In this article, the term "at least one" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, "at least one of A and B" can mean: A exists alone, A and B exist simultaneously, or B exists alone.

[0034] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion.

[0035] Example 1: This example proposes a soft-turn-on control circuit for the Boost synchronous transistor in a bidirectional Buck-Boost converter. It is applied to a four-switch bidirectional Buck-Boost power topology to achieve gradual soft-turn-on of the Boost synchronous transistor when the power flow direction is switched, suppressing reverse current spikes and eliminating the risk of circuit lock-up caused by control and power mismatch.

[0036] It should be noted that the switching transistors inside the control circuit of this invention and the power transistors in the power stage are devices with different functions. To avoid ambiguity, this embodiment uses the following names: the small-signal switching transistor used to reset Vref in the control circuit is the first reset switching transistor, and the small-signal switching transistor used to reset ramp is the second reset switching transistor; the upper transistor of the Boost bridge arm in the power stage is the Boost synchronous transistor, and the lower transistor is the Boost lower transistor.

[0037] I. Circuit Structure and Connection Relationships like Figure 1 As shown, the soft-turn-on control circuit includes a direction detection and reset unit, a reference voltage generation unit, a ramp signal generation unit, a comparator CMP, and a logic synthesis unit.

[0038] 1. Direction detection and reset unit The direction detection and reset unit includes a delay unit U2 and an XOR gate U1. One direction control signal, Dir, is directly connected to the first input of the XOR gate U1, and the other signal is delayed by the delay unit U2 before being connected to the second input of the XOR gate U1. The output of the XOR gate U1 is connected to the gate of the first reset switch Q4.

[0039] When the Dir signal level flips (rising or falling edge), a level difference will appear at the two inputs of XOR gate U1 within the delay time. XOR gate U1 outputs a high-level reset pulse that matches the delay time of delay unit U2. After the delay time ends, the levels at the two inputs return to the same, and XOR gate U1 outputs a low level. This unit can detect the bidirectional flip of Dir and realize soft-start triggering during bidirectional power switching.

[0040] 2. Reference voltage generation unit The reference voltage generation unit includes a first current source gv1, a first energy storage capacitor, a first clamping diode D2, and a first reset switch Q4.

[0041] The first current source gv1 is connected to the power supply Vcc at its upper end and to the upper end of the first energy storage capacitor at its lower end, with the lower end of the first energy storage capacitor grounded. The first current source gv1 is used to charge the first energy storage capacitor with a constant current, generating a reference voltage Vref that rises slowly over time. The cathode of the first clamping diode D2 is connected to Vcc, and the anode is connected to the Vref node, clamping the highest level of Vref at the power supply voltage Vcc to prevent overcharging.

[0042] The first reset switch Q4 is an NMOS transistor with its drain connected to the Vref node, its source grounded, and its gate connected to the output of the XOR gate U1. When the reset pulse arrives, Q4 is turned on, discharging the first energy storage capacitor to ground level, causing Vref to rise again from 0.

[0043] 3. Ramp signal generation unit The ramp signal generation unit includes a second current source gv2, a second energy storage capacitor, a second clamping diode D3, a second reset switch Q3, an inverter U4, and an RS flip-flop U5.

[0044] The second current source gv2 is connected to the power supply Vcc at its upper end and to the upper end of the second energy storage capacitor at its lower end, with the lower end of the second energy storage capacitor grounded. The second current source gv2 is used to charge the second energy storage capacitor with a constant current, generating a periodically rising ramp signal. The cathode of the second clamping diode D3 is connected to Vcc-0.3V, and the anode is connected to the ramp node, clamping the highest level of ramp at Vcc-0.3V. This ensures that the peak value of ramp is always lower than the final clamping voltage Vref, allowing SR1 to reliably maintain a high level in steady state.

[0045] The second reset switch Q3 is an NMOS transistor with its drain connected to the ramp node, its source grounded, and its gate connected to the output of RS flip-flop U5. The Boost_TG output from the logic synthesis unit is connected to the set terminal of RS flip-flop U5, and the SR1 signal output from comparator CMP is connected to the reset terminal of RS flip-flop U5 via inverter U4.

[0046] During each switching cycle, the rising edge of Boost_TG sets RS flip-flop U5, outputting a low level, and the second reset switch Q3 is turned off, allowing the ramp to start charging and rising. When the ramp voltage rises to Vref, comparator CMP flips, SR1 generates a falling edge, which triggers RS flip-flop U5 to reset via inverter U4, outputting a high level. The second reset switch Q3 is then turned on, discharging and resetting the second energy storage capacitor, thus achieving synchronous reset of the ramp signal for each switching cycle.

[0047] 4. Comparison Unit The comparator unit is a comparator CMP, with its non-inverting input connected to Vref and its inverting input connected to ramp. When the ramp voltage is lower than Vref, the comparator CMP outputs a high level; when the ramp voltage is higher than Vref, the comparator CMP outputs a low level. Therefore, the conduction pulse width of the output pulse signal SR1 gradually increases as Vref increases; when Vref is higher than the highest level of ramp Vcc-0.3V, the comparator CMP continuously outputs a high level, and SR1 remains constantly high.

[0048] 5. Logic synthesis unit The logic synthesis unit is an AND gate U3 with an inverting input. PWM_Boost is connected to the inverting input of AND gate U3, SR1 is connected to the non-inverting input of AND gate U3, and AND gate U3 outputs the Boost synchronous tube drive signal Boost_TG.

[0049] The logical relationship is as follows: Boost_TG outputs a high level when SR1 is high and PWM_Boost is low. That is, the high-level range of Boost_TG is the intersection of the high-level range of SR1 and the low-level range of PWM_Boost, and the conduction width is the smaller of the two. Here, PWM_Boost is the main drive signal of the lower Boost transistor. The Boost synchronous transistor and the lower Boost transistor have a complementary conduction relationship. Therefore, the low level of PWM_Boost corresponds to the conduction range that the Boost synchronous transistor should have.

[0050] II. Power Topology of Application like Figure 4 As shown, the control circuit in this embodiment is applied to a four-switch bidirectional Buck-Boost power topology, and the complete topology is similar to... Figure 6 The power stages are consistent and include Buck bridge arm, Boost bridge arm and power inductor L; Buck bridge arm consists of upper tube Q1 and lower tube Q2; Boost bridge arm consists of Boost synchronous tube and Boost lower tube; power inductor L is connected between the midpoints of the two bridge arms.

[0051] The Buck bridge arm has a B→A current detection circuit consisting of a sampling resistor RA and an operational amplifier, outputting a detection signal CS2; the Boost bridge arm has an A→B current detection circuit consisting of a sampling resistor RB and an operational amplifier, outputting a detection signal CS3. The drive terminal of the Boost synchronous transistor is connected to the Boost_TG signal output by this control circuit.

[0052] III. Working Principle and Process 1. Boost Mode Working Process like Figure 2As shown, when the converter is working in Boost mode, PWM_Boost is a periodic square wave signal. The Boost lower transistor is chopping, and the Boost synchronous transistor is corresponding to synchronous freewheeling. The time when it should be turned on corresponds to the low level of PWM_Boost.

[0053] During the initial soft-switching phase, Vref rises slowly from 0, with an amplitude much lower than the peak value of ramp. Within each switching cycle, the time it takes for ramp to rise to the Vref level is very short, resulting in a narrow pulse width for SR1. At this point, the conduction width of SR1 is less than the low-level width of PWM_Boost. After an AND operation, the conduction width of Boost_TG is determined by SR1, thus limiting the turn-on time of the Boost synchronous transistor to a relatively narrow range.

[0054] As Vref gradually increases, the conduction pulse width of SR1 increases synchronously, the conduction width of Boost_TG also gradually widens, and the turn-on time of the Boost synchronizing tube increases linearly.

[0055] When Vref rises above the highest level of ramp, Vcc-0.3V, comparator CMP stops toggling, and SR1 remains at a constant high level. At this point, the output of AND gate U3 is entirely determined by the inverted PWM_Boost, and the conduction width of Boost_TG is controlled by the main PWM signal. The soft-start process ends, and the circuit enters the steady-state Boost operating state.

[0056] 2. Buck Mode Working Process like Figure 3 As shown, when the converter is operating in Buck mode, PWM_Boost remains at a constant low level, and the Boost synchronous transistor should be on throughout as a synchronous freewheeling transistor.

[0057] During the initial soft-start phase, Vref rises slowly from 0, and the conduction pulse width of SR1 is relatively narrow. Since PWM_Boost is always low and becomes a constant high level after inversion, the output of AND gate U3 is entirely determined by SR1. Therefore, the conduction width of Boost_TG is consistent with SR1, and the turn-on time of the Boost synchronous transistor gradually increases with SR1.

[0058] When Vref rises above the highest level of ramp, SR1 remains at a constant high level, Boost_TG continues to output a high level, the Boost synchronous tube enters a fully conducting state, the soft-start process ends, and the circuit enters a steady-state Buck operating state.

[0059] 3. Transient operation process of power flow direction switching like Figure 5As shown, when VA < VB and the power flow direction switches, the level of the Dir signal flips, and the system switches from Buck mode to Boost mode. At this time, the control stage has switched modes, but the inductor current in the power stage cannot change abruptly. If the synchronous rectifier is fully turned on directly, an extremely large reverse current will be generated, causing CS2 to exceed the current limiting threshold, and Vcomp will be clamped and locked.

[0060] At the moment Dir flips, the direction detection reset unit outputs a reset pulse, which resets Vref to 0 and starts to rise slowly again, and the on-duty ratio of the Boost synchronous rectifier gradually increases from narrow to wide. In this process, the reverse current is quickly cut off and then gradually released without generating spikes. The CS2 signal drops rapidly along with the reverse current signal, will not exceed the current limiting threshold, Vcomp can rise smoothly with the voltage loop, and finally switches to the Boost mode.

[0061] During the switching process, the current detection signal CS2 changes gently with the inductor current, the loop compensation voltage Vcomp gradually rises from the Buck interval to the Boost interval, and finally the circuit stably operates in the Boost mode, the VB voltage enters a steady state, which effectively avoids the mode lock-up problem.

[0062] The above description is only a preferred embodiment of the present invention, and is not intended to limit the protection scope of the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any variations, modifications, substitutions, integrations and parameter changes to the embodiments, which are made through conventional alternatives or can achieve the same function without departing from the principle and spirit of the present invention, shall fall within the protection scope of the present invention within the spirit and principle of the present invention.

Claims

1. A soft-turn-on control circuit for the Boost synchronous transistor in a bidirectional Buck-Boost converter, characterized in that, It includes a direction detection and reset unit, a reference voltage generation unit, a ramp signal generation unit, a comparison unit, and a logic synthesis unit; The input terminal of the direction detection and reset unit is connected to the direction control signal Dir, and the output terminal is connected to the reset control terminal of the reference voltage generation unit, which is used to output a reset pulse when the Dir signal level flips. The reference voltage generation unit includes a first current source, a first energy storage capacitor, and a first reset switch. One end of the first current source is connected to the power supply voltage Vcc, and the other end is connected to the upper end of the first energy storage capacitor, while the lower end of the first energy storage capacitor is grounded. The first current source is used to charge the first energy storage capacitor with a constant current to generate a reference voltage Vref that rises slowly over time. The first reset switch is turned on in response to the reset pulse to discharge and reset the first energy storage capacitor, causing Vref to rise again from a 0 level. The ramp signal generation unit includes a second current source, a second energy storage capacitor, and a second reset switch. One end of the second current source is connected to the power supply voltage Vcc, and the other end is connected to the upper end of the second energy storage capacitor, while the lower end of the second energy storage capacitor is grounded. The second current source is used to charge the second energy storage capacitor with a constant current to generate a periodically rising ramp signal. The second reset switch is used to turn on during each switching cycle to discharge and reset the second energy storage capacitor. The non-inverting input of the comparator is connected to Vref, the inverting input is connected to ramp, and the output is a pulse signal SR1; the conduction pulse width of SR1 gradually increases as Vref increases. The logic synthesis unit connects SR1 and the Boost lower transistor main drive signal PWM_Boost, inverts PWM_Boost and performs an AND operation with SR1 to output the Boost synchronous transistor drive signal Boost_TG. During the soft turn-on phase, the conduction width of Boost_TG is limited by SR1, and during the steady-state phase, the conduction width of Boost_TG is determined by the inverted signal of PWM_Boost.

2. The soft-turn-on control circuit for the Boost synchronous transistor of the bidirectional Buck-Boost converter according to claim 1, characterized in that, The direction detection and reset unit includes a delay unit and an XOR gate; one path of the Dir signal is directly connected to the first input terminal of the XOR gate, and the other path is delayed by the delay unit and then connected to the second input terminal of the XOR gate; the output terminal of the XOR gate is connected to the control electrode of the first reset switch transistor; when the Dir signal level flips, the XOR gate outputs a reset pulse that matches the delay duration of the delay unit.

3. The soft-turn-on control circuit for the Boost synchronous transistor of the bidirectional Buck-Boost converter according to claim 1, characterized in that, The reference voltage generation unit further includes a first clamping diode, wherein the highest level of Vref is clamped at the power supply voltage Vcc by the first clamping diode; the ramp signal generation unit further includes a second clamping diode, wherein the highest level of ramp is clamped at Vcc-0.3V by the second clamping diode.

4. The soft-turn-on control circuit for the Boost synchronous transistor of the bidirectional Buck-Boost converter according to claim 1, characterized in that, The ramp signal generation unit also includes an inverter and an RS flip-flop; Boost_TG is connected to the set terminal of the RS flip-flop, SR1 is connected to the reset terminal of the RS flip-flop via the inverter, and the output terminal of the RS flip-flop is connected to the control electrode of the second reset switch; the rising edge of Boost_TG in each switching cycle sets the RS flip-flop, the second reset switch is turned off, and ramp starts charging; the falling edge of SR1 triggers the RS flip-flop to reset, and the second reset switch is turned on to reset the ramp signal.

5. The soft-turn-on control circuit for the Boost synchronous transistor of the bidirectional Buck-Boost converter according to claim 1, characterized in that, The logic synthesis unit is an AND gate with an inverting input; PWM_Boost is connected to the inverting input of the AND gate, and SR1 is connected to the non-inverting input of the AND gate; the conduction width of Boost_TG is the smaller of the conduction width of SR1 and the low-level width of PWM_Boost.

6. The soft-turn-on control circuit for the Boost synchronous transistor of the bidirectional Buck-Boost converter according to claim 1, characterized in that, This control circuit is applied to a four-switch bidirectional Buck-Boost power topology; the four-switch bidirectional Buck-Boost power topology includes a Buck bridge arm, a Boost bridge arm, and a power inductor, and the upper transistor of the Boost bridge arm is a Boost synchronous transistor; the driving terminal of the Boost synchronous transistor is connected to Boost_TG.

7. The soft-turn-on control circuit for the Boost synchronous transistor of the bidirectional Buck-Boost converter according to claim 6, characterized in that, When the converter operates in Boost mode, PWM_Boost is a periodic square wave signal; during the soft-turn-on phase, the conduction width of Boost_TG is determined by SR1 and gradually increases; when Vref is higher than the highest level of ramp, SR1 remains at a constant high level, and the conduction width of Boost_TG is determined by the inverted PWM_Boost, and the circuit enters steady-state operation.

8. The soft-turn-on control circuit for the Boost synchronous transistor of the bidirectional Buck-Boost converter according to claim 6, characterized in that, When the converter is operating in Buck mode, PWM_Boost remains at a constant low level; the conduction width of Boost_TG is the same as that of SR1, and gradually increases as Vref increases; when Vref is higher than the highest level of ramp, SR1 remains at a constant high level, and the Boost synchronous transistor enters the fully conducting state.

9. The soft-turn-on control circuit for the Boost synchronous transistor of the bidirectional Buck-Boost converter according to claim 1, characterized in that, When the power flow direction of the bidirectional Buck-Boost converter switches and the Dir signal level flips, the direction detection and reset unit outputs a reset pulse to reset Vref and gradually increase it again. The duty cycle of the Boost synchronous tube gradually increases, suppressing reverse current spikes and preventing the loop compensation voltage from being clamped by the current loop, which could cause mode lock-up.

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