Adaptive multi-sampling rate variable order cic filter hardware circuit and system

Abstract

The application discloses a variable-order CIC filter hardware circuit suitable for multiple sampling rates, which is applied to a decimation filter system of a sigma-delta analog-to-digital converter, and comprises a control module, an integrator module, a synchronous selector, a decimator module, a comb filter module and a gain equalization module.

Description

Technical Field

[0001] This application relates to the field of digital signal processing technology, and in particular to a variable-order CIC filter hardware circuit and system adapted to multiple sampling rates. Summary of the Invention

[0002] Sigma-delta analog-to-digital converters (Σ-Δ ADCs) are widely used in digital signal processing scenarios such as audio and sensor signal acquisition. Cascaded integrator-comb (CIC) filters are the most commonly used decimation filters in Σ-Δ ADCs, primarily used for downsampling and filtering the high-speed bitstream output from the Σ-Δ modulator. A CIC filter mainly consists of three parts: an integrator, a downsampling decimator, and a comb filter. Taking a third-order CIC filter as an example, its architecture includes a third-order integrator, a downsampling decimator, and a third-order comb filter. The third-order integrator operates at a high input sampling rate, performing integration and accumulation of the input signal. The downsampling decimator performs downsampling according to a decimation factor R, that is, extracting one valid data point every R input data points. After downsampling, the signal flows to the third-order comb filter operating at a low sampling rate, where the comb filter performs inverse differential operations to achieve the filtered output.

[0003] The existing fixed-order CIC filter hardware architecture cannot adaptively and dynamically adjust the filter order N according to the decimation rate R, resulting in severe application limitations and an inability to adapt to all sampling rate scenarios. Specifically, the shortcomings lie in its two-way adaptability: if a fixed low-order filter architecture is used, the filter's stopband attenuation is severely insufficient in low-decimation-rate scenarios, resulting in weak high-frequency noise suppression and easy out-of-band noise leakage, leading to a significant decrease in ADC sampling accuracy and substandard filtering performance. If a fixed high-order filter architecture is used, although it can compensate for the insufficient stopband attenuation at low rates, the overall filter gain will increase exponentially at high decimation-rate R, easily causing data overflow, signal saturation distortion, and other problems, thus compromising signal integrity. Therefore, fixed-order CIC filters cannot simultaneously achieve filtering performance and signal stability at both large and small decimation rates, exhibiting extremely poor adaptability and versatility.

[0004] In view of this, the embodiments of this application provide a variable-step CIC filter hardware circuit and system that adapts to multiple sampling rates, which has the advantages of improved filtering performance, improved signal stability, adaptability and versatility.

[0005] In a first aspect, embodiments of this application provide a variable-order CIC filter hardware circuit adapted to multiple sampling rates, applied to the decimation filtering system of a Σ-Δ analog-to-digital converter. The hardware circuit includes: a control module, an integrator module, a synchronization selector, a decimator module, a comb filter module, and a gain equalization module. The integrator module is a 2-8 stage cascaded integrator chain, with the output of each stage integrator being independently brought out, supporting dynamic configuration of the 2-8th order of operation. The comb filter module is configured as a 2-8 stage comb filter chain corresponding one-to-one with the integrator module, and the operating order of the comb filter module switches synchronously with the integrator module in real time. The synchronization selector includes an integral selector and a differential selector. The integral selector and the differential selector synchronously select the second to eighth order output signals of the integrator module and the comb filter module, respectively, so that the effective operating order of the integral link and the comb filter link are strictly kept consistent. The extractor module is used to perform R-fold downsampling extraction on the high-speed data stream output by the integrator module. The control module has a built-in parameter mapping lookup table, which is used to match the corresponding decimation factor R, target filter order N, and reference shift bit parameters according to the current input target sampling rate. The control module is configured with a reverse mapping rule: the larger the decimation factor R, the smaller the matched target filter order N, and the smaller the decimation factor R, the larger the matched target filter order N. The gain equalization module is composed of shift register hardware, which achieves full-range gain calibration through binary left or right shift operations.

[0006] In a second aspect, an audio chip is provided, characterized in that the audio chip includes the variable-order CIC filter hardware circuit adapted to multiple sampling rates provided in the first aspect.

[0007] Thirdly, an electronic device is provided, which includes the audio chip of the second aspect.

[0008] As can be seen, this application employs a dynamically configurable integrator chain and comb filter chain of orders 2 to 8, and relies on a synchronization selector to achieve real-time synchronization matching of the orders of the integrator link and the comb filter link, completely breaking the performance limitations of the traditional fixed-order filter architecture. Compared with the two-way defects of fixed low-order filters (insufficient stopband attenuation and severe high-frequency noise leakage at small decimation rates) and fixed high-order filters (excessive gain and easy data overflow distortion at large decimation rates), this circuit can flexibly switch the filter order according to the actual sampling conditions, adapting to all decimation rate working scenarios, and significantly improving the filtering accuracy and adaptability of the cascaded integrator-comb filter. This application also achieves optimal parameter tuning adaptively under operating conditions by using a parameter mapping lookup table built into the control module and a unique hardware matching mechanism for the inverse mapping of decimation factor and filter order. In scenarios with low decimation factor and high sampling rate, the system automatically matches a high-order filter structure, effectively improving stopband attenuation capability, suppressing high-frequency noise interference, and ensuring the accuracy of weak signal acquisition. In scenarios with high decimation factor and low sampling rate, the system automatically matches a low-order filter structure, reducing the overall filter gain from the hardware level and avoiding signal overflow and saturation distortion problems caused by the inherent exponential gain characteristics of CIC filters. This solves the technical contradiction that traditional fixed-order filters cannot handle both high and low gain conditions. This application abandons the industry-standard multiplier gain compensation scheme and uses a pure shift register to build a gain equalization module, completing full-condition gain calibration through binary left and right shift operations. Compared to traditional multiplier compensation methods, this method completely eliminates the problems of large logic resource consumption, high chip area overhead, long operation delay, and high power consumption caused by multipliers. It achieves gain balancing across multiple sampling rate levels with a minimalist hardware structure, effectively offsetting gain exponential fluctuations caused by changes in the decimation factor. It avoids problems such as signal amplitude jumps, waveform distortion, and signal-to-noise ratio fluctuations when switching between multiple sampling rates. While reducing hardware costs and power consumption, it significantly improves the overall stability and real-time performance of the output signal of the Σ-Δ analog-to-digital converter.

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of a variable-order CIC filter hardware circuit adapted to multiple sampling rates is provided for this application; Figure 2 A schematic diagram of the amplitude-frequency response simulation results provided in this application; Figure 3 This is another schematic diagram of the amplitude-frequency response simulation results provided in this application; Figure 4A schematic diagram of the simulation results of the next amplitude-frequency response provided in this application; Figure 5 A schematic diagram of the simulation results of the latter amplitude-frequency response provided in this application; Figure 6 Another schematic diagram of amplitude-frequency response simulation results provided in this application; Figure 7 A schematic diagram of the simulation results of the last amplitude-frequency response provided in this application; Figure 8 This is a structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0011] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0012] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0013] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0014] In this application's embodiments, "multiple" refers to two or more. In this application's embodiments, "connection" refers to various connection methods, such as direct or indirect connections, to achieve communication between devices; this application's embodiments do not impose any limitations on this.

[0015] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0016] The following describes the relevant content, concepts, meanings, technical issues, technical solutions, and beneficial effects involved in the embodiments of this application.

[0017] See Figure 1 , Figure 1 This application provides a schematic diagram of a variable-order CIC filter hardware circuit that adapts to multiple sampling rates and is applied to the decimation filtering system of a Σ-Δ analog-to-digital converter. The circuit includes: a control module 101, an integrator module 102, a synchronization selector, a decimator module 104, a comb filter module, and a gain equalization module 106. The integrator module 102 is a 2-8 stage cascaded integrator chain, with the output of each stage integrator being independently brought out, supporting dynamic configuration of the 2-8th order of operation. The comb filter module is configured as a 2-8 stage comb filter chain corresponding one-to-one with the integrator module 102. The operating order of the comb filter module switches synchronously in real time with the integrator module. The comb filter module includes: integrator 1051 and differential 1052. The synchronization selector includes an integral selector 1031 and a differential selector 1032. The integral selector and the differential selector synchronously select the second to eighth order output signals of the integrator module 102 and the comb filter module, respectively, so that the effective operating order of the integral link and the comb filter link are strictly kept consistent. The decimator module 104 performs R-fold downsampling on the high-speed data stream output by the integrator module 102. The decimator module 104 can be selected in different forms, such as an decimator module or an interpolator module, depending on the different technical application scenarios.

[0018] The control module 101 has a built-in parameter mapping lookup table, which is used to match the corresponding decimation factor R, target filter order N and reference shift bit parameters according to the current input target sampling rate; the control module is configured with a reverse mapping rule: the larger the decimation factor R, the smaller the matched target filter order N, and the smaller the decimation factor R, the larger the matched target filter order N. The gain equalization module 106 is distributed at the output of each differential path, and each differential branch is independently configured with a shift unit to achieve full-range gain calibration through binary left shift or right shift operations.

[0019] The variable-order cascaded integrator comb filter hardware circuit defined in this application addresses the industry pain points of existing fixed-order filters, such as their inability to adapt to multi-sampling-rate conditions, gain exponent imbalance caused by decimation rate changes, and high resource consumption of traditional gain compensation. Through overall hardware architecture optimization and adaptive matching mechanism, the following core technical effects are achieved: The controller of this application receives an external decimation factor command and outputs an order control signal N (2~8), a decimation factor R (4~256), and shift control parameters n1~n7. After the input signal passes through cascaded integrators 1~8, the integrator selector selects the corresponding order integration signal according to N. The selected signal is sent to the decimator to complete R-rate downsampling. The decimated output is sent to cascaded differentials 1~8, and the differential outputs of each stage are respectively compensated for gain by shift units. The differential selector synchronously selects the corresponding branch signal after shift compensation according to the order N and outputs it. The controller has a built-in lookup table to match the target order and the reference shift parameters according to the decimation factor, and corrects the shift control parameters in combination with the output bit width. This application uses a 2~8 order dynamically configurable integrator chain and comb filter chain, and relies on a synchronization selector to achieve real-time synchronous matching of the order of the integrator link and the comb filter link, completely breaking the performance limitations of the traditional fixed order filter architecture. Compared to the shortcomings of fixed low-order filters, such as insufficient stopband attenuation and severe high-frequency noise leakage at small decimation rates, and fixed high-order filters, such as excessive gain and data overflow distortion at large decimation rates, this circuit can flexibly switch the filter order according to the actual sampling conditions, adapting to all decimation rate scenarios and significantly improving the filtering accuracy and adaptability of the cascaded integrator-comb filter. This application also features a unique hardware matching mechanism that uses a built-in parameter mapping lookup table in the control module to achieve adaptive optimal parameter tuning under various operating conditions. In scenarios with low decimation factor and high sampling rate, the system automatically matches a high-order filter structure, effectively improving stopband attenuation capability, suppressing high-frequency noise interference, and ensuring the accuracy of weak signal acquisition. In scenarios with high decimation factor and low sampling rate, the system automatically matches a low-order filter structure, reducing the overall filter gain from the hardware level and avoiding signal overflow and saturation distortion problems caused by the inherent exponential gain characteristics of CIC filters. This solves the technical contradiction that traditional fixed-order filters cannot handle both high and low gain conditions. This application abandons the industry-standard multiplier gain compensation scheme and uses a pure shift register to build a gain equalization module, completing full-condition gain calibration through binary left and right shift operations. Compared to traditional multiplier compensation methods, this method completely eliminates the problems of large logic resource consumption, high chip area overhead, long operation delay, and high power consumption caused by multipliers. It achieves gain balancing across multiple sampling rate levels with a minimalist hardware structure, effectively offsetting gain exponential fluctuations caused by changes in the decimation factor. It avoids problems such as signal amplitude jumps, waveform distortion, and signal-to-noise ratio fluctuations when switching between multiple sampling rates. While reducing hardware costs and power consumption, it significantly improves the overall stability and real-time performance of the output signal of the Σ-Δ analog-to-digital converter.

[0020] Optionally, the above-mentioned synchronization selector synchronizes the output of the latch integrator with the output of the comb filter each time the filter order is switched, ensuring that the data stream is synchronized and aligned at the moment of order switching.

[0021] The above technical solution further restricts the hardware working mechanism of the synchronization selector. On the basis of dynamically switching the filter order in the variable order filter architecture, an order switching synchronization latch mechanism is added, which effectively makes up for the hardware timing defects of the variable order cascaded integrator comb filter in the process of dynamic order adjustment.

[0022] Existing variable-order filter architectures are prone to signal update timing discrepancies between the integrator link and the comb filter link when switching filter orders in real time. This can easily lead to data stream misalignment between the preceding and following stages and temporary order matching failures at the moment of switching, thereby introducing instantaneous noise, pulse spikes, and signal jump noise, disrupting the continuity and stability of the filtered output signal, and in severe cases, causing instantaneous sampling data distortion in the Σ-Δ analog-to-digital converter. This application addresses this issue by using a synchronization selector to synchronously latch the output signals of the integrator module and the comb filter module at each filter order switching moment, ensuring complete timing alignment between the preceding and following stages. This guarantees that the operating orders of the integrator link and the comb filter link are always strictly matched and data is updated synchronously during dynamic order switching. This hardware synchronous latching mechanism completely avoids the data misalignment and timing disorder problems caused by dynamic order adjustment, eliminates instantaneous noise and signal jitter generated at the moment of order switching, and makes the multi-sampling rate and variable-order adaptive adjustment process smoother and more stable. It further improves the integrity and reliability of the filter output signal under all operating conditions, ensuring the continuous high-precision and stable operation of the analog-to-digital converter system.

[0023] Optionally, the decimation factor R of the control module takes values ​​in the range of [4, 256]. As R increases from small to large, the filtering order decreases from 8th to 3rd, achieving optimal order matching across the entire sampling rate range, where R is a multiple of 4.

[0024] The above technical solution specifically defines the range of decimation factor values ​​and the adaptive adjustment rule of the order for the control module. Based on the variable-order filtering architecture and inverse mapping mechanism of claim 1, it clarifies the effective working range of the system and the boundary of the order linkage adjustment, making the adaptive matching logic more rigorous and controllable, and effectively solving the technical problems of inconsistent filtering performance and lack of parameter matching standards in wide sampling rate switching scenarios. This solution limits the working range of the decimation factor R to [4, 256], covering the common high, medium, and low sampling rate application scenarios of Σ-Δ analog-to-digital converters. At the same time, it sets a gradient matching rule that the filtering working order decreases from 8th order to 3th order as the decimation factor increases from small to large. Under small decimation factor conditions, the system automatically configures the highest-order 8th-order filter, greatly improving the stopband attenuation depth and effectively suppressing high-frequency quantization noise and out-of-band spurious signals at high sampling rates, ensuring the signal-to-noise ratio and sampling accuracy of weak analog signal acquisition. Under large decimation factor conditions, the system progressively reduces the filter order to 3rd order, suppressing the inherent exponential gain of the cascaded integrator-comb filter from a hardware structure perspective, avoiding data overflow, truncation distortion, and signal saturation problems caused by excessively high gain at large decimation rates. Through interval closure and gradient-level linkage mapping constraints, this scheme achieves precise optimal matching of filter order, decimation rate, and gain level across all sampling rate ranges, completely solving the shortcomings of traditional fixed-order filters that are only optimal under a single operating condition and have poor adaptability to all scenarios. This allows the filter circuit to maintain excellent noise reduction performance and stable output dynamic range during dynamic switching of a wide range of sampling rates, significantly improving the chip's multi-scenario adaptability and operational robustness.

[0025] See Figure 2 , Figure 2 A schematic diagram of the amplitude-frequency response simulation results provided in this application, wherein Figure 2In this scheme, N=8, R=4, and fs=1536kHz. Specifically, R=4 represents a small decimation factor at the lower limit of the interval, corresponding to a high sampling rate and low scalar operation within the defined working interval R∈[4,256]. The reverse mapping rule of the above scheme is: the smaller R is, the higher the configuration order N is; therefore, this operation automatically matches the maximum 8th order filter architecture. With a fixed low-order filter at a low scalar of R=4, the stopband roll-off is slow, the out-of-band attenuation is shallow, high-frequency quantization noise leakage is severe, the high-frequency shaping noise of the Σ-Δ modulator cannot be effectively filtered out, and the signal-to-noise ratio deteriorates significantly. This scheme, based on the weight 4 adaptive rule, forces a high-order N=8 with a small R, resulting in the following amplitude-frequency characteristics: a flat passband, an extremely fast stopband roll-off, and a significantly improved out-of-band attenuation depth. It can completely filter out high-frequency quantization spurious signals at a high sampling rate of 1536kHz, significantly improving the accuracy of weak signal acquisition. R=4 (minimum decimation factor) → Matches the maximum order of 8, corresponding to high sampling rate scenarios, prioritizing the maximization of noise reduction performance; this fully confirms the inverse adaptive logic defined in claim 4: the smaller the decimation factor, the larger the filter order, which differs from the deficiency of conventional fixed-order CIC in that it cannot specifically enhance the noise reduction capability at low sampling rates. As can be seen from the amplitude-frequency curve, the 8th-order architecture has no high-frequency noise rise at high sampling rates and extremely low passband ripple, proving that the above interval boundary configuration and order gradient matching rule can maintain optimal filtering performance under the minimum sampling rate limit conditions across the entire interval, filling the shortcoming of traditional fixed-order filters at low sampling rates.

[0026] See Figure 3 , Figure 3 This is another schematic diagram of the amplitude-frequency response simulation results provided in this application, wherein... Figure 3In the given parameters N=7, R=8, and fs=768kHz, the gradient adaptive matching effect can be further determined by combining the amplitude-frequency response simulation conditions (N=7, R=8, fs=768kHz). This condition belongs to a typical application scenario with medium decimation and medium sampling rates. According to the inverse gradient mapping rule defined in claim 4, compared with the extreme low-rate condition of R=4, the decimation factor R increases, and the system adaptively downgrades to match the 7th order filter. This parameter configuration perfectly fits the core control logic of increasing the decimation factor and gradually decreasing the filter order within the R∈[4,256] interval. From the amplitude-frequency response characteristics, it can be seen that the 7th order filter architecture, while ensuring a flat passband gain and no signal distortion, has moderate and sufficient stopband attenuation capability, which can effectively filter out quantization noise under this medium-high sampling rate. At the same time, compared with the 8th order high-order architecture, it effectively reduces the overall inherent gain of the cascaded integrator comb filter, avoiding the waste of dynamic range and potential overflow risk caused by excessive gain redundancy under medium-rate conditions. The simulation results verify the gradient adaptation advantage of the step-by-step order adjustment of the technical solution, proving that this application not only optimizes performance under extreme conditions, but also achieves a dynamic balance between noise reduction performance and gain stability under normal conditions in the entire middle range. It takes into account both the filtering and noise reduction requirements and the data output stability, and solves the adaptation defects of traditional fixed-order filters in the middle range, which are either insufficient attenuation or excessive gain. It further demonstrates the technical superiority of the inverse gradient mapping mechanism in adapting to all scenarios.

[0027] See Figure 4 , Figure 4 This is a schematic diagram of the simulation results of the next amplitude-frequency response provided in this application, wherein... Figure 4In this simulation, N=6, R=16, and fs=384kHz. The gradient adaptive control advantage of the technical solution is continuously verified under the amplitude-frequency response simulation condition (N=6, R=16, fs=384kHz). This condition falls under a medium-to-high decimation rate and medium-to-low sampling rate application scenario. Compared to the R=8 condition, the decimation factor is further increased. According to the technical solution's reverse mapping rule, the system adaptively matches a 6th-order filter, strictly adhering to the gradient adaptation logic of "increasing decimation factor and decreasing filter order step by step." From the amplitude-frequency characteristics, it can be seen that as the decimation factor continues to increase, appropriately reducing the filter order not only retains the stopband attenuation capability required for the operating condition and effectively filters out residual quantization noise at a 384kHz sampling rate, ensuring a smooth and distortion-free passband signal, but also further suppresses the exponential gain surge problem caused by the large decimation factor in the cascaded integrator-comb filter. Compared to high-order fixed architectures, this adaptive order reduction method reduces the overall gain redundancy of the filter at the hardware level, completely avoiding data overflow and signal saturation distortion problems that are prone to occur under medium-to-high sampling rate conditions. It also reduces circuit cascading overhead and improves system operating efficiency. Simulation results under this condition fully verify the precise adaptability of the gradient order adjustment technique, proving that this invention can dynamically balance filtering and noise reduction performance with gain stability according to the sampling rate level, continuously addressing the technical pain points of traditional fixed-order filters being unable to adapt to multiple sampling rates and exhibiting performance trade-offs.

[0028] See Figure 5 , Figure 5 This is a schematic diagram of the simulation results of the latter amplitude-frequency response provided in this application, wherein... Figure 5In the given conditions, N=5, R=32, and fs=192kHz. Combined with the amplitude-frequency response simulation (N=5, R=32, fs=192kHz), the gradient adaptive control logic and technical advantages of the solution can be further verified: This condition pertains to a high decimation factor and low sampling rate application scenario. Compared to the R=16 condition, the decimation factor is further increased. Based on the inverse gradient mapping rule defined by the technical solution, the system adaptively matches a 5th-order filter, continuously adhering to the core adaptation rule of "increasing decimation factor and decreasing filter order step by step." Under this condition, the sampling rate is significantly reduced, and the high-frequency quantization noise at the output of the Σ-Δ analog-to-digital converter is significantly reduced, eliminating the need for high-order filtering to meet noise reduction requirements, thus greatly improving adaptability. The amplitude-frequency response results show that the 5th-order filter architecture still possesses adequate stopband attenuation capability, effectively filtering out out-of-band residual noise and ensuring a pure, distortion-free passband signal. Simultaneously, compared to 6th-order and higher-order architectures, it further reduces the inherent exponential gain of the cascaded integrator-comb filter, fundamentally avoiding the computational overflow and signal saturation distortion problems caused by excessive gain accumulation at high decimation rates. Furthermore, appropriately reducing the filter order simplifies the cascaded circuit logic, reduces hardware resource overhead and computational latency, and improves the overall efficiency of the filter. The simulation results further refine the full-range adaptability verification, fully demonstrating that the gradient back-mapping mechanism of the technical solution can accurately match the optimal filter order according to different decimation rates, balancing signal filtering quality, output gain stability, and hardware operating efficiency in high-decimation, low-sampling scenarios, completely resolving the technical defects of traditional fixed-order filters in high-decimation conditions, such as excessive gain and resource waste.

[0029] See Figure 6 , Figure 6 Another schematic diagram of amplitude-frequency response simulation results provided in this application, wherein Figure 6In the given conditions, N=5, R=32, and fs=192kHz; combined with the amplitude-frequency response simulation condition (N=4, R=64, fs=96kHz), the extreme gradient adaptation performance of the technical solution can be further verified: this condition belongs to an application scenario with ultra-high decimation factor and low sampling rate. Compared with the condition of R=32, the decimation factor is doubled. According to the reverse gradient mapping rule of the technical solution, the system adaptively matches the 4th order filter, strictly continuing the adaptive control logic of "the higher the decimation factor, the lower the filter order". Under this condition, the system sampling rate is further reduced, and the high-frequency quantization noise of the Σ-Δ analog-to-digital converter is mainly concentrated in the ultra-high frequency band. The noise energy is significantly reduced, and the low-order filter structure can fully meet the system filtering requirements. The amplitude-frequency response characteristics show that the 4th-order filter architecture can achieve effective stopband attenuation, completely filtering out residual quantization noise outside the operating bandwidth, ensuring a smooth passband signal without clutter interference. Simultaneously, compared to 5th-order and higher architectures, it further suppresses the exponential gain superposition effect caused by high-rate decimation in cascaded integrator-comb filters, minimizing the filter's inherent gain and completely avoiding problems such as data bit width overflow, signal saturation, and waveform clipping distortion that easily occur under ultra-high decimation rates. Furthermore, the lower filter order further simplifies the multi-stage integration and comb operation chain, significantly reducing hardware logic resources and lowering chip dynamic power consumption and computational latency. This test fully verifies the adaptability advantages of the technical solution under ultra-high decimation conditions, proving that the inverse gradient mapping mechanism of this invention can accurately adapt to ultra-high decimation rates and low sampling rate operating scenarios. While ensuring filter performance meets standards, it optimally balances gain stability and hardware resource overhead, solving the inherent technical defects of traditional fixed high-order filters in high-rate scenarios, such as severe gain overkill, resource redundancy waste, and excessive power consumption.

[0030] See Figure 7 , Figure 7 This is a schematic diagram of the simulation results of the last amplitude-frequency response provided in this application, in which... Figure 7In the given conditions, N=3, R=128, and fs=48kHz; combined with the amplitude-frequency response simulation (N=3, R=128, fs=48kHz), the full-range extreme adaptability of the technical solution can be finally verified: this condition belongs to the extreme application scenario of extremely high decimation rate and low audio standard sampling rate. Compared with the condition of R=64, the decimation factor is further increased. According to the reverse gradient mapping rule of the technical solution, the system adaptively matches the minimum 3rd order basic filter order, strictly following the extreme control logic of "maximum decimation rate and lowest filter order", which perfectly fits the parameter matching constraint of R∈[4,256] in the entire working range. This condition is the mainstream working scenario of conventional audio Σ-Δ analog-to-digital converters, with low sampling rate and extremely low high-frequency quantization noise energy, and no need for high-order filtering to participate in noise reduction. The amplitude-frequency response curves show that the 3rd-order basic filter architecture still possesses the stopband attenuation capability required by the system design, completely filtering out residual out-of-band quantization noise. The passband frequency response is flat and distortion-free, fully ensuring the purity of the low-frequency audio signal acquisition. Simultaneously, this application employs a minimum 3rd-order filter architecture, minimizing the exponential gain accumulation effect of the cascaded integrator-comb filter from a hardware perspective. This completely solves the fatal problems of explosive gain growth, easy data overflow, and audio signal saturation distortion inherent in traditional fixed high-order filters at extremely high decimation rates. Furthermore, the minimum-order filter link maximally simplifies the integration and comb operation units, significantly reducing chip logic resource consumption, dynamic operation power consumption, and signal delay, achieving lightweight and efficient filtering in low-sampling-rate scenarios. The complete closed-loop verification under extreme conditions demonstrates the core innovative advantages of the technical solution, proving that the present invention, through a piecewise gradient inverse mapping mechanism, can dynamically match the optimal order parameters across all sampling rate ranges, perfectly achieving a bidirectional optimal balance between high-order noise reduction at low magnification, low-order anti-overflow at high magnification, and resource saving, thus completely overcoming the industry technical bottleneck that traditional fixed-order filters cannot simultaneously handle high and low magnification conditions.

[0031] Optionally, the synchronization selector has built-in synchronization latch timing logic. At the instant when the control module switches the target filter order, it synchronously latches the multi-level output data of the current integrator module and the multi-level output data of the comb filter module, and synchronously releases the output after the order switching is completed, so that the order switching actions of the integration link and the comb filter link are completely time-aligned.

[0032] The above technical solution, based on the variable-order filter hardware architecture, further defines the hardware synchronous latch timing logic of the synchronous selector, specifically addressing the technical problems of timing asynchrony and data mismatch in variable-order chained integrator-comb filters during dynamic order switching. Traditional variable-order filter architectures suffer from timing deviations in signal updates and path selection between the integrator link and the comb filter link during dynamic order switching. This asynchronous order switching between the two links easily leads to misalignment of data streams between stages and temporary mismatch of effective orders during order switching, resulting in instantaneous pulse spikes, noise clutter, and signal jumps. This leads to transient signal distortion and data jitter, severely affecting the continuity and stability of the sampled signal of the Σ-Δ analog-to-digital converter (ADC), failing to meet the requirements of high-precision signal acquisition. This technical solution addresses this by adding hardware synchronous latching timing logic to the synchronous selector. At the instant of each dynamic switching of the filter order, it synchronously latches the multi-stage output data of the integrator module and the comb filter module. The output data is then synchronously released after the order switching configuration is complete. This ensures that the order switching timing and data update times of the integrator link and the comb filter link are completely aligned, guaranteeing that the effective operating order of the two filter links remains strictly consistent and the data stream is synchronously matched throughout the order adjustment process. This hardware latching synchronization mechanism completely eliminates problems such as timing disorder, data misalignment, and transient noise caused by dynamic order adjustment. It achieves disturbance-free, jump-free, and distortion-free signal output during multi-sampling rate switching and dynamic adjustment of the filter order, significantly improving the stability and robustness of the variable-order filtering system and ensuring high-precision, high-fidelity signal acquisition performance of the Σ-Δ ADC under all operating conditions.

[0033] Optionally, the gain equalization module is entirely composed of a pure shift register hardware array. For the inherent exponential gain deviations corresponding to different decimation factors R and different dynamic filter orders N, the corresponding fixed shift number is matched by looking up a table, and the full-domain gain calibration is completed by pure binary left and right shift operations.

[0034] The aforementioned technical solution further substantially limits the hardware implementation and gain calibration mechanism of the gain equalization module, completely overcoming many technical defects caused by relying on multipliers for gain compensation in multi-sampling rate switching scenarios of traditional cascaded integrator-comb filters, achieving outstanding technical results. Existing technologies generally use external hardware multipliers to perform gain correction compensation for the exponential gain imbalance caused by changes in decimation factor and filter order. However, multiplier circuits are complex and consume a large number of logic gate resources, which not only increases chip hardware area and cost but also introduces significant computational delay and static power consumption, hindering the low-power, small-size, and high-real-time chip design requirements of Σ-Δ analog-to-digital converters. Furthermore, multiplier compensation operations have fixed quantization errors, resulting in poor gain calibration consistency during multi-sampling rate switching, easily causing output signal gain deviation and signal-to-noise ratio fluctuations. This technical solution utilizes a shift register hardware array to construct the gain equalization module, abandoning the traditional gain compensation architecture that relies on multipliers and adders. Instead, it uses a pre-established parameter lookup table to precisely match the corresponding number of shift bits for the inherent exponential gain deviations corresponding to different decimation factors R and different dynamic filtering orders N. Full-domain gain calibration is achieved through pure binary left and right shift operations. The shift operation hardware structure is extremely simple, with a single operational logic and no need for complex arithmetic units, significantly reducing chip logic resource consumption, circuit power consumption, and signal transmission delay, effectively reducing chip hardware overhead. Simultaneously, the lookup table-based shift gain calibration method offers fast response speed and stable calibration accuracy. It can provide full coverage and error-free compensation for exponential gain fluctuations under different sampling rates and filtering orders, achieving full-range output gain flattening. This completely solves the problems of gain jumps, waveform distortion, and unstable signal-to-noise ratio during dynamic switching of multiple sampling rates. While significantly optimizing chip hardware performance and power consumption, it greatly improves the signal output accuracy and stability of adaptive filtering in multiple scenarios.

[0035] The aforementioned gain equalization module uses a 20-bit output width as the baseline hardware level. It incorporates a dual-layer hardware quantization shift rule of baseline shift + width compensation shift, and is deeply linked with the RN dynamic tradeoff mode. The system pre-stores the baseline shift bits n1~n7 corresponding to each decimation factor R and each filter order N. Then, it automatically calculates the width compensation shift amount based on the actual configured output width, and finally obtains the total number of shift bits through hardware logic to complete gain calibration. The global hardware quantization compensation rule is as follows: when the output width is greater than 20 bits, the additional left shift bits are equal to the difference between the actual output width and 20 bits; when the output width is less than 20 bits, the additional right shift bits are equal to the difference between 20 bits and the actual output width; the total number of shift bits is equal to the baseline shift bits plus the width compensation shift bits.

[0036] Specifically, 20-bit is used as the base level: Output bit width > 20 bits: Additional left shift = actual bit width - 20; Output bit width < 20 bits: Extra right shift = 20 - actual bit width; Total number of shift bits = base shift + bit width compensation shift.

[0037] For example: R=4, N=8, shift the reference left by 3 bits; 24-bit output: Total left shift = 3 + 4 = 7 bits; 16-bit output: Total shift = 3 - 4 = right shift by 1 bit; R=256, N=2, left shift the reference by 3 bits; 24-bit output: Total left shift of 7 bits.

[0038] Optionally, the integrator module adopts a multi-stage cascaded accumulation hardware structure, relying on register timing registers and adders to achieve high-speed integration operations through stage-by-stage accumulation; the comb filter module adopts a register delay link combined with a subtraction operation structure to achieve differential comb filtering function; the decimator module adopts a counter periodic gating hardware structure, and completes accurate downsampling decimation through R counting period matching; the synchronization selector is entirely composed of a multiplexer (MUX) hardware array to achieve multi-order path synchronous gating and timing matching; the gain equalization module is composed of a shift register array, and achieves global gain calibration through pure hardware left and right shift operations; the control module adopts a combinational logic lookup table architecture with registers pre-stored initial parameters.

[0039] The above technical solution provides a complete and systematic definition of the underlying hardware implementation architecture of the entire filter circuit. It abandons the conventional implementation methods commonly used in traditional CIC filters, such as multiplier compensation, floating-point operations, and software configuration parameter tuning. Instead, it constructs a minimalist pure hardware operation system consisting of only three basic hardware components: adders, registers, and multiplexers. This solution addresses the technical shortcomings of traditional variable-order CIC filters, such as high resource overhead, long operation delay, high power consumption, unstable timing, and reliance on algorithm intervention, from the root of the hardware architecture. It is deeply adapted to and mutually empowers the core adaptive trade-off mechanism of this application, which is "high-order reinforcement and noise reduction at low-order magnification and overflow suppression at high-order magnification".

[0040] Specifically, this application brings significant technical benefits to the dedicated hardware structure limitations of each core module: the integrator module adopts a multi-stage cascaded accumulation structure with registers and adders, which has regular hardware timing and strong real-time accumulation operation, and can stably support high-speed parallel operation of dynamic integration links from 2nd to 8th order, ensuring the integrity and continuity of high-order filtering under high sampling rate conditions; the comb filter module adopts a register delay link combined with a subtraction operation structure, which is extremely simple in structure and has no redundant operation, and can accurately match the differential filtering requirements after dynamic order change, ensuring constant differential filtering accuracy under different order configurations; the decimator module is based on a counter periodic gating hardware structure. It achieves precise downsampling at the R-fold, with fixed hardware triggering logic and no computational errors, adaptable to the dynamic switching requirements of the full range of extraction factors; the synchronization selector relies on a multi-channel selector hardware array to achieve synchronous selection of multi-order paths, with extremely low hardware switching latency, perfectly matching dynamic order synchronization and timing latching mechanisms; the gain equalization module relies on a shift register array to achieve pure hardware shift gain calibration, completely avoiding the resource and power consumption problems caused by the complex operations of multipliers; the control module adopts a combinational logic lookup table architecture with pre-stored parameters in registers, outputting matching parameters in real time in pure hardware, without the need for software algorithm iterative calculations, resulting in fast parameter response and high operational stability.

[0041] Compared to existing variable-order CIC schemes that mostly rely on multipliers for gain compensation and algorithms to configure order parameters, this application eliminates multipliers, complex arithmetic units, and software logic, significantly reducing chip logic gate resource usage, shrinking chip hardware area, lowering dynamic operating power consumption and signal transmission delay, and significantly improving the hardware integration and real-time performance of the filter circuit. Simultaneously, the unified, purely hardware-based minimalist architecture is highly adaptable to dynamic trade-offs and control logic across all operating conditions. Under low-decimation-rate, high-order noise reduction conditions, it stably supports high-precision noise reduction operations, maximizing the system's signal-to-noise ratio. Under high-decimation-rate, low-order operating conditions, the minimalist hardware structure suppresses gain accumulation and eliminates data overflow distortion. While ensuring filtering performance and signal stability across all operating conditions, it achieves a multi-dimensional optimal balance between hardware resources, power consumption, and real-time performance, significantly improving the hardware feasibility, operating condition robustness, and chip adaptability of the variable-order, multi-sampling-rate filter circuit.

[0042] This application provides an audio chip, which includes the aforementioned variable-step CIC filter hardware circuit adapted to multiple sampling rates.

[0043] Figure 8 This is a structural block diagram of an electronic device provided in an embodiment of this application. For example... Figure 8As shown, the electronic device 800 may include one or more of the following components: a processor 801, a memory 802 coupled to the processor 801, wherein the memory 802 may store one or more computer programs, which may be configured to implement the methods described in the examples above when executed by one or more processors 801. The electronic device may also include an audio chip 803, which may also be integrated within the processor 801. Figure 8 The electronic device 800 shown can be a Bluetooth speaker, headphones, TWS earphones, smart TV, projector, gaming audio device, children's story machine, etc.

[0044] Processor 801 may include one or more processing cores. Processor 801 connects to various parts within the electronic device 800 using various interfaces and lines, and performs various functions and processes data of the electronic device 800 by running or executing instructions, programs, code sets, or instruction sets stored in memory 802, and by calling data stored in memory 802. Optionally, processor 801 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). Processor 801 may integrate one or more of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. It is understood that the aforementioned modem may also not be integrated into processor 801, but may be implemented separately through a communication chip.

[0045] The memory 802 may include random access memory (RAM) or read-only memory (ROM). The memory 802 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 802 may include a program storage area and a data storage area. The program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as touch functionality, sound playback functionality, image playback functionality, etc.), and instructions for implementing the various method examples described above. The data storage area may also store data created by the electronic device 800 during use.

[0046] It is understood that the electronic device 800 may include more or fewer structural elements than those shown in the above block diagram, such as a power module, physical buttons, WiFi (Wireless Fidelity) module, speaker, Bluetooth module, sensor, etc., without limitation.

[0047] This application also provides a computer storage medium storing a computer program / instructions thereon, which, when executed by a processor, implements some or all of the steps of any of the methods described in the above method embodiments.

[0048] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods described in the above method embodiments.

[0049] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0050] In the several embodiments provided in this application, it should be understood that the disclosed methods, apparatuses, and systems can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and there may be other division methods in actual implementation; for example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0051] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0052] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can be physically included separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0053] While this application discloses the above information, it is not limited thereto. Any person skilled in the art can easily conceive of variations or substitutions without departing from the spirit and scope of this application, and can make various alterations and modifications, including combinations of the different functions and implementation steps described above, as well as software and hardware implementation methods, all of which are within the protection scope of this application.

Claims

1. A variable-order CIC filter hardware circuit adaptable to multiple sampling rates, applied to the decimation filtering system of a Σ-Δ analog-to-digital converter, characterized in that, The hardware circuit includes: a control module, an integrator module, a synchronization selector, a decimator module, a comb filter module, and a gain equalization module. The integrator module is a 2-8 stage cascaded integrator chain, with the output of each stage integrator being independently brought out, supporting dynamic configuration of the 2-8th order of operation. The comb filter module is configured as a 2-8 stage comb filter chain corresponding one-to-one with the integrator module, and the operating order of the comb filter module switches synchronously in real time with the integrator module. The synchronization selector includes an integral selector and a differential selector. The integral selector and the differential selector synchronously select the second to eighth order output signals of the integrator module and the comb filter module, respectively, so that the effective operating order of the integral link and the comb filter link are strictly kept consistent. The extractor module is used to perform R-fold downsampling extraction on the high-speed data stream output by the integrator module. The control module has a built-in parameter mapping lookup table, which is used to match the corresponding decimation factor R, target filter order N, and reference shift bit parameters according to the current input target sampling rate. The control module is configured with a reverse mapping rule: the larger the decimation factor R, the smaller the matched target filter order N, and the smaller the decimation factor R, the larger the matched target filter order N. The gain equalization module is distributed at the output of each differential path, and each differential branch is independently configured with a shift unit. Gain calibration is achieved throughout the process through binary left or right shift operations.

2. The variable-order CIC filter hardware circuit for adapting to multiple sampling rates provided in claim 1, characterized in that, The synchronous selector synchronizes the output of the latching integrator with the output of the comb filter each time the filter order is switched, ensuring that the data stream is synchronously aligned at the moment of order switching.

3. The variable-order CIC filter hardware circuit for adapting to multiple sampling rates provided in claim 1, characterized in that, The decimation factor R of the control module has a value range of [4, 256]. As R increases from small to large, the filtering order decreases from 8th to 3rd, achieving optimal order matching across the entire sampling rate range, where R is a multiple of 4.

4. The variable-order CIC filter hardware circuit for adapting to multiple sampling rates provided in claim 1, characterized in that, The synchronous selector has built-in synchronous latch timing logic. At the instant when the control module switches the target filter order, it synchronously latches the multi-level output data of the current integrator module and the multi-level output data of the comb filter module, and synchronously releases the output after the order switching is completed, so that the order switching actions of the integral link and the comb filter link are completely time-aligned.

5. A variable-order CIC filter hardware circuit adaptable to multiple sampling rates according to claim 3, characterized in that, The gain equalization module is entirely composed of a pure shift register hardware array. For the inherent exponential gain deviations corresponding to different decimation factors R and different dynamic filter orders N, it matches the corresponding fixed shift number by looking up a table and completes the global gain calibration by pure binary left and right shift operations.

6. The variable-order CIC filter hardware circuit adapted to multiple sampling rates provided in claim 3, characterized in that, If R∈[4,16] and N=6~8, the low-magnification high-order high-precision noise reduction condition will automatically match the 24-bit ultra-high precision output level; If R∈[16,64] and N=4~6, it is compatible with the 20-bit standard output level; If R∈[64,256] and N=3~4, in the case of high-multiplication low-order anti-overflow operation, it will automatically adapt to 16-bit or 20-bit output level.

7. The variable-order CIC filter hardware circuit for adapting to multiple sampling rates provided in claim 1, characterized in that, The integrator module adopts a multi-stage cascaded accumulation hardware structure, relying on register timing registers and adders to achieve high-speed integration operations through stage-by-stage accumulation; the comb filter module adopts a register delay link combined with a subtraction operation structure to realize differential comb filtering function; the decimator module adopts a counter periodic gating hardware structure, and completes accurate downsampling decimation through R counting period matching; the synchronization selector is entirely composed of a multiplexer (MUX) hardware array, realizing multi-order path synchronous gating and timing matching; the gain equalization module is composed of a shift register array, and realizes global gain calibration through pure hardware left and right shift operations; the control module adopts a combinational logic lookup table architecture with registers pre-stored initial parameters.

8. The variable-order CIC filter hardware circuit for adapting to multiple sampling rates according to claim 1, characterized in that, The 2-8 stage comb filter chain specifically includes: 2-8 stage integrators and 2-8 stage differentials.

9. An audio chip, characterized in that, The audio chip includes a variable-step CIC filter hardware circuit adapted to multiple sampling rates as described in any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the audio chip as described in claim 9.

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