Data compression apparatus and electronic device

Abstract

The embodiment of the present application discloses a kind of data compression device and electronic equipment, device includes data acquisition module, first data compression module and second data compression module;Data acquisition module is used to collect the target to be compressed data of DRAM device under test and send to first data compression module;First data compression module is used to compress the first to be compressed data in target to be compressed data and obtain intermediate target compression data, and intermediate target compression data is sent to second data compression module;Second data compression module is used to compress the second to be compressed data in intermediate target compression data and obtain target compression data.The technical scheme of the embodiment of the present application can be on the premise that guaranteeing fault traceability waveform data is complete without loss, the test feedback data of DRAM device under test is compressed in real time, improve data compression efficiency and the adaptability of compression method, and reduce the bandwidth pressure of data transmission and storage capacity overhead.

Description

Technical Field

[0001] This invention relates to the field of semiconductor automated testing technology, and more particularly to a data compression device and an electronic device. Background Technology

[0002] DRAM (Dynamic Random Access Memory) relies on capacitors to store charge representing data bits. Capacitors will continuously leak current and must be refreshed periodically to maintain data. Compared with SRAM (Static Random-Access Memory), DRAM has a large capacity and low cost, but the memory cells are inherently fragile, making it a key target for chip testing.

[0003] The current mainstream DRAM testing process for DRAM is as follows: After the host computer controller issues test commands, the test engine generates JEDEC (Joint Electron Device Engineering Council) standard test patterns (test vectors, binary timing sequences) for DRAM read / write, refresh, and timing stress. Further, the DRAM PHY (Physical Layer) controller outputs high-frequency excitation signals to the DRAM device under test. Simultaneously, the PHY acquires CA (Command / Address) and DQ (Data Queue) signals in real time. After converting the high-frequency serial signal to a low-frequency parallel signal, the complete raw waveform sampling data is uploaded to the backend industrial computer via the PCIE (Peripheral Component Interconnect Express) high-speed bus for fault analysis, eye diagram analysis, and timing margin tracing.

[0004] In the process of developing this invention, the inventors discovered the following shortcomings in the existing technology: DRAM test faults are divided into three categories: hardware defects in the DUT (Device Under Test) chip itself, external electromagnetic interference in the test link, and timing errors in the test pattern. These three types of faults exhibit completely identical symptoms, and the root cause cannot be distinguished solely by the Pass / Fail result returned by the test machine. Furthermore, many latent timing faults are delayed; errors reported at the current moment are often caused by the accumulation of interface timing distortions from hundreds of nanoseconds to several microseconds prior. Therefore, it is essential to continuously and uninterruptedly collect all CA / DQ waveform data of the DRAM DUT, meaning that fault tracing requires the retention of all waveform data for backtracking and analysis. With the iterative development of DDR4 (Double Data Rate Fourth Generation Synchronous Dynamic Random Access Memory) and DDR5 (Double Data Rate 5 Synchronous Dynamic Random Access Memory), DRAM operating speeds have increased to 6400MT / s and above, and the single-channel DQ bit width has increased to 64bit. In multi-channel parallel testing scenarios, the amount of raw sampling data per second has exceeded GB, resulting in an explosive increase in raw data throughput and putting immense pressure on the hardware acquisition end.

[0005] Existing traditional DRAM test machines all use a lossless direct transmission scheme for raw sampled data to achieve undifferentiated full transmission without on-board hardware real-time compression. The massive amount of raw waveform data continuously occupies the high-speed bandwidth of PCIe 4.0 / 5.0 bus, which can easily cause problems such as bus congestion and bandwidth contention between test commands and waveform data transmission, resulting in a slowdown in the overall test cycle. At the same time, the background solid-state drives and array storage require ultra-large capacity hardware support, and the storage cost of a single test log is high, highlighting the bottleneck of storage hardware cost.

[0006] Currently, the common waveform compression algorithms used in DRAM testing are all serial compression algorithms in the background software. These algorithms have high latency and cannot be synchronized with the sampling of FPGA (Field Programmable Gate Array) hardware, making them unsuitable for real-time acquisition scenarios on FPGA hardware. Existing hardware-level compression solutions only support compression of single repetitive data counts. When faced with the unique DRAM testing scenarios of idle DES (Deselect) instructions, continuous identical DQ levels, and intermittent abrupt waveforms, the compression efficiency is polarized: the compression ratio of continuous idle cycles is extremely low, and there is no compression capability for sudden abrupt waveforms, resulting in extremely poor adaptability. Summary of the Invention

[0007] This invention provides a data compression device and an electronic device that can compress test feedback data of DRAM devices under test in real time while ensuring the integrity and no loss of fault tracing waveform data. This reduces the amount of test feedback data of DRAM devices under test, thereby reducing the bandwidth pressure and storage capacity overhead of data transmission.

[0008] According to one aspect of the present invention, a data compression device is provided, the data compression device being integrated into a DRAM test chip, the data compression device comprising a data acquisition module, a first data compression module, and a second data compression module; wherein:

[0009] The data acquisition module is communicatively connected to the first data compression module. The data acquisition module is used to acquire the target data to be compressed from the DRAM device under test and send the target data to be compressed to the first data compression module. The target data to be compressed includes the test feedback data of the DRAM device under test.

[0010] The first data compression module and the second data compression module are communicatively connected. The first data compression module is used to compress the first data to be compressed in the target data to be compressed to obtain intermediate target compressed data, and send the intermediate target compressed data to the second data compression module. The first data to be compressed includes waveform data with the same data content within a preset continuous sampling period in the target data to be compressed.

[0011] The second data compression module is used to compress the second data to be compressed in the intermediate target compressed data to obtain target compressed data; wherein, the second data to be compressed includes waveform data in the intermediate target compressed data whose data content is different between adjacent data groups.

[0012] According to another aspect of the present invention, an electronic device is provided, the electronic device including a DRAM test chip; the DRAM test chip is configured with the data compression device described in the first aspect.

[0013] This invention provides a data compression device integrated into a DRAM test chip. A first data compression module compresses waveform data with identical content within consecutive sampling periods, while a second data compression module compresses waveform data with different content between adjacent data groups. These two stages process waveform data with different statistical characteristics, enabling real-time hardware compression of massive waveform sampling data from the CA / DQ interface in high-speed DRAM testing scenarios. It accommodates both long-period repetitive waveforms and short-period abrupt waveforms, unique to DRAM, and solves the problems of high latency and poor adaptability in existing DRAM test feedback data compression methods. It can perform real-time compression of DRAM test feedback data while ensuring the integrity and losslessness of fault tracing waveform data, improving data compression efficiency and method adaptability, and reducing bandwidth pressure and storage capacity overhead. Furthermore, the data compression device is integrated into the DRAM test chip, allowing test feedback data to undergo two-stage compression processing at the sampling source, eliminating the need for bus transmission to the backend for software processing. This eliminates the latency introduced by cross-bus transmission and software processing, meeting the real-time requirements of high-speed sampling scenarios.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the test framework for a DRAM test chip provided in Embodiment 1 of the present invention;

[0017] Figure 2 This is a schematic diagram of a data compression device provided in Embodiment 1 of the present invention;

[0018] Figure 3 This is a schematic diagram of a data compression device provided in Embodiment 2 of the present invention;

[0019] Figure 4 This is a schematic diagram of the storage structure of a first compressed data buffer provided in Embodiment 2 of the present invention;

[0020] Figure 5 This is a schematic diagram of a data compression device provided in Embodiment 3 of the present invention;

[0021] Figure 6 This is a schematic diagram illustrating the effect of generating compressed index values ​​based on compressed data blocks, provided in Embodiment 3 of the present invention.

[0022] Figure 7 This is a schematic diagram of the structure of a second compressed data buffer provided in Embodiment 3 of the present invention;

[0023] Figure 8 This is a schematic diagram of the structure of an electronic device provided in Embodiment 4 of the present invention. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] Example 1

[0027] Figure 1 This is a schematic diagram of the test framework for a DRAM test chip provided in Embodiment 1 of the present invention. In a specific example, such as... Figure 1As shown, in the DRAM test chip, the CPU (Central Processing Unit) is responsible for overall test management and issuing test patterns. The NOC (Optical Network-on-Chip) network is responsible for communication between various components on the DRAM test chip. The Test Engine is responsible for parsing the test patterns issued by the CPU, generating various test timing sequences such as DRAM read / write and refresh according to JEDEC standards, receiving test feedback from the DRAM Device Under Test (DUT), and checking various test results. The DRAM PHY can output high-frequency excitation signals to the DUT and perform high-to-low frequency signal conversion. The data compression device is responsible for compressing the acquired low-frequency DRAM CA / DQ signals and transmitting them to external devices for processing via the PCIe interface. The AXI2 ABP is responsible for converting between the high-speed interface of the AXI (Advanced eXtensible Interface) protocol and the low-speed interface of the APB (Advanced Peripheral Bus) protocol. AXI_M1 represents the CPU's AXI master interface, AXI_S1 represents the CPU's AXI slave interface, AXI_M2 represents the PCIe AXI master interface, AXI_S2 represents the PCIe AXI slave interface, AXI_S3, AXI_S4, and AXI_S5 represent the NOC's AXI interfaces, APB1 represents the first interface of the AXI2 ABP, APB2 represents the second interface of the AXI2 ABP, and CA / DQ_S2P represents the DRAM PHY circuit that performs serial-to-parallel conversion for the CA and DQ high-speed serial interfaces.

[0028] Figure 2 This is a schematic diagram of a data compression device provided in Embodiment 1 of the present invention. This data compression device can be integrated into a DRAM test chip, which can be a DRAM chip that requires fault testing or functional testing. Figure 2 As shown, the structure of the data compression device may include a data acquisition module 110, a first data compression module 120, and a second data compression module 130; wherein:

[0029] The data acquisition module 110 is communicatively connected to the first data compression module 120. The data acquisition module 110 is used to acquire the target data to be compressed of the DRAM device under test and send the target data to be compressed to the first data compression module 120. The target data to be compressed includes the test feedback data of the DRAM device under test.

[0030] The DRAM device under test (DUT) can be a DUT chip. The target data to be compressed can be the uncompressed raw test feedback data collected from the DRAM DUT. Test feedback data can be understood as all the return response data collected after applying test stimuli (such as test vectors, voltage, timing, and temperature conditions) to the DRAM DUT, used to determine whether the DRAM DUT has failed, locate the failure location, and statistically analyze failure characteristics.

[0031] In this embodiment of the invention, the data acquisition module 110 of the data compression device can provide basic data acquisition functions. It can communicate with the DRAM device under test (DUT) and acquire the test feedback data of the DRAM DUT. Based on the test feedback data of the DRAM DUT, it performs two-stage compression processing on it. The data acquisition module 110 can acquire the full waveform data of the DRAM DUT.

[0032] The first data compression module 120 and the second data compression module 130 are communicatively connected. The first data compression module 120 is used to compress the first data to be compressed in the target data to be compressed to obtain intermediate target compressed data, and send the intermediate target compressed data to the second data compression module 130. The first data to be compressed includes waveform data with the same data content within a preset continuous sampling period in the target data to be compressed.

[0033] The first data compression module 120 performs a first-level compression process on the full waveform data of the DRAM device under test acquired by the data acquisition module 110. The first data to be compressed can be data that can be compressed within the target data to be compressed. The intermediate target compressed data can be the compressed data obtained after the first data compression module 120 performs a first-level compression process on the full waveform data of the DRAM device under test acquired by the data acquisition module 110. Waveform data with the same content within a preset continuous sampling period can be understood as a long-period repetitive idle waveform data in the data stream. It is a feedback waveform data that is sampled and captured after an excitation is applied to the DRAM device under test. This type of feedback waveform data contains sampled data corresponding to multiple long idle periods, which is used to characterize the bus electrical state of the DRAM device under test in a long-term static state. Combined with the readback data after the idle period ends, it helps to identify data retention failure and abnormal bus disturbances during the idle period.

[0034] The second data compression module 130 is used to compress the second data to be compressed in the intermediate target compressed data to obtain the target compressed data; wherein, the second data to be compressed includes waveform data in the intermediate target compressed data whose data content is different between adjacent data groups.

[0035] The second data compression module 130 is used to perform a second-level compression process on the intermediate target compressed data after the first-level compression process of the first data compression module 120. The second data to be compressed can be data that can be compressed within the intermediate target compressed data. The target compressed data can be the compressed data obtained after the second data compression module 130 performs a second-level compression process on the intermediate target compressed data. Data grouping refers to cutting a continuous multi-bit data stream into independent data blocks of a preset fixed length. Waveform data with different data content between adjacent data groups can be understood as a kind of intermittently abrupt waveform data in the data stream. It is another type of device-side feedback waveform data obtained by sampling and capturing after applying excitation to the DRAM device under test. This type of feedback waveform data characterizes the actual level jumps, pulse distortions, and signal response characteristics of the CA / DQ bus of the DRAM device under test under intermittent signal disturbance conditions, and is used to accurately identify timing failures, crosstalk soft failures, and intermittent probabilistic read / write anomalies induced by bus disturbances.

[0036] To address the problems of insufficient transmission bandwidth, high storage costs, large software compression latency, poor adaptability of existing hardware compression schemes, and sampling read / write timing conflicts in existing DRAM ATE (Automatic Test Equipment) or SLT (System-Level Test) testing of massive waveform sampling data, the data compression device of this invention provides a two-level hardware real-time sampling compression architecture, namely a first data compression module and a second data compression module. The first data compression module receives the full waveform data of the DRAM device under test acquired by the data acquisition module, and analyzes and identifies long-duration, continuous, long-period repetitive idle waveform data as the first data to be compressed. It then applies an adapted coarse compression method to this first data to be compressed to obtain intermediate target compressed data. In other words, the first data compression module can perform first-level compression processing on waveform data with identical content within a preset continuous sampling period in the target data to be compressed, thereby reducing recurring waveform data.

[0037] Furthermore, the first data compression module can send the intermediate target compressed data obtained from the compression process to the second data compression module. The second data compression module can analyze and identify short-interval intermittent abrupt change waveform data in the intermediate target compressed data as the second data to be compressed. It then applies an adapted fine-compression method to the second data to be compressed, obtaining the final target compressed data. That is, the second data compression module can perform a second level of compression processing on waveform data in the intermediate target compressed data where the data content differs between adjacent data groups, reducing repetitive data beyond short-interval sudden change waveforms. One intermediate target compressed data point can correspond to one target compressed data point, and multiple target compressed data points can be concatenated to generate complete compressed data. Finally, the generated complete compressed data can be sent to external devices for analysis and processing, such as fault analysis.

[0038] Therefore, the aforementioned data compression device differs from existing single-stage compression methods by employing a two-stage compression approach: "coarse compression + fine compression." The first stage of data compression can adapt to long-duration, continuous, repetitive idle waveforms, while the second stage can adapt to short-interval, bursty waveforms. This perfectly matches the multi-dimensional waveform characteristics of DRAM test instructions, which are characterized by numerous idle periods and few read / write bursts. Compared to traditional single-stage compression methods, this significantly improves the average data compression efficiency. Furthermore, the data compression device processes the entire compression process in parallel hardware, eliminating software latency. This drastically reduces PCIe transmission bandwidth pressure and background storage capacity overhead, while ensuring the integrity and completeness of fault tracing waveform data.

[0039] This invention provides a data compression device integrated into a DRAM test chip. The data compression device comprises a data acquisition module, a first data compression module, and a second data compression module. The data acquisition module is communicatively connected to the first data compression module and is used to acquire test feedback data from the DRAM device under test as target data to be compressed, and send the target data to the first data compression module. The first and second data compression modules are communicatively connected and are used to compress waveform data with identical data content within a preset continuous sampling period from the target data to be compressed, using this as the first data to be compressed, to obtain intermediate target compressed data, and send the intermediate target compressed data to the second data compression module. The second data compression module is used to compress waveform data with different data content between adjacent data groups from the intermediate target compressed data, using this as the second data to be compressed, to obtain the target compressed data. The aforementioned data compression device can perform real-time hardware compression processing of massive waveform sampling data from the CA / DQ interface in high-speed DRAM testing scenarios. It takes into account both long-period repetitive waveforms and short-period abrupt waveforms, two unique DRAM data scenarios. It solves the problems of high latency and poor adaptability of existing DRAM test feedback data compression methods. It can perform real-time compression of DRAM test feedback data while ensuring the integrity and no loss of fault tracing waveform data, thereby improving data compression efficiency and the adaptability of compression methods, and reducing the bandwidth pressure and storage capacity overhead of data transmission.

[0040] Example 2

[0041] Figure 3 This is a schematic diagram of a data compression device provided in Embodiment 2 of the present invention. This embodiment is based on the above embodiment and is further specified, providing various specific optional implementation methods for other functional modules of the data compression device and the internal structure of the first data compression module.

[0042] Correspondingly, such as Figure 3 As shown, based on the data acquisition module 110, the first data compression module 120, and the second data compression module 130, the data compression device may further include a register control module 140. The register control module 140 is communicatively connected to the data acquisition module 110, the first data compression module 120, and the second data compression module 130, and is used to configure the compression enable of the first data compression module 120 and the second data compression module 130, as well as to configure the data acquisition mode of the data acquisition module 110. The data acquisition module 110 is also used to: obtain the data acquisition mode configured by the register control module 140, and filter the full acquisition data of the DRAM device under test according to the data acquisition mode to obtain the target data to be compressed.

[0043] The register control module 140 is a control and configuration unit of the data compression device. It can communicate with the host computer CPU via the APB bus and supports dynamic configuration of the compression enable of the first data compression module 120 and the second data compression module 130. That is, the register control module 140 can be configured to enable only the first data compression module 120 or the second data compression module 130 for single-level data compression processing, or it can be configured to enable both modules simultaneously for two-level data compression processing, or it can be configured to disable both modules simultaneously, i.e., not compressing the full waveform data. The register control module 140 can also dynamically and adaptively configure the data acquisition mode of the data acquisition module 110 according to the current test mode of the DRAM test chip, i.e., configure the sampling CA / DQ selection. For example, the current test mode of the DRAM test chip may include, but is not limited to, chip testing, DIMM (Dual In-Line Memory Module Testing) testing, and single-channel / multi-channel testing. Under the configuration control of the register control module 140, the data acquisition module 110 can select the signals that need to be tested and is of interest, shield redundant CA / DQ channels that do not need to be sampled, and only compress the valid signals to be tested to reduce invalid data entering the compression link and further reduce the front-end processing pressure.

[0044] In addition, the register control module 140 can also be configured to report compression busy flags, cache full flags, and compression ratio statistics of the first data compression module and the second data compression module in real time. The CPU can monitor the compression working status in real time based on the information reported by the register control module 140, thereby adapting to the differentiated configuration of compression parameters in different scenarios.

[0045] In an optional embodiment of the present invention, such as Figure 3 As shown, the first data compression module 120 may include a first data compression unit 121 and a first compressed data buffer 122, wherein: the first data compression unit 121 is communicatively connected to the data acquisition module 110 and is used to compress continuously repeated first data to be compressed in the target data to be compressed into a single intermediate target compressed data, thereby obtaining a first set number of intermediate target compressed data and a repetition count value corresponding to each intermediate target compressed data; wherein each intermediate target compressed data corresponds one-to-one with its corresponding repetition count value; the first compressed data buffer 122 is communicatively connected to the first data compression unit 121 and is used to store each intermediate target compressed data and the repetition count value corresponding to each intermediate target compressed data.

[0046] The first data compression unit 121 can be used to perform a first-level coarse compression process on the target data to be compressed. The first compressed data buffer 122 can be used to store the data after coarse compression by the first data compression unit 121 and the statistical information associated with the compressed data. The first preset number can be configured according to actual needs, such as 32 or 64.

[0047] In this embodiment of the invention, specifically, the first data compression unit 121 within the first data compression module 120 can detect consecutively repeated first data to be compressed in the target data to be compressed, and compress the consecutively repeated first data to be compressed into a corresponding intermediate target compressed data, the data content of each intermediate target compressed data being different. Considering the memory usage limitations of the data compression device, the first data compression module 120 can preset the storage capacity of the compressed data. For example, if it is necessary to compress into 64 different sample data, the first preset number can be set to 64. Accordingly, the first data compression unit 121 can compress all consecutively repeated first data to be compressed in the target data to be compressed into a first preset number of intermediate target compressed data. At the same time, the first data compression unit 121 can also count the repetition count value corresponding to each intermediate target compressed data. Accordingly, each intermediate target compressed data processed by the first data compression unit 121 can be stored in the first compressed data buffer 122, and the first compressed data buffer 122 can store the corresponding repetition count value for each intermediate target compressed data. For continuously distributed, non-repeating data, the first data compression unit 121 may not perform compression processing and may directly store the data in the first compressed data buffer 122.

[0048] In a specific example, assuming the first data compression unit 121 detects that the 1st to 10th data items in the target data to be compressed are consecutively repeated data A, then the 1st to 10th data items can be compressed into a corresponding intermediate target compressed data item, that is, the 1st to 10th data items can be compressed into a single data item A, and data A can be stored in the storage area corresponding to the first compressed data buffer 122, and the repetition count value 10 corresponding to the record data A can be stored in the first compressed data buffer 122; at the same time, if the first data compression unit 121 detects that the 11th to 60th data items in the target data to be compressed are consecutively repeated data B, then the 11th to 60th data items can be compressed into a corresponding intermediate target compressed data item, that is, the 11th to 60th data items can be compressed into a single data item B, and data B can be stored in the storage area corresponding to the first compressed data buffer 122, and the repetition count value 50 corresponding to the record data B can be stored in the first compressed data buffer 122. If the first data compression unit 121 detects that the 61st data item in the target data to be compressed is data C and the 62nd data item is data D, then the 61st data item C and the 62nd data item D can be directly stored in the corresponding storage areas of the first compressed data buffer 122, and the first compressed data buffer 122 stores the repeat count value 1 corresponding to data C and the repeat count value 1 corresponding to data D. This process continues until a first predetermined number of different intermediate target compressed data items are obtained based on the compression processing of the target data to be compressed.

[0049] In an optional embodiment of the present invention, such as Figure 3 As shown, the first data compression unit 121 may include a first set number of first compression counters and a first data compression controller, wherein: the first data compression controller is communicatively connected to each of the first compression counters, and is used to compare the data content of each adjacent data of the target data to be compressed, identify the continuously repeated first data to be compressed, and compress the corresponding intermediate target compressed data according to each continuously repeated first data to be compressed; the first data compression controller is also used to update the count value of the corresponding first compression counter according to the number of repetitions of the first data to be compressed, and obtain the repetition count value corresponding to each intermediate target compressed data.

[0050] The first compression counter can be used to count the repetition counts corresponding to each intermediate target compressed data. The first data compression controller can compare and verify the data content of the target data to be compressed to identify duplicate and non-duplicate data.

[0051] Specifically, the first data compression unit 121 can be configured with a first set quantity (the first set quantity is as follows: ...). Figure 3The system includes a first compression counter (n) and a first data compression controller. During the first-stage coarse compression of the target data to be compressed, the first data compression unit 121 can compare the data content of each adjacent data item of the received target data to be compressed using the first data compression controller. If the data content of two adjacent target data items is the same, they can be identified as consecutively repeating first data items to be compressed; if the data content of two adjacent target data items is different, they can be identified as two different data items. Accordingly, the first data compression controller can identify consecutively repeating first data items to be compressed and compress each consecutively repeating first data item to generate corresponding intermediate target compressed data. Simultaneously, the first data compression controller can also update the count value of the corresponding first compression counter based on the number of repetitions of each type of first data item to be compressed, so as to obtain the repetition count value corresponding to each intermediate target compressed data item through the first compression counter. It is understood that the first compression counter is set with a maximum statistical value; when the repetition count value of the first compression counter exceeds its set maximum statistical value, the next first compression counter can be activated to continue counting.

[0052] In an optional embodiment of the present invention, the first data compression controller may further be configured to: when it is determined that the data content of the current target data to be compressed is the same as that of the previous target data to be compressed, increment the current count value of the current first compression counter corresponding to the current target data to be compressed; when it is determined that the data content of the current target data to be compressed is different from that of the previous target data to be compressed, store the previous target data to be compressed as an intermediate target data and store it in the first compression data buffer, and simultaneously start the next first compression counter to count the number of repetitions of the current target data to be compressed; return to the operation of incrementing the count value of the current first compression counter corresponding to the current target data to be compressed when it is determined that the data content of the current target data to be compressed is the same as that of the previous target data to be compressed, until the first set number of first compression counters has been counted.

[0053] The current target data to be compressed can be determined from the target data to be compressed, and is the target data that currently needs to be compressed. The current first compression counter can be the first compression counter used to count the repetition count value corresponding to the intermediate target data to be compressed.

[0054] Specifically, the first data compression controller can also determine whether the data content of the current target data to be compressed is the same as the data content of the previous target data to be compressed. If it is determined that the data content of the current target data to be compressed is the same as the previous target data to be compressed, it can be determined that the current target data to be compressed and its previous target data to be compressed are consecutively repeated data. Therefore, the current count value of the first compression counter used to count the repetitions of the current target data to be compressed can be incremented by 1. If it is determined that the data content of the current target data to be compressed is different from the previous target data to be compressed, it can be determined that the current target data to be compressed is different from its previous target data to be compressed. In this case, the first data compression controller can treat the previous target data to be compressed as an intermediate target data and store the compressed intermediate target data in the first compression data buffer. At the same time, the current count value of the first compression counter is stored at the corresponding position in the first compression data buffer as the repetition count value of the intermediate target data. Furthermore, the first data compression controller can start the next first compression counter to recount the repetition count of the current target data to be compressed. This process continues until all the first compression counters, representing a predetermined number, have completed their counts. In other words, each first compression counter can count the number of repetitions of each different intermediate target compressed data. The predetermined number of first compression counters can collectively count a predetermined number of intermediate target compressed data.

[0055] In an optional embodiment of the present invention, the first data compression controller may further be used to: when it is determined that the current count value of the current first compression counter has reached the pre-designed value, store the current target data to be compressed as an intermediate target data and store it in the first compression data buffer 122, and at the same time start the next first compression counter to continue counting the number of repetitions of the current target data to be compressed.

[0056] The pre-designed value can be the maximum count value of the first compression counter. The maximum count value of the first compression counter is determined by the number of bits (c) of the counter. If the first compression counter uses binary, the maximum count value is 2. c -1, if the first compression counter uses N-ary, then the maximum count value is N-1. For example, when the first compression counter uses binary and has 8 bits, then the maximum count value of the first compression counter is 2. 8 -1=255, the pre-designed value can be 255.

[0057] If the number of consecutively repeated first data items in the target data to be compressed exceeds the maximum count value of the first compression counter, such as 300 consecutively repeated first data items in the target data to be compressed and the maximum count value of the first compression counter is 255, then when the current count value of the first compression counter reaches the pre-designed value, regardless of whether the subsequent target data to be compressed is repeated, the current target data to be compressed can be forcibly stored as an intermediate target compressed data in the first compressed data buffer, and the next first compression counter is started to continue counting the number of repetitions of the current target data to be compressed, so as to prevent the sampling data from being disordered due to the overflow of the first compression counter.

[0058] In an optional embodiment of the present invention, such as Figure 3 As shown, there can be multiple first compressed data buffers 122. Each first compressed data buffer 122 can be used to store a first set number of intermediate target compressed data and a count value of the first set number of intermediate target compressed data. The first data compression controller can also be used to: send a secondary data compression start command to the second data compression module 130 when it is determined that the first compression counter has finished counting and the current first compressed data buffer has finished storing data, so that the second data compression module 130 can compress the second data to be compressed in each of the intermediate target compressed data stored in the current first compressed data buffer again; update the current first compressed data buffer according to the data buffer status of each first compressed data buffer 122, so that the first data compression controller can use the updated current first compressed data buffer to continuously compress the first data to be compressed in the target data to be compressed.

[0059] The secondary data compression start command can trigger the second data compression module 130 to re-compress the intermediate target compressed data stored in the current first compressed data buffer. The current first compressed data buffer can be the first compressed data buffer currently used to store the intermediate target compressed data.

[0060] In a specific example, let's consider 64 sets of first compression counters, each with a full-scale range of 255. Assuming each target data to be compressed is a 512-bit sample, initially, the first data compression controller can load the first 512-bit target data and activate first compression counter 0, setting its initial value to 0. The first data compression controller synchronously acquires the next 512-bit target data and compares it bit-by-bit with the buffered data of the previous 512-bit target data. If all bits of the two target data sets correspond perfectly, first compression counter 0 increments by 1. If the two target data sets are inconsistent, the previous 512-bit target data is stored as intermediate target compressed data in the first compression data buffer, and the next idle first compression counter (number 1) is switched to start counting again. When the 8-bit first compression counter reaches 255 (full scale), regardless of whether the current target data to be compressed is repeated, the target data to be compressed is forcibly stored as intermediate target compressed data in the first compression data buffer, and a new first compression counter is switched to prevent sampling data corruption caused by counter overflow. After the 64th first compression counter has finished counting, 64 sets of repeated count values ​​and the corresponding 64 pieces of intermediate target compressed data are written into the first compression data buffer. At the same time, a switching handshake signal is sent to the second data compression module so that the second data compression module can start the next round of compression processing on the intermediate target compressed data stored in the first compression data buffer.

[0061] Optionally, the first compressed data buffer can be implemented using at least two independent sets of true dual-port RAM (Random Access Memory) for time-sharing read / write. If two sets of first compressed data buffers are configured, the two sets of first compressed data buffers can be updated using a PING-PANG switching method. For example, ... Figure 3 As shown, after setting the first compressed data buffer a as the current first compressed data buffer, if the current first compressed data buffer is full, it can switch to the first compressed data buffer b as the current first compressed data buffer, so as to continuously perform the first-level coarse compression processing on the sampled data stream using the current first compressed data buffer. If there are more than 3 sets of first compressed data buffers configured, each first compressed data buffer can sequentially and cyclically select an available first compressed data buffer to update as the current first compressed data buffer.

[0062] Figure 4 This is a schematic diagram of the storage structure of a first compressed data buffer provided in Embodiment 2 of the present invention. In a specific example, such as Figure 4As shown, the bit width of the first compressed data buffer can be configured to 512 bits, and the depth can be configured to 65. The first 64 addresses of the first compressed data buffer (e.g., Figure 4 The cache addresses 0 to 63 can store 64 different intermediate target compressed data entries, and the 65th address (e.g., ...) Figure 4 The first compressed data buffer (address 64) uniformly stores the repetition count values ​​corresponding to the 64 intermediate target compressed data. Specifically, CNT1 corresponds to the 512-bit repetition count value of DATA1, CNT2 corresponds to the 512-bit repetition count value of DATA2, and so on. Utilizing the hardware characteristics of true dual-port RAM—independent read / write and simultaneous read / write to different addresses—the first compressed data buffer can simultaneously write the 64th intermediate target compressed data entry to address 65 while writing the repetition count values ​​of the 64 first compression counters. The advantage of this setup is that, since the first compression counter is appended after every 64 intermediate target compressed data entries, when the first-level sampled data cannot be compressed at all, writing the 64th intermediate target compressed data entry and its corresponding repetition count value to the first compressed data buffer simultaneously does not consume extra time and prevents sampled data loss.

[0063] In an optional embodiment of the present invention, such as Figure 3 As shown, the first data compression unit 121 may further include a first compression ratio calculator, which is communicatively connected to the first data compression controller and is used to: acquire the compressed data volume and the original data volume of the first data compression unit 121 in real time; calculate the first compression ratio of the first data compression unit 121 in real time based on the compressed data volume and the original data volume of the first data compression unit 121; the register control module 140 is also used to: control the compression function of the first data compression unit 121 to be turned off when it is determined that the first compression ratio of the first data compression unit is greater than the first compression ratio threshold.

[0064] The first compression ratio calculator can calculate the data compression ratio of the first data compression unit in real time. The first compression ratio can be the data compression ratio of the first data compression unit. The first compression ratio threshold can be configured according to actual needs, and the specific value of the first compression ratio threshold is not limited in this embodiment of the invention.

[0065] Specifically, the first data compression unit 121 can obtain the compressed data volume and the original data volume in real time through the first compression ratio calculator. The compressed data volume can be the amount of the first data to be compressed by the first data compression unit 121. The original data volume can be the amount of the target data to be compressed that the first data compression unit 121 receives before compression. Correspondingly, the first compression ratio calculator can calculate the first compression ratio of the first data compression unit in real time based on the compressed data volume and the original data volume. If the first compression ratio calculated by the first compression ratio calculator is higher than the first compression ratio threshold set by the register control module 140, then the first-level compression is considered insignificant, and the first-level compression function of the first data compression unit 121 on the sampled data can be automatically disabled through the register control module 140 to avoid additional compression overhead.

[0066] In a specific example, continuing with the above example, in the optimal compression scenario, the DRAM is idle for a long time, and all waveforms repeat. In this case, all 64 groups of 8-bit first compression counters are full. Without compression, the original data volume includes 64 data entries to be compressed, each repeated 256 times, so the original data volume is 64 × 256 entries. With compression, the compressed data for each first compression counter needs to be transmitted once, for a total of 64 entries. In addition, one repetition count value for 64 first compression counters is transmitted, for a total of 65 entries. Therefore, in the optimal compression scenario, the first compression rate is: 65 / (64 × 256) = 0.397%, achieving extreme compression of massive idle waveforms. In the worst compression scenario, the DRAM performs continuous high-speed random read and write operations, and the waveform data has no repetition. In this case, the first compression rate is: (64 + 1) / 64 = 101.5%. This is because in this case, for a maximum of 64 sampled data entries, one repetition count value for the first compression counter is transmitted additionally.

[0067] The above technical solution uses the first data compression unit of the first data compression module to compress continuously repeating first data to be compressed into a single intermediate target compressed data, obtaining a first set number of intermediate target compressed data and the repetition count value corresponding to each intermediate target compressed data. Simultaneously, the first compressed data buffer of the first data compression module stores each intermediate target compressed data and its corresponding repetition count value, thus completing effective coarse compression processing of the first data to be compressed in the target data. This enables batch compression of long-period globally repetitive waveforms such as long-duration idle DES instructions and continuous fixed DQ levels in DRAM, thereby improving the adaptability of the data compression device to long-period globally repetitive waveform data compression.

[0068] Example 3

[0069] Figure 5 This is a schematic diagram of a data compression device provided in Embodiment 3 of the present invention. This embodiment is based on the above embodiment and provides a variety of specific optional implementation methods for the internal structure of the second data compression module.

[0070] Correspondingly, such as Figure 5 As shown, the data compression device may include a data acquisition module 110, a first data compression module 120, a second data compression module 130, and a register control module 140. The second data compression module 130 may include a second data compression unit 131 and a second compressed data buffer 132.

[0071] The second data compression unit 131 is communicatively connected to the first compressed data buffer 122 of the first data compression module 120. It is used to obtain intermediate target compressed data from the first compressed data buffer 122, compress the continuously repeated second data to be compressed in the intermediate target compressed data into a secondary compressed data block, generate target compressed data corresponding to the intermediate target compressed data according to each secondary compressed data block, and generate compression index value for each target compressed data. The data content of each secondary compressed data block is different. The compression index value is used to indicate the number of compressions of the target compressed data. The second compressed data buffer 132 is communicatively connected to the second data compression unit 131 and is used to store each target compressed data and the compression index value of each target compressed data.

[0072] The second data compression unit 131 can be used to perform a second level of fine compression processing on the intermediate target compressed data. The second compressed data buffer 132 can be used to store the data after fine compression processing by the second data compression unit 131 and statistical information associated with the compressed data. The second-level compressed data block can be data obtained by compressing continuously repeated second data to be compressed.

[0073] In specific embodiments of the present invention, such as... Figure 5As shown, intermediate target compressed data requiring further compression can be obtained from the first compressed data buffer 122 through the second data compression unit 131 within the second data compression module 130. The second data compression unit 131 can parse and identify consecutively repeated second data to be compressed in the read intermediate target compressed data, and compress the consecutively repeated second data to be compressed to obtain a secondary compressed data block; alternatively, it can not compress non-consecutive and non-repeating second data to be compressed, directly generating a secondary compressed data block. That is, one intermediate target compressed data can correspond to multiple secondary compressed data blocks. For example, if the first to third data blocks in an intermediate target compressed data are the same data block, these three data blocks can be compressed into one secondary compressed data block. If the first to third data blocks in an intermediate target compressed data are different data blocks, the first to third data blocks can be directly retained, resulting in three secondary compressed data blocks. After generating multiple secondary compressed data blocks of the intermediate target compressed data, each secondary compressed data block can be concatenated to obtain the target compressed data corresponding to the intermediate target compressed data. Meanwhile, the second data compression unit 131 can also generate a compression index value corresponding to the target compressed data based on the compression status of the secondary compressed data block, so as to characterize the compression quantity of the target compressed data through the compression index value.

[0074] Optionally, a compression index value can be generated for each intermediate target compressed data segment. The compression index value can be composed of multiple concatenated index values; that is, it can be an array of multiple index values, each representing the compression status of the corresponding secondary compressed data block. In other words, one index value can be generated for each secondary compressed data block. Different index values ​​can represent compressed and uncompressed states. For example, when the index value corresponding to a secondary compressed data block is 0, it indicates that the secondary compressed data block is compressed; when the index value corresponding to a secondary compressed data block is 1, it indicates that the secondary compressed data block is not compressed.

[0075] Accordingly, each piece of target compressed data processed by the second data compression unit 131 can be stored in the second compressed data buffer 132. Simultaneously, the second compressed data buffer 132 can be configured with an index value storage area, and the second data compression unit 131 can store the compression index value corresponding to each piece of target compressed data in the index value storage area of ​​the second compressed data buffer 132.

[0076] In an optional embodiment of the present invention, such as Figure 5As shown, the second data compression unit 131 may include a second data compression logic unit, a second data compression controller, and a compression index processing unit, wherein: the second data compression logic unit is communicatively connected to the compression index processing unit, and is used to group intermediate target compressed data into multiple compressed data blocks, compare the data content of each adjacent compressed data block, identify consecutively repeated second data to be compressed, and compress and generate corresponding secondary compressed data blocks based on each consecutively repeated second data to be compressed; the compression index processing unit is used to generate a compression index value of the target compressed data based on the number of repetitions in the compression of the second data to be compressed; the second data compression controller is used to store the compression index value of the target compressed data generated by the compression index processing unit into the second compressed data buffer 132.

[0077] The second data compression logic unit can execute the compression comparison logic of the second data compression unit 131. The second data compression controller can control the writing of the target compressed data and the corresponding compression index value into the second compressed data buffer 132. The compression index processing unit can be used to generate and record the compression index value of the target compressed data.

[0078] Specifically, the second data compression unit 131 can obtain intermediate target compressed data requiring further compression processing from the first compressed data buffer 122 through the second data compression logic unit, and group each intermediate target compressed data to obtain multiple compressed data blocks. For example, when the intermediate target compressed data is 512 bits, it can be grouped into 16-bit blocks, resulting in a total of 32 compressed data blocks, each 16 bits long. Correspondingly, the second data compression logic unit can sequentially compare the data content of every two adjacent compressed data blocks of an intermediate target compressed data. If two or more consecutively adjacent compressed data blocks have the same data content, these compressed data blocks can be determined as consecutively repeated second data to be compressed. The second data compression logic unit can compress the consecutively repeated second data to be compressed into a secondary compressed data block, which can be one of the consecutively repeated compressed data blocks, and will not compress non-consecutive, non-repeating second data to be compressed.

[0079] Correspondingly, the compression index processing unit can count the number of repetitions in the compression of the second data to be compressed in real time to generate the overall compression index value corresponding to the target compressed data. Optionally, the compression index processing unit can be further divided into a compression index bit recording unit and a compression index bit caching unit. The compression index bit recording unit can record the compression index value of each target compressed data. For example, when the intermediate target compressed data is 512 bits and the compressed data block is 16 bits, a total of 32 compressed data blocks can be divided. Each compressed data block can generate an index value based on whether the data content is repeated. Therefore, the 32 index values ​​of the 32 compressed data blocks of an intermediate target compressed data can constitute the compression index value of the target compressed data corresponding to that intermediate target compressed data. The compression index bit recording unit can record the 32 compression index values ​​of each target compressed data. Optionally, when the compression index value is full, such as when the compression index value reaches 512 bits, the compression index processing unit can write the compression index value into the compression index bit caching unit. Optionally, the compressed index bit cache unit can be implemented by a 512-bit wide FIFO to cache the compressed index value so that when the second-level compressed data is idle, the compressed index value can be retrieved from the FIFO-type compressed index bit cache unit and further cached in the index value storage area of ​​the second compressed data cache area 132.

[0080] Correspondingly, the second data compression controller can control the storage of the compressed index value generated by the compressed index processing unit into the second compressed data buffer. For example, the second data compression controller can read the compressed index value from the compressed index bit cache unit of the compressed index processing unit and write it into the index value storage area of ​​the second compressed data buffer 132. At the same time, the second data compression controller can also monitor the storage status of the second compressed data buffer 132 to switch the second compressed data buffer 132 according to its status.

[0081] In an optional embodiment of the present invention, the second data compression logic unit may further be configured to: generate a first index value for the current compressed data block and discard the current compressed data block if the data content of the current compressed data block and the previous compressed data block are the same; generate a second index value for the current compressed data block and save the current compressed data block as the secondary compressed data block if the data content of the current compressed data block and the previous compressed data block are different; generate current target compressed data corresponding to the current intermediate target compressed data based on the saved secondary compressed data block; and concatenate the index values ​​of each compressed data block corresponding to the current intermediate target compressed data to generate a compression index value for the current target compressed data.

[0082] The current compressed data block can be the compressed data block that needs to be determined whether to undergo secondary compression. The first index value can be used to indicate that the current compressed data block has been compressed. For example, the first index value can be 0, indicating that the current compressed data block has the same data content as the previous compressed data block. The second index value can be used to indicate that the current compressed data block has not been compressed. For example, the second index value can be 1, indicating that the current compressed data block has different data content from the previous compressed data block. The current intermediate target compressed data can be the intermediate target compressed data currently undergoing secondary compression. The current target compressed data can be the final compressed data generated after the current intermediate target compressed data undergoes secondary compression.

[0083] Figure 6 This is a schematic diagram illustrating the effect of generating compressed index values ​​based on compressed data blocks, as provided in Embodiment 3 of the present invention. In a specific example, such as... Figure 6 As shown, assuming an intermediate target compressed data is divided into 8 compressed data blocks on average, such as the first intermediate target compressed data being divided into 8 compressed data blocks Data1, the second intermediate target compressed data being divided into 8 compressed data blocks Data2, the third intermediate target compressed data being divided into 8 compressed data blocks Data3, and so on, all intermediate target compressed data can be divided into 8 compressed data blocks. For each intermediate target compressed data, the second data compression logic unit can compare the data content of the current compressed data block with the data content of the previous compressed data block. For example, if the previous compressed data block of the first compressed data block Data1 of the first intermediate target compressed data is empty, then the index value of compressed data block Data1 is 1. Since the data content of the next 7 compressed data blocks Data1 is the same, the compression index values ​​of the second to eighth compressed data blocks Data1 are all 0. Compressed data blocks with an index value of 1 can be saved as a secondary compressed data block, while compressed data blocks with an index value of 0 are duplicates and can be discarded, thus achieving compression of duplicate compressed data blocks. Furthermore, target compressed data can be generated based on the saved secondary compressed data blocks, corresponding to the intermediate target compressed data. Simultaneously, the index values ​​of the compressed data blocks corresponding to each intermediate target compressed data can be concatenated to generate the compression index value of the corresponding target compressed data.

[0084] In an optional embodiment of the present invention, such as Figure 5As shown, the second data compression unit 131 may further include a compressed data shift splicer, which is communicatively connected to the second data compression controller. The second data compression controller is used to send the secondary compressed data block to the compressed data shift splicer. The compressed data shift splicer is used to splice the secondary compressed data block according to the receiving order of the secondary compressed data block to generate target spliced ​​compressed data of a set length.

[0085] The compressed data shifter and splicer can splice stored secondary compressed data blocks. A secondary compressed data block is a compressed data block whose index value is the second index value. The set length can be configured according to actual needs, for example, it can be the length of the target data to be compressed. This embodiment of the invention does not limit the specific value of the set length. The target spliced ​​compressed data can be data generated by splicing multiple secondary compressed data blocks with different data contents.

[0086] Specifically, the second data compression logic unit can send the secondary compressed data block, i.e., the compressed data block with the index value of the second index value, to the compressed data shifter for processing. The compressed data shifter can sequentially splice the secondary compressed data blocks according to the receiving order and the set length, thereby generating multiple target spliced ​​compressed data lines of the set length.

[0087] In a specific example, assuming the intermediate target compressed data output after the first-level compression is 512 bits long, this 512-bit intermediate target compressed data can be equally divided into 32 16-bit compressed data blocks. Each compressed data block is then compared for data redundancy. If the current 16-bit compressed data block is completely identical to the previous corresponding 16-bit compressed data block, only the index bit of the current compressed data block is set to 0, and the duplicate compressed data block is discarded, without occupying effective buffer space. If the current 16-bit compressed data block is inconsistent with the previous corresponding 16-bit compressed data block, the index bit of the current compressed data block is marked as 1. Simultaneously, this group of valid 16-bit compressed data blocks is sent as a second-level compressed data block to the compressed data shifter and splicer, seamlessly splicing it with the previously valid second-level compressed data blocks to form the 512-bit target compressed data, thus obtaining the second-level effective compressed data.

[0088] In an optional embodiment of the present invention, such as Figure 5As shown, there can be multiple second compressed data buffers. The second data compression controller can also be used to: store the combined compression index values ​​of each target compressed data in the current second compressed data buffer in a top-to-bottom order; wherein the data length of the combined compression index value is the same as the data length of the target data to be compressed and the intermediate target compressed data; store the target concatenated compressed data of each target compressed data in the current second compressed data buffer in a bottom-to-top order; wherein the data length of the target concatenated compressed data is the same as the data length of the target data to be compressed and the intermediate target compressed data; when it is determined that the current second compressed data buffer is full, count the number of index values ​​stored in the current second compressed data buffer, and use the number of index values ​​as the data length of the current cached compressed data stored in the current second compressed data buffer.

[0089] The current second compressed data buffer can be the second compressed data buffer currently used to store and process the target compressed data. The combined compression index value can be a combination of multiple compression index values. The current cached compressed data can be the total compressed data stored in the current second compressed data buffer.

[0090] In an optional embodiment of the present invention, the target cache address of the second compressed data cache area can be used to store the data length and compressed data type of the cached compressed data; wherein, the compressed data type may include a first compressed data type, a second compressed data type, a third compressed data type, and a fourth compressed data type; the first compressed data type indicates that neither the first data compression module nor the second data compression module compresses the data; the second compressed data type indicates that the first data compression module compresses the data and the second data compression module does not compress the data; the third compressed data type indicates that the first data compression module does not compress the data and the second data compression module compresses the data; the fourth compressed data type indicates that both the first data compression module and the second data compression module compress the data.

[0091] The target cache address can be the cache address in the second compressed data cache area used to store the data length and compressed data type of the cached compressed data.

[0092] Figure 7 This is a schematic diagram of the structure of a second compressed data buffer provided in Embodiment 3 of the present invention. In a specific example, such as Figure 7As shown, the number of second compressed data buffers can be two or more. For example, if configured with two second compressed data buffers, these two buffers can consist of two simple dual-port RAMs with a width of 512 bits and a depth of 4096 bits. The two RAMs can use a PING-PANG switching method and a fixed format to store the second-level compressed data. For example... Figure 7 As shown, the first 24 bits of cache address 0 in the second compressed data buffer can be used to store the total length of the effective data after the second-level compression, and the following 8 bits can store the compressed data type. Optionally, the length of the effective data can be counted in units of the length of the second-level compressed data block, for example, in units of 16 bits. Correspondingly, the second data compression controller can store the combined compression index values ​​of each target compressed data in the current second compressed data buffer in a top-down order, such as storing each 512-bit combined compression index value in a top-down order. This combined compression index value can be generated by combining 512-bit index values. Each index value in the combined compression index value can represent the compression status of the corresponding 16-bit compressed data block. At the same time, the second data compression controller can store the target concatenated compressed data (such as...) of each target compressed data in the current second compressed data buffer in a bottom-up order. Figure 7 (The second-level compressed data cache is shown). Each target concatenated compressed data can consist of multiple target compressed data. Since the data length of each target compressed data may be different, the number of target compressed data included in each target concatenated compressed data may also be different. The data length of the target concatenated compressed data is the same as the data length of the target data to be compressed and the intermediate target compressed data.

[0093] During the processing of the second-level effective compressed data, the second data compression controller can monitor the storage status of the current second-level compressed data buffer in real time. Once it is determined that the current second-level compressed data buffer is full, the second data compression controller can count the number of index values ​​stored in the current second-level compressed data buffer, use the counted number of index values ​​as the data length of the current cached compressed data stored in the current second-level compressed data buffer, and write the data length of the current cached compressed data into the cache address used to store the data length of the cached compressed data in the current second-level compressed data buffer. At the same time, the second data compression controller can automatically switch to the next second-level compressed data buffer as the updated current second-level compressed data buffer, so as to continue the second-level fine compression process using the updated second-level compressed data buffer.

[0094] Optionally, the second data compression controller may be configured with a second compression counter to count the number of index values ​​currently stored in the second compressed data buffer. When the second compressed data buffer is full, the final count value of the second compression counter is the actual compressed length of the second-level effective compressed data.

[0095] The target cache address of the second compressed data buffer can also store compressed data types. Optionally, the compressed data types can include a first compressed data type, a second compressed data type, a third compressed data type, and a fourth compressed data type. For example, the first compressed data type can be identified by 00, indicating that neither the first nor the second data compression module compresses the data; that is, there is no first-level data compression or second-level data compression, and the data compression device transmits the raw sampled data to the external system. The second compressed data type can be identified by 01, indicating that the first data compression module compresses the data while the second data compression module does not; that is, there is only first-level data compression and no second-level data compression. The third compressed data type can be identified by 10, indicating that the first data compression module does not compress the data while the second data compression module compresses it; that is, there is only second-level data compression and no first-level data compression. The fourth compressed data type can be identified by 11, indicating that both the first and second data compression modules compress the data; that is, there is both second-level and first-level data compression. Which compressed data type is enabled can be specified by the register control module or switched in real time based on compression ratio statistics. Real-time switching based on the compression ratio can maximize the compression ratio and reduce unnecessary compression overhead.

[0096] In an optional embodiment of the present invention, such as Figure 5 As shown, the second data compression unit 131 may further include a second compression ratio calculator, which is communicatively connected to the second data compression controller and is used to: acquire the compressed data volume and the original data volume of the second data compression unit 131 in real time; calculate the second compression ratio of the second data compression unit 131 in real time based on the compressed data volume and the original data volume of the second data compression unit; the register control module 140 may also be used to: control the compression function of the second data compression unit 131 to be turned off when it is determined that the second compression ratio of the second data compression unit is greater than the second compression ratio threshold.

[0097] The second compression ratio calculator can calculate the data compression ratio of the second data compression unit in real time. The second compression ratio can be the data compression ratio of the second data compression unit. The second compression ratio threshold can be configured according to actual needs; this embodiment of the invention does not limit the specific value of the second compression ratio threshold.

[0098] Specifically, the second data compression unit 131 can obtain the compressed data volume and the original data volume in real time through the second compression ratio calculator. The compressed data volume can be the amount of the second data to be compressed by the second data compression unit 131. The original data volume can be the amount of intermediate target compressed data accessed by the second data compression unit 131 before compression. Correspondingly, the second compression ratio calculator can calculate the second compression ratio of the second data compression unit in real time based on the compressed data volume and the original data volume. If the second compression ratio calculated by the second compression ratio calculator is higher than the second compression ratio threshold set by the register control module 140, the second-level compression is considered insignificant, and the second-level compression function of the second data compression unit 131 for the intermediate target compressed data can be automatically disabled through the register control module 140 to avoid additional compression overhead.

[0099] In a specific example, continuing with the above example, in the optimal compression scenario, assuming all compressed data blocks of the 512-bit intermediate target compressed data are duplicates, then in this case, except for the first compressed data block which needs to transmit valid compressed data, the rest can be transmitted using index values. Each 1-bit index value is equivalent to 16 bits of valid compressed data, so the second compression ratio in this case is 1 / 16 = 6.25%. In the worst-case compression scenario, all compressed data blocks of the 512-bit intermediate target compressed data are unique, with no duplicate compressed data blocks. In this case, the second compression ratio is: (16+1) / 16 = 106.25%.

[0100] In another specific example, continuing with the above example, if both the first-level compression and the second-level compression are enabled simultaneously, in the optimal compression scenario, each first-level compressed data buffer will transmit 64 identical 512-bit intermediate target compressed data entries to the second-level compression unit, plus one 64-bit repetition count value from the first-level compression. The repetition count value is essentially different from the first-level compressed data in the first 16-bit comparison, therefore at least two types of first-level compressed data cannot be compressed by the second level. The remaining 63 data entries are all repetitions and can all be effectively compressed. Therefore, in the optimal compression scenario, the compression ratio when the data compression device simultaneously enables both the first-level and second-level compression is: (65 / (64×256))×(((1 / 16)×(63 / 65))+((17 / 16)×2 / 65))=0.037%. In the worst-case compression scenario, all compressed data blocks in the 512-bit intermediate target compressed data are different. In this case, the compression ratio when the data compression device simultaneously enables the first and second levels of compression is: ((64+1) / 64)×(16+1) / 16=107.9%. That is, the compression ratio when the first and second levels of compression are enabled simultaneously is the product of the first compression ratio and the second compression ratio.

[0101] Therefore, in the testing scenario of DRAM test chips, the data compression device can achieve a compression ratio of 0.037% under optimal conditions, which can significantly reduce data transmission volume. However, under worst conditions, it increases additional data transmission overhead by 7.9%. When the additional overhead exceeds the effective compression, the corresponding first and / or second data compression modules can be dynamically shut down to reduce the additional compression overhead and decrease data transmission volume. Optionally, if the compression ratio of each level configured by the test system exceeds 95%, it can be considered that the compression at that level is not very meaningful, and the compression function of that level can be automatically shut down to reduce additional compression overhead.

[0102] In a specific application scenario, the overall workflow of a two-stage compression system for a data compression device may include the following operations:

[0103] Step 1: Power on the test machine and initialize it. The CPU configures the register control module of the data compression device through the APB bus, enabling the first and second data compression modules of the data compression device and starting the two-stage compression function.

[0104] Step 2: The DRAM PHY outputs CA / DQ sampling data to the data acquisition module of the data compression device in real time.

[0105] Step 3: The data acquisition module of the data compression device can filter the CA / DQ data to be sampled and send it to the first data compression module to complete the repetitive waveform counting compression processing.

[0106] Step 4: The intermediate target compressed data generated by the first data compression module is stored in the first compressed data buffer of the true dual-port to implement ping-pong caching.

[0107] Step 5: The second data compression module reads the intermediate target compressed data stored in the first-level cache data store, removes duplicate data from the compressed data blocks based on the short code index, and completes the secondary compression process.

[0108] Step Six: The final compressed target data is uploaded to the backend system via the PCIe interface. The backend system can then losslessly reconstruct the original waveform based on the target compressed data and the corresponding "index value + repeat count value," meeting the requirements for fault backtracking analysis.

[0109] The aforementioned data compression device employs a heterogeneous two-stage data compression approach combining coarse and fine compression. The first stage uses repetition counting to adapt to long-duration, continuous, repetitive idle waveforms, while the second stage uses short code indexing to adapt to short-interval, burst-change waveforms. This perfectly matches the waveform characteristics of DRAM test commands, which are characterized by numerous idle periods and few read / write bursts. Compared to traditional single-stage compression, the average compression efficiency is improved by more than 10 times. Simultaneously, the data compression device dynamically selects sampling channels through a register control module, supporting ATE die testing and SLT memory module system testing. It is compatible with various DRAM products, including DDR4 and DDR5, with different bit widths and channel numbers, and is suitable for multiple test scenarios, offering far greater versatility than existing fixed-channel compression solutions. The multi-stage compression scheme significantly reduces PCIe transmission bandwidth usage, avoids preemptive conflicts between test commands and waveform data buses, thereby improving overall system testing efficiency. Simultaneously, it reduces the capacity of the background storage hard drive, significantly lowering testing costs. The data compression device can be processed in parallel pipeline based on the hardware logic of the test chip throughout the entire process. No background CPU is required to participate in the compression operation. Sampling, compression and transmission can be completed synchronously with nanosecond-level processing latency. It has high real-time performance and fully matches the timing requirements of high-speed real-time sampling of DRAM. It can effectively solve the inherent defects of high latency in background software compression.

[0110] Example 4

[0111] Figure 8A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0112] like Figure 8 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded into the RAM 13 from storage unit 18. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0113] Optionally, the electronic device 10 may also include a DRAM test chip ( Figure 8(Not shown) The DRAM test chip may be configured with a data storage device provided in any embodiment of the present invention. The data storage device includes: a data acquisition module, a first data compression module, and a second data compression module; wherein: the data acquisition module is communicatively connected to the first data compression module, and the data acquisition module is used to acquire target data to be compressed from the DRAM device under test and send the target data to be compressed to the first data compression module; wherein the target data to be compressed includes test feedback data of the DRAM device under test; the first data compression module and the second data compression module are communicatively connected, and the first data compression module is used to compress a first data to be compressed in the target data to obtain intermediate target compressed data, and send the intermediate target compressed data to the second data compression module; wherein the first data to be compressed includes waveform data with the same data content within a preset continuous sampling period in the target data to be compressed; the second data compression module is used to compress a second data to be compressed in the intermediate target compressed data to obtain target compressed data; wherein the second data to be compressed includes waveform data with different data content between adjacent data groups in the intermediate target compressed data.

[0114] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0115] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above.

[0116] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0117] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0118] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0119] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0120] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the embodiments of the present invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in the embodiments of the present invention can be achieved, and this is not limited herein.

[0121] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A data compression device, characterized in that, The data compression device is integrated into the DRAM test chip, and the data compression device includes a data acquisition module, a first data compression module, and a second data compression module; wherein: The data acquisition module is communicatively connected to the first data compression module. The data acquisition module is used to acquire the target data to be compressed from the DRAM device under test and send the target data to be compressed to the first data compression module. The target data to be compressed includes the test feedback data of the DRAM device under test. The first data compression module and the second data compression module are communicatively connected. The first data compression module is used to compress the first data to be compressed in the target data to be compressed to obtain intermediate target compressed data, and send the intermediate target compressed data to the second data compression module. The first data to be compressed includes waveform data with the same data content within a preset continuous sampling period in the target data to be compressed. The second data compression module is used to compress the second data to be compressed in the intermediate target compressed data to obtain target compressed data; wherein, the second data to be compressed includes waveform data in the intermediate target compressed data whose data content is different between adjacent data groups.

2. The data compression device according to claim 1, characterized in that, Also includes: A register control module is communicatively connected to the data acquisition module, the first data compression module, and the second data compression module, and is used to configure the compression enable of the first data compression module and the second data compression module, and to configure the data acquisition mode of the data acquisition module. The data acquisition module is further configured to: obtain the data acquisition mode configured by the register control module, and filter the full acquisition data of the DRAM device under test according to the data acquisition mode to obtain the target data to be compressed.

3. The data compression device according to claim 2, characterized in that, The first data compression module includes a first data compression unit and a first compressed data buffer, wherein: The first data compression unit is communicatively connected to the data acquisition module and is used to compress the first data to be compressed that is continuously repeated in the target data to be compressed into a single intermediate target compressed data, thereby obtaining a first set number of intermediate target compressed data and a repetition count value corresponding to each intermediate target compressed data; wherein, each intermediate target compressed data corresponds one-to-one with the corresponding repetition count value. The first compressed data buffer is communicatively connected to the first data compression unit and is used to store each of the intermediate target compressed data and the repetition count value corresponding to each of the intermediate target compressed data.

4. The data compression device according to claim 3, characterized in that, The first data compression unit includes a first compression counter of a first predetermined number and a first data compression controller, wherein: The first data compression controller is communicatively connected to each of the first compression counters, and is used to compare the data content of each adjacent data of the target data to be compressed, identify the continuously repeated first data to be compressed, and compress and generate the corresponding intermediate target compressed data according to each continuously repeated first data to be compressed. The first data compression controller is further configured to update the count value of the corresponding first compression counter according to the number of repetitions of the first data to be compressed, so as to obtain the repetition count value corresponding to each intermediate target compressed data.

5. The data compression device according to claim 4, characterized in that, The first data compression controller is also used for: If it is determined that the data content of the current target data to be compressed is the same as that of the previous target data to be compressed, the current count value of the current first compression counter corresponding to the current target data to be compressed is incremented and updated. If it is determined that the data content of the current target data to be compressed is different from that of the previous target data to be compressed, the previous target data to be compressed is taken as an intermediate target data and stored in the first compressed data buffer. At the same time, the next first compression counter is started to count the number of repetitions of the current target data to be compressed. If the data content of the current target data to be compressed is the same as that of the previous target data to be compressed, the operation of incrementing the count value of the current first compression counter corresponding to the current target data to be compressed continues until the first compression counter count of the first set number is completed.

6. The data compression apparatus according to claim 5, characterized in that, The first data compression controller is also used for: If the current count value of the first compression counter reaches the pre-designed value, the current target data to be compressed is stored as an intermediate target data and stored in the first compression data buffer. At the same time, the next first compression counter is started to continue counting the number of repetitions of the current target data to be compressed.

7. The data compression apparatus according to claim 5 or 6, characterized in that, The number of the first compressed data buffers is multiple, and each first compressed data buffer is used to store the first predetermined number of intermediate target compressed data and the count value of the first predetermined number of intermediate target compressed data; the first data compression controller is further used to: When the first compression counter reaches the set number and the current first compressed data buffer is fully stored, a secondary data compression start command is sent to the second data compression module so that the second data compression module can compress the second data to be compressed in each of the intermediate target compressed data stored in the current first compressed data buffer again. The current first compressed data cache is updated according to the data cache status of each of the first compressed data caches, so that the first data compression controller uses the updated current first compressed data cache to continuously compress the first data to be compressed in the target data to be compressed.

8. The data compression device according to claim 4, characterized in that, The first data compression unit further includes a first compression ratio calculator, which is communicatively connected to the first data compression controller and is used for: The compressed data volume and the original data volume of the first data compression unit are obtained in real time; The first compression ratio of the first data compression unit is calculated in real time based on the amount of compressed data and the amount of original data in the first data compression unit. The register control module is further configured to: control the shutdown of the compression function of the first data compression unit when it is determined that the first compression ratio of the first data compression unit is greater than the first compression ratio threshold.

9. The data compression device according to claim 3, characterized in that, The second data compression module includes a second data compression unit and a second compressed data buffer, wherein: The second data compression unit is communicatively connected to the first compressed data buffer of the first data compression module. It is used to obtain the intermediate target compressed data from the first compressed data buffer, compress consecutively repeated second data to be compressed in the intermediate target compressed data into a secondary compressed data block, generate target compressed data corresponding to the intermediate target compressed data based on each secondary compressed data block, and generate a compression index value for each target compressed data. The data content of each secondary compressed data block is different. The compression index value is used to represent the compression quantity of the target compressed data. The second compressed data buffer is communicatively connected to the second data compression unit and is used to store each of the target compressed data and the compression index value of each of the target compressed data.

10. The data compression apparatus according to claim 9, characterized in that, The second data compression unit includes a second data compression logic unit, a second data compression controller, and a compression index processing unit, wherein: The second data compression logic unit is communicatively connected to the compression index processing unit, and is used to group the intermediate target compressed data into multiple compressed data blocks, compare the data contents of each adjacent compressed data block, identify the continuously repeating second data to be compressed, and compress and generate the corresponding secondary compressed data block according to each continuously repeating second data to be compressed. The compression index processing unit is used to generate a compression index value for the target compressed data based on the number of repetitions in the second data to be compressed. The second data compression controller is used to store the compression index value of the target compressed data generated by the compression index processing unit into the second compressed data cache.

11. The data compression apparatus according to claim 10, characterized in that, The second data compression logic unit is also used for: If it is determined that the data content of the current compressed data block is the same as that of the previous compressed data block, a first index value is generated for the current compressed data block, and the current compressed data block is discarded. If it is determined that the data content of the current compressed data block is different from that of the previous compressed data block, a second index value is generated for the current compressed data block, and the current compressed data block is saved as the second-level compressed data block; Generate the current target compressed data corresponding to the current intermediate target compressed data based on the saved secondary compressed data blocks; The index values ​​of each compressed data block corresponding to the current intermediate target compressed data are concatenated to generate the compression index value of the current target compressed data. The first index value is used to indicate that the current compressed data block has the same data content as the previous compressed data block, and the second index value is used to indicate that the current compressed data block has different data content from the previous compressed data block.

12. The data compression apparatus according to claim 11, characterized in that, The second data compression unit further includes a compressed data shifter and splicer, which is communicatively connected to the second data compression logic unit, wherein: The second data compression logic unit is used to send the secondary compressed data block to the compressed data shift splicer; The compressed data shifter splicer is used to splice the secondary compressed data blocks according to the receiving order of the secondary compressed data blocks to generate target spliced ​​compressed data of a set length.

13. The data compression apparatus according to claim 12, characterized in that, The second compressed data buffer has multiple locations, and the second data compression controller is further configured to: In the current second compressed data buffer, the combined compression index values ​​of each target compressed data are stored sequentially from top to bottom; wherein, the data length of the combined compression index value is the same as the data length of the target data to be compressed and the intermediate target compressed data; In the current second compressed data buffer, the target concatenated compressed data of each target compressed data is stored sequentially from bottom to top; wherein, the data length of the target concatenated compressed data is the same as the data length of the target data to be compressed and the intermediate target compressed data; If it is determined that the current second compressed data buffer is full, the number of index values ​​stored in the current second compressed data buffer is counted, and the number of index values ​​is used as the data length of the current cached compressed data stored in the current second compressed data buffer.

14. The data compression apparatus according to claim 13, characterized in that, The target cache address of the second compressed data cache area is used to store the data length and compressed data type of the cached compressed data; The compressed data types include a first compressed data type, a second compressed data type, a third compressed data type, and a fourth compressed data type; The first compressed data type indicates that neither the first data compression module nor the second data compression module has compressed the data; The second compressed data type indicates that the first data compression module compresses the data, but the second data compression module does not compress it. The third compressed data type indicates that the first data compression module did not compress the data and the second data compression module compressed the data. The fourth compressed data type indicates that both the first data compression module and the second data compression module compress the data.

15. The data compression apparatus according to claim 10, characterized in that, The second data compression unit further includes a second compression ratio calculator, which is communicatively connected to the second data compression controller and is used for: The compressed data volume and the original data volume of the second data compression unit are obtained in real time; The second compression ratio of the second data compression unit is calculated in real time based on the amount of compressed data and the amount of original data in the second data compression unit; The register control module is further configured to: control the shutdown of the compression function of the second data compression unit when it is determined that the second compression ratio of the second data compression unit is greater than the second compression ratio threshold.

16. An electronic device, characterized in that, The electronic device includes a DRAM test chip; the DRAM test chip is configured with a data compression device as described in any one of claims 1-15.

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