Clock-gated serial-to-parallel conversion circuit based on state difference detection
By using a clock-gated serial-to-parallel conversion circuit based on state difference detection, and utilizing the Johnson loop pointer and the clock-gated unit based on state difference detection, the problems of high dynamic power consumption and complex control logic in the prior art are solved, and a low-power and simple control serial-to-parallel conversion is achieved.
Patent Information
- Application Number
- CN202611545102.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-10-08
- Publication Date
- 2026-11-03
AI Technical Summary
Existing serial-to-parallel conversion circuits struggle to balance the dynamic power consumption of high data registers and local clock networks with complex control logic, resulting in high levels of invalid clock activity and data shifts.
A clock-gated serial-to-parallel conversion circuit based on state difference detection is adopted. Using Johnson's circular pointer and the clock gating unit for state difference detection, the gated clock pulse is generated by the difference detection module. The data storage unit is only updated in the valid state sequence, thus avoiding full-width data shift and binary carry chain.
While maintaining a single clock domain and a simple control path, it reduces invalid clock activity in data storage units and local clock networks, reduces the stepwise movement between data registers, and lowers dynamic power consumption and control logic complexity.
Smart Images
Figure CN123034828A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to serial-to-parallel conversion technology for digital integrated circuits, specifically a clock-gated serial-to-parallel conversion circuit based on state difference detection, which utilizes Johnson's circular pointer and clock gating technology based on state difference detection to achieve serial input and parallel output. Background Technology
[0002] Serial transmission reduces the number of chip pins and crosstalk caused by long-distance parallel transmission, and is therefore widely used in communication interfaces, data acquisition interfaces, on-chip interconnects, and control systems. The receiving end typically needs to convert continuously arriving serial data into parallel data for use by subsequent circuits.
[0003] A common serial-input parallel-output circuit employs a full-width shift register architecture. For example... Figure 1 As shown, in this architecture, for each N-bit parallel output, for every bit of serial data received, all N data registers need to receive a clock pulse, causing the stored data to move sequentially along the register chain. If one clock pulse received by one register is considered one clock activity, then receiving one frame of data by a single N-bit shift register will generate N squared clock activities; when there are K concurrent inputs, the total number of clock activities is K multiplied by N squared. The global high-frequency data shift and continuous clock triggering will keep the internal nodes of the registers and the local clock network in a high state of toggling activity, thereby increasing dynamic power consumption.
[0004] To reduce clock activity caused by full-width shift, existing serial-to-parallel conversion circuits such as Figure 2 As shown, this architecture employs a tree-like hierarchical structure, dividing the data register into multiple levels and progressively decreasing the update frequency at each level. While this architecture can reduce some data movement, it typically requires a binary counter for position decoding or the use of multi-frequency clocks and corresponding control logic, thus increasing the complexity of the control logic and hardware overhead.
[0005] In summary, existing serial-to-parallel converter circuits typically require a trade-off between high dynamic power consumption in the data register and local clock network and complex control logic. Therefore, a new serial-to-parallel converter circuit is needed that can effectively reduce unnecessary clock activity and data shifting while maintaining a single clock domain and a simpler control path. Summary of the Invention
[0006] To address the aforementioned problems and shortcomings, and to resolve the difficulty in balancing the dynamic power consumption of high data registers and local clock networks with complex control logic, this invention provides a clock-gated serial-to-parallel conversion circuit based on state difference detection. While maintaining a single clock domain and a simpler control path, it reduces invalid clock activity in data storage units and their local clock networks, and reduces the stepwise movement of serial data between data registers.
[0007] A clock-gated serial-to-parallel converter circuit based on state difference detection is characterized by comprising K serial input lines, K data storage unit groups, N-bit Johnson loop pointers, and N clock gating units based on state difference detection. Wherein, K is a positive integer ≥ 1, and N is a positive integer ≥ 2; the K data storage unit groups share the N-bit Johnson loop pointers and the N clock gating units based on state difference detection.
[0008] The K serial input lines are numbered sequentially from 0 to K-1, where j is any integer from 0 to K-1. Each serial input line corresponds to a data storage unit group. Each data storage unit group includes N data storage units, which are numbered from 0 to N-1, where i is any integer from 0 to N-1.
[0009] The serial input line numbered j is directly connected to the data input terminals of each data storage unit numbered from 0 to N-1 in the data storage unit group corresponding to j, so that the serial input data on the serial input line simultaneously reaches the data input terminals of N data storage units in the corresponding data storage unit group.
[0010] The N-bit Johnson circular pointer includes N pointer storage units. The data input terminal of pointer storage unit numbered i is used to receive the next state signal generated according to the Johnson inverse feedback relationship. Its data output terminal is used to output the current status signal. Its clock terminal is connected to the gated clock output terminal of the clock gate unit based on state difference detection, numbered i; the next state signal of the first pointer storage unit numbered 0 is the inverted value of the current state signal of the Nth pointer storage unit numbered N-1, and the next state signal of the pointer storage unit numbered i is the current state signal of the pointer storage unit numbered i-1; in the predetermined legal state sequence of the N-bit Johnson circular pointer, only one pointer storage unit has a next state signal that is different from the current state signal in each sampling period.
[0011] The N clock gating units based on state difference detection correspond one-to-one with the N pointer storage units; the clock gating unit numbered i based on state difference detection compares the next state signal of the pointer storage unit numbered i. and current state signal And generate one gated clock pulse. The clock output is sent to the clock terminal of the pointer storage unit numbered i, and to the clock terminals of the K data storage units numbered i in the K data storage unit group. Each clock gating unit based on state difference detection receives the system clock CLK.
[0012] When the Johnson loop pointer is in a valid state that can be reached after reset and the valid edge of the system clock arrives, only one clock gating unit based on state difference detection will output a valid gating clock pulse. Only the data storage unit that receives the valid gating clock pulse will perform data writing, while the other data storage units will retain the original stored data.
[0013] Furthermore, the clock gating unit based on state difference detection is composed of an XOR gate and an integrated clock gating unit (ICG). For the clock gating unit numbered i based on state difference detection, its XOR gate detects the next state signal of the pointer storage unit numbered i. With the current state signal Only when and Output a valid state difference signal when there is inconsistency. It also drives the integrated clock gating unit (ICG) to turn on, thereby generating a gated clock pulse. .
[0014] Furthermore, the N-bit Johnson cyclic pointer is reset to an all-zero state; the N-bit Johnson cyclic pointer changes bit by bit from an all-zero state to an all-one state in the first data frame, and changes bit by bit from an all-one state to an all-zero state in the second data frame adjacent to the first data frame.
[0015] Furthermore, each serial input data is written to N data storage units in the corresponding data storage unit group in high-order priority. The output of data storage unit numbered 0 corresponds to the highest bit of the parallel output, and the output of data storage unit numbered N-1 corresponds to the lowest bit of the parallel output.
[0016] Furthermore, each serial input data is written to N data storage units in the corresponding data storage unit group in low-order priority. The output of data storage unit numbered 0 corresponds to the least significant bit of the parallel output, and the output of data storage unit numbered N-1 corresponds to the most significant bit of the parallel output.
[0017] Furthermore, each clock gating unit also includes an enable latch structure, which is used to latch the corresponding gating enable in the ineffective phase of the system clock CLK to generate a glitch-free gating clock.
[0018] Furthermore, within one frame of the predetermined legal state sequence, N sampling periods, each pointer storage unit and each data storage unit respectively receive a gated clock pulse output by the corresponding clock gate unit.
[0019] Furthermore, the specific workflow of the clock-gated serial-to-parallel conversion circuit based on state difference detection is as follows:
[0020] The same gated clock output of the state difference detection-based clock gating unit i is connected to the clock output of the pointer storage unit i and the clock outputs of the K data storage units i in the K data storage unit group. When the Johnson loop pointer is in a valid state reachable after reset and the valid edge of the system clock arrives, exactly one of the N state difference detection-based clock gating units outputs a valid gated clock pulse to synchronously trigger the state update of the pointer storage unit i and the data writing of the K data storage units i in the K data storage unit group.
[0021] The serial input line number j corresponds to the outputs of N data storage units in the data storage unit group number j, which together constitute the N-bit parallel output of number j. After N effective edges of the system clock, the N data storage units in each data storage unit group complete one data write, forming a frame of N-bit parallel data.
[0022] In summary, this invention utilizes a Johnson cyclic pointer and a state difference detection-based gated clock to achieve serial input and parallel output. The Johnson cyclic pointer employs inverted feedback, with only one position change per cycle in a valid state sequence. The difference detection module generates position-level gating enable based on the difference between the pointer candidate state signal and the current state signal: the same output of the state difference detection-based clock gating unit numbered i simultaneously drives the pointer storage unit numbered i and K data storage units of the same number i, to synchronously complete pointer advancement and data writing. This invention reduces invalid clock activity in data storage units and their local clock networks while maintaining a single clock domain and a relatively simple control path, reducing the step-by-step movement of serial data between data registers; it avoids full-width data shifts, binary carry chains, and position decoding, reducing the activity of registers and local clock networks. Attached Figure Description
[0023] Figure 1 This is a structural diagram of a shift register circuit for serial-to-parallel conversion in the prior art.
[0024] Figure 2 A structural diagram of a serial-to-parallel conversion circuit for a tree-type hierarchical deserializer in the prior art;
[0025] Figure 3This is a structural diagram of a clock-gated serial-to-parallel conversion circuit based on state difference detection, as shown in the embodiment.
[0026] Figure 4 This is a schematic diagram illustrating the collaborative working mechanism between the Johnson loop pointer and state difference detection in the embodiment.
[0027] Figure 5 This is a schematic diagram of the four-bit data serialization process in the embodiment. Detailed Implementation
[0028] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0029] Example:
[0030] A clock-gated serial-to-parallel converter circuit based on state difference detection includes K serial input lines, K data storage unit groups, N-bit Johnson loop pointers, and N clock gating units based on state difference detection.
[0031] This embodiment uses two data storage unit groups, A and B, such as... Figure 3 As shown, the actual design can be flexibly configured into K groups of ≥1, with each group consisting of N data storage units. In terms of signal connection, the serial input line numbered j corresponds to the data storage unit group numbered j, and the serial input data on this serial input line is broadcast to the data input terminals of all N data storage units within the corresponding data storage unit group.
[0032] In the predetermined valid state sequence of the Johnson circular pointer, there is exactly one next state signal for each sampling period in the pointer storage unit. With the current state signal Because they are different, there is exactly one valid gating clock pulse among the N clock gating units based on state difference detection. Although each serial input data arrives at the data input terminals of the N data storage units in the corresponding data storage unit group simultaneously, this unique valid gating clock pulse only triggers the K data storage units numbered i in each data storage unit group to perform data writing, and will not trigger the synchronous update of all data storage units in the K data storage unit groups.
[0033] Combination Figure 3 As can be seen from the internal connections, the N-bit Johnson circular pointer consists of N pointer storage units. Upon reset, each pointer storage unit is set to 0. The first pointer storage unit (number 0) receives the inverted value of the current state of the Nth pointer storage unit (number N-1), and the remaining pointer storage units receive the current state of the previous pointer storage unit, thus forming the N-bit Johnson circular pointer.
[0034] Figure 3The dashed box in the middle indicates the clock gating unit based on state difference detection. The clock gating unit internally contains difference detection logic composed of XOR gates and an ICG. The clock gating unit numbered i, based on state difference detection, receives the next state signal from the pointer. and current state signal and according to the formula The corresponding state difference signal is generated. This mechanism causes the pointer to start from an all-zero reset state, and the state difference propagates sequentially from the pointer storage unit numbered 0 to the pointer storage unit numbered N-1, with the pointer state changing to all one bit by bit; in the next data frame, the state difference propagates again from the pointer storage unit numbered 0 to the pointer storage unit numbered N-1, with the pointer state changing back to all zero bit by bit.
[0035] When the effective edge of the system clock CLK arrives, the clock gating unit based on state difference detection, which detects state difference number i, generates a gated clock pulse. The gated clock pulse directly reaches the clock terminal of the K data storage units numbered i in the K data storage unit group (K=2 in this embodiment), so that pointer state updates and data writing are controlled by the same gated clock pulse. Synchronous triggering avoids complex control paths and data shifting.
[0036] Combination Figure 4 Taking the circuit configuration with N=4 as an example, this paper details the working mechanism of the Johnson loop pointer and the state difference detection logic.
[0037] The current state signals of the four pointer storage units are Q0, Q1, Q2, and Q3, respectively, and represent the current state of the Johnson loop pointer in the order [Q3, Q2, Q1, Q0]. According to the Johnson inverted feedback relationship, D0 is the inverted signal of Q3, D1=Q0, D2=Q1, and D3=Q2. The clock gating unit numbered i, based on state difference detection, compares the next state signal D of the pointer storage unit at position i. i With the current state signal Q i And generate a state difference signal E i .
[0038] After reset, the current state of all four pointer storage units is 0, i.e., the current state is 0000. At this time, the next state obtained according to the aforementioned Johnson inverse feedback relationship is 0001. Only D0 and Q0 are different, so only the state difference signal E0 is valid. The first clock gating unit based on state difference detection outputs a gated clock pulse G0, which updates the first pointer storage unit from 0 to 1, changing the pointer state from 0000 to 0001; at the same time, it writes data onto the serial input line in the first data storage unit (number 0) of each group, while the other three clock gating units based on state difference detection do not output gated clock pulses.
[0039] After the first pointer storage unit is updated, the current state becomes 0001, and the corresponding next state is 0011. At this time, D0 and Q0 become consistent again, while D1 and Q1 differ. The only valid state difference signal changes from E0 to E1. When the next valid edge of the system clock arrives, the second clock gating unit based on state difference detection outputs a gating clock G1; G1 synchronously triggers the update of the second pointer storage unit and the writing of the second data storage unit (number 1) in each group. This process continues, with state differences appearing sequentially in pointer storage units numbered 0, 1, 2, and 3, and the pointer states evolving sequentially to 0000, 0001, 0011, 0111, and 1111.
[0040] When the pointer reaches state 1111, the next state is 1110, and the state difference reappears in pointer memory cell numbered 0. Therefore, during the subsequent four valid edges of the system clock, the pointer state evolves sequentially from 1111 to 1110, 1100, 1000, and 0000, corresponding to the output gate clocks G0, G1, G2, and G3. Thus, the Johnson cyclic pointer cycles through eight valid states, selecting all four data storage cells sequentially every four valid edges of the system clock, without requiring a full pointer reset between adjacent data frames.
[0041] Under the above legal conditions, each time a valid edge of the system clock arrives, only one pointer memory unit's D is accessed. i With Q i Because they are different, only one clock gating unit based on state difference detection outputs a valid gated clock pulse. This gated clock pulse simultaneously updates the state of the corresponding pointer storage unit and writes data to the K data storage units in the K data storage unit group that have the same number as the pointer storage unit. The updated pointer state then determines the pointer storage unit where the state difference occurs when the next valid edge of the system clock arrives, thus forming a working process in which state difference detection, target data storage unit selection, pointer update, and data writing work together.
[0042] Evolution of the four-digit data serialization process
[0043] Combination Figure 5 This document details the process of serializing four data bits. The four data storage units are numbered 0, 1, 2, and 3, and a serial input line connects to the data input terminals of each unit. This embodiment employs a least-bit-first writing method, assuming the first frame of serial data arrives in the order A0, A1, A2, and A3.
[0044] After reset, the Johnson loop pointer's initial state is 0000. During the arrival of the four valid edges of the system clock corresponding to the first frame, the gated clocks G0, G1, G2, and G3 sequentially output valid pulses, writing A0, A1, A2, and A3 into data storage units numbered 0, 1, 2, and 3, respectively; simultaneously, the pointer state evolves sequentially from 0000 to 0001, 0011, 0111, and 1111. After the first frame is received, the four-bit parallel output is [A3, A2, A1, A0].
[0045] When receiving the second frame of data, there is no need to reset the Johnson loop pointer. Assuming the second frame of serial data arrives in the order of B0, B1, B2, and B3, the gate clocks G0, G1, G2, and G3 will again output valid pulses sequentially, writing B0, B1, B2, and B3 into data storage units numbered 0, 1, 2, and 3 respectively; the pointer state will evolve sequentially from 1111 to 1110, 1100, 1000, and 0000. After the second frame is received, the four-bit parallel output is updated to [B3, B2, B1, B0], and the circuit can continue receiving subsequent data frames in the same manner.
[0046] As can be seen from the above process, each time the effective edge of the system clock arrives, only one data storage unit receives the gated clock and writes the current serial input data. The data that has been written does not need to be moved between data storage units one by one.
[0047] As can be seen from the above embodiments, this invention utilizes a Johnson cyclic pointer and a gated clock for state difference detection to achieve serial input and parallel output. The Johnson cyclic pointer employs inverted feedback, with only one position change per cycle in a valid state sequence. The difference detection module generates position-level gating enable based on the difference between the pointer candidate state signal and the current state signal. This invention avoids full-width data shifting, binary carry chains, and position decoding, reducing the activity of registers and local clock networks.
Claims
1. A clock-gated serial-to-parallel conversion circuit based on state difference detection, characterized in that: It includes K serial input lines, K data storage unit groups, N-bit Johnson loop pointers, and N clock gating units based on state difference detection; where K is a positive integer ≥ 1 and N is a positive integer ≥ 2; the K data storage unit groups share the N-bit Johnson loop pointers and the N clock gating units based on state difference detection. The K serial input lines are numbered sequentially from 0 to K-1, where j is any integer from 0 to K-1. Each serial input line corresponds to a data storage unit group. Each data storage unit group includes N data storage units, which are numbered from 0 to N-1, where i is any integer from 0 to N-1. The serial input line number j is directly connected to the data input terminals of each data storage unit numbered from 0 to N-1 in the data storage unit group corresponding to j, so that the serial input data on the serial input line can simultaneously reach the data input terminals of N data storage units in the corresponding data storage unit group. The N-bit Johnson circular pointer includes N pointer storage units. The data input terminal of the pointer storage unit numbered i is used to receive the next state signal generated according to the Johnson inverse feedback relationship. Its data output terminal is used to output the current status signal. Its clock terminal is connected to the gated clock output terminal of the clock gate unit based on state difference detection, numbered i; the next state signal of the first pointer storage unit numbered 0 is the inverted value of the current state signal of the Nth pointer storage unit numbered N-1, and the next state signal of the pointer storage unit numbered i is the current state signal of the pointer storage unit numbered i-1; in the predetermined legal state sequence of N-bit Johnson circular pointers, only one pointer storage unit has a next state signal that is different from the current state signal in each sampling period; The N clock gating units based on state difference detection correspond one-to-one with the N pointer storage units; the clock gating unit numbered i based on state difference detection compares the next state signal of the pointer storage unit numbered i. and current state signal And generate one gated clock pulse. The clock output is sent to the clock terminal of the pointer storage unit numbered i, and to the clock terminals of the K data storage units numbered i in the K data storage unit group. Each clock gating unit based on state difference detection receives the system clock CLK. When the Johnson loop pointer is in a valid state that can be reached after reset and the valid edge of the system clock arrives, only one clock gating unit based on state difference detection will output a valid gating clock pulse. Only the data storage unit that receives the valid gating clock pulse will perform data writing, while the other data storage units will retain the original stored data.
2. The clock-gated serial-to-parallel conversion circuit based on state difference detection as described in claim 1, characterized in that: The clock gating unit based on state difference detection is composed of an XOR gate and an integrated clock gating unit (ICG). For clock-gated cell numbered i based on state difference detection, its XOR gate detects the next state signal of the pointer storage cell numbered i. With the current state signal Only when and Output a valid state difference signal when there is inconsistency. It also drives the integrated clock gating unit (ICG) to turn on, thereby generating a gated clock pulse. .
3. The clock-gated serial-to-parallel conversion circuit based on state difference detection as described in claim 1, characterized in that: The N-bit Johnson cyclic pointer is reset to an all-zero state; the N-bit Johnson cyclic pointer changes bit by bit from an all-zero state to an all-one state in the first data frame, and changes bit by bit from an all-one state to an all-zero state in the second data frame adjacent to the first data frame.
4. The clock-gated serial-to-parallel conversion circuit based on state difference detection as described in claim 1, characterized in that: Each serial input data is written to N data storage units in the corresponding data storage unit group in high-order priority. The output of data storage unit numbered 0 corresponds to the highest bit of the parallel output, and the output of data storage unit numbered N-1 corresponds to the lowest bit of the parallel output.
5. The clock-gated serial-to-parallel conversion circuit based on state difference detection as described in claim 1, characterized in that: Each serial input data is written to N data storage units in the corresponding data storage unit group in low-order priority. The output of data storage unit numbered 0 corresponds to the least significant bit of the parallel output, and the output of data storage unit numbered N-1 corresponds to the most significant bit of the parallel output.
6. The clock-gated serial-to-parallel conversion circuit based on state difference detection as described in claim 1, characterized in that: Each clock gating unit also includes an enable latch structure, which is used to latch the corresponding gating enable during the ineffective phase of the system clock CLK.
7. The clock-gated serial-to-parallel conversion circuit based on state difference detection as described in claim 1, characterized in that: Within one frame of the predetermined legal state sequence, N sampling periods, each pointer storage unit and each data storage unit receive a gated clock pulse output by the corresponding clock gate unit once.
8. The clock-gated serial-to-parallel conversion circuit based on state difference detection as described in claim 1, characterized in that, The specific workflow is as follows: The same gated clock output terminal of the state difference detection-based clock gating unit numbered i is connected to the clock terminal of the pointer storage unit numbered i and the clock terminals of the K data storage units numbered i in the K data storage unit group. When the Johnson loop pointer is in a valid state that can be reached after reset and the valid edge of the system clock arrives, only one of the N clock gating units based on state difference detection outputs a valid gating clock pulse to synchronously trigger the pointer storage unit numbered i to update its state, and to write data to the K data storage units numbered i in the K data storage unit group. The serial input line number j corresponds to the outputs of N data storage units in the data storage unit group number j, which together constitute the N-bit parallel output of number j. After N effective edges of the system clock, the N data storage units in each data storage unit group complete one data write, forming a frame of N-bit parallel data.