Method for manufacturing back contact cell, back contact cell and battery assembly
By designing the metal electrode area as a textured surface and the non-electrode area as a polished surface on the back of the silicon wafer of the N-type back contact cell, the problems of limited contact area and easy cracking of tunneling silicon oxide in the prior art are solved, and the high efficiency of photoelectric conversion of the cell is achieved.
Patent Information
- Application Number
- CN202611294562.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-25
- Publication Date
- 2026-11-03
AI Technical Summary
Existing N-type back contact batteries have limited contact area between the metal electrode and the silicon wafer, resulting in high ohmic contact resistance. This increases the series resistance of the battery, reduces the fill factor (FF), and causes stress concentration on the polished surface, making the tunneling silicon oxide prone to cracking, damaging the passivation layer, leading to a surge in recombination and a decrease in VOC, thus reducing the battery conversion efficiency.
By designing the topography of the back side of the silicon wafer, the metal electrode area has a textured structure and the non-electrode area has a polished structure. This increases the contact area between the metal electrode and the silicon wafer, reduces interfacial recombination loss, and increases the optical path by reflecting photons through the textured structure, thereby improving the photoelectric conversion efficiency.
It effectively improves the battery's fill factor FF and long-wavelength short-circuit current Jsc, reduces the contact series resistance Rs, minimizes the impact of tunneling silicon oxide cracking, increases the open-circuit voltage Voc, and improves the battery's conversion efficiency.
Smart Images
Figure CN123035773A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of solar cell technology, specifically relating to a method for preparing a back contact cell, the back contact cell, and a cell assembly. Background Technology
[0002] Back-contact solar cells are a type of solar cell technology that integrates all positive and negative metal contacts on the back side. Their front side has no grid lines, allowing them to absorb more sunlight. Current N-type back-contact solar cell structures have a fully polished back surface. This uniformly polished back surface design has the following drawbacks: The limited effective contact area between the metal electrode and n+polysi increases the ohmic contact resistance, thereby increasing the series resistance of the battery and reducing the fill factor FF (FF is an abbreviation for Fill Factor, which reflects how close the actual output capacity of the battery is to the ideal limit; the closer the value is to 1 or 100%, the higher the quality of the battery). Moreover, stress concentration occurs on the polished surface, and the stress generated by thermal expansion and contraction during metal sintering cannot be mitigated by the micro-grooves on the textured surface. This makes the tunneling silicon oxide prone to cracking, damaging tunneling passivation, causing a surge in recombination and a decrease in VOC (VOC is an abbreviation for Open Circuit Voltage), thus reducing the battery's conversion efficiency. Summary of the Invention
[0003] This invention provides a method for preparing a back-contact battery, a back-contact battery, and a battery assembly. The aim is to improve the internal reflection efficiency of the battery by designing the topography partitions on the back of the silicon wafer, while increasing the contact area between the metal electrode and the silicon wafer and reducing interfacial recombination losses, thereby improving the battery conversion efficiency.
[0004] Firstly, to achieve the above objectives, the technical solution adopted by the present invention is: to provide a method for preparing a back contact battery, the method comprising: Clean the N-type single-crystal silicon substrate and texturize both sides; Cleaning and polishing removes the velvety texture from the non-electrode areas, creating a polished structure. The textured surface of the back electrode area is retained; A primary tunneling silicon oxide layer and a p+polysi layer are fabricated on the corresponding textured structure on the back side of an N-type single-crystal silicon substrate. A secondary tunneling silicon oxide layer and an n+polysi layer are prepared on the corresponding textured structure on the back side of an N-type single-crystal silicon substrate. Passivation antireflection layers are fabricated on the front and back sides of an N-type single-crystal silicon substrate, and metal electrodes are fabricated on the textured surfaces of p+polysi layers and n+polysi layers.
[0005] In conjunction with the first aspect, in one implementable manner, the method includes the following steps: S10, clean the N-type monocrystalline silicon substrate and texturize both sides; S20, a mask layer is prepared on the textured surface on the back side of an N-type single-crystal silicon substrate; S30, laser grooving, removes the mask layer from the non-electrode area; S40, cleaning and polishing, removes the velvety surface structure of the non-electrode area and forms a polished structure; S50, cleans the mask layer of the back electrode area of the N-type single crystal silicon substrate to expose the textured surface structure of the back electrode area; S60, a primary tunneling silicon oxide layer and a p-type silicon dioxide layer are fabricated on the back side of an N-type single-crystal silicon substrate. + The polysi layer forms a velvety structure accordingly; S70 involves boron diffusion on both the front and back sides of an N-type single-crystal silicon substrate, forming a P-type silicon on the front side. + emitter; S80, laser grooving, to remove the n+polysi region of the primary tunneling silicon oxide layer and p+polysi layer on the back side of the N-type single crystal silicon substrate; S90, cleaning the laser-damaged layer, the primary tunneling silicon oxide layer and the p+polysi layer that extend to the edge of the N-type single crystal silicon substrate; S100, a secondary tunneling silicon oxide layer and an n+polysi layer are prepared on the back side of an N-type single crystal silicon substrate, thereby forming a textured structure accordingly; S110, phosphorus diffusion is performed on the back side of an N-type single-crystal silicon substrate; S120, laser etching, to remove secondary tunneling silicon oxide and n+polysi layer in the p+polysi region on the back side of the N-type single crystal silicon substrate; S130, clean the laser-damaged layer, remove the silicon oxide layer on the back side and the secondary tunneling silicon oxide layer and n+polysi layer that extend to the edge of the N-type single crystal silicon substrate and the front side. S140, passivation antireflection layers are prepared on the front and back sides of an N-type single-crystal silicon substrate, and metal electrodes are prepared on the textured surface of the back electrode region.
[0006] In conjunction with the first aspect, in one feasible manner, the process of cleaning the N-type single-crystal silicon substrate and texturing both sides in S10 includes: S101, texturing: Immerse an N-type single crystal silicon substrate in a KOH solution for texturing. The concentration of the KOH solution is 2%-5%, the temperature is 70℃-90℃, and the duration is 5-15 minutes. S102, rinse with deionized water to dilute the residual KOH solution; S103 is cleaned using a mixed solution of KOH and H2O2, with the KOH solution concentration being 2.5%-5.5% and the H2O2 concentration being 5%-12%, at a temperature of 60℃-75℃ for 2-5 minutes. S104 is cleaned using a mixed acid solution containing sulfur (F) and HCl, with the concentration of the F-containing acid solution being 1%-10% and the concentration of the HCl acid solution being 1%-10%; this removes metal ion contaminants. S105, neutralize and clean with a mixed acid solution of HF and HCl, with the concentration of HF solution being 1%-10% and the concentration of HCl solution being 1%-10%, for 1-5 minutes; S106 was then rinsed again with deionized water.
[0007] In conjunction with the first aspect, in one feasible manner, in S20, a mask layer is prepared on the textured surface on the back side of an N-type single-crystal silicon substrate, including: SiN mask layers were prepared using a PECVD device; the SiH4 flow rate was 2000-3000 sccm, the NH3 flow rate was 10000-15000 sccm, and N2 was used as the carrier gas; the deposition temperature was 360℃-480℃; and the deposition time was 800-1500 seconds.
[0008] In conjunction with the first aspect, in one feasible manner, in S40, cleaning and polishing are performed to remove the textured surface of the non-electrode region and form a polished structure, including: S401 is polished using KOH solution with a concentration of 4%-12%, at a temperature of 60℃-80℃ for 5-20 minutes. S402, use deionized water to wash and dilute the remaining KOH solution; S403 is cleaned using a mixed solution of KOH and H2O2, with the KOH solution concentration being 0.5%-3% and the H2O2 concentration being 4%-12%, at a temperature of 60℃-75℃ for 2-5 minutes. S404 is cleaned by neutralization with a mixture of HF and HCl, with HF concentration of 1%-10% and HCl concentration of 1%-10%, to remove metal ion contaminants in 1-3 minutes. S405 was finally rinsed again with deionized water.
[0009] In conjunction with the first aspect, in one feasible manner, in S50, cleaning the mask layer of the back electrode region of the N-type single-crystal silicon substrate to expose the textured surface structure of the back electrode region includes: A tank-type cleaning device was used to clean the SiN film mask layer on the back side of the N-type single crystal silicon substrate using HF solution.
[0010] In conjunction with the first aspect, in one feasible manner, in S50, the concentration of HF solution is 5%-15%, the time is 5-20 minutes, and the cleaning temperature is room temperature; finally, the residual acid solution is rinsed with deionized water.
[0011] Secondly, embodiments of the present invention also provide a back contact battery, which is fabricated using a back contact battery preparation method. The back contact battery includes an N-type monocrystalline silicon substrate, and textured structures are formed on both the front and back electrode regions of the N-type monocrystalline silicon substrate. On the textured structure of the back anode electrode region, a primary tunneling silicon oxide layer, a p+polysi layer, a back passivation antireflection layer, and an anode metal electrode are disposed in a direction away from the N-type monocrystalline silicon substrate. On the textured structure of the back cathode electrode region, a secondary tunneling silicon oxide layer, an n+polysi layer, a back passivation antireflection layer, and a cathode metal electrode are disposed in a direction away from the N-type monocrystalline silicon substrate. The back passivation antireflection layer covers the back of the N-type monocrystalline silicon substrate and separates the anode metal electrode from the cathode metal electrode.
[0012] In conjunction with the second aspect, in one feasible approach, the mask layer thickness is 90-200 nm.
[0013] Thirdly, embodiments of the present invention also provide a battery assembly, including a back contact battery.
[0014] The method for preparing a back-contact battery provided by this invention, compared with the prior art, differentiates the back side of the battery in design, specifically designing the metal electrode area with a textured surface and the non-electrode area with a polished surface. The advantages are as follows: (1) The metal electrode area is designed with a textured surface. Under the same size, the surface area of the textured surface is larger than that of the polished surface. Therefore, the metal electrode prepared on the textured surface will have a larger contact surface area with the p+polysi layer and n+polysi layer of the textured surface, which can reduce the contact series resistance Rs and increase the fill factor FF. The micro-unevenness of the textured surface can also relieve the metal sintering stress and reduce the local poor soldering of the electrode. The textured surface can also effectively release the stress generated by the thermal expansion and contraction of the metal during sintering, and avoid the tunneling silicon oxide cracking from affecting the passivation effect.
[0015] (2) At the same time, the non-metallic electrode area on the back is designed with a polished structure. Under this design, the remaining photons transmitted from the silicon body to the back are reflected by the polished surface and remain in the silicon wafer, rather than being emitted from the silicon wafer by the diffuse reflection of the textured surface. The polished surface increases the internal reflection of light and extends the optical path, so that the photons are absorbed by the silicon substrate a second time, reducing the loss of long-wave infrared photons from the back, thereby increasing the long-wave short-circuit current Jsc of the battery. Moreover, the defects and dangling bonds on the polished surface are far less than those on the textured surface. The flat polished surface is more conducive to the uniform formation of the passivation anti-reflection film, avoiding the problems of thin coating and passivation failure at the textured groove, thereby increasing the open-circuit voltage Voc of the battery, and finally improving the photoelectric conversion efficiency of the battery.
[0016] In summary, the back-contact battery provided by the embodiments of the present invention has a textured surface structure in the metal electrode area on the back of the battery that can effectively improve the fill factor FF of the battery, and a polished structure in the non-metal electrode area that can effectively improve the long-wave short-circuit current Jsc and open-circuit voltage Voc of the battery, thereby effectively improving the conversion efficiency of the battery.
[0017] It is understandable that the beneficial effects of the third aspect mentioned above can be found in the relevant descriptions in the second aspect above, and will not be repeated here.
[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the structure of a back contact battery provided in an embodiment of the present invention; Explanation of reference numerals in the attached figures: 1. N-type single crystal silicon substrate; 2. Primary tunneling silicon oxide layer; 3. p+ polysi layer; 4. Anode metal electrode; 5. Back passivation antireflection layer; 6. n+ polysi layer; 7. Cathode metal electrode; 8. Secondary tunneling silicon oxide layer; 9. P+ emitter; 10. Front passivation antireflection layer. Detailed Implementation
[0020] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.
[0021] The design concept of this invention is to differentiate the surface morphology of the metal electrode area and the non-metal electrode area on the back of the battery. The electrode area is designed with a textured surface structure, while the non-electrode area is designed with a polished surface structure.
[0022] Please see Figure 1 The preparation method of the back contact battery provided by the present invention will now be described.
[0023] Example 1 Combination Figure 1 As shown, the method for preparing the back contact battery includes the following steps: S10, clean the N-type monocrystalline silicon substrate and texturize both sides; S20, a mask layer is prepared on the textured surface on the back side of an N-type single-crystal silicon substrate; S30, laser grooving, removes the mask layer from the non-electrode area; S40, cleaning and polishing, removes the velvety surface structure of the non-electrode area and forms a polished structure; S50, cleaning removes the mask layer of the back electrode area of the N-type single crystal silicon substrate, exposing the textured structure of the back electrode area; S60, a primary tunneling silicon oxide layer and a p-type silicon dioxide layer are fabricated on the back side of an N-type single-crystal silicon substrate. + The polysi layer forms a velvety structure accordingly; S70 involves boron diffusion on both the front and back sides of an N-type single-crystal silicon substrate, forming a P-type silicon on the front side. + emitter; S80, laser grooving, to remove the n+polysi region of the primary tunneling silicon oxide layer and p+polysi layer on the back side of the N-type single crystal silicon substrate; S90, cleaning to remove the laser-damaged layer, the primary tunneling silicon oxide layer and the p+polysi layer that extend to the edge of the N-type single crystal silicon substrate; S100, a secondary tunneling silicon oxide layer and an n+polysi layer are prepared on the back side of an N-type single crystal silicon substrate, thereby forming a textured structure accordingly; S110, phosphorus diffusion on the back side of an N-type single-crystal silicon substrate; The purpose of phosphorus diffusion on the back side is to achieve the following: Forming the passivation contact structure: After depositing an intrinsic polysilicon layer on the tunneling silicon oxide layer on the back side, phosphorus atoms need to be incorporated into it through phosphorus diffusion. In this way, the tunneling silicon oxide layer and the phosphorus-doped polysilicon layer together constitute the passivation contact structure.
[0024] Achieving field passivation: Heavily doped polycrystalline silicon layers cause band bending on the silicon wafer surface, resulting in a field passivation effect. This effectively reduces recombination on the silicon wafer surface and at metal contacts, thus reducing carrier loss.
[0025] Improving conductivity and crystallization: Phosphorus diffusion transforms the polycrystalline silicon layer from its intrinsic state into a heavily doped N-type (N+) layer, greatly improving its conductivity; at the same time, the high-temperature diffusion process itself also crystallizes the previously deposited amorphous silicon layer, transforming it into polycrystalline silicon.
[0026] S120, laser etching, to remove the secondary tunneling silicon oxide layer and n+polysi layer in the p+polysi region on the back side of the N-type single crystal silicon substrate; S130, cleans the laser-damaged layer, removes the excess silicon oxide layer on the back side and the secondary tunneling silicon oxide layer and n+polysi layer that extend to the edge of the N-type single crystal silicon substrate and the front side; During the high-temperature diffusion process, the gas phase inevitably coats the entire silicon wafer, resulting in the formation of doped layers and phosphosilicate glass on the front and edges of the wafer. These doped layers deposited on the front and edges are harmful and must be completely removed through subsequent single-sided cleaning or etching steps (such as using hydrofluoric acid HF or potassium hydroxide KOH solution) to ensure battery performance.
[0027] S140, passivation antireflection layers are prepared on the front and back sides of an N-type single-crystal silicon substrate, and metal electrodes are prepared on the textured surface of the back electrode region.
[0028] In the embodiments, the n+polysi layer is a polysi layer doped with a P source (phosphorus source); the p+polysi layer is a polysi layer doped with a B source (boron source).
[0029] Example 2 In S10, the process of cleaning the N-type single-crystal silicon substrate and texturing both sides includes: S101, texturing: Immerse an N-type single crystal silicon substrate in a KOH solution for texturing. The concentration of the KOH solution is 2%, the temperature is 70°C, and the duration is 5 minutes. S102, rinse with deionized water to dilute the residual KOH solution; S103 was cleaned using a mixed solution of KOH and H2O2, with a KOH concentration of 2.5% and an H2O2 concentration of 5%, at a temperature of 60°C for 2 minutes. S104 is cleaned using a mixed acid solution containing sulfur (F) and HCl, with the concentration of the F-containing acid solution being 1% and the concentration of the HCl acid solution being 1%; this removes metal ion contaminants. S105, neutralize and clean using a mixed acid solution of HF and HCl, with the concentration of HF solution being 1% and the concentration of HCl solution being 1%, for 1 minute; S106 was then rinsed again with deionized water.
[0030] This process uses a tank-type texturing and cleaning equipment for double-sided texturing, which means that the front and back sides of the N-type single crystal silicon substrate are simultaneously texturized. The front texturing is used for subsequent anti-reflection enhancement, while the back texturing provides a basis for retaining the texturing structure in the subsequent metal electrode area. The texturing in the non-electrode area will be polished and removed in the subsequent process.
[0031] The surface reflectivity of the N-type monocrystalline silicon substrate after texturing is <12%.
[0032] In S20, a mask layer is fabricated on the textured surface on the back side of the N-type single-crystal silicon substrate, including: SiN mask layers were prepared using a PECVD system; the SiH4 flow rate was 2000 sccm, the NH3 flow rate was 10000 sccm, and N2 was used as the carrier gas; the deposition temperature was 360℃; and the deposition time was 800 seconds. The mask layer thickness was 90 nm, which was appropriately increased compared to the thickness of conventional polished mask layers to compensate for the film inhomogeneity caused by the undulations of the textured surface.
[0033] In this process, the mask layer is fabricated on a textured surface, unlike the conventional process of fabricating a mask layer on a polished surface. For the same dimensions, the textured surface, with its pyramidal roughness, has a larger specific surface area compared to a polished surface. This presents greater challenges to the adhesion and film uniformity of the mask layer on the textured surface, thus requiring specialized control of process parameters. Furthermore, due to the larger specific surface area of the textured surface, the actual coverage of a mask layer of the same thickness is greater. The film deposition directionality on the sloped surface of the textured pyramid is affected by geometric shading effects, and the film layer may be thinner at the valleys. This necessitates improving coverage uniformity by increasing deposition power and extending deposition time.
[0034] In S40, cleaning and polishing remove the velvety texture of the non-electrode areas, forming a polished structure, including: S401 was polished using a KOH solution with a concentration of 4%, at a temperature of 60°C for 5 minutes. S402, use deionized water to wash and dilute the remaining KOH solution; S403 was cleaned using a mixed solution of KOH and H2O2, with a KOH concentration of 0.5% and an H2O2 concentration of 4%, at a temperature of 60°C for 2 minutes. S404 was cleaned by neutralization with a mixture of HF and HCl, with HF concentration of 1% and HCl concentration of 1%, to remove metal ion contaminants in 1 minute. S405 was finally rinsed again with deionized water.
[0035] This process uses a tank cleaning device. After the mask layer of the non-electrode area is removed by laser grooving, the textured surface of the non-electrode area is polished to transform it into a polished surface structure. At the same time, the laser-damaged layer is cleaned.
[0036] The surface reflectivity of the polished N-type single-crystal silicon substrate is >35%.
[0037] In S50, the mask layer of the back electrode region of the N-type single-crystal silicon substrate is cleaned to expose the textured surface structure of the back electrode region, including: A tank-type cleaning device was used to remove the SiN film mask layer on the back side of the N-type single crystal silicon substrate using HF solution. The concentration of HF solution was 5%, the cleaning time was 5 minutes, and the cleaning temperature was room temperature. Finally, deionized water was used to rinse off the residual acid solution.
[0038] Example 3 In S10, the process of cleaning the N-type single-crystal silicon substrate and texturing both sides includes: S101, texturing: Immerse an N-type single crystal silicon substrate in a KOH solution for texturing. The concentration of the KOH solution is 5%, the temperature is 90℃, and the duration is 15 minutes. S102, rinse with deionized water to dilute the residual KOH solution; S103 was cleaned using a mixed solution of KOH and H2O2, with a KOH concentration of 5.5% and an H2O2 concentration of 12%, at a temperature of 75°C for 5 minutes. S104 is cleaned using a mixed acid solution containing sulfur (F) and HCl, with both the F-containing acid solution and the HCl solution having a concentration of 10%; this removes metal ion contaminants. S105, neutralize and clean using a mixed acid solution of HF and HCl, with the concentration of HF solution being 10% and the concentration of HCl solution being 10%, for 5 minutes; S106 was then rinsed again with deionized water.
[0039] The surface reflectivity of the N-type monocrystalline silicon substrate after texturing is <12%.
[0040] In S20, a mask layer is fabricated on the textured surface on the back side of the N-type single-crystal silicon substrate, including: A SiN mask layer was prepared using a PECVD apparatus; the SiH4 flow rate was 3000 sccm, the NH3 flow rate was 15000 sccm, and N2 was used as the carrier gas; the deposition temperature was 480℃; and the deposition time was 1500 seconds. The mask layer thickness was 200 nm.
[0041] In S40, cleaning and polishing remove the velvety texture of the non-electrode areas, forming a polished structure, including: S401 was polished using a KOH solution with a concentration of 12% at a temperature of 80°C for 20 minutes. S402, use deionized water to wash and dilute the remaining KOH solution; S403 was cleaned using a mixed solution of KOH and H2O2, with a KOH concentration of 3% and an H2O2 concentration of 12%, at a temperature of 75°C for 5 minutes. S404 was cleaned by neutralization with a mixture of HF and HCl, with HF concentration of 10% and HCl concentration of 10%, to remove metal ion contaminants in 3 minutes. S405 was finally rinsed again with deionized water.
[0042] The surface reflectivity of the polished N-type single-crystal silicon substrate is >35%.
[0043] In S50, the mask layer of the back electrode region of the N-type single-crystal silicon substrate is cleaned to expose the textured surface structure of the back electrode region, including: A tank-type cleaning device was used to remove the SiN film mask layer on the back side of the N-type single crystal silicon substrate using HF solution. The concentration of HF solution was 15%, the cleaning time was 20 minutes, and the cleaning temperature was room temperature. Finally, the residual acid solution was rinsed with deionized water.
[0044] Example 4 In S10, the process of cleaning the N-type single-crystal silicon substrate and texturing both sides includes: S101, texturing: Immerse an N-type single crystal silicon substrate in a KOH solution for texturing. The concentration of the KOH solution is 3%, the temperature is 80℃, and the duration is 10 minutes. S102, rinse with deionized water to dilute the residual KOH solution; S103 was cleaned using a mixed solution of KOH and H2O2, with a KOH concentration of 4% and an H2O2 concentration of 8%, at a temperature of 65°C for 4 minutes. S104 is cleaned using a mixed acid solution containing sulfur (F) and HCl, with the F-containing acid solution having a concentration of 6% and the HCl acid solution having a concentration of 5%; this removes metal ion contaminants. S105, neutralize and clean using a mixed acid solution of HF and HCl, with a concentration of 6% for both solutions, for 3 minutes. S106 was then rinsed again with deionized water.
[0045] The surface reflectivity of the N-type monocrystalline silicon substrate after texturing is <12%.
[0046] In S20, a mask layer is fabricated on the textured surface on the back side of the N-type single-crystal silicon substrate, including: A SiN mask layer was prepared using a PECVD apparatus; the SiH4 flow rate was 2500 sccm, the NH3 flow rate was 12000 sccm, and N2 was used as the carrier gas; the deposition temperature was 400℃; and the deposition time was 1000 seconds. The thickness of the mask layer was 100 nm.
[0047] In S40, cleaning and polishing remove the velvety texture of the non-electrode areas, forming a polished structure, including: S401 was polished using KOH solution at a concentration of 8% at a temperature of 70°C for 15 minutes. S402, use deionized water to wash and dilute the remaining KOH solution; S403 was cleaned using a mixed solution of KOH and H2O2, with a KOH concentration of 1.5% and an H2O2 concentration of 8%, at a temperature of 65°C for 3 minutes. S404 was cleaned by neutralization with a mixture of HF and HCl, with a concentration of 6% for both HF and HCl, to remove metal ion contaminants over a period of 2 minutes. S405 was finally rinsed again with deionized water.
[0048] In S50, the mask layer of the back electrode region of the N-type single-crystal silicon substrate is removed by cleaning, exposing the textured structure of the back electrode region, including: A tank-type cleaning device was used to remove the SiN film mask layer on the back side of the N-type single crystal silicon substrate by cleaning with HF solution; the concentration of HF solution was 10%, the time was 15 minutes, and the cleaning temperature was room temperature; finally, the residual acid solution was rinsed with deionized water.
[0049] Table 1 compares the batteries prepared using this invention with existing polished surfaces: Table 1 As can be seen from the comparative data in Table 1, the back contact battery prepared by the present invention has improved fill factor FF, long-wave short-circuit current Jsc and open-circuit voltage Voc, and the battery conversion efficiency has also been improved.
[0050] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0051] Based on the same inventive concept, embodiments of the present invention also provide a back contact battery, such as... Figure 1 As shown, a back-contact battery is fabricated using a back-contact battery fabrication method. The back-contact battery includes an N-type monocrystalline silicon substrate 1, with textured structures formed on both the front and back electrode regions of the N-type monocrystalline silicon substrate 1. On the textured structure of the back anode electrode region, a primary tunneling silicon oxide layer 2, a p+ polysi layer 3, a back passivation antireflection layer 5, and an anode metal electrode 4 are disposed in the direction away from the N-type monocrystalline silicon substrate 1. On the textured structure of the back cathode electrode region, a secondary tunneling silicon oxide layer 8, an n+ polysi layer 6, a back passivation antireflection layer 5, and a cathode metal electrode 7 are disposed in the direction away from the N-type monocrystalline silicon substrate 1. The back passivation antireflection layer 5 covers the back of the N-type monocrystalline silicon substrate 1 and separates the anode metal electrode 4 and the cathode metal electrode 7. On the front of the N-type monocrystalline silicon substrate 1, a p+ emitter 9 and a front passivation antireflection layer 10 are sequentially arranged.
[0052] The mask layer thickness ranges from 90 to 200 nm. For example, mask layer thicknesses include 90 nm, 92 nm, 95 nm, 98 nm, 100 nm, 106 nm, 110 nm, 125 nm, 130 nm, 140 nm, 148 nm, 151 nm, 159 nm, 160 nm, 167 nm, 170 nm, 173 nm, 180 nm, 186 nm, 190 nm, 195 nm, and 200 nm.
[0053] The back-contact battery provided in this embodiment of the invention features a textured surface design for the metal electrode area on the back, which increases the contact area with the metal electrode and thus improves the fill factor FF. The polished surface design for the non-metal electrode area on the back increases internal light reflection, thereby improving the short-circuit current Jsc of the battery. Furthermore, the polished surface has far fewer defects and dangling bonds than the textured surface, and the smooth polished surface is more conducive to the uniform formation of the passivation antireflection film, avoiding the problems of thin coating and passivation failure at the textured grooves. This improves the open-circuit voltage Voc of the battery and ultimately enhances the photoelectric conversion efficiency of the battery.
[0054] The preparation method of the present invention is also applicable to the preparation of back contact batteries such as half-cell, three-cell, and four-cell batteries.
[0055] Based on the same inventive concept, embodiments of the present invention also provide a battery assembly, including a back contact battery.
[0056] The battery assembly provided in this embodiment of the invention has the same effect as the back contact battery, with improvements in fill factor FF, long-wave short-circuit current Jsc and open-circuit voltage Voc, and improved battery conversion efficiency.
[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for preparing a back-contact battery, characterized in that, The method includes: Clean the N-type single-crystal silicon substrate and texturize both sides; Cleaning and polishing removes the velvety texture from the non-electrode areas, creating a polished structure. The textured surface of the back electrode area is retained; A primary tunneling silicon oxide layer and a p+polysi layer are fabricated on the corresponding textured structure on the back side of an N-type single-crystal silicon substrate. A secondary tunneling silicon oxide layer and an n+polysi layer are prepared on the corresponding textured structure on the back side of an N-type single-crystal silicon substrate. Passivation antireflection layers are fabricated on the front and back sides of an N-type single-crystal silicon substrate, and metal electrodes are fabricated on the textured surfaces of p+polysi layers and n+polysi layers.
2. The method for preparing a back contact battery as described in claim 1, characterized in that, The method includes the following steps: S10, clean the N-type monocrystalline silicon substrate and texturize both sides; S20, a mask layer is prepared on the textured surface on the back side of an N-type single-crystal silicon substrate; S30, laser grooving, removes the mask layer from the non-electrode area; S40, cleaning and polishing, removes the velvety surface structure of the non-electrode area and forms a polished structure; S50, cleaning removes the mask layer of the back electrode area of the N-type single crystal silicon substrate, exposing the textured structure of the back electrode area; S60, a primary tunneling silicon oxide layer and a p-type silicon dioxide layer are fabricated on the back side of an N-type single-crystal silicon substrate. + The polysi layer forms a velvety structure accordingly; S70 involves boron diffusion on both the front and back sides of an N-type single-crystal silicon substrate, forming a P-type silicon on the front side. + emitter; S80, laser grooving, to remove the n+polysi region of the primary tunneling silicon oxide layer and p+polysi layer on the back side of the N-type single crystal silicon substrate; S90, cleaning to remove the laser-damaged layer, the primary tunneling silicon oxide layer and the p+polysi layer that extend to the edge of the N-type single crystal silicon substrate; S100, a secondary tunneling silicon oxide layer and an n+polysi layer are prepared on the back side of an N-type single crystal silicon substrate, thereby forming a textured structure accordingly; S110, phosphorus diffusion is performed on the back side of an N-type single-crystal silicon substrate; S120, laser etching, to remove secondary tunneling silicon oxide and n+polysi layer in the p+polysi region on the back side of the N-type single crystal silicon substrate; S130, clean the laser-damaged layer, remove the silicon oxide layer on the back side and the secondary tunneling silicon oxide layer and n+polysi layer that extend to the edge of the N-type single crystal silicon substrate and the front side. S140, passivation antireflection layers are prepared on the front and back sides of an N-type single-crystal silicon substrate, and metal electrodes are prepared on the textured surface of the back electrode region.
3. The method for preparing a back contact battery as described in claim 2, characterized in that, In S10, the process of cleaning the N-type single-crystal silicon substrate and texturing both sides includes: S101, texturing: Immerse an N-type single crystal silicon substrate in a KOH solution for texturing. The concentration of the KOH solution is 2%-5%, the temperature is 70℃-90℃, and the duration is 5-15 minutes. S102, rinse with deionized water to dilute the residual KOH solution; S103 is cleaned using a mixed solution of KOH and H2O2, with the KOH solution concentration being 2.5%-5.5% and the H2O2 concentration being 5%-12%, at a temperature of 60℃-75℃ for 2-5 minutes. S104 is cleaned using a mixed acid solution containing sulfur (F) and HCl, with the concentration of the F-containing acid solution being 1%-10% and the concentration of the HCl acid solution being 1%-10%; this removes metal ion contaminants. S105, neutralize and clean with a mixed acid solution of HF and HCl, with the concentration of HF solution being 1%-10% and the concentration of HCl solution being 1%-10%, for 1-5 minutes; S106 was then rinsed again with deionized water.
4. The method for preparing a back contact battery as described in claim 2, characterized in that, In S20, a mask layer is fabricated on the textured surface on the back side of the N-type single-crystal silicon substrate, including: SiN mask layers were prepared using a PECVD device; the SiH4 flow rate was 2000-3000 sccm, the NH3 flow rate was 10000-15000 sccm, and N2 was used as the carrier gas; the deposition temperature was 360℃-480℃; and the deposition time was 800-1500 seconds.
5. The method for preparing a back contact battery as described in claim 2, characterized in that, In S40, cleaning and polishing remove the velvety texture of the non-electrode areas, forming a polished structure, including: S401 is polished using KOH solution with a concentration of 4%-12%, at a temperature of 60℃-80℃ for 5-20 minutes. S402, use deionized water to wash and dilute the remaining KOH solution; S403 is cleaned using a mixed solution of KOH and H2O2, with the KOH solution concentration being 0.5%-3% and the H2O2 concentration being 4%-12%, at a temperature of 60℃-75℃ for 2-5 minutes. S404 is cleaned by neutralization with a mixture of HF and HCl, with HF concentration of 1%-10% and HCl concentration of 1%-10%, to remove metal ion contaminants in 1-3 minutes. S405 was finally rinsed again with deionized water.
6. The method for preparing a back contact battery as described in claim 2, characterized in that, In S50, the mask layer of the back electrode region of the N-type single-crystal silicon substrate is removed by cleaning, exposing the textured structure of the back electrode region, including: A tank-type cleaning device was used to remove the SiN film mask layer on the back side of the N-type single crystal silicon substrate by cleaning with HF solution.
7. The method for preparing a back contact battery as described in claim 6, characterized in that, The concentration of HF solution is 5%-15%, the time is 5-20 minutes, and the cleaning temperature is room temperature; finally, rinse the residual acid solution with deionized water.
8. A back contact battery, prepared by the method for preparing a back contact battery as described in claim 1, characterized in that, The back contact battery includes an N-type monocrystalline silicon substrate (1), and textured structures are formed on both the front and back electrode areas of the N-type monocrystalline silicon substrate (1). On the textured structure of the back anode electrode area, a primary tunneling silicon oxide layer (2), a p+polysi layer (3), a back passivation antireflection layer (5), and an anode metal electrode (4) are disposed in the direction away from the N-type monocrystalline silicon substrate (1). On the textured structure of the back cathode electrode area, a secondary tunneling silicon oxide layer (8), an n+polysi layer (6), a back passivation antireflection layer (5), and a cathode metal electrode (7) are disposed in the direction away from the N-type monocrystalline silicon substrate (1). The back passivation antireflection layer (5) covers the back of the N-type monocrystalline silicon substrate (1) and separates the anode metal electrode (4) from the cathode metal electrode (7).
9. The back contact battery as described in claim 8, characterized in that, The mask layer thickness is 90-200nm.
10. A battery assembly, characterized in that, Includes the back contact battery as described in claim 8 or 9.