Display device and electronic device including the same

Abstract

The present disclosure relates to display devices and electronic devices including the same. The present disclosure provides a display device including a substrate, first scan lines disposed on the substrate and extending in a first direction, and second scan lines extending in the first direction. The first scan lines include first-first scan lines and first-second scan lines disposed in different layers. The second scan lines include second-first scan lines and second-second scan lines disposed in different layers, and the first scan lines and the second scan lines are disposed to intersect each other. In some aspects, the display device further includes a pixel unit including eight sub-pixels, wherein four sub-pixels are arranged in a first row and the other four sub-pixels are arranged in a second row, and each sub-pixel circuit is electrically connected to a corresponding sub-pixel. The first scan lines and the second scan lines transmit signals to the sub-pixel circuits electrically connected to the four sub-pixels arranged in the first row and the second row, respectively.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2025-0058486, filed on May 2, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to display devices and electronic devices including display devices. More specifically, this disclosure relates to display devices with improved reliability and quality, and electronic devices including such display devices. Background Technology

[0004] Display devices visually display data. Display devices can use light-emitting diodes (LEDs) to provide images. As the applications of display devices become increasingly diverse, various designs have been explored to improve their quality.

[0005] Therefore, there is a need for display devices with improved reliability and image quality. Summary of the Invention

[0006] This disclosure aims to address problems including improved reliability and image quality. This disclosure describes a display device with improved reliability and quality, as well as an electronic device including the intended display device.

[0007] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the specific embodiments of this disclosure given below.

[0008] According to some embodiments, a display device is provided, the display device comprising: a substrate; a first scan line disposed on the substrate, extending in a first direction, and including a first-first scan line and a first-second scan line disposed in different layers; and a second scan line extending in the first direction, the second scan line including a second-first scan line and a second-second scan line disposed in different layers, wherein the first scan line and the second scan line are configured to intersect each other.

[0009] According to some implementations, on the cross-section of the substrate, the first-first scan line is disposed below the first-second scan line.

[0010] According to some implementations, the first-first scan line and the first-second scan line are electrically connected through a first contact hole.

[0011] According to some implementations, at least a portion of the first-second scan lines overlaps with the first-first scan lines.

[0012] According to some embodiments, on the cross-section of the substrate, the second-first scan line is disposed below the second-second scan line.

[0013] According to some embodiments, the second-first scan line and the second-second scan line are electrically connected through a second contact hole.

[0014] According to some implementations, at least a portion of the second-second scan line overlaps with the second-first scan line.

[0015] According to some implementations, the first-first scan line and the second-first scan line are disposed on the same layer.

[0016] According to some implementations, in a second direction intersecting the first direction, the first-first scan line and the second-first scan line are arranged at the same position.

[0017] According to some implementations, the first-second scan line and the second-second scan line are disposed on the same layer.

[0018] According to some implementations, in a second direction intersecting the first direction, the first-second scan line and the second-second scan line are arranged at the same position.

[0019] According to some embodiments, the display device further includes: a pixel unit disposed on a substrate and comprising eight sub-pixels, wherein four of the eight sub-pixels of the pixel unit are arranged in a first row, and the other four of the eight sub-pixels of the pixel unit are arranged in a second row.

[0020] According to some implementations, the eight sub-pixels in the pixel unit are arranged in a PenTile array.

[0021] According to some embodiments, the display device further includes: a pixel circuit unit, comprising eight sub-pixel circuits, each of the eight sub-pixel circuits being electrically connected to a corresponding sub-pixel among the eight sub-pixels in the pixel unit.

[0022] According to some implementations, the eight sub-pixel circuits of the pixel circuit unit are arranged in a first direction.

[0023] According to some implementations, the first scan line transmits signals to sub-pixel circuits electrically connected to four sub-pixels arranged in the first row.

[0024] According to some implementations, the second scan line transmits signals to sub-pixel circuits electrically connected to four sub-pixels arranged in the second row.

[0025] According to some implementations, the first scan line and the second scan line intersect by passing through two sub-pixel circuits arranged in a first direction.

[0026] According to some embodiments, an electronic device is provided, comprising: a display panel; and a lower cover forming an outer surface and having an opening exposing a portion of the display panel, wherein the display panel comprises: a substrate; a pixel unit disposed on the substrate and comprising eight sub-pixels, wherein four of the eight sub-pixels of the pixel unit are arranged in a first row, and the other four of the eight sub-pixels of the pixel unit are arranged in a second row; a pixel circuit unit comprising eight sub-pixel circuits arranged in a first direction, and each of the eight sub-pixel circuits being electrically connected to a corresponding sub-pixel among the eight sub-pixels of the pixel unit; a first scan line disposed on the substrate, extending in the first direction, and comprising a first-first scan line and a first-second scan line disposed in different layers; and a second scan line extending in the first direction, the second scan line comprising a second-first scan line and a second-second scan line disposed in different layers; wherein the first scan line is configured to transmit a signal to the sub-pixel circuits electrically connected to the four sub-pixels arranged in the first row, the second scan line is configured to transmit a signal to the sub-pixel circuits electrically connected to the four sub-pixels arranged in the second row, and the first scan line and the second scan line are arranged to intersect each other.

[0027] According to some embodiments, in the cross-section of the substrate, the first-first scan line is disposed below the first-second scan line, and the second-first scan line is disposed below the second-second scan line.

[0028] The advantages of the display device disclosed herein are not limited to those described above, and various other effects are described in the following detailed embodiments. Attached Figure Description

[0029] The above and other aspects, features and advantages of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which: Figure 1 This is a block diagram of a central processing unit according to an embodiment of the present disclosure; Figure 2 This is a schematic diagram of an electronic device according to some embodiments of the present disclosure; Figure 3 This is a schematic perspective view of a display device according to an embodiment of the present disclosure; Figure 4 This is a schematic equivalent circuit diagram of a sub-pixel of a display panel according to an embodiment of the present disclosure; Figure 5 This is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure; Figure 6 This is a schematic plan view of a structure in which pixels of a display panel are arranged according to an embodiment of the present disclosure; Figure 7 This is a schematic plan view of a structure with sub-pixel circuits arranged according to an embodiment of the present disclosure; Figure 8 This is a schematic layout diagram showing the positions of a plurality of thin-film transistors and capacitors included in a sub-pixel circuit of a display device according to an embodiment of the present disclosure; Figure 9 This is a schematic plan view of scan lines and node connection lines included in a sub-pixel circuit according to embodiments of the present disclosure; and Figure 10 yes Figure 9 A schematic cross-sectional view of the scan lines shown. Detailed Implementation

[0030] While specific embodiments are illustrated in the accompanying drawings and described in detail herein, this disclosure can be modified in various ways and implemented in many different forms. Therefore, it will be understood that this disclosure is not limited to the specific form disclosed and should be construed as including all modifications, equivalents, or substitutions contained within the spirit and scope of this disclosure.

[0031] Furthermore, for ease of description, spatial relative terms such as “below,” “lower,” “above,” and “upper” may be used in this document to describe the relationship between one element or feature and another element or feature as shown in the accompanying drawings.

[0032] It should also be understood that when a layer is referred to as being "on" another layer or substrate, it may be directly on the other layer or substrate, or one or more intervening layers may also be present. Throughout the specification, the same reference numerals indicate the same parts.

[0033] In the following description, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, the same or corresponding parts are given the same reference numerals, and redundant descriptions thereof are omitted.

[0034] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0035] It will also be understood that, when used in this specification, the terms “include” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or groups thereof.

[0036] Furthermore, the terms “about,” “usually,” and “basically” are intended (and will be understood by a person of ordinary skill to mean) slight deviations from absolute values ​​included within the scope of such modified terms.

[0037] In the examples below, unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0038] In the examples below, terms such as “including” or “having” mean that the features or components described in the specification are present, without pre-excluding the possibility that one or more other features or components may be added.

[0039] In the examples below, when a part such as a membrane, region, component, etc. is referred to as being on or above another part, it includes not only the case where the part is directly on top of the other part, but also the case where another membrane, region, component, etc. is inserted between the part and the other part.

[0040] In the accompanying drawings, the dimensions of the components may be enlarged or reduced for ease of illustration. For example, the dimensions and thicknesses of each component shown in the drawings are arbitrarily depicted for ease of illustration, and therefore this disclosure is not necessarily limited to what is shown.

[0041] In some implementations, where the implementation is otherwise feasible, the specific process sequence can be performed in a different order than that described. For example, the two processes described in the sequence can be performed substantially simultaneously, or they can be performed in the reverse order of the described sequence.

[0042] In this specification, “A and / or B” refers to A, B, or both A and B, and “at least one of A and B” indicates either A or B, or both A and B.

[0043] In the following examples, when referring to the connection of membranes, regions, components, etc., it includes cases where the membranes, regions, or components are directly connected, and / or cases where another membrane, region, or component is inserted between them and they are indirectly connected. For example, when referring to electrical connections of membranes, regions, components, etc. in this specification, it refers to cases where the membranes, regions, components, etc. are directly electrically connected, and / or cases where another membrane, region, component, etc. is inserted between them and they are indirectly electrically connected.

[0044] The x-axis, y-axis, and z-axis are not limited to three axes in an orthogonal coordinate system, and can be interpreted in a broad sense that includes them. For example, the x-axis, y-axis, and z-axis can be orthogonal to each other, but they can also refer to different directions that are not orthogonal to each other.

[0045] The display device according to the embodiments may be included in various electronic devices. In some aspects, the electronic device according to the embodiments includes the display device described above, and may also include modules or devices with additional functions in addition to the display device.

[0046] Figure 1 This is a block diagram of a central processing unit according to an embodiment of the present disclosure.

[0047] refer to Figure 1 According to one embodiment, the electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0048] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0049] The data required for the operation of the processor 12 or the display module 11 can be stored in the memory 13. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals are sent to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0050] The power module 14 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0051] At least one of the components of the electronic device 10 described above may be included in the display device according to the embodiments described above. Furthermore, some of the individual modules functionally included within the module may be included in the display device, while other modules may be provided separately from the display device. For example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided within the electronic device 10 in the form of other devices besides the display device.

[0052] Figure 2 This is a schematic diagram of an electronic device according to some embodiments.

[0053] refer to Figure 2Electronic devices including display devices can include not only image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e, but also wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c, as well as vehicle electronic devices 10_3 including display modules such as CID (central information display) and interior mirror displays arranged on dashboards, center consoles, and vehicle instrument panels.

[0054] Figure 3 This is a schematic perspective view of a display device according to an embodiment.

[0055] refer to Figure 3 The display device 1 may include a display area DA and a peripheral area PA arranged around the display area DA. The peripheral area PA may surround the display area DA. The display device 1 may provide an image using light emitted from pixels P arranged in the display area DA, and the peripheral area PA may be a non-display area where no image is displayed.

[0056] In the following description, organic light-emitting display devices will be used as examples of display device 1 according to embodiments, but the display device is not limited thereto. In one embodiment, display device 1 may be an inorganic light-emitting display (or an inorganic EL display) or a display device such as a quantum dot light-emitting display. For example, the light-emitting layer of the display element disposed in display device 1 may include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, or inorganic materials and quantum dots.

[0057] Figure 3 A display device 1 having a flat display surface is shown, but the present disclosure is not limited thereto. In one embodiment, the display device 1 may include a three-dimensional display surface or a curved display surface.

[0058] Figure 3 A display device 1, which may be included in a mobile phone terminal, is shown. Although not shown, the mobile phone terminal can be configured by arranging electronic modules, camera modules, power modules, etc., mounted on a motherboard together with the display device 1 in a bracket / housing or the like. Specifically, the display device 1 can be applied to large electronic devices such as televisions and monitors, as well as small and medium-sized electronic devices such as tablets, car navigation systems, game consoles, and smartwatches.

[0059] exist Figure 3 In the diagram, the display area DA of the display device 1 is shown as a square, but the shape of the display area DA can be a circle, an ellipse, or a polygon such as a triangle or a pentagon.

[0060] Display device 1 may include pixels P arranged in display area DA. Each pixel P may include an organic light-emitting diode (OLED). Each pixel P may emit light, for example, red, green, blue, or white light via the organic light-emitting diode (OLED). As described above, pixel P can be understood as a pixel that emits light of one color among red, green, blue, and white.

[0061] Figure 4 This is a schematic equivalent circuit diagram of a sub-pixel of a display panel according to an embodiment.

[0062] refer to Figure 4 The subpixel circuit PC may include multiple thin-film transistors and at least one capacitor. For example, the subpixel circuit PC may include at least one driving transistor, at least one switching transistor, and at least one capacitor. For example, the subpixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a storage capacitor Cst, and a holding capacitor Chd.

[0063] The first transistor T1 is a driving transistor that outputs a driving current corresponding to the data signal, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be switching transistors that transmit signals by turning on / off. The first terminal (first electrode) of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be a source region or a drain region, and the second terminal (second electrode) can be another region.

[0064] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be a PMOS (P-channel MOSFET), and the remaining transistors can be NMOS (N-channel MOSFETs). For example, the fifth transistor T5 can be a PMOS, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 can be NMOS. Alternatively, the fifth transistor T5 and the sixth transistor T6 can be PMOS, and the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be NMOS. Or, all transistors can be NMOS, or all transistors can be PMOS.

[0065] At least one of the transistors may be a transistor with a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and the remaining transistors may be transistors with an oxide semiconductor layer. For example, the fifth transistor T5 may include a semiconductor layer made of polycrystalline silicon with high reliability, and each of the remaining transistors may include an oxide semiconductor layer with characteristics of high carrier mobility and low leakage current. The following describes the case where the fifth transistor T5 is a PMOS including a silicon semiconductor layer and the remaining transistors are NMOS including oxide semiconductor layers.

[0066] The sub-pixel circuit PC can be electrically connected to the gate line that transmits signals to the gate electrode of each of the transistors. For example, the sub-pixel circuit PC can be connected to the scan line GWL that transmits the scan signal GW, the initialization gate line GBL that transmits the initialization signal GB, the reference gate line GRL that transmits the reference signal GR, the first transmit control line EML that transmits the first transmit control signal EM, the second transmit control line EMBL that transmits the second transmit control signal EMB, and the data line DL that transmits the data signal DATA. Furthermore, the sub-pixel circuit PC can be connected to the drive voltage line PL that transmits the drive voltage ELVDD, the reference voltage line VRL that transmits the reference voltage VREF, and the initialization voltage line VL that transmits the initialization voltage VINT.

[0067] A first transistor T1, acting as a driving transistor, can be electrically connected between the driving voltage line PL and the second node N2. The first transistor T1 may include a first gate electrode G1 connected to the first node N1, a first terminal electrically connected to the driving voltage line PL, and a second terminal connected to the second node N2. The first terminal may be the drain region, and the second terminal may be the source region. The first terminal of the first transistor T1 can be electrically connected to the driving voltage line PL via a fifth transistor T5, and the second terminal of the first transistor T1 can be electrically connected to the pixel electrode of the light-emitting diode (LED). The first transistor T1 can receive a data signal DATA and control the amount of driving current Id flowing to the LED based on the switching operation of the second transistor T2.

[0068] A second transistor T2, acting as a data writing transistor, can be electrically connected between the data line DL and the first node N1. The second transistor T2 may include a gate electrode connected to the scan line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second transistor T2 is turned on by the scan signal GW transmitted to the scan line GWL to electrically connect the data line DL and the first node N1, thereby transmitting the data signal DATA from the data line DL to the first node N1.

[0069] The third transistor T3, serving as the first initialization transistor, can be electrically connected between the first node N1 and the reference voltage line VRL. The third transistor T3 may include a gate electrode connected to the reference gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The third transistor T3 is turned on by a reference signal GR transmitted to the reference gate line GRL, and can transmit the reference voltage VREF from the reference voltage line VRL to the first node N1.

[0070] The fourth transistor T4, serving as the second initialization transistor, can be electrically connected between the first transistor T1 and the initialization voltage line VL. The fourth transistor T4 may include a gate electrode connected to the initialization gate line GBL, a second terminal connected to the sixth transistor T6 and the first terminal connected to the light-emitting diode (LED), and a second terminal connected to the initialization voltage line VL. The fourth transistor T4 is turned on by the initialization signal GB transmitted to the initialization gate line GBL, and can transmit the initialization voltage VINT from the initialization voltage line VL to the pixel electrode of the LED. That is, the fourth transistor T4 can initialize the potential of the pixel electrode of the LED to the initialization voltage VINT.

[0071] The fifth transistor T5, serving as the light-emitting control transistor, can be electrically connected between the drive voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate electrode connected to the first emitter control line EML, a first terminal connected to the drive voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 can be turned on or off according to a first emitter control signal EM from the first emitter control line EML.

[0072] A sixth transistor T6, serving as the motion control transistor, can be connected between the first transistor T1 and the light-emitting diode (LED). The sixth transistor T6 may include a gate electrode connected to the second emission control line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the LED. The sixth transistor T6 is turned on by a second emission control signal EMB from the second emission control line EMBL to electrically connect the second node N2 and the pixel electrode of the LED.

[0073] For reference only. Figure 4 The diagram shows a fifth transistor T5 operating in response to a first emission control signal EM, and a sixth transistor T6 operating in response to a second emission control signal EMB; however, this disclosure is not limited thereto. For example, the fifth transistor T5 and the sixth transistor T6 may operate in response to the same emission control signal.

[0074] For reference, the reference signal GR can actually be synchronized with the scan signal GW of the sub-pixel circuit PC arranged in the previous row. The initialization signal GB can actually be synchronized with the scan signal GW. Alternatively, the initialization signal GB can be substantially synchronized with the scan signal GW or the reference signal GR of the sub-pixel circuit PC arranged in the next row.

[0075] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2. That is, the sub-pixel circuit PC included in the display panel according to the embodiment can be a source follower type circuit in which the storage capacitor Cst is connected between the first node N1 and the second node N2. The first storage electrode CEs1 of the storage capacitor Cst can be connected to the first node N1, and the second storage electrode CEs2 can be connected to the second node N2. The storage capacitor Cst can store a voltage corresponding to the threshold voltage of the first transistor T1 and the data signal DATA.

[0076] A holding capacitor Chd can be connected between the drive voltage line PL and the second node N2. The first holding electrode CEh1 of the holding capacitor Chd can be electrically connected to the drive voltage line PL, and the second holding electrode CEh2 can be electrically connected to the second node N2. The holding capacitor Chd ensures that the voltage at the second node N2 of the first transistor T1 remains constant despite fluctuations in surrounding signals.

[0077] A light-emitting diode (LED) includes a pixel electrode electrically connected to a second node N2 and a common electrode above the pixel electrode, and the common electrode can be supplied with a common voltage ELVSS. The common electrode can be integrated into multiple LEDs.

[0078] exist Figure 4 In the diagram, the subpixel circuit PC is shown to include six transistors and two capacitors, but this disclosure is not limited thereto. For example, the subpixel circuit PC may contain five transistors and two capacitors. The subpixel circuit PC may contain seven transistors and one capacitor.

[0079] Figure 5 This is a schematic cross-sectional view of the display panel according to the embodiment.

[0080] Specifically, Figure 5 A cross-section of a subpixel PX in the display panel is shown, and some parts may be omitted. References will be made below. Figure 5 Describe in detail the multilayer films stacked on the display device.

[0081] refer to Figure 5 The display panel may include a substrate 100, a buffer layer 111, a sub-pixel circuit layer PCL, a display element layer DEL, and a thin film encapsulation layer TFE.

[0082] Substrate 100 may be glass, or may include polymeric resins such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc. Substrate 100 comprising polymeric resins may have flexible, rollable, and bendable properties. Substrate 100 may have a multilayer structure including a base layer and a barrier layer (not shown), wherein the base layer comprises the aforementioned polymeric resins.

[0083] The buffer layer 111 may include inorganic insulating materials such as silicon nitride, silicon oxide, and silicon oxide, and may be a single layer or multiple layers including the aforementioned inorganic insulating materials.

[0084] The sub-pixel circuit layer PCL can be disposed on the buffer layer 111. The sub-pixel circuit layer PCL may include a thin-film transistor (TFT) contained in the sub-pixel circuit and an inorganic insulating layer IIL, a first planarization layer 116, and a second planarization layer 117 disposed below and / or above the components of the thin-film transistor TFT. The inorganic insulating layer IIL may include a first gate insulating layer 112, a second gate insulating layer 113, a third gate insulating layer 114, and an interlayer insulating layer 115.

[0085] A thin-film transistor (TFT) includes a semiconductor layer A, which may include polycrystalline silicon. Alternatively, semiconductor layer A may include amorphous silicon, oxide semiconductor, organic semiconductor, etc. Semiconductor layer A may include a channel region and drain and source regions respectively disposed on both sides of the channel region. The gate electrode G may overlap with the channel region.

[0086] The gate electrode G may include a low-resistance metallic material. The gate electrode G may include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be formed as a multilayer or a single layer comprising the above materials.

[0087] The first gate insulating layer 112 between the semiconductor layer A and the gate electrode G may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon nitride oxide (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) x Inorganic insulating materials, such as zinc oxide (ZnO). x () can be ZnO and / or ZnO2.

[0088] The second gate insulating layer 113 can be configured to cover the gate electrode G. Similar to the first gate insulating layer 112, the second gate insulating layer 113 can include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon nitride oxide (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) x Inorganic insulating materials, such as zinc oxide (ZnO). x () can be ZnO and / or ZnO2.

[0089] The upper electrode CE2 of the storage capacitor Cst can be placed on the second gate insulating layer 113. The upper electrode CE2 can overlap with the gate electrode G below the upper electrode CE2. In this case, the gate electrode G and the upper electrode CE2, which overlap with the second gate insulating layer 113 therebetween, can form the storage capacitor Cst of the sub-pixel circuit. That is, the gate electrode G can serve as the lower electrode CE1 of the storage capacitor Cst. In this way, the storage capacitor Cst and the thin-film transistor TFT can be formed by overlapping each other. In some embodiments, the storage capacitor Cst can be formed without overlapping with the thin-film transistor TFT.

[0090] The upper electrode CE2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may be a single layer or multiple layers of the aforementioned materials.

[0091] The third gate insulating layer 114 may cover the upper electrode CE2. The third gate insulating layer 114 may include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon nitride oxide (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) x Zinc oxide (ZnO) x The gate insulating layer 114 can be ZnO and / or ZnO2. The third gate insulating layer 114 can be a single layer or multiple layers including the aforementioned inorganic insulating materials.

[0092] Interlayer insulating layer 115 may include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon nitride oxide (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) x Zinc oxide (ZnO)x The interlayer insulation layer 115 can be a single layer or multiple layers including the aforementioned inorganic insulating materials.

[0093] The drain electrode D and the source electrode S can each be located on the interlayer insulating layer 115. The drain electrode D and the source electrode S can comprise materials with good conductivity. The drain electrode D and the source electrode S can comprise conductive materials including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can be formed as a multilayer or a single layer comprising the above materials. As an example, the drain electrode D and the source electrode S can have a Ti / Al / Ti multilayer structure.

[0094] The first planarization layer 116 may be arranged to cover the drain electrode D and the source electrode S. The first planarization layer 116 may include an organic insulating layer. The first planarization layer 116 may include an organic insulator such as a general polymer (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a p-xylene polymer, a vinyl alcohol polymer, or mixtures thereof.

[0095] A connecting electrode CML can be disposed on the first planarization layer 116. In this case, the connecting electrode CML can be connected to the drain electrode D or the source electrode S through the contact holes of the first planarization layer 116. The connecting electrode CML can include a material with good conductivity. The connecting electrode CML can include conductive materials comprising molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can be formed from multiple layers or a single layer comprising the above materials. In one embodiment, the connecting electrode CML can have a Ti / Al / Ti multilayer structure.

[0096] The second planarization layer 117 may be configured to cover the connection electrode CML. The second planarization layer 117 may include an organic insulating layer. The second planarization layer 117 may include organic insulators such as general-purpose polymers (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and mixtures thereof.

[0097] The display element layer DEL can be disposed on the sub-pixel circuit layer PCL. The display element layer DEL can include the display element DE. The display element DE can be an organic light-emitting diode (OLED). The pixel electrode 211 of the display element DE can be electrically connected to the connection electrode CML through the contact hole of the second planarization layer 117. In FIG11, the pixel electrode 211 of the display element DE is shown to be electrically connected to the thin-film transistor TFT through the connection electrode CML, but the connection electrode CML can be omitted, and the pixel electrode 211 of the display element DE can be directly connected to the thin-film transistor TFT.

[0098] Pixel electrode 211 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, pixel electrode 211 may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. In another embodiment, pixel electrode 211 may also include a film formed of ITO, IZO, ZnO, or In2O3 above / below the aforementioned reflective film.

[0099] A pixel defining film 118 having an opening 118OP exposing the central portion of the pixel electrode 211 can be disposed on the pixel electrode 211. The pixel defining film 118 may include organic insulating materials and / or inorganic insulating materials. The opening 118OP may define an emission region (hereinafter referred to as the light-emitting region) EA of light emitted from the display element DE. For example, the width of the opening 118OP may correspond to the width of the light-emitting region EA of the display element DE.

[0100] Spacer 119 may be disposed on pixel defining film 118. In the manufacturing method for manufacturing a display device, spacer 119 can be used to prevent damage to substrate 100. When manufacturing display panel, a mask may be used. In this case, when the mask enters the opening 118OP of pixel defining film 118 or comes into close contact with pixel defining film 118 to deposit deposition material on substrate 100, defects such as damage or destruction of substrate 100 by mask can be prevented.

[0101] Spacer 119 may include an organic insulating material such as polyimide. Alternatively, spacer 119 may include an inorganic insulator such as silicon nitride or silicon oxide, or may include both organic and inorganic insulators.

[0102] In one embodiment, spacer 119 may comprise a different material than pixel defining film 118. Alternatively, in another embodiment, spacer 119 may comprise the same material as pixel defining film 118, in which case pixel defining film 118 and spacer 119 may be formed together in a masking process using halftone masks or the like.

[0103] Intermediate layer 212 may be disposed on pixel defining film 118. Intermediate layer 212 may include light-emitting layer 212b disposed in opening 118OP of pixel defining film 118. Light-emitting layer 212b may include a polymer or low molecular weight organic material that emits light of a predetermined color.

[0104] The first functional layer 212a and the second functional layer 212c can be disposed above and below the light-emitting layer 212b, respectively. The first functional layer 212a may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer 212c is a component disposed on the light-emitting layer 212b and may be optional. The second functional layer 212c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer 212a and / or the second functional layer 212c may be a common layer formed to cover the entire substrate 100, similar to the counter electrode 213 described below.

[0105] The counter electrode 213 can be made of a conductive material with a low work function. For example, the counter electrode 213 may include a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the counter electrode 213 may also include a layer such as ITO, IZO, ZnO, or In2O3 on a (semi-)transparent layer comprising the aforementioned materials.

[0106] In some embodiments, a capping layer (not shown) may also be provided on the counter electrode 213. The capping layer may include LiF, inorganic materials, and / or organic materials.

[0107] A thin-film encapsulation layer (TFE) can be disposed on the counter electrode 213. In one embodiment, the thin-film encapsulation layer (TFE) includes at least one inorganic encapsulation layer and at least one organic encapsulation layer, and Figure 5 The thin-film encapsulation layer TFE is shown to include a first inorganic encapsulation layer 310, an organic encapsulation layer 320 and a second inorganic encapsulation layer 330 stacked in sequence.

[0108] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may comprise one or more inorganic materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon nitride. The organic encapsulation layer 320 may comprise a polymer-based material. Polymer-based materials may include acrylic resins, epoxy resins, polyimides, and polyethylene. In one embodiment, the organic encapsulation layer 320 may comprise an acrylate.

[0109] Although not shown, the touch electrode layer can be disposed on the thin-film encapsulation layer TFE, and an optical functional layer can be disposed on the touch electrode layer. The touch electrode layer can obtain coordinate information based on external inputs, such as touch events. The optical functional layer can reduce the reflectivity of light incident from the outside toward the display device (external light) and / or improve the color purity of light emitted from the display device. In one embodiment, the optical functional layer may include a phase retarder and / or a polarizer. The phase retarder may be film-type or liquid crystal coated type, and may include λ / 2 phase retarders and / or λ / 4 phase retarders. The polarizer may also be film-type or liquid crystal coated type. The film-type may include a stretched synthetic resin film, and the liquid crystal coated type may include liquid crystals arranged in a predetermined array. The phase retarder and polarizer may also include protective films.

[0110] In another embodiment, the optical functional layer may include a black matrix and color filters. The color filters may be arranged to consider the color of light emitted from each pixel of the display device. Each color filter may contain a red, green, or blue pigment or dye. Alternatively, in addition to the pigments or dyes described above, each color filter may also include quantum dots. Alternatively, some color filters may not contain the pigments or dyes described above and may contain scattering particles such as titanium oxide.

[0111] In another embodiment, the optical functional layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. First reflected light and second reflected light reflected from the first reflective layer and the second reflective layer, respectively, can undergo destructive interference, thereby reducing the external light reflectivity.

[0112] The adhesive component can be disposed between the touch electrode layer and the optical functional layer. The adhesive component can be any type known in the art, without limitation. The adhesive component can be a pressure-sensitive adhesive (PSA).

[0113] Figure 6 It is a schematic plan view of a structure in which pixels of a display panel are arranged according to an embodiment. Figure 7 It is a schematic plan view of a structure with sub-pixel circuits arranged according to an embodiment.

[0114] refer to Figure 6 Subpixels (PX) can be arranged within the display area (DA) of the display panel. Subpixels (PX) arranged on the display panel can be arranged in PenTile form. Array (diamond array) arrangement.

[0115] The first sub-pixel PX1 can emit red light. The second sub-pixel PX2 can emit green light. In addition, the third sub-pixel PX3 can emit blue light. However, this disclosure is not limited thereto.

[0116] A pixel unit PXG can contain eight sub-pixels PX. Specifically, a pixel unit PXG can include two first sub-pixels PX1, four second sub-pixels PX2, and two third sub-pixels PX3.

[0117] In the first row R1, a first sub-pixel PX1, two second sub-pixels PX2, and a third sub-pixel PX3 can be arranged in the pixel unit PXG. In the second row R2, a third sub-pixel PX3, two second sub-pixels PX2, and a first sub-pixel PX1 can be arranged in the pixel unit PXG.

[0118] refer to Figure 7 The subpixel circuit PC can be arranged in the display area DA of the display panel. Each subpixel circuit PC electrically connected to the subpixel PX can be arranged in a first direction (e.g., in the x direction or the -x direction).

[0119] The first sub-pixel circuit PC1 can be electrically connected to the first sub-pixel PX1 that emits red light. The second sub-pixel circuit PC2 can be electrically connected to the second sub-pixel PX2 that emits green light. The third sub-pixel circuit PC3 can be electrically connected to the third sub-pixel PX3 that emits blue light.

[0120] The pixel circuit unit PCG may include sub-pixel circuits PC. Specifically, the pixel circuit unit PCG may include two first sub-pixel circuits PC1, four second sub-pixel circuits PC2, and two third sub-pixel circuits PC3. Figure 7 The eight sub-pixel circuits PC shown can each be connected to Figure 6 The eight sub-pixels PX shown.

[0121] exist Figure 7The sub-pixel circuits PC arranged in a first direction (e.g., the x-direction or the -x-direction) will be described in order from the first sub-pixel circuit PC1 arranged on the leftmost side (e.g., the -x-direction) to the sub-pixel circuits PC arranged on the right side (e.g., the x-direction). Specifically, the first sub-pixel circuit PC1 arranged on the leftmost side (e.g., in the -x-direction) and the adjacent second sub-pixel circuit PC2 can be electrically connected to the sub-pixel PX arranged in the first row R1. The third sub-pixel circuit PC3 and the second sub-pixel circuit PC2 arranged on their right side (e.g., in the x-direction) can be electrically connected to the sub-pixel PX arranged in the second row R2. Thus, the first sub-pixel circuit PC1 and the second sub-pixel circuit PC2 arranged on their right side (e.g., in the x-direction) can be electrically connected to the sub-pixel PX arranged in the second row R2.

[0122] The sub-pixel circuit PC can have an aspect ratio of approximately 1:8. The initialization gate line GBL, reference gate line GRL, first emission control line EML, second emission control line EMBL, reference voltage line VRL, and initialization voltage line VL applied to a pixel circuit unit PCG can be a single wiring. The initialization gate line GBL, reference gate line GRL, first emission control line EML, second emission control line EMBL, reference voltage line VRL, and initialization voltage line VL can extend on the display panel in a first direction (e.g., in the x-direction or -x-direction).

[0123] A scan line GWL applied to a pixel circuit unit PCG can be two consecutively arranged wirings. The scan line GWL can extend on the display panel in a first direction (e.g., the x-direction or the -x-direction). The scan line GWL can include a first scan line GWL1 and a second scan line GWL2. The first scan line GWL1 and the second scan line GWL2 can intersect each other. The first scan line GWL1 and the second scan line GWL2 can pass through two sub-pixel circuits PC (see...). Figure 4The first scan line GWL1 and the second scan line GWL2 can intersect each other with two sub-pixel circuits PC between them. The first scan line GWL1 can transmit signals to the sub-pixel circuit PC electrically connected to the sub-pixel PX arranged in the first row R1. The second scan line GWL2 can transmit signals to the sub-pixel circuit PC electrically connected to the sub-pixel PX arranged in the second row R2. With regard to pixel unit PXG and pixel circuit unit PCG, the first scan line GWL1 can transmit signals to the sub-pixel circuit PC electrically connected to the four sub-pixel PXs arranged in the first row R1, which are among the eight sub-pixels PX included in pixel unit PXG. The second scan line GWL2 can transmit signals to the sub-pixel circuit PC electrically connected to the four sub-pixel PXs arranged in the second row R2, which are among the eight sub-pixels PX included in pixel unit PXG. This will... Figure 9 and Figure 10 A detailed description will be provided in the following section.

[0124] Although not shown, the data lines DL can each be responsible for the first sub-pixel circuit PC1 of a first sub-pixel PX1 and the third sub-pixel circuit PC3 of a third sub-pixel PX3 within a pixel circuit unit PCG, or for the second sub-pixel circuit PC2 of two second sub-pixels PX2 within a pixel circuit unit PCG. The data lines DL can extend on the display panel in a second direction (e.g., in the y-direction or -y-direction).

[0125] Figure 8 This is a schematic layout diagram showing the positions of multiple thin-film transistors and capacitors arranged in the sub-pixel circuit of a display device according to an embodiment. Specifically, Figure 8 Showing more details Figure 7 The diagram shows a portion of the sub-pixel circuit plan view.

[0126] refer to Figure 8 In one embodiment, the sub-pixel circuit of the display device may include initialization voltage lines VL_B and VL_RG, initialization gate line GBL, first emission control line EML, second emission control line EMBL, reference gate line GRL, scan lines GWL1 and GWL2, reference voltage line VRL, and data lines DL_RB and DL_G extending along a first direction (e.g., the x-direction or the -x-direction). However, this disclosure is not limited thereto. Although not shown, the sub-pixel circuit may include power lines extending in a second direction (e.g., in the y-direction or the -y-direction) (see [link to relevant documentation]). Figure 4 The driving voltage line PL).

[0127] In addition, the sub-pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a storage capacitor Cst, and a holding capacitor Chd (see [link to relevant documentation]). Figure 4 The sub-pixel circuitry may include a holding capacitor Chd, but the holding capacitor Chd is not in... Figure 8 As shown in the image.

[0128] In one embodiment, the fifth transistor T5 may be configured as a thin-film transistor comprising silicon semiconductor. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 may be configured as thin-film transistors comprising oxide semiconductor.

[0129] The semiconductor layer of the fifth transistor T5 can be formed of polycrystalline silicon. The semiconductor layer of the fifth transistor T5 can be bent into various shapes.

[0130] The semiconductor layer of the fifth transistor T5 may each include a channel region, a source region on each side of the channel region, and a drain region. For example, the source and drain regions may be doped with impurities, and these impurities may include N-type or P-type impurities. The source and drain regions may correspond to the source electrode and drain electrode, respectively. The source and drain regions may be interchangeable depending on the characteristics of the transistor. In the following text, the terms source region and drain region will be used instead of source electrode and drain electrode.

[0131] The fifth transistor T5 may include a fifth semiconductor layer and a fifth gate electrode G5. The fifth semiconductor layer may include a fifth channel region C5, a fifth source region S5 on both sides of the fifth channel region C5, and a fifth drain region D5. The fifth source region S5 may be electrically connected to the drive voltage line PL (see...). Figure 4 The fifth drain region D5 can be electrically connected to the first drain region D1 of the first transistor T1. The fifth gate electrode G5 can be configured as a portion of the first emitter control line EML.

[0132] The semiconductor layers of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are arranged in the same layer and may include the same material. For example, the semiconductor layer may be an oxide semiconductor.

[0133] The semiconductor layer may include a channel region, source regions on either side of the channel region, and drain regions. For example, the source and drain regions may be regions in which carrier concentration is increased through plasma treatment. The source and drain regions may correspond to the source electrode and drain electrode, respectively. Hereinafter, the terms source region and drain region will be used instead of source electrode and drain electrode.

[0134] The first transistor T1 may include a first semiconductor layer comprising an oxide semiconductor and a first gate electrode G1. The first semiconductor layer may include a first channel region C1 and a first source region S1 and a first drain region D1 on both sides of the first channel region C1. The first source region S1 may be electrically connected to the sixth drain region D6 of the sixth transistor T6, which is disposed on the same layer. Furthermore, the first drain region D1 may be electrically connected to the fifth drain region D5 of the fifth transistor T5 via a connection portion (not shown). The first gate electrode G1 may be configured as a portion of the gate conductive layer 151. The gate conductive layer 151 may be electrically connected to the node connection line 180. This will be described in more detail later.

[0135] The second transistor T2 may include a second semiconductor layer comprising an oxide semiconductor and a second gate electrode G2. The second semiconductor layer may include a second channel region C2 and a second source region S2 and a second drain region D2 on both sides of the second channel region C2. The second source region S2 may be electrically connected to a node connection line 180 disposed on the same layer. The second drain region D2 may be electrically connected to a data line DL_G via a connection portion (not shown). The second gate electrode G2 may be configured as a portion of the first scan line GWL1.

[0136] The third transistor T3 may include a third semiconductor layer comprising an oxide semiconductor and a third gate electrode G3. The third semiconductor layer may include a third channel region C3 and a third source region S3 and a third drain region D3 on both sides of the third channel region C3. The third source region S3 may be electrically connected to a reference voltage line VRL via a connection portion (not shown). The third drain region D3 may be electrically connected to a node connection line 180 disposed on the same layer. The third gate electrode G3 may be configured as a portion of the reference gate line GRL.

[0137] The fourth transistor T4 may include a fourth semiconductor layer comprising an oxide semiconductor and a fourth gate electrode G4. The fourth semiconductor layer may include a fourth channel region C4 and a fourth source region S4 and a fourth drain region D4 on either side of the fourth channel region C4. The fourth source region S4 may be electrically connected to the initialization voltage line VL_RG via a connection portion (not shown). The fourth drain region D4 may be electrically connected to the sixth source region S6 of the sixth transistor T6, which is disposed on the same layer. The fourth gate electrode G4 may be configured as a portion of the initialization gate line GBL.

[0138] The sixth transistor T6 may include a sixth semiconductor layer comprising an oxide semiconductor and a sixth gate electrode G6. The sixth semiconductor layer may include a sixth channel region C6 and a sixth source region S6 and a sixth drain region D6 on either side of the sixth channel region C6. The sixth source region S6 may be electrically connected to the fourth drain region D4 of the fourth transistor T4, which is disposed on the same layer. The sixth drain region D6 may be electrically connected to the first source region S1 of the first transistor T1, which is disposed on the same layer. The sixth gate electrode G6 may be configured as a portion of the second emitter control line EMBL.

[0139] The storage capacitor Cst may include a first storage electrode CEs1 and a second storage electrode CEs2. The first storage electrode CEs1 can be electrically connected to the connection portion 173 through the contact hole 23. The connection portion 173 can be electrically connected to the node connection line 180 through the contact hole 23. In other words, the storage capacitor Cst can be electrically connected to the node connection line 180 through the connection portion.

[0140] Furthermore, the gate conductive layer 151 can be electrically connected to the first storage electrode CEs1 of the storage capacitor Cst through the contact hole 31. The first storage electrode CEs1 of the storage capacitor Cst can be electrically connected to the connection portion 173 through the contact hole 17. The connection portion 173 can be electrically connected to the node connection line 180 through the contact hole 23. In summary, the gate conductive layer 151 including the first gate electrode G1 can be electrically connected to the node connection line 180.

[0141] Figure 9 It is a schematic plan view of scan lines and node connection lines included in the sub-pixel circuit according to the embodiment. Figure 10 yes Figure 9 A schematic cross-sectional view of the scan lines shown. Specifically, Figure 10 It is along Figure 9 The schematic cross-sectional view shown is taken from line II-II' of the plan view.

[0142] refer to Figure 9 and Figure 10 The first scan line GWL1 may extend in a first direction (e.g., the x-direction or the -x-direction). The first scan line GWL1 may include a first-first scan line GWL1-1 and a first-second scan line GWL1-2. The first scan line GWL1 may be electrically connected to a line arranged in the first row R1 (see...). Figure 6 Subpixel PX in ) (see Figure 6 The sub-pixel circuits transmit scan signals. In other words, the first scan line GWL1 can transmit scan signals to the sub-pixel circuits arranged in... Figure 9 The first sub-pixel circuit PC1 and the second sub-pixel circuit PC2 on the upper left side (e.g., in the -x direction) transmit signals.

[0143] The first-first scan line GWL1-1 and the first-second scan line GWL1-2 can be disposed in different layers. The first-first scan line GWL1-1 can be disposed below the first-second scan line GWL1-2. Therefore, in the vertical cross-section of the substrate 100, the first-second scan line GWL1-2 can be disposed above the first-first scan line GWL1-1. At least a portion of the first-second scan line GWL1-2 can overlap with the first-first scan line GWL1-1, for example, in a direction perpendicular to the substrate 100. The first-first scan line GWL1-1 and the first-second scan line GWL1-2 can be electrically connected through the first contact hole CNT1.

[0144] The second scan line GWL2 may extend in a first direction (e.g., the x-direction or the -x-direction). The second scan line GWL2 may include a second-first scan line GWL2-1 and a second-second scan line GWL2-2. The second scan line GWL2 may be electrically connected to a line arranged in the second row R2 (see...). Figure 6 Subpixel PX in ) (see Figure 6 The sub-pixel circuit of the second scan line GWL2 transmits the scan signal. In other words, the second scan line GWL2 can transmit the scan signal to the sub-pixel circuit arranged in the sub-pixel circuit. Figure 9 The third sub-pixel circuit PC3 and the second sub-pixel circuit PC2 on the upper right side (e.g., in the x direction) transmit signals.

[0145] The second-first scan line GWL2-1 and the second-second scan line GWL2-2 can be disposed in different layers. In a vertical cross-section of the substrate 100, the second-first scan line GWL2-1 can be disposed below the second-second scan line GWL2-2. The second-second scan line GWL2-2 can be disposed above the second-first scan line GWL2-1. At least a portion of the second-second scan line GWL2-2 can overlap with the second-first scan line GWL2-1, for example, in a direction perpendicular to the substrate 100. The second-first scan line GWL2-1 and the second-second scan line GWL2-2 can be electrically connected through the second contact hole CNT2.

[0146] The first scan line GWL1 and the second scan line GWL2 can be arranged to intersect each other. The first scan line GWL1 and the second scan line GWL2 can intersect each other by passing through two sub-pixel circuits. In other words, the intersection point of the first scan line GWL1 and the second scan line GWL2 can be separated by the two sub-pixel circuits.

[0147] The first scan line GWL1-1 and the second scan line GWL2-1 can be disposed in the same layer and can comprise the same material. Furthermore, the first scan line GWL1-1 and the second scan line GWL2-1 can be arranged at the same location in a second direction (e.g., the y-direction or the -y-direction).

[0148] The first-second scan line GWL1-2 and the second-second scan line GWL2-2 can be disposed in the same layer and can comprise the same material. Furthermore, the first-second scan line GWL1-2 and the second-second scan line GWL2-2 can be arranged at the same location in a second direction (e.g., the y-direction or the -y-direction).

[0149] In a comparative example, the first and second scan lines can be arranged so that they do not intersect each other, are separated in a second direction (e.g., the y-direction or the -y-direction), and extend in a first direction (e.g., the x-direction or the -x-direction). In this case, the distance between the node connection lines 180 of the sub-pixel circuits receiving signals from the first scan line can be different from the distance between the node connection lines 180 of the sub-pixel circuits receiving signals from the second scan line. Therefore, the coupling capacitance between the first scan line and the node connection line 180 can be different from the coupling capacitance between the second scan line and the node connection line 180. In other words, the coupling capacitance between the first scan line and the node connection line 180 can be different from the coupling capacitance between the second scan line and the node connection line 180. Figure 6 Subpixel PX in ) (see Figure 6 The coupling capacitance of the first scan line and node connection line 180 generated in the sub-pixel circuit of ) is connected to the second row R2 (see Figure 6 Subpixel PX in ) (see Figure 6 The coupling capacitance of the second scan line and node connection line 180 generated in the sub-pixel circuit of the ) can be different. This is because the connection to the line arranged in the first row R1 (see...) Figure 6 Subpixel PX in ) (see Figure 6 The coupling capacitance in the sub-pixel circuit of ) is connected to the circuit arranged in the second row R2 (see Figure 6 Subpixel PX in ) (see Figure 6 The difference in coupling capacitance in the sub-pixel circuits of the first row R1 (see...) Figure 6 Subpixel PX in ) (see Figure 6 ) and placed in the second row R2 (see Figure 6 Subpixel PX in ) (see Figure 6 There may be brightness differences between them, and in the first row R1 (see Figure 6 ) and the second line R2 (see Figure 6 There may be residual horizontal lines between them.

[0150] In one embodiment, the first scan line GWL1 and the second scan line GWL2 can intersect each other by passing through two sub-pixel circuits. Therefore, the distance between the node connection lines 180 of the sub-pixel circuits receiving signals from the first scan line GWL1 can be similar to the distance between the node connection lines 180 of the sub-pixel circuits receiving signals from the second scan line GWL2. Therefore, the coupling capacitance between the first scan line GWL1 and the node connection lines 180 can be similar to the coupling capacitance between the second scan line GWL2 and the node connection lines 180. In other words, when connected to the circuit arranged in the first row R1 (see... Figure 6 Subpixel PX in ) (see Figure 6 The coupling capacitance of the first scan line GWL1 and node connection line 180 generated in the sub-pixel circuit of ) is connected to the second row R2 (see Figure 6 Subpixel PX in ) (see Figure 6 The coupling capacitances of the second scan line GWL2 and the node connection line 180 generated in the sub-pixel circuit of the ) can be similar to each other. This is because the connection to the line arranged in the first row R1 (see...) Figure 6 Subpixel PX in ) (see Figure 6 The coupling capacitance in the sub-pixel circuit of ) is connected to the circuit arranged in the second row R2 (see Figure 6 Subpixel PX in ) (see Figure 6 The coupling capacitance in the sub-pixel circuits is similar, thus preventing coupling in the first row R1 (see...) Figure 6 Subpixel PX in ) (see Figure 6 ) and placed in the second row R2 (see Figure 6 Subpixel PX in ) (see Figure 6 There will be a difference in brightness between them, and it can also prevent the first row R1 (see Figure 6 ) and the second line R2 (see Figure 6 The presence of residual horizontal lines between the two improves the quality and reliability of the display device.

[0151] According to some embodiments, as described above, a display device with improved reliability and quality, as well as an electronic device including the display device, can be realized.

[0152] Although this disclosure has been described with reference to embodiments illustrated in the accompanying drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the subject matter disclosed should not be limited to any single embodiment described herein.

Claims

1. A display device, comprising: Substrate; A first scan line is disposed on the substrate, extends in a first direction, and includes a first-first scan line and a first-second scan line disposed in different layers; as well as The second scan line extends in the first direction and includes a second-first scan line and a second-second scan line disposed in different layers, wherein... The first scan line and the second scan line are arranged to intersect each other.

2. The display device according to claim 1, wherein, In a direction perpendicular to the substrate, the first-first scan line is positioned below the first-second scan line.

3. The display device according to claim 1, wherein, The first-first scan line and the first-second scan line are electrically connected to each other through the first contact hole.

4. The display device according to claim 1, wherein, In a direction perpendicular to the substrate, at least a portion of the first-second scan line overlaps with the first-first scan line.

5. The display device according to claim 1, wherein, In a direction perpendicular to the substrate, the second-first scan line is disposed below the second-second scan line.

6. The display device according to claim 1, wherein, The second-first scan line and the second-second scan line are electrically connected to each other through the second contact hole.

7. The display device according to claim 1, wherein, In a direction perpendicular to the substrate, at least a portion of the second-second scan line overlaps with the second-first scan line.

8. The display device according to claim 1, wherein, The first-first scan line and the second-first scan line are disposed on the same layer.

9. The display device according to claim 8, wherein, In a second direction intersecting the first direction, the first-first scan line and the second-first scan line are arranged at the same position.

10. The display device according to claim 1, wherein, The first-second scan line and the second-second scan line are disposed on the same layer.

11. The display device according to claim 10, wherein, In a second direction intersecting the first direction, the first-second scan line and the second-second scan line are arranged at the same position.

12. The display device according to claim 1, further comprising: A pixel unit is disposed on the substrate and includes eight sub-pixels, wherein four of the eight sub-pixels of the pixel unit are arranged in a first row and the other four sub-pixels of the eight sub-pixels of the pixel unit are arranged in a second row.

13. The display device according to claim 12, wherein, The eight sub-pixels included in the pixel unit are arranged in a PenTile array.

14. The display device according to claim 12, further comprising: A pixel circuit unit includes eight sub-pixel circuits, each of the eight sub-pixel circuits being electrically connected to a corresponding sub-pixel among the eight sub-pixels in the pixel unit.

15. The display device according to claim 14, wherein, The eight sub-pixel circuits of the pixel circuit unit are arranged in the first direction.

16. The display device according to claim 14, wherein, The first scan line is configured to transmit signals to the sub-pixel circuits electrically connected to the four sub-pixels arranged in the first row.

17. The display device according to claim 14, wherein, The second scan line is configured to transmit signals to the sub-pixel circuits electrically connected to the four sub-pixels arranged in the second row.

18. The display device according to claim 14, wherein, The first scan line and the second scan line intersect by passing through two sub-pixel circuits arranged in the first direction.

19. Electronic devices, including: Display panel; as well as The lower cover forms the outer surface and has an opening that exposes the portion of the display panel. The display panel includes: Substrate; A pixel unit is disposed on the substrate and includes eight sub-pixels, wherein four of the eight sub-pixels of the pixel unit are arranged in a first row, and the other four sub-pixels of the eight sub-pixels of the pixel unit are arranged in a second row; A pixel circuit unit includes eight sub-pixel circuits arranged in a first direction, and each of the eight sub-pixel circuits is electrically connected to a corresponding sub-pixel among the eight sub-pixels in the pixel unit; A first scan line is disposed on the substrate, extends in the first direction, and includes a first-first scan line and a first-second scan line disposed in different layers; and The second scan line extends in the first direction and includes a second-first scan line and a second-second scan line disposed in different layers, wherein... The first scan line is configured to transmit signals to the sub-pixel circuitry electrically connected to the four sub-pixels arranged in the first row. The second scan line is configured to transmit signals to the sub-pixel circuitry electrically connected to the four sub-pixels arranged in the second row, and The first scan line and the second scan line are arranged to intersect each other.

20. The electronic device according to claim 19, wherein, In a direction perpendicular to the substrate, the first-first scan line is disposed below the first-second scan line, and the second-first scan line is disposed below the second-second scan line.

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