Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display panels, and specifically discloses a display panel and a display device, which can improve the imaging effect of an under-screen camera and improve the display effect and use performance of the display panel.

Description

Technical Field

[0001] This invention belongs to the field of display technology, and particularly relates to a display panel and display device. Background Technology

[0002] With the advancement of technology, digital display devices such as smartphones and tablets have been widely used. Among them, the display panel is an indispensable human-computer interaction interface in these display devices. OLED (Organic Light Emitting Diode) display panels, for example, have advantages such as self-illumination, energy saving, flexibility, and good adaptability. Furthermore, display devices using this technology do not require a backlight and feature fast response times and excellent display effects, attracting user attention and being widely used in smartphones, tablets, and other terminal products.

[0003] Due to the structural limitations of existing display panels, the display effect requirements of display panels cannot be met.

[0004] Therefore, there is an urgent need for a new display panel and display device. Summary of the Invention

[0005] This invention provides a display panel and display device. A first signal line serves as the boundary trace of a first light-transmitting area, arranged along the edge of the first light-transmitting area without traversing the interior of the first light-transmitting area. This reduces the obstruction of light by the metal trace, improves the light transmission performance of the first light-transmitting area, enhances the imaging effect of the under-display camera, and improves the display effect and performance of the display panel.

[0006] One embodiment of the present invention provides a display panel, including a first display area and a second display area at least partially surrounding the first display area. The first display area includes a light-transmitting area and a first light-emitting area adjacent to the light-transmitting area. The display panel includes: a substrate; pixel circuits arranged in an array on one side of the substrate, at least a portion of the pixel circuits including a first pixel circuit located in the first display area and a second pixel circuit located in the second display area, the density of the second pixel circuits being less than the density of the first pixel circuits; and array traces extending at least partially from the first display area to the second display area, the array traces being connected to at least one row of the pixel circuits, and at least a portion of the array traces forming a partial edge of the light-transmitting area; wherein the light-transmitting area includes a first light-transmitting area, the array traces include a first signal line and a second signal line transmitting the same signal, the number of pixel circuits connected to the first signal line is less than the number of pixel circuits connected to the second signal line, and at least a portion of the first signal line forms the edge of the first light-transmitting area.

[0007] According to one aspect of the present invention, in the second display area, the pixel circuits connected to the first signal line and the pixel circuits connected to the second signal line are located in adjacent rows; in the first display area, the pixel circuits connected to the first light-transmitting area and the second signal line are located in adjacent rows; the first signal line includes a first segment, a second segment, and a third segment connected together; the first segment is located in the second display area, and at least a portion of the first segment and at least a portion of the third segment extend along the row direction, and at least a portion of the second segment and the third segment are located around the light-transmitting area, the extension direction of the second segment intersects the row direction; the first light-transmitting area includes a first sub-light-transmitting area and a second sub-light-transmitting area, the first sub-light-transmitting area is close to the second display area, the second sub-light-transmitting area is located on the side of the first sub-light-transmitting area away from the second display area, at least a portion of the second segment and at least a portion of the third segment are respectively located around the first sub-light-transmitting area, and at least a portion of the third segment is located around the second sub-light-transmitting area; preferably, the first signal line includes a first signal sub-line and a second signal sub-line, the third segment of the first signal sub-line is disposed adjacent to the second display area, and the third segment of the first signal sub-line is located in the first display area, and the third segment of the second signal sub-line is disposed adjacent to the first light-emitting area.

[0008] According to one aspect of the present invention, a plurality of first light-emitting units are provided in the first light-emitting area; along the thickness direction of the display panel, the first light-emitting unit includes a first electrode layer, a light-emitting layer and a second electrode layer stacked together; along the thickness direction of the display panel, the third segment and at least a portion of the first electrode layer overlap.

[0009] According to one aspect of the present invention, along the thickness direction of the display panel, the display panel further includes a first conductive layer, a second conductive layer, and a third conductive layer disposed on one side of the substrate and stacked thereon, wherein a first insulating layer is disposed between the first conductive layer and the second conductive layer, and a second insulating layer is disposed between the second conductive layer and the third conductive layer; a first segment is located on the first conductive layer, a second segment is located on the second conductive layer, and a third segment is located on the third conductive layer; the first segment and the second segment are connected through a first via of the first insulating layer, and the second segment and the third segment are connected through a second via of the second insulating layer.

[0010] According to one aspect of the present invention, the first display area includes a plurality of first circuit units arranged sequentially along a row direction, each first circuit unit including at least two pixel circuits, the orthographic projection of the first circuit unit on the substrate being located within the orthographic projection range of the first light-emitting area on the substrate; in the row direction, there is a first gap between adjacent first circuit units, and in the row direction, pixel circuits located between the same first circuit unit have a second gap, the first gap being larger than the second gap; the third segment includes a bent portion and a straight portion, the straight portion extending along the row direction, the bent portion being disposed relative to the straight portion toward the region where the first gap is located; preferably, along the thickness direction of the display panel, the region where the first gap is located overlaps with the second light-transmitting area.

[0011] According to one aspect of the present invention, the display panel includes a non-display area located on the side of the second display area away from the first display area. The display panel further includes a plurality of first gate driving circuits located in the non-display area. Each first gate driving circuit is connected to at least one row of the pixel circuits. The first gate driving circuits connected to the first signal lines and the first gate driving circuits connected to the second signal lines are arranged adjacent to each other in the column direction. The first signal lines and the second signal lines are connected to the pixel circuits in adjacent rows within the first display area. Preferably, the array traces further include third signal lines and fourth signal lines transmitting the same signal. The third signal lines and the fourth signal lines are connected to the pixel circuits in adjacent rows within the second display area. The third signal line is connected to the same pixel circuit as the first signal line, and the fourth signal line is connected to the same pixel circuit as the second signal line. In the same pixel circuit, the third signal line... The transistor connected to the signal line is different from that connected to the first signal line; the display panel further includes a plurality of second gate driving circuits located in the non-display area, and in the second display area, the third signal line and the fourth signal line of adjacent rows of pixel circuits are connected to the same second gate driving circuit; preferably, the third signal line includes a fourth segment and a fifth segment connected together, the fourth segment is located in the second display area, and the fifth segment extends along the edge of the light-transmitting area to the first light-emitting area; the fourth signal line includes a sixth segment and a seventh segment connected together, the sixth segment is located in the second display area, and the seventh segment is located in the first display area, and on the side of the second display area closer to the first display area, the fifth segment and the seventh segment are connected, the extension direction of the fifth segment intersects the extension direction of the fourth segment, and the extension directions of the fourth segment and the sixth segment are the same; preferably, at least part of the fifth segment forms part of the edge of the light-transmitting area.

[0012] According to one aspect of the present invention, the first light-emitting area is arranged in an array within the second display area, and the light-transmitting area further includes a second light-transmitting area, the area of ​​the first light-transmitting area being larger than the area of ​​the second light-transmitting area; the first light-transmitting area and the first light-emitting area are arranged alternately along the column direction, and the second light-transmitting area and the first light-emitting area are arranged alternately along the row direction; the fourth signal line includes a first connecting line and a second connecting line, the first connecting line and the second connecting line connecting different transistors in the same pixel circuit; the seventh segment of the first connecting line includes a redundant portion, the redundant portion forming a first partial edge of the second light-transmitting area; the seventh segment of the second connecting line includes a first sub-segment, a second sub-segment, a third sub-segment, and a fourth sub-segment, the first sub-segment and the fourth sub-segment being located within adjacent first light-emitting areas, the third sub-segment extending along the column direction, the first sub-segment, the second sub-segment, and the fourth sub-segment extending along the row direction, the first sub-segment and the fourth sub-segment being located in the same conductive layer, and the first sub-segment and the second sub-segment being located in different conductive layers; the second sub-segment and the third sub-segment forming a second partial edge of the second light-transmitting area.

[0013] According to one aspect of the present invention, along the thickness direction of the display panel, the display panel further includes at least two conductive layers disposed on one side of the substrate; the fourth segment and the fifth segment are located in different conductive layers.

[0014] According to one aspect of the present invention, the array trace further includes a first reset signal line; the first reset signal line includes an eighth segment extending along the row direction and a ninth segment extending along the column direction, which are connected to each other; the first reset signal line is disposed in the first light-emitting area and the second display area, wherein the eighth segment of the reset signal line is disposed in the first light-emitting area, and the eighth segment and the ninth segment are disposed in the second display area; preferably, a portion of the reset signal line extends along the edge of the light-transmitting area; preferably, in the second display area, the orthographic projection of the eighth segment and the ninth segment on the substrate forms a grid structure; preferably, along the thickness direction of the display panel, the display panel further includes a first conductive layer, a second conductive layer and a third conductive layer stacked on one side of the substrate, wherein the first conductive layer, the second conductive layer and the third conductive layer are stacked on one side of the substrate, and the first conductive layer, the second conductive layer and the third conductive layer are stacked on one side of the substrate, and the third conductive layer and the third conductive layer are stacked on one side of the substrate, and the third conductive layer and the third conductive layer are stacked on one side of the substrate, respectively. A first insulating layer is provided between the layers, and a second insulating layer is provided between the second conductive layer and the third conductive layer; the eighth segment is located in the first conductive layer or the second conductive layer, and the ninth segment is located in the third conductive layer; preferably, in the second display area, at least a portion of the orthogonal projections of the first signal line and the reset signal line on the substrate overlap; preferably, the array traces further include a second reset signal line and a fifth signal line that transmit different signals, the second reset signal line and the fifth signal line being located in different layers among the first conductive layer, the second conductive layer, and the third conductive layer; along the column direction, the second reset signal line and the fifth signal line are located on the same side of the first light-emitting area, and along the thickness direction of the display panel, the second reset signal line and the fifth signal line at least partially overlap. Preferably, the array traces further include data lines, the data lines extending at least partially along the column direction, and the data lines forming a partial edge of the light-transmitting area.

[0015] Another aspect of the present invention provides a display device, including a display panel as described in any of the above embodiments.

[0016] Compared with existing technologies, the display panel provided in this invention includes a substrate, pixel circuits, and array traces. The array traces include a first signal line and a second signal line that transmit the same signal. The first signal line and the second signal line can both be scan signal lines or both be reset / reference voltage signal lines. Due to the limitation of the light-transmitting area of ​​the first display area, the first signal line passes through the first display area, and fewer pixel circuits can be connected. The second signal line is mainly arranged in the second display area, connecting a complete number of pixel circuits. Therefore, the load of the first signal line and the load of the second signal line are naturally different. At least a portion of the first signal line forms the boundary of the first light-transmitting area, that is, the first signal line acts as the boundary trace of the first light-transmitting area, arranged along the edge of the first light-transmitting area, without crossing the interior of the first light-transmitting area. This reduces the obstruction of light by the metal traces, improves the light transmission performance of the first light-transmitting area, enhances the imaging effect of the under-display camera, and improves the display effect and performance of the display panel. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a display panel provided in one embodiment of the present invention; Figure 2 This is provided by one embodiment of the present invention. Figure 1 A partial schematic diagram at point B in the middle; Figure 3 This is provided by another embodiment of the present invention. Figure 1 A partial schematic diagram at point B in the middle; Figure 4 This is a partial schematic diagram of a display panel provided in one embodiment of the present invention; Figure 5 This is a partial schematic diagram of a display panel provided in one embodiment of the present invention; Figure 6 This is a schematic diagram of the first electrode layer of a display panel provided in one embodiment of the present invention. Figure 7 This is a schematic diagram of the film structure of the first display area provided in one embodiment of the present invention; Figure 8 This is a schematic diagram of the connection of the first scan signal line provided in one embodiment of the present invention; Figure 9 This is provided by yet another embodiment of the present invention. Figure 1 A partial schematic diagram at point B in the middle; Figure 10This is provided by yet another embodiment of the present invention. Figure 1 A partial schematic diagram at point B in the middle; Figure 11 This is a schematic diagram of a pixel circuit provided in one embodiment of the present invention.

[0019] In the attached image: 110 - First gate drive circuit; 120 - Second gate drive circuit; 200 - Array trace; 210 - First signal line; 201 - First signal sub-line; 202 - Second signal sub-line; 211 - First segment; 212 - Second segment; 213 - Third segment; 220 - Second signal line; 230 - Third signal line; 231 - Fourth segment; 232 - Fifth segment; 240 - Fourth signal line; 241 - Sixth segment; 242 - Seventh segment; 250 - Fifth signal line; 300 - Pixel circuit; 310 - First pixel circuit; 320 - Second pixel circuit; 400 - First reset signal line; 410 - Eighth segment; 420 - Ninth segment; 500 - Reset signal drive unit; 600-substrate; 700 - First light-emitting unit; 710 - First electrode layer; 720 - Light-emitting layer; 730 - Second electrode layer; 800 - Pixel definition layer; 810 - First subpixel definition layer; 820 - Second subpixel definition layer; 900-Light-shielding structure; L1 - First connecting line; L2 - Second connecting line; L21 - First sub-segment; L22 - Second sub-segment; L23 - Third sub-segment; L24 - Fourth sub-segment; R - Redundancy section; FZ - Encapsulation layer; W - Bending section; Q - Active layer; S - Source; D - Drain; G - Gate; C - Capacitor; C1 - First electrode; C2 - Second electrode; M1 - First conductive layer; M2 - Second conductive layer; M3 - Third conductive layer; V - Second reset signal line; N1 - First adapter line; N2 - Second adapter line; K1 - First via; K2 - Second via; J1 - First insulating layer; J2 - Second insulating layer; P1 - First circuit unit; P2 - Second circuit unit; H1 - First light-transmitting opening; H2 - Second light-transmitting opening; VDATA - Data line; T1 - Drive transistor; T2 - Data write transistor; T3 - Threshold compensation transistor; T4 - First reset transistor; T5 - First control transistor; T6 - Second control transistor; T7 - ​​Second reset transistor; ELVDD - First power supply voltage signal line; ELVSS - Second power supply voltage signal line; VREF1 - First reset signal line; VREF2 - Second reset signal line; EM - Light emission control signal line; S1 - First scan signal line; S2 - Second scan signal line; S3 - Third scan signal line; S4 - Fourth scan signal line; AA1 - First display area; AA2 - Second display area; TA - Transmitting area; ZA - Transmitting area; ZA1 - First transmitting area; ZA11 - First sub-transmitting area; ZA12 - Second sub-transmitting area; ZA2 - Second transmitting area; FA - First emitting area; NA - Non-display area; X - Row direction; Y - Column direction; Z - Thickness direction of the display panel. Detailed Implementation

[0020] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention.

[0021] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0022] To better understand this invention, the following is combined with... Figures 1 to 11 The display panel and display device according to embodiments of the present invention will be described in detail.

[0023] Please see Figures 1 to 3 , Figure 1 This is a schematic diagram of a display panel provided in one embodiment of the present invention; Figure 2This is provided by one embodiment of the present invention. Figure 1 A partial schematic diagram at point B in the middle; Figure 3 This is provided by another embodiment of the present invention. Figure 1 A partial schematic diagram at point B in the middle.

[0024] This invention provides a display panel including a first display area AA1 and a second display area AA2 at least partially surrounding the first display area AA1. The first display area AA1 includes a light-transmitting area TA and a first light-emitting area FA adjacent to the light-transmitting area TA. The display panel includes: a substrate 600; and pixel circuits 300 arranged in an array on one side of the substrate 600. At least a portion of the pixel circuits 300 includes a first pixel circuit 310 located in the first display area AA1 and a second pixel circuit 320 located in the second display area AA2. The density of the second pixel circuits 320 is less than the density of the first pixel circuits 310. The array trace 200 extends at least partially from the first display area AA1 to the second display area AA2. The array trace 200 is connected to at least one row of pixel circuits 300. At least a portion of the array trace 200 forms a partial edge of the light-transmitting area TA. The light-transmitting area TA includes the first light-transmitting area ZA1. The array trace 200 includes a first signal line 210 and a second signal line 220 that transmit the same signal. The number of pixel circuits 300 connected to the first signal line 210 is less than the number of pixel circuits 300 connected to the second signal line 220. At least a portion of the first signal line 210 forms the edge of the first light-transmitting area ZA1.

[0025] The display panel provided in this embodiment of the invention includes a substrate 600, pixel circuits 300, and array traces 200. The array traces 200 include a first signal line 210 and a second signal line 220 that transmit the same signal. The first signal line 210 and the second signal line 220 can both be scan signal lines or both reset / reference voltage signal lines. Due to the limitation of the light-transmitting area TA of the first display area AA1, the first signal line 210 passes through the first display area AA1, and can connect fewer pixel circuits 300; the second signal line 220 is mainly arranged in the second display area AA2, connecting a full number of pixel circuits 300. Therefore, the load of the first signal line 210 and the load of the second signal line 220 are naturally different. At least a portion of the first signal line 210 forms the boundary of the first light-transmitting area ZA1. That is, the first signal line 210 serves as the boundary trace of the first light-transmitting area ZA1, arranged along the edge of the first light-transmitting area ZA1, without crossing the interior of the first light-transmitting area ZA1. This reduces the obstruction of light by the metal trace, improves the light transmission performance of the first light-transmitting area ZA1, enhances the imaging effect of the under-display camera, and improves the display effect and performance of the display panel.

[0026] Compared to existing technologies, in this embodiment, the first signal line 210 no longer directly traverses the internal area of ​​the light-transmitting area TA. Instead, the line is arranged at the edge of the light-transmitting area TA, which significantly reduces the coverage area of ​​the metal lines inside the light-transmitting area TA, reduces the obstruction of incident light by the metal lines, improves the light transmittance of the light-transmitting area TA of the first display area AA1, improves the amount of light entering the under-display camera, improves the image quality, and reduces the problems of image shadows and local exposure abnormalities caused by the metal lines.

[0027] It should be noted that the first display area AA1 is the display area corresponding to optical components such as the under-display camera and facial recognition elements. This area needs to balance display and light transmission functions. The first display area AA1 includes a light-transmitting area TA and a first light-emitting area FA adjacent to the light-transmitting area TA. The light-transmitting area TA is the area directly above the under-display camera. This area requires high light transmittance and should minimize the obstruction by metal traces. The first light-emitting area FA is the area within the first display area AA1 containing light-emitting pixels for display functionality.

[0028] Optionally, the transmittance of the first display area AA1 is greater than that of the second display area AA2 to meet the transmittance requirements of optical components such as under-display cameras. The transmittance of the first display area AA1 and the transmittance of the second display area AA2 are measured as transmitted light flux / incident light flux, and are obtained by testing with the display panel in a black screen (not lit) state using an industry-standard integrating sphere haze or transmittance tester.

[0029] The second display area AA2 is the normal display area of ​​the display panel. This area has no special requirements for light transmittance, which is usually less than 5%. Various signal lines and pixel circuits 300 can be laid out in a conventional manner.

[0030] Optionally, the display panel includes a non-display area NA located on the side of the second display area AA2 away from the first display area AA1. The non-display area NA is the border area of ​​the display panel, which can be used to arrange the gate G driving circuit, data driving circuit and other peripheral circuits.

[0031] It is understandable that the first signal line 210 can be an array trace 200 that needs to pass through the first display area AA1. The first signal line 210 can extend from the second display area AA2 to the light-transmitting area TA and go around the edge of the light-transmitting area TA, thereby avoiding the center of the light-transmitting area TA, reducing the obstruction of the light-transmitting area TA, and reducing the impact on the light entering optical components such as the under-display camera.

[0032] Optionally, the pixel circuits 300 arranged in the array are arranged along the row direction or along the column direction. Specifically, the active layers corresponding to transistors with the same function in multiple pixel circuits 300 are arranged along the row direction or along the column direction, or the capacitors with the same function in multiple pixel circuits 300 are arranged along the row direction or along the column direction. In the second display area AA2, the pixel circuit 300 connected by the first signal line 210 and the pixel circuit 300 connected by the second signal line 220 are located in adjacent rows. In the first display area AA1, the pixel circuit 300 connected by the first light-transmitting area ZA1 and the second signal line 220 is located in adjacent rows. At this time, the second signal line 220 can be located in the first light-emitting area FA, or the light-transmitting area TA formed by the first signal line 210 can be located in adjacent rows with the second signal line 220 located in the second display area AA2.

[0033] Please see Figure 2 , Figure 4 as well as Figure 5 In some optional embodiments, the first signal line 210 includes a first segment 211, a second segment 212, and a third segment 213 connected to each other; the first segment 211 is located in the second display area AA2, and at least a portion of the first segment 211 and at least a portion of the third segment 213 extend along the row direction X, and at least a portion of the second segment 212 and the third segment 213 are located around the light-transmitting area TA, with the extension direction of the second segment 212 intersecting the row direction X. The second segment 212 and the third segment 213 may extend along adjacent edges of the light-transmitting area TA, respectively.

[0034] In this embodiment, a first gate driving circuit 110 corresponds to a first signal line 210, driving a row of light-emitting units.

[0035] Optionally, the first light-transmitting area ZA1 includes a first sub-light-transmitting area ZA11 and a second sub-light-transmitting area ZA12. The first sub-display area is close to the second display area AA2, and the second sub-light-transmitting area ZA12 is located on the side of the first sub-light-transmitting area ZA11 away from the second display area AA2. At least a portion of the second segment 212 and at least a portion of the third segment 213 are located around the first sub-light-transmitting area ZA11, and at least a portion of the third segment 213 is located around the second sub-light-transmitting area ZA12.

[0036] Please see Figures 4 to 6 Optionally, the array trace 200 also includes a data line VDATA, which extends at least partially along the column direction Y and forms a portion of the edge of the light-transmitting area T. For example, the data line VDATA can separate the first sub-light-transmitting area ZA11 and the second sub-light-transmitting area ZA12, that is, the data line VDATA can form the edges of the first sub-light-transmitting area ZA11 and the second sub-light-transmitting area ZA12 respectively.

[0037] Optionally, the first signal line 210 includes a first signal sub-line 201 and a second signal sub-line 202. The third segment 213 of the first signal sub-line 201 is arranged adjacent to the second display area AA2, and the third segment 213 of the first signal sub-line 201 is located in the first display area AA1. The third segment 213 of the second signal sub-line 202 is arranged adjacent to the first light-emitting area FA to match the arrangement of the first display area AA1.

[0038] The first segment 211 is located in the second display area AA2, and at least a portion of the first segment 211 extends along the row direction X. The first segment 211 is the main part of the first signal line 210 in the normal display area, and extends along the row direction X after being output from the gate G driving unit, transmitting a scan signal towards the first display area AA1.

[0039] In this embodiment, the second segment 212 extends along the column direction Y, and the second segment 212 and the third segment 213 can be perpendicular to each other. The second segment 212 and the third segment 213 extend along adjacent edges of the light-transmitting area TA, respectively.

[0040] Specifically, the light-transmitting area TA has multiple edges. The second segment 212 extends along one edge of the light-transmitting area TA (e.g., the upper edge or the lower edge), and the third segment 213 extends along another edge of the light-transmitting area TA adjacent to that edge (e.g., the left edge or the right edge). This allows the first signal line 210 to form an L-shaped bypass path along two adjacent edges within the light-transmitting area TA, avoiding the central opening area of ​​the light-transmitting area TA.

[0042] Optionally, there are various ways to set the working principle and circuit structure of the pixel circuit 300. The pixel circuit 300 can be a 2T1C, 4T1C, 7T1C, 7T2C, 8T1C or 8T2C circuit structure, etc.

[0043] Please see Figure 11 As an example, the pixel circuit 300 may include a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first reset transistor T4, a second reset transistor T7, a first control transistor T5, a second control transistor T6, and a second reset transistor T7. The array trace 200 may also include a first power supply voltage signal line ELVDD, a second power supply voltage signal line ELVSS, a first reset signal line VREF1, a second reset signal line VREF2, a light emission control signal line EM, a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, and a fourth scan signal line S4.

[0044] The first terminal of the first control transistor T5 can be electrically connected to the second plate C2 of the capacitor C, and both the first terminal of the first control transistor T5 and the second plate C2 of the capacitor C can be electrically connected to the first power supply voltage signal line ELVDD. The first power supply voltage signal line ELVDD can provide a positive power supply voltage signal to the first control transistor T5 and the capacitor C. The first terminal of the data writing transistor T2 can be electrically connected to the data signal line Vdata, and the data signal line Vdata can provide a data signal to the data writing transistor T2. The second terminal of the data writing transistor T2, the second terminal of the first control transistor T5, and the first terminal of the driving transistor T1 can be electrically connected to each other.

[0045] The second terminal of the driving transistor T1 is electrically connected to the first terminal of the threshold compensation transistor T3. As a further example, the second terminal of the driving transistor T1, the first terminal of the threshold compensation transistor T3, and the first terminal of the second control transistor T6 can be electrically connected to each other. The first terminal of the first reset transistor T4 can be electrically connected to the first reset signal line VREF1, which provides a first reset signal to the first reset transistor T4. The second terminal of the threshold compensation transistor T3, the control terminal of the driving transistor T1, and the second terminal of the first reset transistor T4 can be electrically connected to the first plate C1 of the capacitor C.

[0046] The first terminal of the second reset transistor T7 can be electrically connected to the second reset signal line VREF2, which can provide a second reset signal to the second reset transistor T7. The second terminal of the second reset transistor T7 and the second terminal of the second control transistor T6 can be electrically connected to the first electrode layer 710 of the first light-emitting unit 700. The second electrode layer 730 of the first light-emitting unit 700 can be electrically connected to the second power supply voltage signal line ELVSS (e.g., a negative power supply voltage signal line).

[0047] The control terminal of the second control transistor T6 can be electrically connected to the control terminal of the first control transistor T5, and both the control terminals of the second control transistor T6 and the first control transistor T5 can be electrically connected to the light emission control signal line EM. The control terminal of the first reset transistor T4 can be electrically connected to the first scan signal line S1, the control terminal of the data writing transistor T2 can be electrically connected to the second scan signal line S2, and the control terminal of the threshold compensation transistor T3 can be electrically connected to the third scan signal line S3. The control terminal of the second reset transistor T7 can be electrically connected to the fourth scan signal line S4.

[0048] It should be noted that the control signal line connected to the gate of the data writing transistor T2 is the first signal line 210 in this embodiment, and the multiple control signal lines connected to the data writing transistor T2 are configured one-to-one with the multiple first gate driving circuits.

[0049] Please see Figure 6In some optional embodiments, a plurality of first light-emitting units 700 are provided in the first light-emitting area FA; along the thickness direction Z of the display panel, the first light-emitting unit 700 includes a first electrode layer 710, a light-emitting layer 720 and a second electrode layer 730 stacked together; along the thickness direction Z of the display panel, the third segment 213 and at least a portion of the first electrode layer 710 overlap.

[0050] In this embodiment, by at least partially overlapping the third segment 213 with the first electrode layer 710, the scanning signal lines are laid out using the layout projection area already covered by the first electrode layer 710. This avoids the third segment 213 introducing additional metal traces in the middle of the light-transmitting area TA, reducing the metal's obstruction of light, preserving the effective light-transmitting area of ​​the light-transmitting area TA, and improving the imaging effect of the under-display camera. At the same time, it can save layout space and help improve the pixel density of the first display area AA1. Furthermore, this stacked structure is compatible with existing thin-film processes and is easy to implement in mass production.

[0051] Optionally, the first electrode layer 710 may include a multilayer structure, such as a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed, for example, using silver, a metallic material with excellent light reflectivity. Each conductive oxide layer can be formed, for example, from a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0052] Optionally, the material of the second electrode layer 730 can be one of the following metals: silver (Ag), aluminum (Al), lithium (Li), magnesium (Mg), ytterbium (Yb), calcium (Ca), or indium (In). It can also be an alloy of the aforementioned metals, such as magnesium-silver alloy (Mg / Ag) or lithium-aluminum alloy (Li / Al). This embodiment does not limit this.

[0053] Each of the first light-emitting units 700 may include stacked HIL (Hole Inject Layer), HTL (Hole Transport Layer), light-emitting structure, EIL (Electron Inject Layer), and ETL (Electron Transport Layer).

[0054] Optionally, the second display area AA2 also includes a second light-emitting unit connected to the second pixel circuit 320, and the film structure of the second light-emitting unit can be the same as that of the first light-emitting unit 700.

[0055] like Figure 7 As shown, optionally, the display panel also includes a pixel definition layer 800 disposed on one side of the substrate 600, the pixel definition layer 800 including a pixel opening, and the first light-emitting unit 700 being at least partially located within the pixel opening.

[0056] Along the direction away from the substrate 600, the pixel definition layer 800 includes a first sub-pixel definition layer 810 and a second sub-pixel definition layer 820. The first sub-pixel definition layer 810 includes a light-shielding material. In this embodiment, the first sub-pixel definition layer 810 includes a light-shielding material to provide a light-shielding function, while the second sub-pixel definition layer 820 can be prepared using a conventional light-transmitting material.

[0057] Optionally, the first subpixel definition layer 810 includes a first light-transmitting opening H1.

[0058] Optionally, the display panel also includes a light-shielding structure 900 disposed on the side of the pixel definition layer 800 facing away from the substrate 600. The light-shielding structure 900 forms a second light-transmitting opening H2. The orthographic projection of the second light-transmitting opening H2 on the substrate 600 and the orthographic projection of the first light-emitting unit 700 on the substrate 600 at least partially overlap.

[0059] Optionally, an encapsulation layer FZ may also be provided between the pixel definition layer 800 and the light-shielding structure 900.

[0060] Optionally, the light-transmitting area TA of the display panel is formed by the overlapping area of ​​the light-transmitting area ZA, the first light-transmitting opening H1, and the second light-transmitting opening H2 on the substrate 600. The orthographic projection of the first subpixel definition layer 810 on the substrate 600 and the orthographic projection of the light-shielding structure 900 on the substrate 600 both cover the orthographic projection of the array trace 200 on the substrate 600 to avoid trace reflection problems.

[0061] Optionally, the orthographic projection of the first subpixel definition layer 810 onto the substrate 600 covers the edge of the orthographic projection of the first electrode layer 710 onto the substrate 600.

[0062] In these optional embodiments, the second electrode layer 730 and the first electrode layer 710 can serve as pixel electrode layers of the display panel. One of the second electrode layer 730 and the first electrode layer 710 can serve as an anode layer, and the other can serve as a cathode layer to drive the light-emitting layer 720 to emit light. This application embodiment uses the first electrode layer 710 as the anode layer of the display panel and the second electrode layer 730 as the cathode layer of the display panel for illustrative purposes.

[0063] During the light emission process of the light-emitting unit, the first electrode layer 710 is used to generate holes, and the second electrode layer 730 is used to generate electrons. Holes and electrons combine in the light-emitting unit to make the light-emitting unit emit light.

[0064] In order for the light-emitting unit to emit light, a pixel voltage is provided to the first electrode layer 710 and a common voltage is provided to the second electrode layer 730, respectively. A potential difference is formed between the second electrode layer 730 and the first electrode layer 710, so that the light-emitting layer 720 disposed between the second electrode layer 730 and the first electrode layer 710 emits light.

[0065] Please see Figure 8 In some optional embodiments, along the thickness direction Z of the display panel, the display panel further includes a substrate 600, a first conductive layer M1, a second conductive layer M2 and a third conductive layer M3 stacked together, a first insulating layer J1 is provided between the first conductive layer M1 and the second conductive layer M2, and a second insulating layer J2 is provided between the second conductive layer M2 and the third conductive layer M3. The first segment 211 is located in the first conductive layer M1, the second segment 212 is located in the second conductive layer M2, and the third segment 213 is located in the third conductive layer M3. The first segment 211 and the second segment 212 are connected through the first via K1 of the first insulating layer J1, and the second segment 212 and the third segment 213 are connected through the second via K2 of the second insulating layer J2.

[0066] It should be noted that in this embodiment, by setting the first segment 211, the second segment 212, and the third segment 213 in different conductive layers and using vias to achieve interlayer connection, the direction conversion and detour of the scanning signal line can be achieved without increasing the trace density in the same layer, thus avoiding trace short circuits. Specifically, the first segment 211 extends along the row direction X in the first conductive layer M1 to the edge of the light-transmitting area TA, and then switches to the second conductive layer M2 through the first via K1. In the second conductive layer M2, the second segment 212 extending along the column direction Y is formed. After the second segment 212 extends to the adjacent edge of the light-transmitting area TA, it switches to the third conductive layer M3 through the second via K2. In the third conductive layer M3, the third segment 213 extending along the row direction X is formed, thereby completing the L-shaped detour.

[0067] In this embodiment, the first signal line 210 passes through the adjacent edge of the light-transmitting area TA via a three-segment winding and multi-layer via replacement, which can effectively reduce the occlusion of the scanning signal line on the central area of ​​the light-transmitting area TA and help improve the light transmittance.

[0068] Please see Figures 4 to 5In some optional embodiments, the first display area AA1 includes a plurality of first circuit units P1 arranged sequentially along the row direction X. Each first circuit unit P1 includes at least two pixel circuits 300. The orthographic projection of the first circuit unit P1 on the substrate 600 is located within the orthographic projection range of the first light-emitting area FA on the substrate 600. In the row direction X, there is a first gap between adjacent first circuit units P1. The first gap has a first spacing d1 in the first direction. In the row direction X, the pixel circuits 300 located between the same first circuit unit P1 have a second gap d2. The first gap d1 is greater than the second gap d2.

[0069] In this embodiment, within the same first circuit unit P1, the pixel circuits 300 are arranged closely with a small second gap, which can ensure the pixel arrangement density within the first light-emitting area FA and achieve a high PPI display effect in the first display area AA1. A larger first gap d1 is provided between adjacent first circuit units P1. This gap area can be used to lay array traces 200, such as scan signal lines. The array traces 200 can utilize the layout space formed by the first gap to bypass and bend along the edge of the light-transmitting area TA. The traces can be arranged in the gap between the first circuit units P1 without intruding into the light-transmitting area TA or compressing the pixel arrangement space inside the unit.

[0070] Optionally, the pixel circuit 300 includes an active region. Within the same first circuit unit P1, the orthographic projections of adjacent active regions onto the substrate include mutually close first edges, and the distance between the first edges is a second spacing. In different first circuit units P1, the distance between mutually close first edges is a first distance. The active region is the area where the active layer Q is disposed.

[0071] Optionally, along the thickness direction of the display panel, the area where the first gap d1 is located overlaps with the second light-transmitting area ZA2, that is, the area where the first gap d1 is located can be the second light-transmitting area ZA2.

[0072] Optionally, the second display area AA2 includes multiple second circuit units P2 arranged in an array along the row direction X and the column direction Y, and the second circuit unit P2 includes four pixel circuits 300.

[0073] Optionally, the third segment 213 includes a bent portion W and a straight portion, the straight portion extending along the row direction X, and the bent portion W being positioned relative to the straight portion toward the area where the first gap d1 is located.

[0074] In this embodiment, the bent portion W is positioned relative to the straight portion towards the area where the first gap d1 is located, along the direction perpendicular to the thickness of the display panel, that is, within the plane of the display panel. In this embodiment, the bent portion W protrudes only towards the first light-emitting area FA and does not protrude into the inner blank light-transmitting area TA.

[0075] By limiting the bend W to face the area where the first gap d1 is located relative to the straight part, the layout space required for the trace adjustment is achieved using the first light-emitting area FA, preventing the trace pattern from intruding into the light-transmitting area TA, reducing the obstruction of light by the metal trace, and ensuring the imaging performance of the under-display camera; at the same time, the bend W can provide clearance space for the surrounding pixel circuits 300, vias, and other signal lines, improving the freedom of layout routing; the length of the third segment 213 trace can also be adjusted by the bend W, fine-tuning the parasitic resistance and parasitic capacitance C of the scanning signal line, achieving inter-row load matching, and improving the uniformity of display brightness in the first display area AA1.

[0076] Please see Figures 3 to 5 In some alternative embodiments, the display panel includes a non-display area NA located on the side of the second display area AA2 away from the first display area AA1. The display panel also includes a plurality of first gate driving circuits 110 located in the non-display area NA. Each first gate driving circuit 110 is connected to at least one row of pixel circuits 300. The first gate driving circuit 110 connected to the first signal line 210 and the first gate driving circuit 110 connected to the second signal line 220 are arranged adjacent to each other in the column direction Y. The first signal line 210 and the second signal line 220 are connected to adjacent row pixel circuits 300 located in the first display area AA1.

[0077] Optionally, the array trace 200 also includes a third signal line 230 and a fourth signal line 240 that transmit the same signal. The third signal line 230 and the fourth signal line 240 are connected to adjacent row pixel circuits 300 located in the second display area AA2. The third signal line 230 is connected to the same pixel circuit 300 as the first signal line 210, and the fourth signal line 240 is connected to the same pixel circuit 300 as the second signal line 220. In the same pixel circuit 300, the transistors connected to the third signal line 230 and the first signal line 210 are different.

[0078] The display panel also includes a plurality of second gate driving circuits 120 located in the non-display area NA. In the second display area AA2, the third signal line 230 and the fourth signal line 240 of the adjacent row pixel circuits 300 are connected to the same second gate driving circuit 120.

[0079] In this embodiment, the first signal line 210 and the second signal line 220 of adjacent rows of the first display area AA1 are respectively connected to the adjacent first gate drive circuit 110, and each row is driven independently to reduce crosstalk between rows.

[0080] The third signal line 230 and the fourth signal line 240 share the output of the same second gate drive circuit 120. The same drive signal is simultaneously supplied to the third signal line 230 and the fourth signal line 240 to realize the drive control of the third signal line 230 and the fourth signal line 240.

[0081] In the same pixel circuit 300, the first signal line 210 and the third signal line 230 are connected to different transistors; the second signal line 220 and the fourth signal line 240 are connected to different transistors. This allows for separate control of different functional transistors within the pixel circuit 300, preventing interference between them. This facilitates precise execution of the pixel's internal reset, compensation, and charging timing, reduces the risk of timing coupling in the pixel circuit 300, and minimizes image retention and color shift defects.

[0082] Optionally, the third signal line 230 includes a fourth segment 231 and a fifth segment 232 connected to each other. The fourth segment 231 is located in the second display area AA2, and the fifth segment 232 extends along the edge of the light-transmitting area TA to the first light-emitting area FA.

[0083] The fourth signal line 240 includes a sixth segment 241 and a seventh segment 242 connected to each other. The sixth segment 241 is located in the second display area AA2, and the seventh segment 242 is located in the first display area AA1. The second display area AA2 is located on the side closer to the first display area AA1. The fifth segment 232 and the seventh segment 242 are connected. The extension direction of the fifth segment 232 intersects the extension direction of the fourth segment 231. The extension directions of the fourth segment 231 and the sixth segment 241 are the same. At least a portion of the fifth segment 232 is projected onto the substrate 600 to form the boundary of the light-transmitting area TA.

[0084] It should be noted that in this embodiment, a second gate driving circuit 120 simultaneously drives two sub-signal lines, corresponding to driving two adjacent rows of light-emitting units.

[0085] The third signal line 230 includes a fourth segment 231 and a fifth segment 232 connected to each other. The fourth segment 231 is located in the second display area AA2, extends along the row direction X after being output from the gate G driving unit, and transmits the scan signal towards the first display area AA1. At least a portion of the fifth segment 232 forms the edge of the light-transmitting area TA.

[0086] The fifth segment 232 is the part of the third signal line 230 that bypasses the center area of ​​the light-transmitting area TA, and finally extends to the first light-emitting area FA.

[0087] The sixth segment 241 is located in the second display area AA2, and also extends along the row direction X after being output from the second gate driving circuit 120. The seventh segment 242 is located in the first display area AA1, and can be used to provide scanning signals to the light-emitting units in the first light-emitting area FA. Alternatively, in another embodiment, the seventh segment 242 can also be located in the second display area AA2.

[0088] In this embodiment, the fifth segment 232 of the third signal line 230 extends along the edge of the light-transmitting area TA to the first light-emitting area FA, and then connects with the seventh segment 242 of the fourth signal line 240 within the first light-emitting area FA.

[0089] In this connection method, the scan signals of adjacent rows are transmitted by the fourth segment 231 and the sixth segment 241 respectively before entering the light-transmitting area TA. Within the light-transmitting area TA, only the fifth segment 232 is retained (the sixth segment 241 of the fourth signal line 240 is merged with the third signal line 230 through layer switching or other methods before entering the light-transmitting area TA). After exiting the light-transmitting area TA and reaching the first light-emitting area FA, the fifth segment 232 connects with the seventh segment 242, and then splits into two lines to drive the adjacent two rows of pixels respectively. This reduces the number of lines within the light-transmitting area TA, improves light transmittance, and balances the signal load between adjacent rows.

[0090] Please see Figures 4 to 5 In some optional embodiments, the first light-emitting area FA is arranged in an array within the second display area AA2, and the light-transmitting area TA further includes a second light-transmitting area ZA2. The area of ​​the first light-transmitting area TA1 is larger than the area of ​​the second light-transmitting area ZA2. The first light-transmitting area TA1 and the first light-emitting area FA are arranged alternately along the column direction Y, and the second light-transmitting area ZA2 and the first light-emitting area FA are arranged alternately along the row direction X.

[0091] The fourth sub-signal line includes a first connecting line L1 and a second connecting line L2, which connect different transistors in the same pixel circuit 300. The seventh segment 242 of the first connecting line L1 includes a redundant portion R, which forms the first partial edge of the second light-transmitting area ZA2. The seventh segment 242 of the second connecting line L2 includes a first sub-segment L21, a second sub-segment L22, a third sub-segment L23, and a fourth sub-segment L24. The first sub-segment L21 and the fourth sub-segment L24 are both located within adjacent first light-emitting areas FA. The third sub-segment L23 extends along the column direction Y. The first sub-segment L21, the second sub-segment L22, and the fourth sub-segment L24 extend along the row direction X. The first sub-segment L21 and the fourth sub-segment L24 are located in the same conductive layer, while the first sub-segment L21 and the second sub-segment L22 are located in different conductive layers.

[0092] The second sub-segment L22 and the third sub-segment L23 form the second part of the edge of the second light-transmitting area ZA2.

[0093] It should be noted that the first light-emitting area FA and the first circuit unit P1 are set in a one-to-one correspondence, while the second light-transmitting area ZA2 can refer to the light-transmitting area between adjacent first circuit units P1 along the row direction X.

[0094] In this embodiment, the bent portion W protruding towards the first light-emitting area FA can be arranged close to the redundant portion R of the seventh segment 242, that is, the redundant portion R can be arranged to protrude in the direction of the bent portion W, and the bent portion W can be arranged to protrude in the direction of the redundant portion R, so as to increase the area of ​​the first light-transmitting area TA1 and the second light-transmitting area ZA2.

[0095] Please see Figure 5 Optionally, the orthographic projection of the first electrode layer 710 on the substrate 600 covers the orthographic projection of at least one of the redundant portion R and the bent portion W on the substrate 600.

[0096] Optionally, the first segment L21 can be electrically connected to the first adapter line N1 located on another conductive layer through a via. The first adapter line N1 is connected to the second segment L22. The first adapter line N1 and the second segment L22 can be located on the same conductive layer or on different conductive layers.

[0097] The second sub-segment L22 can be directly connected to the third sub-segment L23. Alternatively, the second sub-segment L22 can be electrically connected to the second adapter N2 located on another conductive layer via a via. The second adapter N2 can be located on the same conductive layer as the first adapter N1. Then, the second adapter N2 is connected to the third sub-segment L23 via a via.

[0098] Optionally, the first sub-segment L21, the third sub-segment L23, and the fourth sub-segment L24 can be located in the first conductive layer M1, the first adapter line N1 and the second adapter line N2 can be located in the second conductive layer M2, and the second sub-segment L22 can be located in the third conductive layer M3. By restricting the first sub-segment L21 and the second sub-segment L22 to be located in different conductive layers, the second sub-segment L22 can avoid other signal traces. For example, the array trace 200 also includes a fifth signal line 250, which is disposed in the same layer as the first sub-segment L21, and the fifth signal line 250 is located on one side of the second light-transmitting area ZA2 along the column direction Y.

[0099] Optionally, the orthographic projection of the fifth signal line 250 onto the substrate 600 partially coincides with the second sub-segment L22.

[0100] Optionally, the orthographic projection of the first adapter line N1 and the corresponding via on the substrate 600 forms the third edge of the second light-transmitting region ZA2. The first adapter line N1, the second adapter line N2, and the corresponding via are all located on the periphery of the second light-transmitting region ZA2.

[0101] Optionally, the third signal line 230, the fourth signal line 240, and the fifth signal line 250 can all be scan signal lines.

[0102] Optionally, along the thickness direction Z of the display panel, the display panel also includes a substrate 600 and at least two conductive layers disposed on one side of the substrate 600; the fourth segment 231 and the fifth segment 232 are located in different conductive layers, and the third signal line 230 achieves bypass by changing layers. The fourth segment 231 extends in the first conductive layer M1, and the fifth segment 232 switches to extend along the edge of the light-transmitting area TA in the second conductive layer M2 or the third conductive layer M3.

[0103] Along the thickness direction Z of the display panel, the seventh segment 242 and the first light-emitting unit 700 at least partially overlap. That is, the seventh segment 242 has an overlapping area with the first light-emitting unit 700 in the thickness direction. This is because the seventh segment 242 is located within the first light-emitting area FA and needs to provide scanning signals to the pixel circuit 300. Its wiring position will inevitably partially overlap with the light-emitting unit in the thickness direction.

[0104] In this embodiment, by using a one-to-two signal line parallel design, only the seventh segment 242 of the fourth signal line 240 is retained in the light-transmitting area TA. This reduces metal obstruction in the light-transmitting area TA and balances the load of adjacent two lines of signals, which is beneficial to improving light transmittance and display uniformity.

[0105] Optionally, the first electrode layer 710 is disposed close to the substrate 600 relative to the light-emitting layer 720.

[0106] Please see Figures 9 to 10 In some optional embodiments, the display panel further includes a first reset signal line 400; a first light-emitting unit 700 is provided in the light-transmitting area TA, and a second light-emitting unit is provided in the second display area AA2; the first reset signal line 400 includes an eighth segment 410 extending along the row direction X and a ninth segment 420 extending along the column direction Y connected to each other; the first reset signal line 400 is provided in the first light-emitting area FA and the second display area AA2, the first light-emitting area FA has the eighth segment 410 of the first reset signal line 400, and the second display area AA2 has the eighth segment 410 and the ninth segment 420.

[0107] It is understood that in this embodiment, the first reset signal line 400 is used to provide a reset voltage signal to the pixel circuit 300 to realize the reset function of the pixel circuit 300. In the first light-emitting area FA, only the eighth segment 410 of the first reset signal line 400 is provided, that is, the first reset signal line 400 extends only along the row direction X in the first light-emitting area FA, and the ninth segment 420 extending along the column direction Y is not provided, so as to reduce the wiring density in the first light-emitting area FA. In the second display area AA2, both the eighth segment 410 and the ninth segment 420 are provided, that is, the first reset signal line 400 has wiring along both the row direction X and the column direction Y in the second display area AA2.

[0108] Optionally, along the thickness direction Z of the display panel, a portion of the first reset signal line 400 and the first light-emitting unit 700 overlap; in the second display area AA2, a portion of the first reset signal line 400 and the second light-emitting unit overlap; and the first reset signal line 400 and the light-transmitting area TA do not overlap.

[0109] In this embodiment, the first reset signal line 400 and the light-transmitting area TA do not overlap. The first reset signal line 400 is only arranged within the first light-emitting area FA and the second display area AA2, and does not pass through the light-transmitting area TA, thereby avoiding additional metal obstruction of the light-transmitting area TA by the first reset signal line 400. In the prior art, the first reset signal line 400 is usually uniformly arranged throughout the entire display area, including passing through the light-transmitting area TA, while this application confines the first reset signal line 400 within the first light-emitting area FA and the second display area AA2, completely avoiding the light-transmitting area TA.

[0110] Along the thickness direction Z of the display panel, a portion of the first reset signal line 400 and the first light-emitting unit 700 overlap; that is, within the first light-emitting area FA, a portion of the eighth segment 410 overlaps with the first light-emitting unit 700 in the thickness direction. In the second display area AA2, a portion of the first reset signal line 400 and the second light-emitting unit overlap; that is, within the second display area AA2, a portion of the eighth segment 410 and the ninth segment 420 overlap with the second light-emitting unit in the thickness direction. Since the first reset signal line 400 is located in the metal layer below or above the light-emitting unit, its overlap with the light-emitting unit in the thickness direction will not directly block the front light emission of the light-emitting unit.

[0111] Optionally, in the second display area AA2, the eighth segment 410 and the ninth segment 420 form a mesh structure. Multiple eighth segments 410 extending along the row direction X and multiple ninth segments 420 extending along the column direction Y are interconnected to form a mesh-like reset signal trace structure. This mesh structure helps to ensure the stability and uniformity of the reset voltage signal within the second display area AA2 and reduces voltage drop differences caused by trace impedance.

[0112] Please see Figure 10 Optionally, a portion of the first reset signal line 400 extends along the edge of the light-transmitting area TA. The first reset signal line 400 and the scan signal line can be located in different conductive layers to avoid mutual interference. The first reset signal line 400 can also be located at the edge of the pixel circuit 300 to avoid affecting the light emission of the corresponding light-emitting unit.

[0113] Optionally, in the second display area AA2, at least a portion of the orthographic projections of the first signal line 210 and the first reset signal line 400 on the substrate 600 overlap. By partially overlapping the first signal line 210 and the first reset signal line 400 in the second display area AA2, the layout space required for in-plane wiring can be saved, while ensuring the light transmittance of the second display area AA2.

[0114] Optionally, the display panel also includes a reset signal driving unit 500, with the first reset signal line 400 electrically connected to the reset signal driving unit 500. The reset signal driving unit 500 can be a driver chip.

[0115] In some optional embodiments, along the thickness direction Z of the display panel, the display panel further includes a substrate 600, a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3 stacked together. A first insulating layer J1 is provided between the first conductive layer M1 and the second conductive layer M2, and a second insulating layer J2 is provided between the second conductive layer M2 and the third conductive layer M3. The eighth segment 410 is located in the first conductive layer M1 or the second conductive layer M2, and the ninth segment 420 is located in the third conductive layer M3.

[0116] By placing the eighth segment 410 and the ninth segment 420 on different conductive layers, short circuits at the intersection of two traces in different directions can be avoided, while also improving layout utilization. The eighth segment 410 and the ninth segment 420 are electrically connected at their intersection via vias, thus forming a complete reset signal network.

[0117] In this embodiment, by confining the first reset signal line 400 within the first light-emitting area FA and the second display area AA2, and without passing through the light-transmitting area TA, the metal trace density within the light-transmitting area TA can be further reduced, which is beneficial for improving light transmittance. The grid-like structure within the second display area AA2 helps ensure the stability of the reset signal.

[0118] Optionally, the array trace 200 also includes a second reset signal line V and a fifth signal line 250 that transmit different signals. The second reset signal line V and the fifth signal line 250 are located in different layers of the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3. Along the column direction Y, the second reset signal line V and the fifth signal line 250 are located on the same side of the first light-emitting area FA. Along the thickness direction Z of the display panel, the second reset signal line V and the fifth signal line 250 at least partially overlap.

[0119] Optionally, the fifth signal line 250 can be disposed on the first conductive layer M1, and the second reset signal line V can be disposed on either the second conductive layer M2 or the third conductive layer M3 to avoid mutual interference. Along the thickness direction Z of the display panel, the second reset signal line V and the fifth signal line 250 at least partially overlap to save layout space, alleviate the problem of tight layout wiring, and facilitate a higher pixel density in the first display area AA1.

[0120] Please see Figure 6 Optionally, the pixel circuit 300 includes a transistor and a capacitor C. The capacitor C includes a first electrode C1 and a second electrode C2. The transistor includes a source S, a drain D, a gate G, and an active layer Q. Multiple conductive layers include a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3. The gate G and the first electrode C1 can be located on the first conductive layer M1, the second electrode C2 can be located on the second conductive layer M2, and the source S and the drain D can be located on the third conductive layer M3.

[0121] This invention also provides a display device, including a display panel as described in any of the above embodiments.

[0122] The display device provided in this embodiment of the invention has the technical effects of the display panel in any of the above embodiments. The explanations of the same or corresponding structures and terms in the above embodiments will not be repeated here.

[0123] The display device provided in the embodiments of the present invention can be an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode (QLED) device, or a micro flat panel display device (Micro-OLED or Micro-LED), etc.

[0124] The display device provided in this embodiment of the invention can be applied to mobile phones or any electronic product with display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. This embodiment of the invention does not impose any special limitations on these.

[0125] The above are merely specific embodiments of the present invention. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the protection scope of the present invention.

[0126] It should also be noted that the exemplary embodiments mentioned in this invention describe methods or systems based on a series of steps or apparatus. However, this invention is not limited to the order of the steps described above; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

Claims

1. A display panel, characterized in that, The display panel includes a first display area and a second display area at least partially surrounding the first display area. The first display area includes a light-transmitting area and a first light-emitting area adjacent to the light-transmitting area. The display panel includes: Substrate; A pixel circuit is arrayed on one side of a substrate, and at least part of the pixel circuit includes a first pixel circuit located in a first display area and a second pixel circuit located in a second display area, wherein the density of the second pixel circuit is less than the density of the first pixel circuit. The array traces extend at least partially from the first display area to the second display area, the array traces are connected to at least one row of the pixel circuits, and at least a portion of the array traces form a partial edge of the light-transmitting area; The light-transmitting area includes a first light-transmitting area, and the array traces include a first signal line and a second signal line that transmit the same signal. The number of pixel circuits connected to the first signal line is less than the number of pixel circuits connected to the second signal line, and at least a portion of the first signal line forms a portion of the edge of the first light-transmitting area.

2. The display panel according to claim 1, characterized in that, In the second display area, the pixel circuits connected to the first signal line and the pixel circuits connected to the second signal line are located in adjacent rows; In the first display area, the pixel circuits connected to the first light-transmitting area and the second signal line are located in adjacent rows; The first signal line includes a first segment, a second segment, and a third segment that are connected to each other; The first segment is located in the second display area, and at least a portion of the first segment and at least a portion of the third segment extend along the row direction, and at least a portion of the second segment and the third segment are located around the light-transmitting area, with the extension direction of the second segment intersecting the row direction; The first light-transmitting area includes a first sub-light-transmitting area and a second sub-light-transmitting area. The first sub-light-transmitting area is close to the second display area, and the second sub-light-transmitting area is located on the side of the first sub-light-transmitting area away from the second display area. At least a portion of the second segment and a portion of the third segment are located on the periphery of the first sub-light-transmitting area, and a portion of the third segment is located on the periphery of the second sub-light-transmitting area. Preferably, the first signal line includes a first signal sub-line and a second signal sub-line, at least a portion of the first signal sub-line is disposed close to the second display area relative to the second signal sub-line, a third segment of the first signal sub-line is disposed adjacent to the second display area, and the third segment of the first signal sub-line is located in the first display area, and the third segment of the second signal sub-line is disposed adjacent to the first light-emitting area.

3. The display panel according to claim 2, characterized in that, Multiple first light-emitting units are provided in the first light-emitting area; Along the thickness direction of the display panel, the first light-emitting unit includes a first electrode layer, a light-emitting layer, and a second electrode layer stacked together; Along the thickness direction of the display panel, the third segment overlaps with at least a portion of the first electrode layer.

4. The display panel according to claim 2, characterized in that, Along the thickness direction of the display panel, the display panel further includes a first conductive layer, a second conductive layer and a third conductive layer disposed on one side of the substrate and stacked thereon, a first insulating layer is provided between the first conductive layer and the second conductive layer, and a second insulating layer is provided between the second conductive layer and the third conductive layer; The first segment is located in the first conductive layer, the second segment is located in the second conductive layer, and the third segment is located in the third conductive layer. The first segment and the second segment are connected through a first via in the first insulating layer, and the second segment and the third segment are connected through a second via in the second insulating layer.

5. The display panel according to claim 2, characterized in that, The first display area includes a plurality of first circuit units arranged sequentially along the row direction. Each first circuit unit includes at least two pixel circuits. The orthographic projection of the first circuit unit on the substrate is located within the orthographic projection range of the first light-emitting area on the substrate. In the row direction, there is a first gap between adjacent first circuit units, and in the row direction, there is a second gap between pixel circuits located in the same first circuit unit. In the row direction, the first spacing of the first gap is greater than the second spacing of the second gap. In the column direction, there is a third gap between adjacent first circuit units, and the third gap in the column direction is greater than the first gap; The light-transmitting area includes a first light-transmitting area and a second light-transmitting area, with at least a portion of the first light-transmitting area located within the third gap and at least a portion of the second light-transmitting area located within the first gap; Preferably, the third segment includes a bent portion and a straight portion, the straight portion extending along the row direction, and the bent portion being disposed relative to the straight portion toward the area where the first gap is located.

6. The display panel according to claim 5, characterized in that, The display panel includes a non-display area located on the side of the second display area away from the first display area. The display panel also includes a plurality of first gate driving circuits located in the non-display area. The plurality of first gate driving circuits are cascaded. Each first gate driving circuit is connected to at least one row of the pixel circuits. The first gate driving circuit connected to the first signal line and the first gate driving circuit connected to the second signal line are arranged adjacent to each other in the column direction. The first signal line and the second signal line are connected to the pixel circuits located in adjacent rows within the first display area. Preferably, the array traces further include a third signal line and a fourth signal line that transmit the same signal. The third signal line and the fourth signal line are connected to adjacent row pixel circuits located in the second display area. The third signal line is connected to the same pixel circuit as the first signal line, and the fourth signal line is connected to the same pixel circuit as the second signal line. In the same pixel circuit, the transistors connected to the third signal line and the first signal line are different. The display panel also includes a plurality of second gate driving circuits located in the non-display area. The plurality of second gate driving circuits are cascaded. In the second display area, the third signal line and the fourth signal line of the pixel circuit in adjacent rows are connected to the same second gate driving circuit. Preferably, the third signal line includes a fourth segment and a fifth segment connected to each other, the fourth segment being located in the second display area, and the fifth segment extending along a portion of the edge of the first sub-transparent area to the first light-emitting area; Within the same first light-transmitting area, the orthographic projection of the fifth segment onto the substrate is located on the side of the second segment facing the second display area; The fourth signal line includes a sixth segment and a seventh segment connected together. The sixth segment is located in the second display area, and the seventh segment is located in the first display area. On the side of the second display area closer to the first display area, the fifth segment and the seventh segment are connected together. The extension direction of the fifth segment intersects the extension direction of the fourth segment, and the extension directions of the fourth segment and the sixth segment are the same.

7. The display panel according to claim 6, characterized in that, The first light-emitting area is arranged in an array within the second display area, and the area of ​​the first light-transmitting area is larger than the area of ​​the second light-transmitting area; The first light-transmitting area and the first light-emitting area are arranged alternately along the column direction, and the second light-transmitting area and the first light-emitting area are arranged alternately along the row direction; The fourth signal line includes a first connecting line and a second connecting line, which are connected to different transistors in the same pixel circuit. The seventh segment of the first connecting line includes a redundant portion, which forms a first portion of the edge of the second light-transmitting area; The seventh segment of the second connecting line includes a first sub-segment, a second sub-segment, a third sub-segment, and a fourth sub-segment. The first sub-segment and the fourth sub-segment are both located within adjacent first light-emitting areas. The third sub-segment extends along the column direction, while the first, second, and fourth sub-segments extend along the row direction. The first sub-segment and the fourth sub-segment are located in the same conductive layer, while the first sub-segment and the second sub-segment are located in different conductive layers. The second segment and the third segment form the second partial edge of the second light-transmitting area.

8. The display panel according to claim 7, characterized in that, Along the thickness direction of the display panel, the display panel further includes at least two conductive layers disposed on one side of the substrate; The fourth segment and the fifth segment are located in different conductive layers.

9. The display panel according to claim 1, characterized in that, The array traces also include a first reset signal line; The first reset signal line includes an eighth segment extending in the row direction and a ninth segment extending in the column direction, which are connected to each other. The first reset signal line is disposed in the first light-emitting area and the second display area. In the first light-emitting area, the eighth segment of the reset signal line is provided. In the second display area, the eighth segment and the ninth segment are provided. Preferably, a portion of the reset signal line extends along the edge of the light-transmitting area; Preferably, in the second display area, the orthographic projections of the eighth segment and the ninth segment onto the substrate form a grid-like structure; Preferably, along the thickness direction of the display panel, the display panel further includes a first conductive layer, a second conductive layer, and a third conductive layer stacked on one side of the substrate, wherein a first insulating layer is provided between the first conductive layer and the second conductive layer, and a second insulating layer is provided between the second conductive layer and the third conductive layer; The eighth segment is located in the first conductive layer or the second conductive layer, and the ninth segment is located in the third conductive layer; Preferably, in the second display area, at least a portion of the orthographic projections of the first signal line and the reset signal line on the substrate overlap; Preferably, the array traces further include a second reset signal line and a fifth signal line that transmit different signals, the second reset signal line and the fifth signal line being located in different layers of the first conductive layer, the second conductive layer and the third conductive layer; Along the column direction, the second reset signal line and the fifth signal line are located on the same side of the first light-emitting area, and along the thickness direction of the display panel, the second reset signal line and the fifth signal line at least partially overlap. Preferably, the array traces further include data lines, at least a portion of which connect pixel circuits located in the first display area and pixel circuits located in the second display area. The data lines extend at least a portion along the column direction and at least a portion of which form a partial edge of the light-transmitting area.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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