A chip dicing method suitable for d2w hybrid bonding multilayer stack

Abstract

The application relates to a chip cutting method suitable for a D2W mixed bonding multilayer stack, and belongs to the field of semiconductor packaging. At least one of the problems of obvious peeling and layering, cracks, particles, low cutting efficiency and uneven cutting quality in the process of double-sided medium layer chip cutting in the D2W mixed bonding multilayer stack is solved. The chip cutting method comprises the following steps: front surface coating of a laser protection liquid; front surface laser grooving; turning over; back surface coating of a laser protection liquid; back surface laser grooving; substrate cutting and wafer expanding. The application reduces the problems of layering, edge unevenness, particle accumulation and the like, improves the chip cutting quality, is higher in cutting efficiency, and is uniform in cutting quality.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a chip dicing method applicable to D2W hybrid bonding multilayer stacking. Background Technology

[0002] Hybrid bonding eliminates traditional metal solder joints, enabling novel packaging technologies that directly achieve metal-to-metal and dielectric-to-dielectric interconnects. This technology breaks through the bandwidth interconnection limit and is an important means to achieve high-density three-dimensional integrated packaging. Among them, chip-to-wafer (D2W) hybrid bonding is compatible with multi-layer stacking of small chips of various sizes and functions. However, D2W hybrid bonding has extremely high requirements for the cleanliness of chip surfaces and edges. Therefore, chip dicing faces significant challenges. How to achieve low-defect, high-quality dicing of multi-layer stacked chips is currently a major problem facing the D2W hybrid bonding process.

[0003] In D2W hybrid bonding multilayer stacking processes, double-sided dielectric layer chips offer significant advantages over single-sided dielectric layer chips in terms of electrical performance, physical protection, and process compatibility. However, double-sided dielectric layer chips are significantly more difficult to dice than single-sided dielectric layer chips, especially when the double-sided dielectric layer also contains metal structures (such as metal wiring layers and metal pads), where the dicing challenges are even more pronounced. Existing dicing methods suffer from numerous problems when applied to double-sided dielectric layer wafer dicing, such as obvious delamination, cracks, and grain defects on the top and bottom surfaces of the chip, as well as low dicing efficiency and uneven dicing quality. These problems severely limit the promotion and use of double-sided dielectric layer chips in high-end applications. Summary of the Invention

[0004] Based on the above analysis, the present invention aims to provide a chip dicing method applicable to D2W hybrid bonding multilayer stacking, in order to solve at least one of the following problems in the dicing of double-sided dielectric layer chips in the D2W hybrid bonding multilayer stacking process: obvious peeling and delamination, cracks, grains, low dicing efficiency, and uneven dicing quality.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] This invention provides a chip dicing method applicable to D2W hybrid bonding multilayer stacking. The wafer to be diced mainly consists of a substrate and dielectric layers located on the upper and lower surfaces of the substrate, respectively. The dielectric layer on the upper surface of the substrate constitutes the dielectric layer on the front side of the wafer, while the dielectric layer on the lower surface of the substrate constitutes the dielectric layer on the back side of the wafer. The dielectric layer on the front side and / or the dielectric layer on the back side of the wafer includes a metal structure.

[0007] The chip cutting method includes the following steps:

[0008] (1) Apply laser protective liquid to the front side:

[0009] The dielectric layer surface on the back side of the wafer is bonded to the first carrier, with the dielectric layer on the front side of the wafer facing upwards; laser protective liquid A is coated on the dielectric layer surface on the front side of the wafer.

[0010] (2) Front laser grooving:

[0011] Laser grooving is performed on the dielectric layer on the front side of the wafer along the dicing path until the groove formed by laser etching penetrates the dielectric layer on the front side of the wafer; after laser grooving on the front side, the laser protective solution A is removed by cleaning.

[0012] (3) Flip:

[0013] Debond the dielectric layer surface on the back side of the wafer from the first carrier, and cover the dielectric layer surface on the front side of the wafer with the second carrier; flip the wafer so that the dielectric layer on the back side of the wafer faces upward; after flipping, ensure that the dielectric layer surface on the front side of the wafer is bonded to the second carrier.

[0014] (4) Apply laser protective liquid to the back side:

[0015] Laser protective solution B is applied to the dielectric layer surface on the back side of the wafer;

[0016] (5) Laser grooving on the back:

[0017] Laser grooving is performed on the dielectric layer on the back side of the wafer along the dicing path until the groove formed by laser etching penetrates the dielectric layer on the back side of the wafer.

[0018] (6) Base cutting and expansion.

[0019] Furthermore, in step (2), the depth of the laser grooving is equal to the thickness of the laser protective liquid A plus 100%-120% of the thickness of the dielectric layer on the front side of the wafer.

[0020] In step (5), the depth of the laser grooving is equal to the thickness of the laser protective liquid B plus 100%-120% of the thickness of the dielectric layer on the back side of the wafer.

[0021] Furthermore, in steps (2) and (5), the width of the cutting channel is 10 μm-400 μm; and / or,

[0022] In steps (2) and (5), the wavelength of the laser grooving is 200-600nm, the power is 10-200W, the pulse frequency is 1kHz-100MHz, the pulse width is 10fs-100ns, and the laser spot diameter is 10-100μm.

[0023] Furthermore, in steps (2) and (5), the width of the laser grooving is equal to (30% - 80%) × the width of the cutting path; and / or,

[0024] The centerline of the laser grooving and the centerline of the cutting path deviate by no more than 10 μm.

[0025] Furthermore, in the wafer to be diced, the thickness of the dielectric layer is 10nm-20μm, the thickness of the substrate is 10μm-780μm, and the metal structure includes metal pads with a pad pitch of 0.4μm-20μm, a pad depth of 10nm-1000nm, and an area of ​​0.03μm for each metal pad. 2 -100μm 2 .

[0026] Furthermore, in steps (2) and (5), the wavelength of the laser grooving is 200-350nm, the power is 100-200W, the pulse frequency is 1kHz-10MHz, the pulse width is 10fs-500ps, and the laser spot diameter is 10-40μm; and / or,

[0027] The laser used for laser grooving is a UV picosecond or UV femtosecond laser.

[0028] Furthermore, in steps (1) and (4), the thicknesses of both laser protective liquid A and laser protective liquid B are controlled to be 1-10 μm; and / or,

[0029] The coating method is spin coating, and the spin coating speed is 1000-3000 rpm.

[0030] Further, in step (2), the cleaning and removal of laser protective liquid A includes: cleaning by spin coating combined with megasonic or two-fluid method within 48 hours after coating laser protective liquid A; after cleaning, the number of particles on the wafer surface and in the grooves formed by laser etching is ≤100 particles@500nm.

[0031] Furthermore, in steps (1) and (3), the first carrier and the second carrier are selected from one of UV blue film, silicon-based wafer carrier, and transparent glass carrier.

[0032] Furthermore, the chip obtained according to the above chip cutting method has a serpentine edge less than 2μm, a chip surface contamination number ≤100 particles @90nm, and a layer width between the dielectric layer and the substrate in the chip ≤1μm.

[0033] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0034] This invention is applicable to wafer cutting with double-sided dielectric layers and metal parts, which is currently difficult to cut. By sequentially laser-grooving the dielectric layers on the front and back sides of the wafer, the difficult-to-cut dielectric layers and their contained metal structures are pre-grooved, avoiding problems such as interface delamination, uneven edges, and particle accumulation caused by direct cutting. This improves chip cutting quality, increases cutting efficiency, and ensures uniform cutting quality.

[0035] (1) Avoiding interface delamination: In traditional dicing methods, when directly dicing a wafer, the dicing force generates a complex stress distribution inside the wafer. For wafers with double-sided dielectric layers and metal structures, this stress can lead to stress concentration at the interface between different material layers, thus causing delamination. However, this invention effectively disperses the dicing stress by dicing the dielectric layer and substrate of different materials in stages, resulting in no obvious delamination between the dielectric layer and the substrate.

[0036] (2) Avoid uneven edges: This invention effectively disperses cutting stress and reduces material deformation and uneven edges by cutting the dielectric layer and substrate of different materials in stages. The cutting process also includes cleaning and flipping steps. The cleaning step can remove particulate impurities generated during the cutting process (such as particles on the wafer surface and in the grooves formed by laser etching), avoiding the influence of these impurities on the cutting edges. The flipping step ensures that the cutting process is carried out evenly on the front and back of the wafer, further reducing uneven edges caused by uneven stress distribution.

[0037] (3) Avoid particle accumulation: Compared with mechanical cutting, the present invention generates relatively fewer particles in the laser grooving of the front and back sides of the wafer in stages, and includes a cleaning and flipping step between the laser grooving of the front and back sides. The cleaning step can effectively remove particle contamination (particles on the wafer surface and in the grooves formed by laser etching) generated during the grooving process; by flipping the wafer, and during the grooving process after flipping, the laser can act on the wafer surface again, further reducing particle accumulation.

[0038] (4) Improved cutting efficiency: Traditional low-defect cutting techniques, such as plasma etching and laser stealth cutting, have limitations in cutting efficiency, especially when processing media containing metallic structures, where the cutting speed is even slower. This invention employs laser grooving and ensures complete grooving when processing media layers containing metallic structures (which are denser than the substrate), significantly improving cutting efficiency.

[0039] (5) In some preferred embodiments, the present invention helps to better avoid problems such as interface delamination, uneven edges, and particle accumulation by controlling the parameters and conditions of laser grooving, coating and cleaning of laser protective liquid, thereby improving chip cutting quality, taking into account cutting efficiency, and reducing the fluctuation of cutting quality in each batch.

[0040] (6) The chip obtained by the chip dicing method provided by this invention has no obvious delamination between the dielectric layer and the substrate, the chip edge is flat, and the chip surface has few particle deposits, which can meet the requirements of D2W hybrid bonding. Specifically, the chip edge serpentine shape obtained by the chip dicing method in the embodiments of this invention is less than 2μm, the number of contaminated particles on the chip surface is ≤100 @90nm, and the delamination width between the dielectric layer and the substrate in the chip is ≤1μm. Therefore, this invention provides a new high-quality chip dicing scheme for D2W hybrid bonding multilayer stacking process.

[0041] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0042] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0043] Figure 1 A flowchart illustrating steps (1) and (2) of the chip cutting method provided in this embodiment of the invention;

[0044] Figure 2 This is a flowchart illustrating step (3) of the chip cutting method provided in this embodiment of the invention.

[0045] Figure 3 A flowchart illustrating steps (4) to (6) of the chip cutting method provided in this embodiment of the invention;

[0046] Figure 4 A flowchart illustrating the chip cutting method provided for Comparative Example 1;

[0047] Figure label:

[0048] 100 - Wafer; 11a - Dielectric layer on the front side of the wafer; 11b - Dielectric layer on the back side of the wafer; 12 - Substrate; 13a - Cutter track on the front side of the wafer; 13b - Cutter track on the back side of the wafer; 200 - Bearing blue film; 20a - First carrier; 20b - Second carrier; 30a - Laser protection solution A on the front side of the wafer; 30b - Laser protection solution B on the back side of the wafer. Detailed Implementation

[0049] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0050] Currently, common methods for cutting multilayer chips include... Figure 4 As shown, the main process flow is as follows: after thinning, the wafer with dielectric layers on both sides is pasted onto the carrier blue film, and the wafer is cut from the surface to the bottom using blade cutting, plasma cutting or laser stealth cutting, etc., and then expanded to realize the chip cutting and separation. However, the inventors found in their research that this direct cutting method has the following problems: (1) it causes obvious peeling, delamination, cracks, particles and other defects on the upper and lower surfaces of the chip, affecting the multi-layer stacking bonding process of the chip; (2) when the dielectric layer includes a metal structure, the presence of metal in the cutting path will affect the cutting efficiency of the blade, plasma or laser, or even damage it; (3) the bonding dielectric material on the upper and lower surfaces of the chip and the substrate material in the middle have large performance differences, which leads to a significant reduction in the cutting efficiency of the dielectric layer and uneven cutting quality.

[0051] Based on this, the present invention provides a chip dicing method applicable to D2W hybrid bonding multilayer stacking. The wafer to be diced mainly consists of a substrate and dielectric layers located on the upper and lower surfaces of the substrate, respectively. The dielectric layer on the upper surface of the substrate constitutes the dielectric layer on the front side of the wafer, while the dielectric layer on the lower surface of the substrate constitutes the dielectric layer on the back side of the wafer. The dielectric layer on the front side and / or the dielectric layer on the back side of the wafer includes a metal structure.

[0052] The chip cutting method includes the following steps:

[0053] (1) Apply laser protective liquid to the front side:

[0054] The dielectric layer surface on the back side of the wafer is bonded to the first carrier, with the dielectric layer on the front side of the wafer facing upwards; laser protective liquid A is coated on the dielectric layer surface on the front side of the wafer.

[0055] (2) Front laser grooving:

[0056] Laser grooving is performed on the dielectric layer on the front side of the wafer along the dicing path until the groove formed by laser etching penetrates the dielectric layer on the front side of the wafer; after laser grooving on the front side, the laser protective solution A is removed by cleaning.

[0057] (3) Flip:

[0058] Debond the dielectric layer surface on the back side of the wafer from the first carrier, and cover the dielectric layer surface on the front side of the wafer with the second carrier; flip the wafer so that the dielectric layer on the back side of the wafer faces upward; after flipping, ensure that the dielectric layer surface on the front side of the wafer is bonded to the second carrier.

[0059] (4) Apply laser protective liquid to the back side:

[0060] Laser protective solution B is applied to the dielectric layer surface on the back side of the wafer;

[0061] (5) Laser grooving on the back:

[0062] Laser grooving is performed on the dielectric layer on the back side of the wafer along the dicing path until the groove formed by laser etching penetrates the dielectric layer on the back side of the wafer; after laser grooving on the back side, laser protective solution B is retained;

[0063] (6) Base cutting and expansion.

[0064] For example, the metal structure includes metal pads and a metal wiring layer. The metal pads are located on the surface of the dielectric layer, and the metal wiring layer is located inside the dielectric layer. The metal wiring layer is suitable for memory devices, logic devices, etc. For example, the number of metal wiring layers is 1 to 5.

[0065] Compared with existing technologies, the present invention is applicable to the scenario of wafer cutting with double-sided dielectric layers and metal parts, which is currently difficult to cut. By sequentially laser-grooving the dielectric layers on the front and back sides of the wafer, the difficult-to-cut dielectric layers and their contained metal structures are grooved in advance, avoiding problems such as interface delamination, uneven edges, and particle accumulation caused by direct cutting. This improves the chip cutting quality, cuts more efficiently, and produces more uniform cutting quality.

[0066] (a) Avoiding Interface Delamination: In traditional dicing methods, direct dicing of the wafer generates a complex stress distribution within the wafer. For wafers with double-sided dielectric layers and metallic structures, this stress leads to stress concentration at the interfaces between different material layers, resulting in delamination. This invention, by dicing the dielectric layer and substrate in stages using different materials, effectively disperses the dicing stress, eliminating significant delamination between the dielectric layer and the substrate.

[0067] (b) Avoiding uneven edges: This invention effectively disperses cutting stress and reduces material deformation and uneven edges by cutting the dielectric layer and substrate of different materials in stages. The cutting process also includes cleaning and flipping steps. The cleaning step can remove particulate impurities generated during the cutting process (such as particles on the wafer surface and in the grooves formed by laser etching), avoiding the influence of these impurities on the cutting edges. The flipping step ensures that the cutting process is carried out evenly on the front and back of the wafer, further reducing uneven edges caused by uneven stress distribution.

[0068] (c) Avoid particle accumulation: Compared with mechanical cutting, the present invention generates relatively fewer particles in the laser grooving of the front and back sides of the wafer in stages, and includes a cleaning and flipping step between the laser grooving of the front and back sides. The cleaning step can effectively remove particle contamination (particles on the wafer surface and in the grooves formed by laser etching) generated during the grooving process; by flipping the wafer, and during the grooving process after flipping, the laser can act on the wafer surface again, further reducing particle accumulation.

[0069] (d) Improved cutting efficiency: Traditional low-defect cutting techniques, such as plasma etching and laser stealth cutting, have limitations in cutting efficiency, especially when processing media containing metallic structures, where the cutting speed is even slower. This invention employs laser grooving and ensures complete grooving when processing media layers containing metallic structures (which are denser than the substrate), significantly improving cutting efficiency.

[0070] (e) More uniform cutting quality: Traditional direct cutting methods often result in uneven cutting quality when processing the dielectric layers on the front and back sides of a wafer and the substrate in between. This is due to significant differences in material properties, varying heat conduction rates, different reaction rates, and stress concentration at the interfaces between different materials. This invention selects appropriate laser grooving conditions for the different dielectric layers on the front and back sides of the wafer, better ensuring consistency in force, energy, speed, and path during the cutting process. Furthermore, by performing laser cutting on the front and back dielectric layers in stages and ensuring complete grooving, excessive stress concentration at the interfaces is avoided, thereby significantly improving the uniformity of cutting quality.

[0071] Preferably, in step (2), the depth of the laser grooving is equal to the thickness of the laser protective liquid A plus 100%-120% of the thickness of the dielectric layer on the front side of the wafer; in step (5), the depth of the laser grooving is equal to the thickness of the laser protective liquid B plus 100%-120% of the thickness of the dielectric layer on the back side of the wafer. By precisely controlling the laser grooving depth, the dielectric layer is completely cut while minimizing the heat-affected zone, avoiding an increase in the exposed area around the cutting path due to excessive laser grooving, effectively reducing problems such as chip edge slag and residual particles generated in the exposed area, thereby helping to ensure the quality and cleanliness of the chip.

[0072] It is understandable that laser protective solutions can be applied using methods such as spin coating, blade coating, and immersion coating. For example, spin coating involves placing the wafer on a high-speed rotating platform, adding the protective solution dropwise to the center of the wafer, and using centrifugal force to distribute the solution evenly. By controlling the rotation speed, rotation time, and drop volume, the thickness of the protective solution can be precisely controlled. Blade coating uses a blade to evenly coat the protective solution onto the wafer surface. The thickness of the protective solution is controlled by adjusting the height and pressure of the blade. Immersion coating involves immersing the wafer in the protective solution. By controlling the immersion speed and time, as well as the pull-out speed and the temperature of the protective solution, the thickness of the protective solution can be precisely controlled. After coating, the thickness of the protective solution can be measured and determined using existing optical measurement methods (such as ellipsometers and optical interferometers).

[0073] Preferably, in steps (2) and (5), the width of the cutting channel is 10μm-400μm.

[0074] For example, the width of the cutting channel is 20μm, 50μm, 80μm, 100μm, 150μm, 200μm, 250μm, 300μm, or 350μm.

[0075] Preferably, in steps (2) and (5), the width of the laser grooving is (30%-80%) × the width of the cutting path.

[0076] Preferably, the centerline of the laser grooving and the centerline of the cutting path deviate by no more than 10 μm.

[0077] By precisely controlling the groove width and centerline position, both the depth and accuracy of the groove can be guaranteed, while over-cutting can be avoided, reducing cutting deviations and improving the uniformity and consistency of cutting quality. At the same time, the heat-affected zone is minimized, avoiding an increase in the exposed area around the cutting path caused by excessive laser grooving. This effectively reduces problems such as chip edge slag and residual particles generated in the exposed area, thus helping to ensure the quality and cleanliness of the chip.

[0078] For example, for harder or more brittle materials, a narrower groove width is selected; preferably, when the material of the dielectric layer is at least one of SiO2, SiNx, SiCN, and TEOS, the width of the laser groove is (30%-50%) × the width of the cutting path.

[0079] For example, a wider groove width is selected for softer or tougher materials; preferably, when the material of the dielectric layer is a polymer material, such as polyimide or benzocyclobutene, the width of the laser groove is (50%-80%) × the width of the cutting path.

[0080] In some embodiments, the chip dicing method of the present invention is applicable to wafers with a size of 4-12 inches and a thickness of 5-800 μm.

[0081] Optionally, in the wafer to be cut, the substrate material is at least one of silicon, glass, and diamond. The dielectric layer material is at least one of silicon oxide, silicon nitride, silicon carbide, SiCO, SiCN, SiCON, lithium niobate, InP, AsGaIn, GaN, and alumina.

[0082] For example, in the wafer to be cut, the thickness of the dielectric layer is 10nm-20μm, and the thickness of the substrate is 10μm-780μm.

[0083] For example, the dielectric layer is made of at least one of SiO2, SiNx, SiCN, and TEOS.

[0084] For example, the dielectric layer further includes metal structures, such as metal pads and metal wiring layers. The metal pads are located on the surface of the dielectric layer, and the metal wiring layers are located inside the dielectric layer. The surface of the wafer dicing track does not include metal pads, but in some possible designs, the dicing track includes a metal wiring layer.

[0085] For example, the area of ​​each metal pad is 0.03 μm. 2 -100μm 2 The pad pitch is 0.4μm-20μm, and the pad depth is 10nm-1000nm.

[0086] For example, the metal pads are made of copper or aluminum.

[0087] Optionally, during the laser grooving process of the dielectric layer, the laser source wavelength is 200-600nm, the laser power is 10-200W, the pulse frequency is 1kHz-100MHz, the pulse width is 10fs-100ns, and the laser spot diameter is 10-100μm.

[0088] Optionally, the laser used for laser grooving includes ultraviolet picosecond, ultraviolet femtosecond, ultraviolet nanosecond, green picosecond, green femtosecond, and green nanosecond lasers.

[0089] For example, the wavelength of the laser grooving is 248nm, 257nm, 266nm, 308nm, 355nm, 365nm, 405nm, 436nm, 515nm, 520nm, 532nm, 543nm, 555nm, or 561nm.

[0090] For example, the power of the laser grooving is 20W, 50W, 80W, 100W, 120W, 140W, 160W, or 180W.

[0091] For example, the pulse frequency of the laser grooving is 5kHz, 10kHz, 25kHz, 50kHz, 75Hz, 100kHz, 250kHz, 500kHz, 750kHz, 1MHz, 2MHz, 5MHz, 8MHz, 10MHz, 50MHz, or 80MHz.

[0092] For example, the pulse width of the laser grooving is 20fs, 50fs, 80fs, 100fs, 150fs, 200fs, 250fs, 300fs, 350fs, 400fs, 450fs, 500fs, 1ps, 5ps, 10ps, 20ps, 50ps, 80ps, 100ps, 500ps, 1ns, 5ns, 10ns, 50ns, or 80ns.

[0093] For example, the laser spot diameter is 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 50μm, 70μm, or 90μm.

[0094] Preferably, the laser used for laser grooving is a UV picosecond or UV femtosecond laser, which can reduce slag residue.

[0095] Preferably, the wavelength of the laser grooving is 200-400 nm. Further, the wavelength of the laser grooving is 200-365 nm. More preferably, the wavelength of the laser grooving is 200-350 nm.

[0096] Preferably, the pulse width of the laser grooving is 10 fs-500 ps. Further, the pulse width of the laser grooving is 10 fs-100 ps. More preferably, the pulse width of the laser grooving is 10 fs-500 fs.

[0097] In some embodiments, the wafer is a double-sided dielectric layer wafer with metal pads. Specifically, in the wafer to be diced, the thickness of the dielectric layer is 10nm-20μm, the thickness of the substrate is 10μm-780μm, the metal structure includes metal pads with a pad pitch of 0.4μm-20μm, a pad depth of 10nm-1000nm, and an area of ​​0.03μm for each metal pad. 2 -100μm 2 For example, the dielectric layer is made of at least one of SiO2, SiNx, SiCN, and TEOS. The metal pads are made of copper or aluminum.

[0098] Preferably, in steps (2) and (5), the wavelength of the laser grooving is 200-350nm, the power is 100-200W, the pulse frequency is 1kHz-10MHz, the pulse width is 10fs-500fs, and the laser spot diameter is 10-40μm.

[0099] By precisely controlling the parameters of laser grooving and selecting a suitable laser, it is beneficial to obtain better laser grooving quality. While ensuring complete cutting of the dielectric layer, the heat-affected zone is minimized, and the exposed area around the cutting path caused by excessive laser grooving is avoided. This effectively reduces problems such as chip edge slag and residual particles generated in the exposed area, thereby helping to ensure the quality and cleanliness of the chip.

[0100] In some embodiments, in steps (1) and (4), the thicknesses of the laser protective liquid A and the laser protective liquid B are both controlled between 0.05 and 100 μm. The coating methods include spin coating, blade coating, and dip coating.

[0101] For example, the thickness of the laser protective liquid A or laser protective liquid B can be 0.1μm, 1μm, 2μm, 4μm, 6μm, 8μm, 10μm, 20μm, 40μm, 60μm, or 80μm.

[0102] For example, the spin coating speed is 200-5000 rpm. For instance, the spin coating speeds are 500 rpm, 1000 rpm, 1400 rpm, 1800 rpm, 2200 rpm, 2600 rpm, 3000 rpm, 3500 rpm, 4000 rpm, and 4500 rpm.

[0103] Preferably, in steps (1) and (4), the thicknesses of both laser protective liquid A and laser protective liquid B are controlled within 1-10 μm. Further, the thicknesses of both laser protective liquid A and laser protective liquid B are controlled within 2-10 μm.

[0104] Preferably, the coating method is spin coating, and the spin coating speed is 1000-3000 rpm.

[0105] By precisely controlling the thickness of the laser protective liquid, selecting spin coating and controlling its speed, while taking into account both coating efficiency and cost, it can effectively buffer the thermal and mechanical stress generated during laser cutting, capture particles generated during cutting, avoid excessive cutting resistance, and improve cutting quality. It is especially suitable for double-sided dielectric layer wafers with metal pads in the above embodiments.

[0106] Preferably, in steps (2) and (6), the cleaning and removal of laser protective solution A (or B, C) includes: cleaning within 48 hours, preferably within 24 hours, after coating with laser protective solution A (or B, C), using a spin coating combined with megasonic or two-fluid method; after cleaning, the number of particles on the wafer surface and in the grooves formed by laser etching is ≤100 particles @ 500nm. Here, ≤100 particles @ 500nm means: the number of particles with a particle size of 500nm or larger is ≤100 particles.

[0107] By controlling the timing of the cleaning protective solution (setting a suitable process window) and the cleaning method, particles on the wafer surface and in the laser trenches can be efficiently removed, ensuring that there is no obvious slag and particle accumulation on the wafer surface and in the trenches formed by laser etching after cleaning, meeting the established particle control standards, and ensuring the cleanliness and quality of the chip.

[0108] Specifically, the step of cleaning using spin coating combined with megasonic or two-fluid methods includes: applying cleaning solution by spin coating and then cleaning by combining megasonic cleaning or two-fluid cleaning.

[0109] For example, the cleaning solution includes deionized water or deionized water combined with other solutions, such as at least one of dilute acid, dilute alkali, or dilute salt. When the cleaning solution contains deionized water and a solution, the concentration of the solution in the cleaning solution is 0.1-10% (mass fraction). For example, the concentration of the solution in the cleaning solution is 0.5%, 1.0%, 2.0%, 4.0%, 6.0%, or 8.0%.

[0110] In some embodiments, after cleaning to remove laser protective solution A or B (or C), the wafer is dried. Specifically, the drying is achieved by a combination of rotation and air blowing; wherein the blowing gas is at least one of nitrogen or argon; during drying, the wafer rotates at a speed of 2000-7000 rpm. After drying, no obvious water residue remains on the wafer surface.

[0111] In some embodiments, for the spin coating combined with megasonic method, preferably, during cleaning, the spin coating speed is 2000-5000 rpm, the megasonic frequency is 0.1-4.0 MHz, the flow rate of the cleaning solution is 10-2000 mL / min, the cleaning time is 30 s-5 min, and the temperature of the cleaning solution is 20-60 ℃.

[0112] In some embodiments, for the spin coating combined with two fluids, preferably, during cleaning, the spin coating speed is 2000-5000 rpm, the two fluid gas pressure is 0.1-2 MPa, the cleaning fluid flow rate is 10-2000 mL / min, the cleaning time is 30 s-5 min, and the cleaning fluid temperature is 20-60 °C.

[0113] For example, during cleaning, the spin coating speed is 2500 rpm, 3000 rpm, 3500 rpm, 4000 rpm, or 4500 rpm. Preferably, the spin coating speed is 2000-3000 rpm.

[0114] For example, during cleaning, the megaphonic frequency is 0.5MHz, 1.0MHz, 1.5MHz, 2.0MHz, 2.5MHz, 3.0MHz, or 3.5MHz. Preferably, the megaphonic frequency is 0.5-2.0MHz.

[0115] For example, during cleaning, the pressure of the two-fluid gas is 0.3 MPa, 0.5 MPa, 0.8 MPa, 1.0 MPa, or 1.5 MPa. Preferably, the pressure of the two-fluid gas is 0.3-1 MPa.

[0116] For example, the flow rate of the cleaning solution is 50 mL / min, 100 mL / min, 500 mL / min, 800 mL / min, 1000 mL / min, 1200 mL / min, 1500 mL / min, or 1800 mL / min. Preferably, the flow rate of the cleaning solution is 800-1500 mL / min.

[0117] For example, in the cleaning process, the cleaning time is 1 min, 1.5 min, 2 min, 3 min, or 4 min. The temperature of the cleaning solution is 25°C, 30°C, 40°C, or 50°C. Preferably, the cleaning time is 1 min to 2 min. Preferably, the temperature of the cleaning solution is 20 to 30°C.

[0118] In some embodiments, in steps (1) and (3), the first carrier and the second carrier are selected from one of UV blue film, silicon-based wafer carrier, and transparent glass carrier, and their area is large enough to cover the surface of the wafer to be cut.

[0119] For example, the UV blue film is bonded to the dielectric layer on the front or back side of the wafer via an adhesion layer on the surface of the UV blue film. The adhesion force of the UV blue film to the wafer is 1000-6000mN / 20mm.

[0120] For example, the silicon-based wafer carrier is bonded to the dielectric layer on the front or back side of the wafer by fusion bonding or temporary bonding, preferably fusion bonding.

[0121] For example, the transparent glass substrate is bonded to a dielectric layer on the front or back side of the wafer via temporary bonding.

[0122] In one embodiment, in step (1), when the first carrier is a UV blue film, the step of bonding the dielectric layer surface on the back side of the wafer with the first carrier includes: attaching a UV blue film to the dielectric layer surface on the back side of the wafer.

[0123] In one embodiment, in step (3), when the second carrier is a UV blue film, the step of ensuring that the dielectric layer surface on the front side of the wafer is bonded to the second carrier includes: attaching a UV blue film to the grooved dielectric layer surface on the front side of the wafer to ensure that the grooved dielectric layer surface on the front side of the wafer is bonded to the UV blue film; and removing the first carrier.

[0124] In one embodiment, in step (1), when the first carrier is a silicon-based wafer carrier, the step of bonding the dielectric layer surface on the back side of the wafer with the first carrier includes: placing the dielectric layer surface on the back side of the wafer on the silicon-based wafer carrier and fixing the dielectric layer surface on the back side of the wafer to the silicon-based wafer carrier by means of fusion bonding or temporary bonding.

[0125] In one embodiment, in step (3), when the second carrier is a silicon-based wafer carrier, the step of ensuring that the dielectric layer surface on the front side of the wafer is bonded to the second carrier includes: covering the grooved dielectric layer surface on the front side of the wafer with the silicon-based wafer carrier, flipping the wafer so that the dielectric layer on the back side of the wafer faces upward; after the flipping, bonding the grooved dielectric layer surface on the front side of the wafer to the silicon-based wafer carrier by fusion bonding or temporary bonding; and removing the first carrier.

[0126] In one embodiment, in step (1), when the first carrier is a transparent glass substrate, the step of bonding the dielectric layer surface on the back side of the wafer with the first carrier includes: placing the dielectric layer surface on the back side of the wafer on the transparent glass substrate and fixing the dielectric layer surface on the back side of the wafer to the transparent glass substrate by temporary bonding.

[0127] In one embodiment, in step (3), when the second carrier is a transparent glass substrate, the step of ensuring that the dielectric layer surface on the front side of the wafer is bonded to the second carrier includes: covering the grooved dielectric layer surface on the front side of the wafer with the transparent glass substrate, flipping the wafer so that the dielectric layer on the back side of the wafer faces upward; after the flipping, bonding the grooved dielectric layer surface on the front side of the wafer to the transparent glass substrate through temporary bonding; and removing the first carrier.

[0128] In one embodiment, in step (3), when the first carrier is a UV blue film, the step of debonding the dielectric layer surface on the back side of the wafer from the first carrier includes: irradiating the back side of the wafer with UV light to perform UV debonding treatment on the dielectric layer surface on the back side of the wafer and the first carrier. Specifically, in the UV debonding treatment, the UV wavelength range is 300-400nm, and the irradiation intensity is 50-300mW / cm². 2 The irradiation time is 10-60 seconds, and the irradiation distance is 5-20 cm. After UV debonding treatment, the adhesion force between the dielectric layer surface on the back of the wafer and the first carrier is 10-500 mN / 20 mm, and there is no adhesive residue on the back of the wafer. Exemplarily, the atmosphere for UV debonding treatment includes at least one of oxygen, nitrogen, argon, and ozone, or a vacuum condition.

[0129] In one embodiment, in step (3), when the first carrier is a silicon-based wafer carrier, the step of debonding the dielectric layer surface on the back side of the wafer from the first carrier includes: using mechanical debonding or laser debonding to debond the dielectric layer surface on the back side of the wafer from the silicon-based wafer carrier.

[0130] In one embodiment, in step (3), when the first carrier is a transparent glass substrate, the step of debonding the dielectric layer surface on the back side of the wafer from the first carrier includes: using laser debonding to debond the dielectric layer surface on the back side of the wafer from the transparent glass substrate.

[0131] In the above embodiments, the mechanical debonding includes: creating initial cracks at the bonding interface using a blade, and separating the silicon-based wafer carrier and the wafer using the mechanical cracks. Specifically, the blade thickness is 50-200 μm, the blade insertion angle is 10-30°, the insertion speed is 0.1-5 mm / s, and the insertion force is 0.1-10 N. For example, the blade material is stainless steel or titanium alloy.

[0132] For example, the blade thickness is 100μm or 150μm. The blade insertion angle is 15°, 20°, or 25°. The insertion speed is 0.5mm / s, 1.0mm / s, 2.0mm / s, 3.0mm / s, or 4.0mm / s. The insertion force is 0.5N, 1.0N, 2.0N, 5.0N, or 8.0N.

[0133] In the above embodiments, the laser debonding includes: irradiating one side of a carrier substrate (such as a silicon-based wafer carrier substrate or a transparent glass carrier substrate) with a laser, acting on the bonding interface to destroy the temporary bonding adhesive between the carrier substrate and the wafer, thereby reducing the interfacial adhesion. In laser debonding, the laser spot size is 10-200 μm, and the scanning speed is 10-1000 mm / s. Exemplarily, in laser debonding, the laser spot size is 20 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, or 180 μm. Exemplarily, in laser debonding, the scanning speed is 20 mm / s, 50 mm / s, 100 mm / s, 200 mm / s, 400 mm / s, 600 mm / s, or 800 mm / s. Exemplarily, in laser debonding, the laser is ultraviolet 355 nm, green 532 nm, or infrared 1064 nm.

[0134] Specifically, in step (6), after laser grooving is completed on the front and back sides of the wafer, substrate cutting is performed along the dicing path. Exemplarily, the substrate cutting method is one of blade cutting, laser stealth cutting, or plasma cutting. For silicon substrates, plasma cutting is preferred.

[0135] In some embodiments, the etching rate of the plasma cutting is 100-1000 nm / min. Preferably, in the plasma cutting, the etching depth = (90%-100%) × substrate thickness. After etching, the perpendicularity of the sidewall of the cutting path is 80-100°.

[0136] It should be noted that the dicing paths of the dielectric layer and the substrate in the wafer of this invention are completely corresponding. This is to ensure precise chip separation and smooth subsequent packaging. It can be understood that the dicing path is the path in the chip dicing process, that is, the boundary line between each chip unit (chip) on the wafer, guiding the actual dicing operation along these predetermined paths.

[0137] For example, the laser protective liquid A (or B, C) is a water-soluble protective liquid. During plasma cutting, the etching process does not damage the water-soluble laser protective liquid on the wafer surface. Therefore, the laser protective liquid retained on the back side of the wafer serves as a mask for plasma cutting.

[0138] For example, the main components of the water-soluble protective liquid include a basic solvent (such as deionized water), an antioxidant (such as organic acid salts), a surfactant (such as polyethylene glycol), a corrosion inhibitor, and other additives; several protective liquids can be compounded to obtain better results.

[0139] It is understandable that the etching process of plasma cutting has an endpoint detection function. When the endpoint is approached, the etching speed is slowed down or the etching power is reduced to avoid damage to the second carrier (such as UV blue film) caused by plasma over-etching.

[0140] For example, the etching gas used in plasma cutting primarily comprises a fluorine-containing gas, such as at least one of CF4, C4F6, and SF6. In some embodiments, the etching gas is also doped with oxygen or helium.

[0141] In step (6), after the substrate is cut, the process further includes cleaning to remove the laser protective solution B (or C), the steps and parameters of which are similar to those for cleaning to remove the laser protective solution A. After cleaning, the substrate is enlarged.

[0142] It is understandable that after the dielectric layer on the front and back sides of the wafer is laser-grooved and the substrate is cut, the wafer has been divided into small chips of a specific size. However, at this point, the chip spacing is still relatively small, and it is necessary to increase the chip spacing by wafer expansion to facilitate subsequent processes such as picking.

[0143] In step (6), the wafer expansion methods include mechanical wafer expansion and temperature-controlled wafer expansion. Specifically, after the substrate is cut, the chip is placed on or transferred to a UV blue film and expanded using either mechanical or temperature-controlled wafer expansion. Mechanical wafer expansion involves placing the cut chip and UV blue film together on the wafer expansion machine stage, and then lifting the stage upwards to expand the UV blue film and increase the chip spacing. Temperature-controlled wafer expansion uses temperature regulation to change the elasticity of the UV blue film, combined with the wafer expansion stage, to control the chip spacing; the process temperature for temperature-controlled wafer expansion is between 0-80℃.

[0144] In some embodiments, the chip spacing after wafer expansion is 50-500 μm. Wafer spacing after expansion = (1.1-10 times) × chip spacing before expansion. For example, the chip spacing after expansion is 2 times, 4 times, 6 times, or 8 times the chip spacing before expansion.

[0145] Preferably, the chip spacing after wafer expansion is 110%-300% of the chip spacing before wafer expansion.

[0146] It should be noted that in the chip cutting method described in the embodiments of the present invention, the substrate is cleaned after cutting. After cleaning, the number of particles with a size greater than 2μm on the second carrier does not exceed 100.

[0147] To further improve the quality of the diced chip, the inventors conceived of cleaning and removing the laser protective solution B from the back side of the wafer before substrate dicing, and then recoating it with laser protective solution C. This allows for the re-protection of potential exposed areas at the dicing edges after laser grooving on the back side. During subsequent substrate dicing, this method can reduce the impact of strong etching energy (such as plasma) on exposed areas around the dicing edges, thereby effectively reducing slag and buildup problems at the dicing and chip edges.

[0148] In some preferred embodiments, step (5) includes:

[0149] The first laser grooving is performed on the dielectric layer on the back side of the wafer: the dielectric layer on the back side of the wafer is laser-grooved along the dicing path until the dicing path formed by the laser etching penetrates the dielectric layer on the back side of the wafer (the first laser grooving on the dielectric layer on the back side of the wafer here is the back side laser grooving mentioned above).

[0150] Furthermore, after performing the first laser grooving on the dielectric layer on the back side of the wafer, step (5) further includes:

[0151] The laser protective solution B is removed by cleaning, exposing the dielectric layer surface on the back of the wafer and the etched grooves in the dielectric layer on the back of the wafer.

[0152] Laser protective liquid C is coated on the dielectric layer surface on the back side of the wafer, so that the laser protective liquid C covers the dielectric layer surface on the back side of the wafer and the inner wall of the etched drill trench in the dielectric layer on the back side of the wafer, and accumulates in the drill trench.

[0153] A second laser grooving is performed on the dielectric layer on the back side of the wafer: using a second laser, the laser protective liquid C accumulated in the etched grooves in the dielectric layer on the back side of the wafer is removed, while the surface of the dielectric layer on the back side of the wafer and the edge of the etched grooves on the back side of the wafer are covered by the laser protective liquid C.

[0154] For example, during the laser grooving process on the dielectric layer on the back side of the wafer, the depth of the second laser grooving is less than or equal to the depth of the first laser grooving, and the width of the second laser grooving is less than or equal to the width of the first laser grooving.

[0155] For example, the thickness of laser protective liquid C is less than or equal to the thickness of laser protective liquid B.

[0156] In some embodiments, the thickness of the laser protective liquid B is t1, and the thickness of the laser protective liquid C is t2, satisfying: t2 = (50% - 100%) × t1. The thickness of the laser protective liquid C is thinner than or equivalent to the thickness of the laser protective liquid B to reduce the heat-affected zone, ensuring that the protective liquid in the trench can be removed during the second laser grooving of the dielectric layer on the back side of the wafer, while avoiding exposure at the edge of the dicing track. However, the thickness of the laser protective liquid C cannot be too thin to ensure that the area around the dicing track is effectively protected, significantly reducing thermal damage and slag accumulation during subsequent substrate cutting, further improving cutting quality and stability.

[0157] For example, t2 = 55% × t1, t2 = 60% × t1, t2 = 65% × t1, t2 = 70% × t1, t2 = 75% × t1, t2 = 80% × t1, t2 = 85% × t1, t2 = 90% × t1, t2 = 95% × t1. Preferably, t2 = (70% - 90%) × t1, to balance protective effect and removal efficiency.

[0158] In some embodiments, the depth of the second laser grooving of the dielectric layer on the back side of the wafer is d2, satisfying: d2 = (100-110%) × t2; where t2 is the thickness of the laser protective liquid C. By precisely controlling the depth of the second laser grooving, it is possible to better ensure the complete removal of the protective liquid accumulated in the trench, while also taking into account process efficiency, reducing the heat-affected zone, and avoiding excessive laser input from affecting the protective layer around the dicing path.

[0159] In some embodiments, the width of the first laser grooving of the dielectric layer on the back side of the wafer is w1, and the width of the second laser grooving of the dielectric layer on the back side of the wafer is w2, satisfying w2 = (85% - 99%) × w1. By precisely controlling the width of the second laser grooving, it is better ensured that excess protective fluid in the grooving groove can be completely removed, and damage to the protective layer around the grooving is avoided. In addition, the control of the width of the second laser grooving is beneficial to coordinate with the energy parameters of the second laser grooving (such as power, pulse width, etc.), better ensuring that the second laser can accurately remove the protective fluid, while reducing the heat-affected zone, improving cutting quality and balancing efficiency.

[0160] For example, w2 = 87% × w1, w2 = 90% × w1, w2 = 92% × w1, w2 = 95% × w1, w2 = 97% × w1. Preferably, w2 = (90% - 95%) × w1, which better balances removal efficiency and protective effect.

[0161] Preferably, the laser power for the second laser grooving of the dielectric layer on the back side of the wafer is less than the laser power for the first laser grooving of the dielectric layer on the back side of the wafer. The main purpose of the second laser grooving is to remove excess protective fluid accumulated in the dicing grooves. Since the second grooving is less difficult than the first, a lower laser power can be used to effectively remove the accumulated protective fluid in the grooves, while also reducing damage to the protective layer around the dicing grooves, ensuring the integrity and effectiveness of the protective layer, and reducing energy consumption.

[0162] In some embodiments, the laser power for the first laser grooving of the dielectric layer on the back side of the wafer is P1, and the laser power for the second laser grooving of the dielectric layer on the back side of the wafer is P2, satisfying P2 = (20% - 50%) × P1. By precisely controlling the power of the second laser grooving, it is better to ensure the removal of the protective liquid in the trench while avoiding unnecessary damage to the protective layer around the dicing track, thereby reducing defects at the edge of the dicing track and the chip edge, and improving the cutting quality and stability. If the power is too low (<20% P1), the laser energy may not be sufficient to completely remove the protective liquid in the trench of the dicing track, increasing the difficulty of subsequent cleaning and processing, affecting the cleanliness of the chip surface, and due to insufficient laser energy, it may take longer to remove the protective liquid, reducing process efficiency. If the power is too high (>50% P1), the heat-affected zone expands, which may cause partial damage to the protective layer around the dicing track.

[0163] For example, P2 = 25% × P1, P2 = 30% × P1, P2 = 35% × P1, P2 = 40% × P1, P2 = 45% × P1. Preferably, P2 = (30% - 40%) × P1, which better balances removal efficiency and protective effect.

[0164] In some embodiments, the projected area of ​​the first laser grooving of the dielectric layer on the back side of the wafer is S1, and the projected area of ​​the second laser grooving of the dielectric layer on the back side of the wafer is S2, satisfying S2 = (90% - 99%) × S1. Preferably, the overlap of the projected areas of the first and second laser groovings of the dielectric layer on the back side of the wafer is above 95-99%. Here, an overlap of above 95-99% means starting from 95% and continuing up to 99% and higher. By controlling the ratio and overlap of the projected areas of the two laser groovings, it is better ensured that the energy of the second laser grooving is sufficient to remove the protective liquid in the dicing groove, while the second laser grooving will not damage the protective layer formed by the protective liquid at the edge of the dicing groove and the surface of the dielectric layer, thereby reducing defects at the edge of the dicing groove and the chip edge, and ensuring the dicing quality and stability of the chip.

[0165] It is understandable that the projected area of ​​laser grooving refers to the area of ​​the wafer surface actually irradiated by the laser beam.

[0166] In some embodiments, the second laser has a wavelength of 200-600nm, a power of 10-200W, a pulse frequency of 10Hz-100MHz, a pulse width of 10fs-500ns, and a laser spot diameter of 10-100μm.

[0167] Preferably, the second laser has a wavelength of 300-600nm, a pulse frequency of 10Hz-500kHz, a pulse width of 1ns-500ns, and a laser spot diameter of 20μm-50μm.

[0168] Preferably, the laser used for the second laser grooving of the dielectric layer on the back side of the wafer is a green nanosecond or ultraviolet nanosecond laser.

[0169] By controlling the parameters of the second laser (such as wavelength, frequency, pulse width, etc.) and utilizing the synergistic effect between these parameters, combined with a suitable laser, it is possible to efficiently remove the protective liquid accumulated in the dicing grooves, and reduce the impact of the heat-affected zone on the protective layer (formed by the protective liquid) around the dicing grooves. This better ensures that after the second laser grooving of the dielectric layer on the back side of the wafer, the surface of the dielectric layer and the edge of the dicing grooves are still covered by the protective liquid, and are fully protected in the subsequent substrate cutting process.

[0170] For example, the laser wavelength of the second laser is 248nm, 257nm, 266nm, 308nm, 355nm, 365nm, 405nm, 436nm, 515nm, 520nm, 532nm, 543nm, 555nm, or 561nm. Preferably, the laser wavelength of the second laser is 500nm-600nm.

[0171] For example, the pulse frequency of the second laser is 20Hz, 50Hz, 100Hz, 250Hz, 500Hz, 800Hz, 1kHz, 2kHz, 5kHz, 10kHz, 20kHz, 50kHz, 80kHz, 100kHz, 120kHz, 150kHz, 170kHz, 200kHz, 300kHz, 400kHz, 500kHz, 1MHz, 2MHz, 5MHz, 10MHz, 50MHz, or 80MHz. Preferably, the pulse frequency of the second laser is 1kHz-200kHz.

[0172] For example, the pulse width of the second laser is 20fs, 50fs, 80fs, 100fs, 200fs, 300fs, 400fs, 500fs, 1ps, 5ps, 20ps, 50ps, 80ps, 100ps, 500ps, 2ns, 5ns, 10ns, 20ns, 50ns, 80ns, 100ns, 120ns, 150ns, 180ns, 200ns, 250ns, 300ns, 350ns, 400ns, or 450ns. Preferably, the pulse width of the second laser is 5ns-200ns.

[0173] For example, the spot diameter of the second laser is 25μm, 30μm, 35μm, 40μm, or 45μm.

[0174] This invention also provides a chip obtained by the above-described chip dicing method, wherein the chip edge has a serpentine shape of less than 2 μm, and the number of contaminated particles on the chip surface is ≤100 @ 90 nm. The dielectric layer and substrate in the chip have no obvious delamination, and the delamination width between the dielectric layer and the substrate is ≤1 μm. Here, ≤100 @ 90 nm means: the number of particles with a size of 90 nm or larger is ≤100.

[0175] In some embodiments, the chip area is 1 mm². 2 -900mm 2 For example, the chip is square or rectangular, with a side length ranging from 1mm to 30mm. For example, the side lengths are 2mm, 4mm, 6mm, 8mm, 10mm, 15mm, 20mm, and 25mm.

[0176] In some embodiments, the thickness of the chip is 10μm-800μm.

[0177] In some embodiments, the chip includes a substrate and dielectric layers located on the upper and lower surfaces of the substrate, respectively; wherein the dielectric layer on the upper surface of the substrate constitutes the dielectric layer on the front side of the chip, and the dielectric layer on the lower surface of the substrate constitutes the dielectric layer on the back side of the chip; the dielectric layer on the front side of the chip and / or the dielectric layer on the back side of the chip includes a metal structure; the thickness of the dielectric layer is 10nm-20μm, and the thickness of the substrate is 10μm-780μm.

[0178] In some embodiments, the metal structure includes metal pads. Specifically, each metal pad has an area of ​​0.03 μm. 2 -100μm 2The pad pitch is 0.4μm-20μm, and the pad depth is 10nm-1000nm. For example, the metal pad structure is circular, square, or rectangular. The diameter of the circular pad is 0.2μm-10μm, and the side length of the square or rectangular pad is 0.2μm-10μm.

[0179] It is understood that the metal pads are located on the surface of the dielectric layer. After processes such as chemical mechanical polishing, the metal pad structure is exposed, and the chip surface exhibits a metal-dielectric topology.

[0180] In some embodiments, the metal structure includes a metal wiring layer located within the dielectric layer. The metal wiring layer is suitable for memory devices, logic devices, etc. For example, the number of metal wiring layers can be 1 to 5.

[0181] In some embodiments, the dielectric layer is made of at least one of silicon oxide, silicon nitride, silicon carbide, SiCO, SiCN, SiCON, lithium niobate, InP, AsGaIn, GaN, alumina, and TEOS (tetraethoxysilane). The substrate is made of at least one of silicon, glass, and diamond.

[0182] The technical solution of the present invention will be further described in detail below with reference to specific embodiments and comparative examples.

[0183] Example 1:

[0184] This embodiment provides a chip dicing method applicable to D2W hybrid bonding multilayer stacking. The wafer 100 to be diced is 12 inches in size and 200 μm thick. Both the front and back sides of the wafer 100 have dielectric layers and metal patterns (i.e., metal pads). Specifically, the wafer 100 includes a substrate 12 and dielectric layers 11a (i.e., the dielectric layer on the front side of the wafer) and 11b (i.e., the dielectric layer on the back side of the wafer) located on the upper surface of the substrate and the lower surface of the substrate, respectively. The dielectric layers 11a and 11b contain metal pads. The substrate 12 is silicon and has a thickness of 198 μm. The dielectric layers 11a and 11b are silicon oxide and each has a thickness of 1 μm. The metal pads are circular copper pads with a diameter of 5 μm, a pitch of 10 μm, and a depth of 100 nm.

[0185] The chip cutting method includes the following steps:

[0186] (1) Apply laser protective liquid to the front side:

[0187] The dielectric layer 11b on the back side of the wafer is attached to the UV blue film (first carrier 20a). The UV blue film is supported by a stainless steel metal frame to achieve the bonding between the dielectric layer on the back side of the wafer and the first carrier, with the dielectric layer 11a on the front side of the wafer facing upwards.

[0188] A water-soluble laser protective solution A (such as...) is applied to the dielectric layer 11a on the front side of the wafer by spin coating. Figure 1 30a); wherein the spin coating speed is 5000 r / min and the thickness of laser protective liquid A is 0.5 μm.

[0189] (2) Front laser grooving:

[0190] Laser grooving is performed on the dielectric layer 11a on the front side of the wafer along the dicing track 13a on the front side of the wafer until the groove formed by laser etching penetrates the dielectric layer 11a on the front side of the wafer. The laser used for grooving is an ultraviolet picosecond laser with a wavelength of 355nm, a power of 50W, a pulse frequency of 100MHz, a pulse width of 100ps, and a laser spot diameter of 10μm. The dicing track width is 100μm, and the width of the laser grooving is 90% × the width of the dicing track. The depth of the laser grooving is equal to the thickness of the laser protective liquid A + the thickness of the dielectric layer 11a on the front side of the wafer = 1.5μm.

[0191] After the front laser grooving is completed, deionized water is coated by spin coating and then cleaned by megasonic cleaning to remove the laser protective solution A. During cleaning, the spin coating speed is 5000 rpm, the megasonic frequency is 1.0 MHz, the cleaning time is 30 s, and the temperature of the cleaning solution is 60 ℃. After cleaning, the number of particles on the wafer surface and in the grooves formed by laser etching is ≤100 particles@500 nm.

[0192] After cleaning, the wafer is dried by a combination of rotation and air blowing; the blowing gas is nitrogen; the wafer rotates at a speed of 2000 rpm, and after drying, there is no obvious water residue on the wafer surface.

[0193] (3) Flip:

[0194] After laser grooving on the front side, the wafer is bonded to a UV blue film frame. A UV debonding machine is used to irradiate the back side of the wafer with UV light, breaking the adhesion between the blue film and the back side of the wafer, thus detaching the dielectric layer 11b surface on the back side of the wafer from the UV blue film (first carrier). In the UV debonding, the UV wavelength is 300nm and the irradiation intensity is 100mW / cm². 2 The irradiation time was 20 seconds and the irradiation distance was 10 cm; the adhesion force after UV degumming treatment was 100 mN / 20 mm.

[0195] Another UV blue film (second carrier 20b) is attached to the surface of the dielectric layer 11a on the front side of the wafer, the UV blue film on the back side is peeled off, and the wafer is flipped so that the dielectric layer 11b on the back side of the wafer faces upward.

[0196] (4) Apply laser protective liquid to the back side:

[0197] Laser protective solution B (e.g., ...) is coated on the dielectric layer 11b surface on the back side of the wafer. Figure 3 In (30b), the coating steps and parameters are the same as in (1);

[0198] (5) Laser grooving on the back:

[0199] Laser grooving is performed on the dielectric layer 11b on the back side of the wafer along the dicing path 13b on the back side of the wafer until the groove formed by laser etching penetrates the dielectric layer 11b on the back side of the wafer; the laser grooving steps and parameters are the same as (2).

[0200] After laser grooving on the back, retain the laser protective solution B;

[0201] (6) Substrate cutting, cleaning, and expansion:

[0202] The substrate 12 was subjected to plasma cutting at an etching rate of 1000 nm / min and an etching depth of 100% × the thickness of the substrate 12. The etching gas was CF4. After etching, the perpendicularity of the sidewall of the cut path was 87°.

[0203] After substrate cutting, cleaning was performed using the same steps and parameters as for cleaning laser protective solution A, to remove laser protective solution B. After cleaning, the number of particles larger than 2μm on the UV blue film (second carrier) did not exceed 100.

[0204] After cleaning, the wafers are expanded using mechanical expansion. The cut chips and UV blue film are placed together on the wafer expander stage. The stage is lifted upwards to expand the UV blue film and increase the chip spacing. The chip spacing after expansion is 200μm.

[0205] In this embodiment, the chip edge serpentine shape is less than 2μm, the number of contaminant particles on the chip surface is less than 100 particles @ 90nm, and the layer width between the dielectric layer and the substrate of the chip is ≤ 1μm.

[0206] Example 2

[0207] The difference between this embodiment and Embodiment 1 is that in steps (2) and (5), the wavelength of the laser grooving is 266nm, the power is 100W, the pulse frequency is 10MHz, the pulse width is 80ps, and the laser spot diameter is 40μm; the width of the laser grooving = 80% × the width of the dicing track; the depth of the laser grooving = the thickness of the laser protective liquid A + 110% × the thickness of the dielectric layer on the front side of the wafer = 0.5μm + 1.1μm = 1.6μm. The remaining steps and parameters are similar to those in Embodiment 1.

[0208] In this embodiment, the chip edge serpentine shape is less than 1.6 μm, the number of contaminated particles on the chip surface is less than 90 particles @ 90 nm, and the layer width between the dielectric layer and the substrate of the chip is ≤ 1 μm.

[0209] Example 3

[0210] The difference between this embodiment and Embodiment 1 is that in steps (2) and (5), the wavelength of the laser grooving is 266nm, the power is 200W, the pulse frequency is 1kHz, the pulse width is 10ps, and the laser spot diameter is 10μm; the width of the laser grooving = 30% × the width of the dicing path; the depth of the laser grooving = the thickness of the laser protective liquid A + 120% × the thickness of the dielectric layer on the front side of the wafer = 0.5μm + 1.2μm = 1.7μm. The remaining steps and parameters are similar to those in Embodiment 1.

[0211] In this embodiment, the chip edge serpentine shape is less than 1.7 μm, the number of contaminant particles on the chip surface is less than 95 particles @ 90 nm, and the layer width between the dielectric layer and the substrate of the chip is ≤ 0.8 μm.

[0212] Example 4

[0213] The difference between this embodiment and embodiment 1 is that in steps (1) and (4), the spin coating speed is 2000 r / min and the thickness of laser protective liquid A or B is 5 μm;

[0214] In steps (2) and (5), the laser used for laser grooving is a UV femtosecond laser with a wavelength of 266 nm, a power of 150 W, a pulse frequency of 5 MHz, a pulse width of 250 fs, and a laser spot diameter of 30 μm; the dicing width is 200 μm, and the laser grooving width = 50% × dicing width; the laser grooving depth = the thickness of the laser protective liquid A + 110% × the thickness of the dielectric layer on the front side of the wafer = 5 μm + 1.1 μm = 6.1 μm. In step (6), the chip spacing after wafer expansion is 500 μm. The remaining steps and parameters are similar to those in Example 1.

[0215] In this embodiment, the chip edge serpentine shape is less than 1.4 μm, the number of contaminant particles on the chip surface is less than 75 particles @ 90 nm, and the layer width between the dielectric layer and the substrate of the chip is ≤ 0.5 μm.

[0216] Example 5

[0217] The difference between this embodiment and embodiment 1 is that in step (1), the back side of the wafer is placed on a silicon-based wafer carrier (first carrier) and the dielectric layer 11b surface on the back side of the wafer is fixed to the silicon-based wafer carrier by fusion bonding.

[0218] In step (3), mechanical debonding is used to debond the dielectric layer 11b surface on the back side of the wafer from the silicon-based wafer carrier. Specifically, an initial crack is created at the bonding interface using a blade with a thickness of 100 μm, an insertion angle of 20°, an insertion speed of 2 mm / s, and an insertion force of 5 N. The silicon-based wafer carrier and the dielectric layer 11b on the back side of the wafer are debonded using the mechanical crack. Another silicon-based wafer carrier (second carrier) is placed over the grooved dielectric layer 11a surface on the front side of the wafer, and the wafer is flipped so that the dielectric layer 11b on the back side of the wafer faces upward. After the flip, the grooved dielectric layer 11a on the front side of the wafer is bonded to the silicon-based wafer carrier (second carrier) through fusion bonding. The first carrier is then removed.

[0219] In step (6), the diced chips on the silicon-based wafer carrier (second carrier) are transferred to the blue film, and wafer expansion is performed by temperature-controlled wafer expansion. By adjusting the temperature, the elasticity of the UV blue film is changed, and combined with the wafer expansion stage, the chip spacing is controlled. The process temperature for temperature-controlled wafer expansion is 30-50℃. The remaining steps and parameters are similar to those in Example 1.

[0220] The chip edge serpentine shape obtained in this embodiment is less than 2μm, the number of contaminant particles on the chip surface is less than 100 @ 90nm, and the layer width between the dielectric layer and the substrate of the chip is ≤ 0.9μm.

[0221] Example 6

[0222] The difference between this embodiment and embodiment 1 is that in step (1), the back side of the wafer is placed on a transparent glass substrate (first carrier) and the dielectric layer 11b surface on the back side of the wafer is fixed to the transparent glass substrate by temporary bonding.

[0223] In step (3), laser debonding is used to debond the dielectric layer 11b surface on the back side of the wafer from the transparent glass substrate. Specifically, the laser irradiates from one side of the transparent glass substrate, acting on the bonding interface to destroy the temporary bonding adhesive between the transparent glass substrate and the wafer, reducing the interfacial bonding force. In laser debonding, the laser is ultraviolet 355nm, the laser spot size is 100μm, and the scanning speed is 500mm / s. Another transparent glass substrate (second carrier) is placed over the grooved dielectric layer 11a surface on the front side of the wafer, and the wafer is flipped so that the dielectric layer 11b on the back side of the wafer faces upward. After the flipping, the grooved dielectric layer 11a on the front side of the wafer is bonded to the transparent glass substrate (second carrier) through temporary bonding. The first carrier is then removed.

[0224] In step (6), the cut chips on the transparent glass substrate (second carrier) are transferred to the blue film, and expansion is performed by temperature-controlled expansion. By adjusting the temperature, the elasticity of the UV blue film is changed, and the chip spacing is controlled in conjunction with the expansion stage. The process temperature for temperature-controlled expansion is 30-50℃. The remaining steps and parameters are similar to those in Example 1.

[0225] The chip edge serpentine shape obtained in this embodiment is less than 2μm, the number of contaminant particles on the chip surface is less than 100 @ 90nm, and the layer width between the dielectric layer and the substrate of the chip is ≤ 0.5μm.

[0226] Example 7

[0227] The difference between this embodiment and embodiment 4 is that step (5) includes:

[0228] The dielectric layer 11b on the back side of the wafer is laser-grooved for the first time until the groove formed by laser etching penetrates the dielectric layer 11b on the back side of the wafer; the steps and parameters of the first laser grooving are the same as those of step (5) in Example 4.

[0229] Clean and remove laser protective solution B; the cleaning steps and parameters are the same as those for cleaning laser protective solution A in step (2) of Example 4;

[0230] Laser protective liquid C is coated on the surface of the dielectric layer 11b on the back side of the wafer, so that the laser protective liquid C covers the surface of the dielectric layer on the back side of the wafer and the inner wall of the etched grooves in the back laser grooving, and accumulates in the etched grooves in the back laser grooving; the spin coating speed is 2000 r / min, and the thickness of the laser protective liquid C is 3.0 μm.

[0231] A second laser grooving is performed on the dielectric layer 11b on the back side of the wafer: using a second laser, the laser protective liquid C accumulated in the etched grooves of the back laser grooving is removed, while the surface of the dielectric layer 11b on the back side of the wafer and the edges of the etched grooves are covered by the laser protective liquid C; wherein, the laser for the second laser grooving is a green nanosecond laser with a wavelength of 532nm, a power of 50% of the power of the first laser grooving, a pulse frequency of 200kHz, a pulse width of 200ns, and a laser spot diameter of 50μm; the width of the second laser grooving = 90% × the width of the first laser grooving; the depth of the second laser grooving = the thickness of the laser protective liquid C = 3.0μm. The remaining steps and parameters are similar to those in Example 4.

[0232] In this embodiment, the chip edge serpentine shape is less than 1.3 μm, the number of contaminated particles on the chip surface is less than 70 particles @ 90 nm, the separation width between the dielectric layer and the substrate is ≤ 0.5 μm, and the slag or accumulation height at the chip edge is ≤ 0.3 μm. The slag and accumulation height in this embodiment are lower than those in Example 4.

[0233] Furthermore, in the chip dicing methods described in Examples 1 to 7, the total time from wafer to chip dicing completion is 12-14 hours.

[0234] Comparative Example 1

[0235] For the wafer 100 in Example 1, the wafer 100 is attached to the carrier blue film 200, and conventional plasma cutting is used to cut directly from the upper surface of the wafer to the lower surface of the wafer. The etching rate is 2000 nm / min, the etching gas is SF6, the resulting chip edge serpentine is 5 μm, the number of contaminant particles on the chip surface is 1000 @ 90 nm, the layer width between the dielectric layer and the substrate of the chip is 5 μm, and the total time from wafer to chip cutting is 14 h.

[0236] Comparative Example 2

[0237] For the wafer 100 in Example 1, the wafer 100 is attached to the carrier blue film 200, and conventional laser stealth dicing is used to directly cut from the upper surface of the wafer to the lower surface of the wafer. The laser wavelength is 1064nm, the spacing between the modified layers is 10 micrometers, the dicing width is 20 micrometers, the resulting chip edge has a serpentine shape of 4μm, the number of contaminant particles on the chip surface is 500 @ 90nm, the layer width between the dielectric layer and the substrate of the chip is 8μm, and the total time from wafer to chip is 20h.

[0238] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A chip dicing method applicable to D2W hybrid bonding multilayer stacking, characterized in that, The wafer to be diced mainly consists of a substrate and dielectric layers located on the upper and lower surfaces of the substrate, respectively. The dielectric layer on the upper surface of the substrate constitutes the dielectric layer on the front side of the wafer, while the dielectric layer on the lower surface of the substrate constitutes the dielectric layer on the back side of the wafer. The dielectric layer on the front side and / or the dielectric layer on the back side of the wafer includes a metal structure. The chip cutting method includes the following steps: (1) Apply laser protective liquid to the front side: The dielectric layer surface on the back side of the wafer is bonded to the first carrier, with the dielectric layer on the front side of the wafer facing upwards; laser protective liquid A is coated on the dielectric layer surface on the front side of the wafer. (2) Front laser grooving: Laser grooving is performed on the dielectric layer on the front side of the wafer along the dicing path until the groove formed by laser etching penetrates the dielectric layer on the front side of the wafer; after laser grooving on the front side, the laser protective solution A is removed by cleaning. (3) Flip: Debond the dielectric layer surface on the back side of the wafer from the first carrier, and cover the dielectric layer surface on the front side of the wafer with the second carrier; flip the wafer so that the dielectric layer on the back side of the wafer faces upward; after flipping, ensure that the dielectric layer surface on the front side of the wafer is bonded to the second carrier. (4) Apply laser protective liquid to the back side: Laser protective solution B is applied to the dielectric layer surface on the back side of the wafer; (5) Laser grooving on the back: Laser grooving is performed on the dielectric layer on the back side of the wafer along the dicing path until the groove formed by laser etching penetrates the dielectric layer on the back side of the wafer. (6) Base cutting and expansion.

2. The chip cutting method according to claim 1, characterized in that, In step (2), the depth of the laser grooving is equal to the thickness of the laser protective liquid A plus 100%-120% of the thickness of the dielectric layer on the front side of the wafer. In step (5), the depth of the laser grooving is equal to the thickness of the laser protective liquid B plus 100%-120% of the thickness of the dielectric layer on the back side of the wafer.

3. The chip cutting method according to claim 1, characterized in that, In steps (2) and (5), the width of the cutting track is 10 μm-400 μm; and / or, In steps (2) and (5), the wavelength of the laser grooving is 200-600nm, the power is 10-200W, the pulse frequency is 1kHz-100MHz, the pulse width is 10fs-100ns, and the laser spot diameter is 10-100μm.

4. The chip cutting method according to claim 1, characterized in that, In steps (2) and (5), the width of the laser grooving = (30% - 80%) × the width of the cutting path; and / or, The centerline of the laser grooving and the centerline of the cutting path deviate by no more than 10 μm.

5. The chip cutting method according to claim 1, characterized in that, In the wafer to be diced, the thickness of the dielectric layer is 10nm-20μm, the thickness of the substrate is 10μm-780μm, and the metal structure includes metal pads with a pad pitch of 0.4μm-20μm, a pad depth of 10nm-1000nm, and an area of ​​0.03μm for each metal pad. 2 -100μm 2 .

6. The chip cutting method according to claim 5, characterized in that, In steps (2) and (5), the wavelength of the laser grooving is 200-350nm, the power is 100-200W, the pulse frequency is 1kHz-10MHz, the pulse width is 10fs-500ps, and the laser spot diameter is 10-40μm; and / or, The laser used for laser grooving is a UV picosecond or UV femtosecond laser.

7. The chip cutting method according to claim 5, characterized in that, In steps (1) and (4), the thicknesses of both laser protective liquid A and laser protective liquid B are controlled to be 1-10 μm; and / or, The coating method is spin coating, and the spin coating speed is 1000-3000 rpm.

8. The chip cutting method according to claim 1, characterized in that, In step (2), the cleaning and removal of laser protective liquid A includes: cleaning by spin coating combined with megasonic or two-fluid method within 48 hours after coating laser protective liquid A; after cleaning, the number of particles on the wafer surface and in the grooves formed by laser etching is ≤100 particles@500nm.

9. The chip cutting method according to claim 1, characterized in that, In steps (1) and (3), the first carrier and the second carrier are selected from one of UV blue film, silicon-based wafer carrier, and transparent glass carrier.

10. The chip obtained by the chip dicing method according to any one of claims 1-9, characterized in that, The chip edge serpentine shape is less than 2μm, the number of contaminated particles on the chip surface is ≤100 @90nm, and the layer width between the dielectric layer and the substrate in the chip is ≤1μm.

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