Packaging structure

Abstract

The present disclosure relates to a package structure. The package structure includes a circuit structure having a first surface, and a molded interposer disposed on the first surface of the circuit structure. The molded interposer includes a first pin and a second pin. The first pin is tilted in a first direction with respect to the first surface in a cross-sectional view, and the second pin is tilted in a second direction with respect to the first surface in the cross-sectional view. The second direction is different from the first direction.

Description

Technical Field

[0001] This disclosure is generally related to packaging structures, and more specifically, to semiconductor packaging structures utilizing an interposer layer that integrates multiple conductive pins. Background Technology

[0002] In packaging processes (such as panels), the formation of vertical communication typically relies on electroplating during lithography to create conductive pillars. However, this process faces several challenges, particularly regarding plating uniformity. During the electroplating process for manufacturing metal pillars, factors such as current, duration, plating solution concentration, and total plating area can affect plating quality, resulting in uneven pillar heights. In some cases, pillars at panel corners tend to be higher, leading to significant height differences across the entire panel, which increases polishing time to achieve uniform height. Furthermore, after plating, the metal pillars exhibit uneven widths (e.g., wider at the top and narrower at the bottom), making it difficult to meet the requirement of small pitch at a given height. Additionally, excessively long plating times can affect overall process efficiency. Therefore, improved packaging structures are needed. Summary of the Invention

[0003] In some embodiments, a package structure includes: a circuit structure having a first surface; and a molded interposer disposed on the first surface of the circuit structure. The molded interposer includes a first pin and a second pin. The first pin is inclined in a first direction relative to the first surface in a cross-sectional view, and the second pin is inclined in a second direction relative to the first surface in the same cross-sectional view. The second direction is different from the first direction.

[0004] In some embodiments, a package structure includes a first pin and a redistributable layer (RDL). The first pin is encapsulated by a first encapsulation body and has an elliptical top surface. The RDL is disposed on the first pin and includes a first via and a dielectric layer partially covering the first via. The first via is disposed on the first pin and contacts the top surface of the first pin. The first via exposes a portion of the top surface of the first pin.

[0005] In some embodiments, a packaging structure includes a first redistributable layer (RDL), a second redistributable layer (RDL), an interposer, and an encapsulation body. The first RDL includes a first dielectric layer and a first via partially covered by the first dielectric layer. The second RDL includes a second dielectric layer and a second via partially covered by the second dielectric layer. The interposer is disposed between the first and second RDLs and includes a first pin. The encapsulation body encapsulates the interposer and has a top surface and a bottom surface opposite the top surface. The top surface of the first pin is substantially aligned with the top surface of the encapsulation body, and the bottom surface of the first pin is substantially aligned with the bottom surface of the encapsulation body. The first and second vias gradually narrow towards the interposer. Attached Figure Description

[0006] The nature of this disclosure will be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features may not be drawn to scale, and the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a cross-section of a packaging structure according to some embodiments of the present disclosure.

[0008] Figure 2A According to some embodiments of this disclosure Figure 1 An enlarged view of the central section "2A".

[0009] Figure 2B According to some embodiments of this disclosure Figure 1 A magnified view of the "2B" section in the middle section.

[0010] Figure 3A This is a top view of an intermediary layer according to some embodiments of the present disclosure.

[0011] Figure 3B This is a top view of an intermediary layer according to some embodiments of the present disclosure.

[0012] Figure 3C This is a top view of an intermediary layer according to some embodiments of the present disclosure.

[0013] Figure 3D This is a top view of an intermediary layer according to some embodiments of the present disclosure.

[0014] Figure 3E This is a top view of an intermediary layer according to some embodiments of the present disclosure.

[0015] Figure 3F This is a top view of an intermediary layer according to some embodiments of the present disclosure.

[0016] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G and Figure 4H The illustration depicts one or more operations of a method for manufacturing an intermediary layer according to some embodiments of the present disclosure.

[0017] Figure 4C-1 According to some embodiments of this disclosure Figure 4C A magnified view of the "4C" section in the middle area.

[0018] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H and Figure 5I The illustration depicts one or more operations of a method for manufacturing a package structure according to some embodiments of the present disclosure.

[0019] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. This disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings. Detailed Implementation

[0020] The following disclosure provides various embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and embodiments are described herein. Of course, these are merely examples and are not intended to be limiting. In this disclosure, reference to forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself establish a relationship between the various embodiments and / or configurations discussed.

[0021] Embodiments of this disclosure are described in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0022] Figure 1 This is a cross-section of a packaging structure 1 according to some embodiments of the present disclosure. The packaging structure 1 may include a substrate 10, one or more electronic components 20 and 20', one or more interposers 30, an encapsulant 40, a redistribution layer (RDL) 50, one or more electronic components 60, an encapsulant 70, and one or more electrical contacts 80.

[0023] The package structure 1 may be or include a stacked package (PoP), a fan-out stacked package (FOPoP), a fan-out chip-on-a-substrate (FOCoS), a fan-out chip-on-a-substrate bridge (FOCoS-B), or the like.

[0024] Embodiments of this disclosure constitute a packaging structure including a molded interposer having a plurality of conductive leads for vertical connection. The conductive leads, encapsulated in the molded interposer, can be formed during the manufacturing process by placing them in a template with multiple holes. The template guides the leads to their predetermined positions, thereby improving the accuracy of these positions. Furthermore, the diameter and shape of the template holes can be adjusted based on the lead size. In addition, the leads of the interposer can exhibit a uniform width, and therefore the molded interposer can simultaneously meet requirements for high height and small pitch. Since the molded interposer does not require electroplating, process time can also be shortened.

[0025] The substrate 10 may include a circuit structure, such as a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. The substrate 10 may include interconnect structures, such as a plurality of conductive traces and / or a plurality of vias. In some embodiments, the substrate 10 includes a ceramic material, a metal plate, an organic substrate, or a lead frame. In some embodiments, the substrate 10 may include a bilayer substrate, comprising a core layer and conductive materials and / or structures disposed on an upper surface and a bottom surface of the substrate 10. The conductive materials and / or structures may include a plurality of conductive traces. The substrate 10 may be or include a redistribution layer (RDL), which includes one or more dielectric layers 10d and conductive layers 10c at least partially covered or embedded in the dielectric layers 10d. The conductive layer 10c may include conductive traces, pads, and vias. The substrate 10 may include a top surface 101 and a bottom surface opposite to the top surface 101. In some embodiments, substrate 10 includes one or more conductive pads (not shown) exposed by a top surface 101 or a bottom surface.

[0026] Electronic components 20 and 20' may be disposed on the top surface 101 of substrate 10. Electronic components 20 and 20' may be attached to substrate 10 via adhesive layer 20h. In some embodiments, adhesive layer 20h may be a single layer. Adhesive layer 20h may be or include conductive materials, such as aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), stainless steel, mixtures, alloys, or other combinations thereof. In another embodiment, adhesive layer 20h may include multiple layers 20h1, 20h2, and 20h3. For example, adhesive layers 20h1, 20h2, and 20h3 may be or include dielectric layers. In some embodiments, electronic components 20 and 20' may have an active surface 201 and a back surface 202 opposite to the active surface 201. The active surface 201 of electronic components 20 and 20' faces away from substrate 10. The back surface 202 can be attached to the top surface 101 of the substrate 10 via the adhesive layer 20h. Electronic components 20 and 20' can be electrically connected to RDL50.

[0027] Electronic components 20 and 20' may be substantially the same size. For example, electronic components 20 and 20' may have the same width and / or thickness. In another embodiment, electronic components 20 and 20' may have different sizes (such as thickness or width). For example, the thickness of electronic components 20 and 20' may vary.

[0028] Each of electronic components 20 and 20' may be a chip or a die, including a semiconductor substrate, one or more integrated circuit devices, and one or more overlay interconnect structures. The integrated circuit devices may include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or combinations thereof. In some configurations, electronic components 20 and 20' include active devices, such as ASICs, PMICs, or the like. For example, electronic components 20 and 20' may be or include storage components or memory, such as dynamic random access memory (DRAM). In some embodiments, electronic components 20 and 20' may be interconnect structures, such as bridging dies.

[0029] RDL 50 may be disposed above substrate 10 and electronic components 20 and 20'. In some embodiments, RDL 50 may include a circuit layer. RDL 50 includes one or more dielectric layers 50d and a conductive layer 50c at least partially covered or embedded in the dielectric layers 50d. The conductive layer 50c may include conductive traces, pads, and vias. The conductive layer 50c may be or include conductive materials such as aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), stainless steel, mixtures, alloys, or other combinations thereof. In some embodiments, the width of RDL 50 may be substantially the same as the width of substrate 10. The width of the dielectric layer 50d of RDL 50 may be substantially the same as the width of substrate 10.

[0030] In some embodiments, electronic components 20 and 20' can be electrically connected to the conductive layer 50c of RDL 50 via one or more conductive posts 20p. The conductive posts 20p can be or include posts, pillars, terminals, pins, or other suitable conductive interconnects. In some embodiments, the conductive posts 20p can be formed by vertical bonding. The conductive posts 20p can be or include conductive materials such as copper (Cu), aluminum (Al), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), platinum (Pt), mixtures, alloys, or other combinations thereof.

[0031] Intermediate layer 30 may be disposed on the top surface 101 of substrate 10 and laterally overlap with electronic components 20 and 20'. Intermediate layer 30 may be disposed between RDL 50 and the top surface 101 of substrate 10 and electrically connected to RDL 50 and the top surface 101 of substrate 10. Intermediate layer 30 may be electrically connected to conductive layer 50c of RDL 50. In some embodiments, intermediate layer 30 contacts RDL 50 and substrate 10.

[0032] In some embodiments, the interposer 30 may be a conductive pillar module or a molded interposer. The interposer 30 may include one or more pins 301, 302, 303, and 304, and an enclosure 30m encapsulating the pins 301, 302, 303, and 304. The enclosure 30m may expose the top and bottom surfaces of the pins 301, 302, 303, and 304. In some embodiments, the side surfaces of the enclosure 30m may be substantially parallel to and not in contact with the side surfaces of the electronic components 20 and 20'.

[0033] In some embodiments, the encapsulation body 30m may include epoxy resin in which fillers are dispersed, encapsulation material (e.g., epoxy resin encapsulation material or other encapsulation material), PI, phenolic compound or material, polymer material in which polysiloxane is dispersed, or combinations thereof.

[0034] In some embodiments, pins 301, 302, 303, and 304 may have the same diameter. In other embodiments, pins 301, 302, 303, and 304 may have different diameters. For example, the diameter of pin 301 is larger than the diameter of pin 302 (see [link]). Figure 2A In some embodiments, the diameters of pins 301, 302, 303, and 304 may be about 15, 20, 30, 40, 50, 60, 70, 80 μm or greater. The shapes of pins 301, 302, 303, and 304 may be substantially the same (see [link]). Figures 3A to 3F (Details within).

[0035] Pins 301, 302, 303, and 304 may be disposed between and extend therebetween the RDL 50 and the top surface 101 of the substrate 10. In some embodiments, pin 301 is spaced apart from pin 302. Pin 303 may be spaced apart from pin 302. Pin 302 may be disposed between pins 301 and 303. Pin 304 may be spaced apart from pin 303. Pin 303 may be disposed between pins 302 and 304. In some embodiments, the pitch (distance between adjacent pins) of pins 301, 302, 303, and 304 may be less than or equal to 25 μm.

[0036] Pins 301, 302, 303, and 304 may have substantially the same height (vertical length) H2. In some embodiments, the height H1 of the conductive post 20p differs from the height H2 of the pin 301. For example, height H1 may be less than height H2. In some embodiments, the height H2 of pins 301, 302, 303, and 304 may be in the range of 0.1 to 1 mm, preferably less than or equal to 0.2 mm. In some embodiments, the diameter of the conductive post 20p differs from the diameter of the pin 301. For example, the diameter of the conductive post 20p is smaller than the diameter of the pin 301.

[0037] In some embodiments, the conductive posts 20p may be parallel to each other. The conductive posts 20p may be tilted or inclined relative to the top surface 401 of the encapsulation 40. The tilt direction of the first conductive post 20p relative to the top surface 401 of the encapsulation 40 is substantially the same as the tilt direction of the second conductive post 20p. In other embodiments, the conductive posts 20p may be substantially parallel to the pins 301, 302, 303, and 304 of the interposer 30.

[0038] Pins 301, 302, 303, and 304 may be conductive, such as electrical, thermal, or grounding pins. In one embodiment, pins 301, 302, 303, and 304 are all electrically conductive pins. In another embodiment, pins 301 and 304 may be grounding pins, and pins 302 and 303 may be conductive pins.

[0039] In some embodiments, pins 301 and 304 may be thermally conductive pins, through which no current passes, and pins 302 and 303 may be conductive pins. Thermally conductive pins 301 and 304 surround conductive pins 302 and 303. In this case, thermally conductive pin 301 may be connected to the dielectric layer 50d of RDL 50. Conductive pin 302 is electrically connected to the conductive layer 50c of RDL 50.

[0040] Pins 301, 302, 303, and 304 may be or include posts, pillars, terminals, or other suitable conductive interconnects. Pins 301, 302, 303, and 304 may be or include conductive materials such as copper (Cu), aluminum (Al), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), platinum (Pt), mixtures, alloys, or other combinations thereof.

[0041] Pins 301, 302, 303, and 304 may be pre-formed and then encapsulated by a capsule 30m to form an interposer layer 30. The top surface of the capsule 30m is substantially aligned with the top surfaces of pins 301, 302, 303, and 304, and the bottom surface of the capsule 30m is substantially aligned with the bottom surfaces of pins 301, 302, 303, and 304. In some embodiments, the side surfaces of the capsule 30m are substantially parallel to and do not contact the side surfaces of electronic components 20 and 20'.

[0042] Encapsulation 40 encapsulates electronic components 20 and 20', conductive pillars 20p, and interposer 30. Encapsulation 40 exposes one end of conductive pillar 20p and the top surface of the pins within interposer 30. Interposer 30 may be spaced apart from conductive pillar 20p by encapsulation 40. In some embodiments, conductive pillar 20p is formed by wire bonding, and the package structure 1 may not contain a seed layer between conductive pillar 20p and the active surface 201 of electronic component 20 or 20'. Encapsulation 40 may have a top surface 401 and a bottom surface 402 opposite to the top surface 401. Top surface 401 is substantially coplanar or aligned with the top surface of one end of conductive pillar 20p and the pins (such as pins 301, 302, 303, and 304) of interposer 30. That is, the top surfaces of the contacts 301, 302, 303, and 304 of the interposer 30 are exposed by the top surface 401 of the encapsulant 40. The bottom surface 402 contacts the top surface 101 of the substrate. The bottom surface 402 may be substantially coplanar or aligned with the bottom surfaces of the contacts (such as contacts 301, 302, 303, and 304) of the interposer 30. In some embodiments, the width of the encapsulant 40 is substantially the same as the width of the substrate 10.

[0043] In some embodiments, the encapsulation body 40 may include an epoxy resin in which fillers are dispersed, an encapsulation material (e.g., an epoxy encapsulation material or other encapsulation material), PI, a phenolic compound or material, a polymeric material in which polysiloxane is dispersed, or a combination thereof. In some embodiments, the encapsulation body 40 may include a material different from that of the encapsulation body 30m. In other embodiments, the encapsulation body 40 may include the same material as that of the encapsulation body 30m.

[0044] In some embodiments, electronic component 60 may be disposed on RDL 50 and vertically overlap with a portion of interposer 30. Electronic component 60 may include one or more conductive terminals 60p projecting from the underside of electronic component 60. Electronic component 60 may be electrically connected to RDL 50 via connector 60c. Connector 60c may include conductive bumps, solder assemblies, solder balls, microbumps, or the like. Connector 60c may be or include conductive materials such as aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), stainless steel, mixtures, alloys, or other combinations thereof.

[0045] In some embodiments, the protective component 60u may cover or encapsulate the connector 60c, the electronic component 60, and the RDL 50. The protective component 60u may partially cover the RDL 50. In some embodiments, the protective component 60u may encapsulate the bottom surface of the electronic component 60 and partially cover the side surfaces of the electronic component 60. In some embodiments, the protective component 60u may be or include an underfill or a dielectric layer. The underfill may include epoxy resin in which filler is dispersed, an encapsulation material (e.g., epoxy encapsulation material or other encapsulation material), polyimide (PI), a phenolic compound or material, a polymer material in which polysiloxane is dispersed, or a combination thereof.

[0046] Each of the electronic components 60 may be a chip or a die, including a semiconductor substrate, one or more integrated circuit devices, and one or more of their overlay interconnect structures. The integrated circuit devices may include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or combinations thereof. In some configurations, electronic component 60 includes active devices, such as ASICs, PMICs, or the like. For example, electronic component 60 may be or include storage components or memory, such as dynamic random access memory (DRAM). In some embodiments, electronic component 60 may differ from electronic components 20 and 20'. For example, electronic component 60 may be an ASIC and / or memory, and electronic components 20 and 20' may be bridging dies and / or PMICs.

[0047] Encapsulation 70 may encapsulate or cover electronic component 60, protective component 60u, and RDL 50. Encapsulation 70 may cover the top surface of electronic component 60. Electronic components 60 may be spaced apart by encapsulation 70. In some embodiments, the width of encapsulation 70 is substantially the same as the width of RDL 50.

[0048] In some embodiments, the encapsulation 70 may include an epoxy resin in which fillers are dispersed, an encapsulation material (e.g., an epoxy resin encapsulation material or other encapsulation material), PI, a phenolic compound or material, a polymeric material in which polysiloxane is dispersed, or a combination thereof.

[0049] In some embodiments, the electrical contact 80 may be disposed on the bottom surface 102 of the substrate 10. The electrical contact 80 may be disposed on the side of the substrate 10 opposite to the encapsulation 40. The electrical contact 80 may be electrically connected to the pins of the interposer 30. The electrical contact 80 may include conductive bumps, solder assemblies, solder balls, or the like. The electrical contact 80 may be or include conductive materials such as aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), stainless steel, mixtures, alloys, or other combinations thereof.

[0050] The proposed packaging structure 1 includes a molded interposer 30 equipped with several conductive pins for vertical connection. The diameter and shape of the conductive pins can be varied. The conductive pins of the molded interposer 30 can simultaneously have a high height and a small pitch. In addition, since the molded interposer eliminates the need for an electroplating process, the total manufacturing time can be reduced.

[0051] Figure 2A According to some embodiments of this disclosure Figure 1 An enlarged view of section "2A" in the middle section. (Reference) Figure 2A The contacts 301, 302, 303, and 304 of the interposer layer 30 may be tilted and angled relative to the top surface 101 in different directions. Contact 301 is tilted and angled relative to the top surface 101 in a direction different from that of contact 302. Contact 302 is tilted and angled relative to the top surface 101 in a direction different from that of contact 303. In some embodiments, contacts 301, 302, 303, and 304 may be at different angles. Contacts 301, 302, 303, and 304 may be tilted to offset by approximately 1, 1.5, or 2 μm. That is, contacts 301, 302, 303, and 304 may be substantially slightly tilted perpendicular to the top surface 101 of the substrate 10.

[0052] In some embodiments, pin 301 may form an angle θ1 with the top surface 101 of substrate 10. Pin 302 may form an angle θ2 with the top surface 101 of substrate 10. Pin 303 may form an angle θ3 with the top surface 101 of substrate 10. Pin 304 may form an angle θ4 with the top surface 101 of substrate 10. The angle θ1 of pin 301 may be different from the angles θ2 of pin 302, θ3 of pin 303, and θ4 of pin 304. The angle θ1 of pin 301 is greater than the angle θ2 of pin 302. In one embodiment, the angle θ1 of pin 301 may be closer to 90° than angles θ2, θ3, and θ4. Because the angle (tilt) of pin 301 is smaller than the angle of pin 302, the length of pin 301 may be smaller than the length of pin 302. In some embodiments, pins 302 and 303 may be tilted at different tilt angles in different directions. For example, the angle θ2 of the connector 302 may be smaller than the angle θ3 of the connector 303. That is, the inclination of the connector 302 relative to the bottom surface of the envelope 30m is greater than the inclination of the connector 303. In some embodiments, the connectors 302 and 304 may be tilted at different angles in the same direction.

[0053] In some embodiments, the contacts 301, 302, 303, and 304 of the interposer layer 30 may have different diameters. The diameter d1 of contact 301 is different from the diameter d2 of conductive contact 302. The diameter d1 of contact 301 is larger than the diameter d2 of contact 302. In some embodiments, contacts 302, 303, and 304 may have the same diameter but different from that of contact 301.

[0054] Both the top and bottom surfaces of the intermediate layer 30 can be ground. Therefore, the surface roughness of the top surface of pin 301 is substantially the same as the surface roughness of the bottom surface of pin 301. The surface roughness of the top surface of pin 302 is substantially the same as the surface roughness of the bottom surface of pin 302. The surface roughness of the top surface of pin 303 is substantially the same as the surface roughness of the bottom surface of pin 303. The surface roughness of the top surface of pin 304 is substantially the same as the surface roughness of the bottom surface of pin 304.

[0055] In some embodiments, the conductive layer 50c of RDL 50 may include one or more vias 50va, 50vb, and 50vc covered by the dielectric layer 50d. The conductive layer 10c of substrate 10 may include one or more vias 10va and 10vb covered by the dielectric layer 10d. Vias 50va, 50vb, and 50vc are disposed on the top surface of the interposer 30 and gradually narrow towards the top surface of the interposer 30, and are connected to the pins of the interposer 30. Vias 10va and 10vb are disposed on the bottom surface of the interposer 30 and gradually narrow towards the bottom surface of the interposer 30, and are connected to the pins of the interposer 30. In some embodiments, vias 50va, 50vb, 50vc, 10va, and 10vb are not aligned with the pins of the interposer 30.

[0056] A via 50va may be disposed on pin 302 and contact the top surface of pin 302. The via 50va may expose a portion of the top surface of pin 302. That is, the via 50va does not completely cover the top surface of pin 302. In some embodiments, the center of the via 50va may not be aligned with the center of the top surface of pin 302. Accordingly, the distance S11 between the left edge of pin 302 and the left edge of the via 50va is greater than the distance between the right edge of pin 302 and the right edge of the via 50va.

[0057] The via 10va can be positioned below the pin 302 and contact the bottom surface of the pin 302. The via 10va may expose a portion of the bottom surface of the pin 302. That is, the via 10va does not completely cover the bottom surface of the pin 302. In some embodiments, the center of the via 10va may not be aligned with the center of the bottom surface of the pin 302. Accordingly, the distance S12 between the left edge of the pin 302 and the left edge of the via 10va is less than the distance between the right edge of the pin 302 and the right edge of the via 10va.

[0058] A via 50vb may be disposed on pin 303 and contact the top surface of pin 303. The via 50vb may expose a portion of the top surface of pin 303. That is, the via 50vb does not completely cover the top surface of pin 303. In some embodiments, the center of the via 50vb may not be aligned with the center of the bottom surface of pin 303. Accordingly, the distance S21 between the left edge of pin 303 and the left edge of the via 50vb is less than the distance between the right edge of pin 303 and the right edge of the via 50vb. In some embodiments, the distance S11 between the left edge of pin 302 and the left edge of via 50va is different from (e.g., greater than) the distance S21 between the left edge of pin 303 and the left edge of the via 50vb.

[0059] The via 10vb may be positioned below and in contact with the bottom surface of the pin 303. The via 10vb may expose a portion of the bottom surface of the pin 303. That is, the via 10vb does not completely cover the bottom surface of the pin 303. In some embodiments, the center of the via 10vb may not be aligned with the center of the bottom surface of the pin 303. Accordingly, the distance S22 between the left edge of the pin 303 and the left edge of the via 10vb is greater than the distance between the right edge of the pin 303 and the right edge of the via 10vb. In some embodiments, the distance S12 between the left edge of the pin 302 and the left edge of the via 10va is different from (e.g., less than) the distance S22 between the left edge of the pin 303 and the left edge of the via 50vb.

[0060] A via 50vc may be disposed on pin 304 and contact the top surface of pin 304. The via 50vc may expose a portion of the top surface of pin 304. That is, the via 50vc does not completely cover the top surface of pin 304. In some embodiments, the center of the via 50vc may not be aligned with the center of the top surface of pin 304. Accordingly, the distance S31 between the left edge of pin 304 and the left edge of the via 50vc is less than the distance between the right edge of pin 304 and the right edge of the via 50vc. In some embodiments, the distance S11 between the left edge of pin 302 and the left edge of the via 50va is different from (e.g., greater than) the distance S31 between the left edge of pin 304 and the left edge of the via 50vc.

[0061] refer to Figure 2AThe encapsulation 40 may include a plurality of fillers. Each of the fillers in the encapsulation 40 may have a different filler size. In some embodiments, the fillers may contact the RDL 50 and the substrate 10. The encapsulation 40 may include fillers 411, 412, and 413. In some embodiments, filler 411 is not completely removed due to a portion being removed by a polishing process. The removed portion of filler 411 may be about 50% of the original amount. In some embodiments, the removed portion of filler 411 may be less than 50% of the original amount. The top surface of filler 411 is formed to be substantially planar by a polishing process. Similar to filler 411, filler 413 is also not completely removed. The removed portion of filler 413 may be about 50% of the original amount. In some embodiments, the removed portion of filler 413 may be less than 50% of the original amount. The top surface of filler 413 is formed to be substantially planar by a polishing process. In some embodiments, filler 412 may have a relatively large diameter. For example, the diameter of filler 412 may be equal to or greater than the thickness of a dielectric layer 50d of RDL 50.

[0062] In some embodiments, the encapsulation 40 may have one or more recesses 421 recessed from the top surface 401, because some filler can be completely removed during the polishing process. A portion of the dielectric layer 50d may fill the recesses 421. Therefore, this portion of the dielectric layer 50d may laterally (or horizontally) overlap with the intermediate layer 30 (i.e., contacts 301, 302, 303, and 304). In some embodiments, the encapsulation 40 may have one or more recesses 422 recessed from the bottom surface, because some filler can be completely removed during the polishing process. A portion of the dielectric layer of the substrate 10 may fill the recesses 422. Therefore, this portion of the dielectric layer of the substrate 10 may laterally (or horizontally) overlap with the intermediate layer 30 (i.e., contacts 301, 302, 303, and 304). In some embodiments, both the top and bottom surfaces of the encapsulation 40 may be polished. In other embodiments, only one of the top and bottom surfaces of the encapsulation 40 may be polished.

[0063] In some embodiments, the encapsulation body 30m may include a plurality of fillers. Each of the fillers in the encapsulation body 30m may have a different filler size. The encapsulation body 30m may be similar to the encapsulation body 40. For example, both the top and bottom surfaces of the encapsulation body 30m may be ground. In some embodiments, the filler may contact the RDL 50 and the substrate 10.

[0064] Encapsulation body 30m may include fillers 31, 32, 33, and 34. In some embodiments, filler 31 is not completely removed due to the removal of a portion by a grinding process. The removed portion of filler 31 may be about 50% of the original amount. In other embodiments, the removed portion of filler 31 may be less than 50% of the original amount. The top surface of filler 31 is formed into a substantially planar surface by a grinding process. That is, the top surface of filler 31 may be substantially coplanar or aligned with the top surface of encapsulation body 30m (and the top surface 401 of encapsulation body 40). Similar to filler 31, filler 32 is also not completely removed. The removed portion of filler 32 may be less than 50% of the original amount. In some embodiments, the removed portion of filler 32 may be about 50% or more of the original amount. The bottom surface of filler 32 is formed into a substantially planar surface by a grinding process. That is, the bottom surface of the filler 32 can be substantially coplanar or aligned with the bottom surface of the capsule 30m (and the bottom surface 402 of the capsule 40).

[0065] In some embodiments, the filler 33 is not completely removed due to the removal of a portion by cutting, sawing, or monomerization. The removed portion of the filler 33 may be about 50% of the original amount. In other embodiments, the removed portion of the filler 33 may be less than or greater than 50% of the original amount. The side surface (left side surface) of the filler 33 is formed substantially planar by a sawing process. That is, the left side surface of the filler 33 may be substantially coplanar or aligned with the left side surface of the capsule 30m. In some embodiments, the filler 34 is not completely removed due to the removal of a portion by cutting, sawing, or monomerization. The removed portion of the filler 34 may be about 50% of the original amount. In other embodiments, the removed portion of the filler 34 may be less than or greater than 50% of the original amount. The side surface (right side surface) of the filler 34 is formed substantially planar by a sawing process. That is, the right side surface of the filler 34 may be substantially coplanar or aligned with the right side surface of the capsule 30m. In some embodiments, the interface between the encapsulation bodies 30m and 40 may be substantially perpendicular to the top surface 101 of the substrate 10. Pins 301, 302, 303 and 304 may be located away from the interface between the encapsulation bodies 30m and 40.

[0066] Figure 2B According to some embodiments of this disclosure Figure 1 A magnified view of section "2B" in the middle section. (Reference) Figure 2B The adhesive layer 20h may be or include a circuit layer, which includes one or more dielectric layers 20hd and a conductive layer 20hc that is at least partially covered or embedded in the dielectric layer 20hd. The conductive layer 20hc may include conductive traces, pads, and vias. The conductive layer 20hc may be or include conductive materials such as aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), stainless steel, mixtures, alloys, or other combinations thereof.

[0067] Figure 2B The bottom surface of the encapsulation 40 may be unpolished, and therefore the interface 405 between the encapsulation 40 and the substrate 10 may be irregular. In some embodiments, the interface 405 may be recessed upwards, that is, away from the substrate 10.

[0068] Figure 3A This is a top view of an interposer 30A according to some embodiments of the present disclosure. The interposer 30A may be an embodiment of the interposer 30. The interposer 30A includes a plurality of pins 311, 312, 313, 314, 315, 316, 317 and 318, and an encapsulation body 30m encapsulating the pins. Figure 3A The locations of the RDL 50 vias 50v1, 50v2, 50v3, 50v4, 50v5, 50v6, 50v7 and 50v8 are also shown.

[0069] Pins 311 to 318 may be circular in a top view. That is, the top surfaces of pins 311 to 318 are circular. Pins 311 to 318 may be spaced apart from each other by an envelope 30m. In some embodiments, pins 311 to 318 may be configured as a row or an array. For example, pins 311, 312, 313, and 314 may be configured as an array, and pins 315, 316, 317, and 318 may be configured as a separate array. The two arrays may be spaced apart by a distance greater than the distance between individual pins. In some embodiments, the two arrays may be configured to perform different functions, such as thermal conductivity, electrical connection, or grounding. Pins 311 to 318 may be configured in a predetermined pattern.

[0070] In some embodiments, the sizes (diameters) of pins 311, 312, 313, and 314 may be the same, and the sizes (diameters) of pins 315, 316, 317, and 318 may be the same. The sizes (diameters) of pins 311, 312, 313, and 314 may be different from (e.g., smaller than) the sizes (diameters) of pins 315, 316, 317, and 318. For example, the diameters of pins 315, 316, 317, and 318 may be 1.2 times, 1.5 times, 1.8 times, or twice the diameters of pins 311, 312, 313, and 314, or greater.

[0071] Pin 311 may be spaced apart from pins 312 and 313. Pin 314 may be spaced apart from pins 312 and 313. In some embodiments, the distance D1 between the center of pin 311 and the center of pin 312 is different from the distance D2 between the center of pin 311 and the center of pin 313. For example, distance D1 may be greater than distance D2. In some embodiments, dashed line L1 connects the centers of pins 311 and 312, while another dashed line L2 connects the centers of pins 311 and 313. Lines L1 and L2 form an angle α1, which may exceed 90°, such as 105°, 110°, or 120° or greater.

[0072] Pin 315 may be spaced apart from pins 316 and 317. Pin 318 may be spaced apart from pins 316 and 317. In some embodiments, the distance D3 between the center of pin 315 and the center of pin 316 is different from the distance D4 between the center of pin 315 and the center of pin 317. For example, distance D3 may be less than distance D4. In some embodiments, dashed line L3 connects the centers of pins 315 and 316, while another dashed line L4 connects the centers of pins 315 and 317. Lines L3 and L4 form an angle α2, which may be approximately 90°, such as 85°, 90°, or 95°. That is, angle α1 may be greater than angle α2.

[0073] refer to Figure 3A The vias 50v1, 50v2, 50v3, 50v4, 50v5, 50v6, 50v7, and 50v8 of RDL 50 are configured in an array. Vias 50v1, 50v3, 50v5, and 50v7 can be configured in a column and spaced apart by the same distance (pitch). Vias 50v2, 50v4, 50v6, and 50v8 can also be configured in a column and spaced apart by the same distance (pitch). In some embodiments, vias 50v1 and 50v2 can be configured in a row and spaced apart by the same distance / pitch as in the column. Similarly, vias 50v3 and 50v4 can be configured in a row and spaced apart by the same distance / pitch as in the column. Vias 50v5, 50v6, and 50v7 and 50v8 can be configured similarly.

[0074] Vias 50v1, 50v2, 50v3, 50v4, 50v5, 50v6, 50v7, and 50v8 may be mounted on pins 311, 312, 313, 314, 315, 316, 317, and 318, respectively. Vias 50v1, 50v2, 50v3, 50v4, 50v5, 50v6, 50v7, and 50v8 may not be aligned with pins 311, 312, 313, 314, 315, 316, 317, and 318. For example, the center of via 50v1 may not be aligned with the center of the top surface of pin 311. In some embodiments, via 50v6 may be located near the boundary of the top surface of pin 316.

[0075] The area of ​​the top surface of pins 311 to 318 can be larger than the area of ​​the bottom surface of vias 50v1 to 50v8, so that the vias of RDL 50 can be completely positioned within pins 311 to 318 for electrical connection. The vias of substrate 10 can have the same configuration.

[0076] Figure 3B This is a top view of intermediary layer 30B according to some embodiments of the present disclosure. Intermediary layer 30B is similar to... Figure 3A Intermediate layer 30A is different from it in terms of the shape of the pins. Intermediate layer 30B includes a plurality of pins 321, 322, 323, 324, 325, 326, 327 and 328, and a casing 30m encapsulating the pins.

[0077] refer to Figure 3B The top surfaces of pins 321, 322, 323, 324, 325, 326, 327, and 328 may be elliptical. Pins 321, 322, 323, 324, 325, 326, 327, and 328 may have different orientations. For example, the major axis 321a of pin 321 extends in a direction different from the major axis 322a of pin 322. The major axis 321a of pin 321 extends in a direction different from the major axis 323a of pin 323. The major axis 321a of pin 321 extends in a direction different from the major axis 324a of pin 324.

[0078] Vias 50v1, 50v2, 50v3, 50v4, 50v5, 50v6, 50v7, and 50v8 can be respectively mounted on pins 321, 322, 323, 324, 325, 326, 327, and 328. Vias 50v1, 50v2, 50v3, 50v4, 50v5, 50v6, 50v7, and 50v8 may not be aligned with pins 321, 322, 323, 324, 325, 326, 327, and 328. For example, the center of via 50v1 may not be aligned with the center of the top surface of pin 321. In some embodiments, via 50v6 may be located near the boundary of the top surface of pin 326.

[0079] In some embodiments, pins 321 to 328 may be tilted, and therefore their top surfaces may be elliptical. In this case, the top surfaces of pins 321 to 328 can be enlarged so that RDL 50 can be accurately formed on the interposer layer 30B. The area of ​​the top surfaces of pins 321 to 328 may be larger than the area of ​​the bottom surfaces of vias 50v1 to 50v8, so that the vias of RDL 50 can be fully positioned within pins 321 to 328 for electrical connection. The vias of the substrate 10 may have the same configuration.

[0080] Figure 3C This is a top view of an interposer 30C according to some embodiments of the present disclosure. The interposer 30C is similar to... Figure 3A Intermediate layer 30A is different from it in terms of the shape of the pins. Intermediate layer 30C includes a plurality of pins 331, 332, 333, 334, 335, 336, 337 and 338, and a casing 30m encapsulating the pins.

[0081] refer to Figure 3C The top surface of pins 331, 332, 333, 334, 335, 336, 337, and 338 can be an irregular circle, such as a teardrop shape. Pins 331, 332, 333, 334, 335, 336, 337, and 338 can have different orientations. For example, the tips of pins 331, 332, 333, 334, 335, 336, 337, and 338 may point in different directions.

[0082] Vias 50v1, 50v2, 50v3, 50v4, 50v5, 50v6, 50v7, and 50v8 may be disposed on pins 331, 332, 333, 334, 335, 336, 337, and 338, respectively. Vias 50v1, 50v2, 50v3, 50v4, 50v5, 50v6, 50v7, and 50v8 may not be aligned with pins 331, 332, 333, 334, 335, 336, 337, and 338. For example, the center of via 50v1 may not be aligned with the center of the top surface of pin 331. In some embodiments, via 50v3 may be located near the tip of the top surface of pin 333. In some embodiments, via 50v6 may be located near the boundary of the top surface of pin 336.

[0083] In some embodiments, pins 331 to 338 may be tilted, and therefore their top surfaces may be teardrop-shaped. In this case, the top surfaces of pins 331 to 338 can be enlarged so that RDL 50 can be accurately formed on the interposer 30C. The area of ​​the top surfaces of pins 331 to 338 may be larger than the area of ​​the bottom surfaces of vias 50v1 to 50v8, so that the vias of RDL 50 can be fully positioned within pins 331 to 338 for electrical connection. The vias of substrate 10 may have the same configuration.

[0084] Figure 3D This is a top view of an intermediary layer 30D according to some embodiments of the present disclosure. The intermediary layer 30D is similar to... Figure 3A Intermediate layer 30A differs from it in pin configuration. Intermediate layer 30D includes multiple pins 341, 342, 343, 344, 345, and 346, and an enclosure 30m encapsulating these pins. Pins 341, 342, 343, 344, 345, and 346 are spaced apart from each other by the enclosure 30m.

[0085] refer to Figure 3D The sizes of pins 341, 342, 343, and 344 may be substantially different from (smaller than) the sizes of pins 345 and 346. Pins 345 and 346 may be disposed on one side of the interposer layer 30D, and pins 341 and 342 may be disposed on the opposite side of the interposer layer 30D. In some embodiments, the top surfaces of pins 341, 342, 343, 344, 345, and 346 may be polygonal, for example, octagonal. Pins 341, 342, 343, 344, 345, and 346 may be oriented along the same axis.

[0086] During manufacturing, leads 341, 342, 343, 345, and 346 can be guided and placed into specific holes in the template. Therefore, the shape of leads 341, 342, 343, 344, 345, and 346 provides a mold-locking effect, enhancing stability and reducing tilting. In some embodiments, an intermediary layer 30D with polygonal leads can be disposed at the edge of the panel to simultaneously provide electrical connection and support.

[0087] Figure 3E This is a top view of an intermediary layer 30E according to some embodiments of the present disclosure. Intermediary layer 30E is similar to... Figure 3A Intermediate layer 30A differs from it in the pin configuration. Intermediate layer 30E includes multiple pins 351 and 352, and a casing 30m encapsulating these pins. Pins 351 and 352 are spaced apart from each other by the casing 30m.

[0088] refer to Figure 3EThe shape of pin 351 may differ from that of pin 352. The top surface of pin 351 may be circular, while the top surface of pin 352 may be polygonal, such as octagonal. Pin 352 may be closer to the edge of the interposer 30E than pin 351. In some embodiments, pins 351 and 352 may provide different functions. For example, pin 351 may serve as an electrical connection, and the polygonal pin 352 may serve as a thermal conductor or ground.

[0089] Figure 3F This is a top view of an intermediary layer 30F according to some embodiments of the present disclosure. The intermediary layer 30F is similar to... Figure 3A Intermediate layer 30A differs from it in pin configuration. Intermediate layer 30F includes multiple pins 361, 362 and 363, and an enclosure 30m encapsulating these pins.

[0090] refer to Figure 3F Pins 361, 362, and 363 may be spaced apart from each other by a capsule 30m. The top surface profiles of pins 361, 362, and 363 may be different. Pins 361 and 362 may have the same shape. The shape of pin 361 may be different from the shape of pin 363. Pins 361 and 362 may be circular, and pin 363 may be rectangular. The size (diameter) of pin 361 may be different from the size (diameter) of pin 362. For example, the diameter of pin 362 may be larger than the diameter of pin 361. In some embodiments, the size (area) of pin 363 may be different from (e.g., larger than) the size (area) of pins 361 and 362.

[0091] In some embodiments, pins 361, 362, and 363 may provide different functions. For example, pin 361 may serve as an electrical connection, and pins 362 and 363 may serve as grounding pins.

[0092] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G and Figure 4H The illustration depicts one or more operations of a method for manufacturing an intermediary layer 30 according to some embodiments of the present disclosure. Figure 4C-1 According to some embodiments of this disclosure Figure 4C A magnified view of the "4C" section in the middle area.

[0093] refer to Figure 4A The carrier 410 has an adhesive layer 410h disposed on its top surface. In some embodiments, the adhesive layer 410h may be a release film coating.

[0094] refer to Figure 4BThe template 420 is placed on the carrier 410. The template 420 may have one or more legs (not shown) that contact the carrier 410 via an adhesive layer 410h for supporting the template 420 thereon. The template 420 may include a plurality of holes 420a for guiding the legs to predetermined positions, whereby the legs can be configured in a predetermined pattern. In some embodiments, the diameter and shape of the holes 420a may be adjusted as needed.

[0095] refer to Figure 4C and 4C-1 The lead 300 can be placed in the hole 420a of the template 420. The lead 300 can be mounted on the carrier 410. In some embodiments, one of the leads 300 can be guided and placed into another of the holes 420a. In some embodiments, the diameter of the lead 300 can correspond to the diameter of the hole 420a of the template 420. The lead 300 can penetrate the hole 420a and contact the adhesive layer 410h. Reference Figure 4C-1 The diameter of the lead 300 may be smaller than the diameter of the hole 420a in the template 420. The lead 300 may be tilted and angled in different orientations. In some embodiments, the lead 300 may be similar to Figure 1 Connectors 301, 302, 303 and 304.

[0096] refer to Figure 4D The lead 300 can be attached to the carrier 410 via the adhesive layer 410h, after which the template 420 can be removed. In some embodiments, a baking process can be performed so that the lead 300 can be attached to the carrier 410 via the adhesive layer 410h. In some embodiments, the lead 300 can be attached to the carrier 410 via soldering or other suitable processes.

[0097] refer to Figure 4E The encapsulation body 30m can be formed on the carrier 410 with the encapsulation connector 300. The encapsulation body 30m can be formed by a molding process.

[0098] refer to Figure 4F The 30m capsule can be ground to form a flat top surface 30m1 and expose the end (top surface) of the pin 300.

[0099] refer to Figure 4G The carrier 410 can be removed, and the resulting structure is monolithized. In some embodiments, a cutting operation can be performed. For example, the cutting operation can be a sawing process, such as laser sawing. Then, a plurality of intermediate layers 30 can be formed, such as... Figure 4H As shown in the three-dimensional (3D) illustration.

[0100] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H and Figure 5I The illustration depicts one or more operations of a method for manufacturing a package structure 1 according to some embodiments of the present disclosure.

[0101] Referring to 5A, the carrier 510 has an adhesive layer 510h disposed on the top surface of the carrier 510. In some embodiments, the adhesive layer 510h may be a release film coating.

[0102] refer to Figure 5B One or more electronic components 20 and 20' and an interposer 30 are placed on a carrier 510. The electronic components 20 and 20' and the interposer 30 are attached to the carrier 510. In some embodiments, one or more conductive posts 20p may be formed on and connected to the electronic components 20 and 20'. The top surface of the conductive post 20p may be substantially aligned with the top surface of the interposer 30.

[0103] refer to Figure 5C Encapsulation 40 can be formed on carrier 510 to encapsulate electronic components 20 and 20' and interlayer 30. Encapsulation 40 can be formed by molding process.

[0104] refer to Figure 5D The encapsulation 40 may be ground to form a planar top surface 401, exposing the pins (such as pins 301) of the interposer 30 and the ends (top surface) of the conductive posts 20p.

[0105] refer to Figure 5E A redistribution layer (RDL) 50 may be formed on the top surface 401 of the encapsulation 40. The RDL 50 includes a dielectric layer 50d and a conductive layer 50c at least partially covered by the dielectric layer 50d. Conductive pillars 20p and an interposer 30 may be electrically connected to the conductive layer 50c of the RDL 50. In some embodiments, the width of the RDL 50 may be substantially the same as the width of the encapsulation 40.

[0106] refer to Figure 5F One or more electronic components 60 may be placed on RDL 50. The electronic components 60 are attached to RDL 50. The conductive terminals 60p of the electronic components 60 may be connected to the conductive layer 50c of RDL 50 via connectors 60c.

[0107] refer to Figure 5G A protective component 60u may be formed on the RDL 50 to cover and encapsulate the electronic component 60 and the connector 60c, and then an encapsulation body 70 may be formed on the RDL 50 to cover and encapsulate the electronic component 60, the protective component 60u, and the RDL 50. In some embodiments, the width of the encapsulation body 70 may be substantially the same as the width of the RDL 50.

[0108] refer to Figure 5H The removable carrier 510 allows another carrier 530 to be attached to the encapsulation 70 via an adhesive layer 530h, enabling the structure to be inverted to form a circuit structure (i.e., substrate 10) on the electronic components 20 and 20' and the interposer 30. In some embodiments, the encapsulation 40 may be ground to form a planar bottom surface 402 and expose the ends (top surface) of the leads (such as leads 301) of the interposer 30. Thus, the RDL (i.e., substrate 10) may be formed on the bottom surface 402.

[0109] refer to Figure 5I One or more electrical contacts 80 may be formed on the substrate 10, and a removable carrier 530 may be provided. The electrical contacts 80 may be connected to the substrate 10. In some embodiments, the electrical contacts 80 may be solder balls. Next, a package structure 1 is formed.

[0110] Unless otherwise specified, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” and “below” are relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not compromised by such arrangement.

[0111] As used herein, the terms “approximately,” “substantially,” “largely,” and “about” are used to describe and explain minor variations. When used in conjunction with an event or situation, these terms may refer to examples where the event or situation occurred precisely or very approximately. For example, when used in conjunction with a numerical value, these terms may refer to a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first value is within a range of variation less than or equal to ±10% of a second value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first value may be considered “substantially” the same as or equal to the second value. For example, "roughly" vertical can refer to an angle variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0112] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered substantially flat.

[0113] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” may contain a plural number of indicators.

[0114] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials are generally defined as materials that exhibit very little or no resistance to the flow of electric current. A unit of measurement for conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m, for example, at least 10 5 S / m or at least 10 6 A material with S / m. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0115] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be flexibly interpreted as including not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0116] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and alternative equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, the process reproduction in this disclosure may differ from actual equipment. Other embodiments may exist that are not specifically described in this disclosure. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are considered to be included within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A packaging structure comprising: A circuit structure having a first surface; A molded interposer layer disposed on the first surface of the circuit structure, wherein the molded interposer layer includes a first pin and a second pin, wherein the first pin is inclined relative to the first surface in a first direction in a cross-sectional view, and wherein the second pin is inclined relative to the first surface in a second direction in a cross-sectional view, wherein the second direction is different from the first direction.

2. The packaging structure according to claim 1, wherein the first angle of the first pin relative to the first surface of the circuit structure is different from the second angle of the second pin relative to the first surface of the circuit structure.

3. The packaging structure according to claim 2, further comprising a first encapsulation body encapsulating the molded interlayer and having a top surface and a bottom surface opposite the top surface, wherein the top surface of the first pin is substantially aligned with the top surface of the first encapsulation body, and the bottom surface of the first pin is substantially aligned with the bottom surface of the first encapsulation body.

4. The packaging structure according to claim 3, wherein the top surface of the first pin is exposed by the top surface of the first encapsulation, and wherein the top surface of the first pin is elliptical in a top view.

5. The packaging structure according to claim 4, wherein the top surface of the second pin is exposed by the top surface of the first encapsulation and is elliptical in the top view, and wherein the major axis of the top surface of the first pin extends in a direction different from the major axis of the top surface of the second pin.

6. The packaging structure according to claim 2, wherein the roughness of the top surface of the first pin is substantially the same as the roughness of the bottom surface of the first pin.

7. The packaging structure of claim 2, wherein the molding interposer includes a third pin that is inclined upward relative to the first surface in the cross-sectional view, wherein the third direction is different from the first direction and the second direction.

8. The packaging structure according to claim 3, further comprising an electronic component encapsulated by the first encapsulation body and a plurality of conductive pillars disposed on the electronic component, wherein the inclination direction of the first conductive pillar among the plurality of conductive pillars relative to the top surface of the first encapsulation body is substantially the same as the inclination direction of the second conductive pillar among the plurality of conductive pillars relative to the top surface of the first encapsulation body.

9. The packaging structure according to claim 1, wherein the molded interlayer includes a second encapsulation body encapsulating the first pin and the second pin, wherein the top surface of the second encapsulation body is substantially aligned with the top surface of the first pin and the second pin, and the bottom surface of the second encapsulation body is substantially aligned with the bottom surface of the first pin and the second pin.

10. The encapsulation structure of claim 9, wherein the second capsule includes a first filler and a second filler, the first filler having a top surface substantially aligned with the top surface of the second capsule, and the second filler having a bottom surface substantially aligned with the bottom surface of the second capsule.

11. The encapsulation structure of claim 10, wherein the second capsule further comprises a third filler having a side surface substantially aligned with a side surface of the second capsule.

12. A packaging structure comprising: The first connector, which is enclosed by a first encapsulating body, has an elliptical top surface; and A redistribution layer (RDL) is disposed on the first pin, wherein the RDL includes a first via and a dielectric layer partially covering the first via. The first through hole is disposed on the first pin and contacts the top surface of the first pin, and the first through hole exposes a portion of the top surface of the first pin.

13. The packaging structure of claim 12, further comprising a second pin encapsulated by the first encapsulation body, wherein the RDL includes a second via disposed on the top surface of the second pin and contacting the top surface of the second pin, wherein a first distance between the left edge of the first pin and the left edge of the first via is different from a second distance between the left edge of the second pin and the left edge of the second via.

14. The packaging structure of claim 13, wherein the inclination of the first pin relative to the bottom surface of the first capsule in a cross-sectional view is greater than the inclination of the second pin, and wherein the first distance is greater than the second distance.

15. The packaging structure of claim 13, wherein the first pin includes a conductive pin and the second pin includes a thermally conductive pin.

16. The packaging structure of claim 15, wherein the first encapsulation encapsulates the conductive pin and the thermally conductive pin to form an interlayer.

17. A packaging structure comprising: The first rework layer (RDL) includes a first dielectric layer and a first via partially covered by the first dielectric layer; The second rework layer (RDL) includes a second dielectric layer and a second via partially covered by the second dielectric layer; An intermediary layer, disposed between the first RDL and the second RDL, the intermediary layer including a first pin; and An encapsulating body that encapsulates the intermediate layer and has a top surface and a bottom surface opposite the top surface. The top surface of the first connector is substantially aligned with the top surface of the capsule, and the bottom surface of the first connector is substantially aligned with the bottom surface of the capsule, wherein the first through hole and the second through hole gradually narrow toward the interlayer.

18. The packaging structure of claim 17, wherein the interposer further comprises a plurality of thermally conductive pins surrounding the first pin, wherein the first pin is a conductive pin.

19. The packaging structure of claim 17, wherein the center of the first via is not aligned with the center of the first pin in a top view.

20. The packaging structure of claim 17, wherein the top surface of the first pin is polygonal in a top view.

Images