Selection device and selection method

Abstract

A selection device (100) connected to a debugger (e.g., a host (400)) for performing debugging of a plurality of processors (e.g., targets (210), (220), and (230)) and multipoint-connected to the plurality of processors, the selection device (100) having: a first holding circuit (e.g., a first register (110)) that holds first identification information indicating any one of the plurality of processors; and a selection circuit (120) that outputs, among one or more pieces of data output from one or more of the plurality of processors, only data output from the one processor indicated by the first identification information to the debugger.

Description

Technical Field

[0001] This disclosure relates to a selection device and a selection method. Background Technology

[0002] Previously, systems existed for debugging multiple processors. Patent Document 1 discloses a system for debugging multiple cores of a multiprocessor using a debugger. The multiple cores disclosed in Patent Document 1 are connected in a ring.

[0003] (Existing patent literature) (Patent Documents) Patent Document 1: Japanese Patent Application Publication No. 2018-88048 Summary of the Invention

[0004] The problem that the invention aims to solve There are situations where a debugger used to debug multiple processors configured on the same chip is connected to those processors in a multi-drop configuration. Even in this configuration, it is expected that the debugger can properly debug multiple processors.

[0005] This disclosure provides a selection device, etc., that can reduce the possibility that the debugger cannot properly perform debugging of the processor.

[0006] Methods for solving problems One aspect of this disclosure relates to a selection device connected to a debugger and a plurality of processors, the debugger being configured to perform debugging on the plurality of processors and being connected to the plurality of processors at multiple points, the selection device comprising: a first holding circuit for holding first identification information representing any one of the plurality of processors; and a selection circuit for outputting only the data output from the processor represented by the first identification information to the debugger from among more than one data output from one or more of the plurality of processors.

[0007] One aspect of this disclosure relates to a selection method performed by a selection device connected to a debugger and a plurality of processors. The debugger is configured to perform debugging on the plurality of processors and is connected to the plurality of processors at multiple points. In the selection method, first identification information representing any one of the plurality of processors is maintained, and from more than one data output from one or more of the plurality of processors, only the data output from the processor represented by the first identification information is output to the debugger.

[0008] The effects of the invention The selection device, etc., involved in one aspect of this disclosure can reduce the possibility that the debugger may not properly perform debugging of the processor. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating the configuration of the debugging system involved in the implementation method.

[0010] Figure 2 This is a diagram illustrating the debugging interface of the host machine involved in the implementation method.

[0011] Figure 3 This is a diagram used to illustrate the debugging interface of the target involved in the implementation method.

[0012] Figure 4 This is a timing diagram illustrating the first example of the processing steps of the debugging system involved in the implementation method.

[0013] Figure 5 This is a timing diagram illustrating a second example of the processing steps of the debugging system involved in the implementation method.

[0014] Figure 6 This is a flowchart illustrating a specific example of the processing steps of the selection device involved in the implementation method.

[0015] Figure 7 This is a flowchart illustrating the selection methods involved in the implementation. Detailed Implementation

[0016] (How this disclosure came about) In recent years, with the development of wearable devices, the requirements for miniaturization and thinning of devices have been increasing. In addition, the systems are also trending towards greater complexity. In recent years, there has been a growing number of LSIs (Large Scale Integration) on devices, which incorporate multiple CPUs (Central Processing Units) and other processors.

[0017] This type of processor has an interface (access port) for debugging. As an example of such an interface (also known as a debug interface), there is JTAG (Joint Test Action Group). Additionally, as another example of a debug interface, there is SWD (Serial Wire Debug).

[0018] SWD is a serial communication interface. Compared to JTAG, it has fewer terminals but offers the same debugging capabilities. Because SWD has fewer terminals than JTAG, it is expected to achieve a smaller footprint (i.e., miniaturization) compared to LSIs using JTAG.

[0019] As a connection method for SWD, a multi-point connection (multi-point connection method) is specified for connecting to multiple processors. This allows for debugging of multiple processors within the LSI without increasing the number of LSI terminals.

[0020] In SWD's multi-point interconnection, the processor design and verification are relatively easy, and there is also a great deal of freedom in terms of memory mapping configuration and debugging connection control of each core.

[0021] However, in the SWD multi-point connection specification, there is no avoidance method in the event of a race condition, which refers to a state in which multiple processors simultaneously return responses due to unexpected faults caused by noise (such as anomalies in the debug path).

[0022] Therefore, the inventors of this application have completed the invention of this application.

[0023] Specifically, according to this disclosure, even with multi-point connections using SWD within the LSI, it is relatively easy to establish a connection (debug access) between any processor (specifically, processor core) in a multiprocessor system and the debugger, even in the event of a fault. Furthermore, for example, according to this disclosure, an anomaly monitoring function for detecting faulty processors can be implemented.

[0024] In addition, the faults referred to herein include, for example, unexpected faults caused by noise, insufficient output protection when the power is cut off, two or more processors being assigned the same identifier, the presence of processors that do not support multi-point connections, the presence of noisy wiring in the processor wiring, or the presence of processors performing other unexpected actions.

[0025] The embodiments will now be described in detail with reference to the accompanying drawings.

[0026] Furthermore, the embodiments described below are all general or specific examples. The numerical values, shapes, materials, constituent elements, the arrangement and connection methods of constituent elements, steps, and the order of steps shown in the following embodiments are all examples and are not intended to limit this disclosure. In addition, constituent elements in the following embodiments that are not described in the independent technical solutions of this disclosure are described as arbitrary constituent elements.

[0027] Furthermore, ordinal numbers such as "first" and "second," unless otherwise specified, do not indicate the quantity or order of constituent elements; they are merely used to distinguish them in order to avoid confusion among constituent elements of the same kind.

[0028] (Implementation Method) [constitute] Figure 1This is a block diagram illustrating the configuration of the debugging system 10 according to the implementation method.

[0029] Debugging system 10 is a system used to perform debugging on multiple processors (specifically, debugging the programs executed by each of the multiple processor cores). In this embodiment, debugging system 10 includes a host 400 and an LSI 300. The host 400 performs debugging on n targets provided by the LSI 300. Furthermore, n can be 2 or more. In this embodiment, the LSI 300 has three targets: targets 210, 220, and 230. The host 400 performs debugging on targets 210, 220, and 230 provided by the LSI 300.

[0030] The host computer 400 is a computer used for debugging. The host computer 400 is implemented, for example, by non-volatile memory storing programs, volatile memory serving as temporary storage for executing programs, and a processor for executing programs. Furthermore, the host computer 400 has a debugging interface for performing debugging of targets 210, 220, and 230 of the LSI 300.

[0031] Figure 2 This diagram illustrates the debugging interface provided by the host 400 involved in the implementation method.

[0032] For example, host 400 has a debugging interface that has a function for transmitting clock signals ( Figure 2 The CLK shown is used to implement a port for synchronization with targets 210, 220, and 230, and for transmitting data used for debugging. Figure 2 The port shown is the DIO port. The debug interface of the host 400 is serially connected to, for example, the port 310 of the LSI 300. Thus, serial communication is performed between the host 400 and the LSI 300.

[0033] Additionally, Host 400 is an example of a debugger.

[0034] Furthermore, although not illustrated, the clock generator can be implemented using any of its constituent elements.

[0035] LSI300 is an LSI that includes multiple processors that can be the targets of debugging performed by host 400. LSI300 is implemented, for example, by a single chip (i.e., a semiconductor substrate). LSI300 includes a selection device 100, targets 210, 220, and 230, and a port section 310. The selection device 100, targets 210, 220, and 230, and port section 310 are disposed on the same chip. That is, for example, the selection circuit 120 and targets 210, 220, and 230 are disposed on the same chip.

[0036] Targets 210, 220, and 230 are processors (specifically, CPU cores) that are the targets of debugging performed by host 400. Targets 210, 220, and 230 each have a debugging interface for host 400 to debug targets 210, 220, and 230.

[0037] Figure 3 This is a diagram illustrating the debugging interface provided by the target 200 involved in the implementation method.

[0038] In addition, targets 210, 220 and 230 have the same characteristics as... Figure 3 The target 200 shown has the same configuration as the debugging interface. Hereinafter, descriptions common to targets 210, 220, and 230 will be used as examples of target 200.

[0039] Target 200 has a debug interface, which includes a port for transmitting clock signals to achieve synchronization with host 400 and a debug access port, which includes data from host 400. Figure 3 The DI input port shown represents the data to be sent to the host 400. Figure 3 The port of DO shown, and the output enable signal ( Figure 3 The port of EN shown. The data and enable signal output from target 200 are output to host 400 via selection device 100 and port unit 310.

[0040] Host 400 has multiple connections to targets 210, 220, and 230. Therefore, data output from host 400 is input to targets 210, 220, and 230 respectively. For example, the data output by host 400 includes a target ID representing any one of targets 210, 220, and 230. Targets 210, 220, and 230 each pre-store a target ID representing itself. Based on the acquired target ID, if the target represented by that target ID is itself, data and an enable signal corresponding to the acquired data are output to host 400; if the target represented by that target ID is not itself, no data or enable signal is output to host 400.

[0041] By performing this process, host 400, for example, when debugging any of targets 210, 220, and 230, establishes one-to-one communication with a target and performs debugging by outputting data containing the target ID of the target to be debugged.

[0042] Port 310 is a port serially connected to host 400. Port 310 includes, for example, two ports: one for transmitting clock signals and one for transmitting data. Data and enable signals output from target 200 are output to host 400 via the data transmission port of port 310, for example. Specifically, only when host 400 is not using a data line, data input to selection circuit 120 from targets 210, 220, or 230 is output to host 400 via the data communication port by switching a switch used to avoid input-output conflicts in host 400 using an enable signal.

[0043] Selection device 100 is an electronic circuit connected to host 400 and targets 210, 220, and 230. Specifically, selection device 100 is connected to targets 210, 220, and 230 respectively via independent buses, and outputs data and enable signals from targets 210, 220, and 230 to host 400 via port 310. Selection device 100 includes a first register 110 and selection circuit 120.

[0044] The first register 110 is a register that holds (stores) the target ID (also called the first target ID) representing any one of targets 210, 220, and 230. The first register 110 is an example of a first holding circuit. The first target ID is an example of first identification information. The first register 110 is implemented, for example, by a latch circuit, but can also be implemented by any configuration such as a flip-flop circuit.

[0045] For example, the first register 110 holds the target ID contained in the data output from the host 400 to targets 210, 220, and 230. For example, when the host 400 begins debugging any of targets 210, 220, and 230, it first outputs the target ID and a request (also called a debug request). For example, the first register 110 latches the target ID output at this time. Additionally, the request is an example of the data output by the host 400.

[0046] Alternatively, the LSI300 may also have a port for receiving the target ID output to the first register 110. This port is connected, for example, to the first register 110 and an external computer. The external computer, for example, outputs the target ID, thereby causing the first register 110 to retain the target ID. Thus, the first register 110 can also retain the target ID. Furthermore, this external computer may or may not be the host computer 400.

[0047] Selection circuit 120 is an electronic circuit that outputs data from targets 210, 220, and 230 to host 400. For example, selection circuit 120 outputs acknowledgment (ACK) signals and enable signals from targets 210, 220, and 230 as responses to requests to host 400. The acknowledgment and enable signals are examples of data output by targets 210, 220, and 230.

[0048] As described above, typically, targets 210, 220, and 230 will output a response signal to host 400 if the target ID represents the target itself; otherwise, they will not output a response signal to host 400. In other words, even if a request is sent to targets 210, 220, and 230, typically only one of targets 210, 220, and 230 will output a response signal.

[0049] Here, it is assumed that at least one of targets 210, 220, and 230 has malfunctioned. Examples of malfunctions include unexpected failures caused by noise, etc. Examples of malfunctions include two or more targets being incorrectly assigned the same target ID. Examples of malfunctions include at least one of targets 210, 220, and 230 experiencing a fixed error in its output value when power is cut off. Examples of malfunctions include at least one of targets 210, 220, and 230 containing a target that operates according to a standard that does not support multi-point connections. Examples of malfunctions include at least one of targets 210, 220, and 230 experiencing an unexpected failure. When these malfunctions occur, the unexpected target—that is, a target that is not represented by the target ID—may also output a response signal to the host 400. In this case, there is a possibility that the host 400 cannot perform proper debugging.

[0050] Therefore, for example, in the event of a contention situation where two or more targets 200 simultaneously output response signals in response to a debug request output by host 400 for subsequent debugging, the selection circuit 120, based on the target ID, outputs only the response signal obtained from the target 200 represented by the target ID to host 400. Thus, among more than one data (e.g., response signal and enable signal) output from one or more targets 210, 220, and 230, the selection circuit 120 outputs only the data output from the target represented by the target ID to host 400.

[0051] In addition, the selection device 100 may further include a detection circuit 130 and a second register 140.

[0052] The detection circuit 130 is an electronic circuit that detects a contention state in which data is simultaneously output from multiple targets. Specifically, when a contention state occurs because data is output from two or more targets 200 among targets 210, 220 and 230, the detection circuit 130 causes the second register 140 to hold contention information related to the contention state.

[0053] The second register 140 is a register that holds (stores) contention information. The second register 140 can be implemented, for example, by a latch circuit, but it can also be implemented by any configuration such as a flip-flop circuit. The second register 140 is an example of a second holding circuit.

[0054] Competition information can be, for example, the enable signals output by two or more targets. For instance, detection circuit 130 causes second register 140 to hold the enable signals output by targets 210, 220, and 230.

[0055] Furthermore, for example, the contention information is a target ID (second target ID) representing two or more targets. The second target ID is an example of second identification information. For example, the detection circuit 130 causes the second register 140 to hold the target ID representing the target among targets 210, 220, and 230 that outputs data to the selection circuit 120. For example, the selection device 100 may pre-store the target IDs of targets 210, 220, and 230 in a memory (not shown), etc., and the detection circuit 130 uses this memory to determine the target ID representing the data output source when data is output from a target, and causes the second register 140 to store the determined target ID as contention information.

[0056] Of course, the detection circuit 130 can also enable the second register 140 to store the target IDs of two or more targets and the enable signals output by each of the two or more targets.

[0057] Furthermore, the host 400 and the second register 140 can also be connected in a communicative manner. Specifically, the second register 140 can be configured to allow the host 400 to access contention information. For example, the host 400 communicates with the second register 140 via the bus used by components such as the CPU included in the LSI300 when accessing the second register 140. The contention information stored in the second register 140 can be configured in an address space or memory space accessible only to the host 400. Alternatively, the contention information can be configured in an address space or memory space accessible only to the host 400, or in an address space or memory space accessible to devices other than the host 400.

[0058] [Processing Steps] Next, the processing steps of the debugging system 10 according to the embodiment will be described. In addition, in the first and second examples described below, the processing steps when debugging target 210 of targets 210, 220 and 230 are described.

[0059] <First example> Figure 4 This is a timing diagram illustrating a first example of the processing steps of the debugging system 10 according to the embodiment. The first example is the processing steps of the debugging system 10 when no race condition occurs.

[0060] First, host 400 outputs the target ID (specifically, the target ID representing target 210) and the request (debugging request) to LSI300 (S110). Thus, the target ID and the request are output to each of targets 210, 220, and 230.

[0061] As an example of how the host 400 connects to a target (also known as a debug connection) to perform debugging on the target, examples include a reset vector capture connection and an attachment connection.

[0062] A reset vector capture connection refers to a connection method where the host 400 controls the timing of the reset release and pauses execution during reset vector instruction fetching. Reset vector capture connections are used, for example, in situations where debugging is desired to begin from the start phase (boot phase) of the target program.

[0063] An additional connection refers to a method of connection between the host 400 and the target while the target is already executing a program. In this connection method, for example, the program being executed by the target will not stop until an interrupt operation is performed. Additionally, in an additional connection, the host 400 can also interrupt the connection during debugging.

[0064] In the debugging system 10, either the reset vector capture connection or the additional connection method can be used. In the case of a reset vector capture connection, for example, after power-on (power-on reset), before the reset is released and the startup sequence begins, the debugging connection (i.e., outputting the target ID and request) is started.

[0065] When the target ID and request are output in step S110, the selection device 100 retains the output target ID (S120).

[0066] In addition, target 210 outputs a response signal in response to the request (S130). Specifically, target 210 outputs a response signal and an enable signal.

[0067] Furthermore, in this example, targets 220 and 230 do not output response signals.

[0068] The selection device 100 outputs the response signal obtained from the target 210 as is (S140). As a result, the host 400 obtains the response signal from the target 210, establishes a debugging connection between the host 400 and the target 210, and begins debugging the target 210 (S150).

[0069] Furthermore, in the communication between the host 400 and the target 210 during debugging after step S150, the host 400 may or may not output the target ID. Moreover, in this communication, if the target ID is output from the host 400, the selection device 100 may not retain the target ID. Furthermore, in this communication, the selection device 100 may or may not determine whether to output debugging data to the host 400 based on the target ID. For example, if debugging data is obtained from the target represented by the target ID, the selection device 100 outputs the data to the host 400; if debugging data is obtained from a target other than the target represented by the target ID, the selection device 100 may not output the data to the host 400.

[0070] <Second Example> Figure 5 This is a timing diagram illustrating a second example of the processing steps of the debugging system 10 according to the embodiment. The second example is the processing steps of the debugging system 10 under a race condition. In addition, when describing each step in the second example, the same symbols are used for cases where the processing is substantially the same as that in the first example, and the description is simplified or omitted.

[0071] First, host 400 outputs the target ID of target 210 and the request to LSI300 (S110).

[0072] Next, the selection device 100 retains the output target ID (S120).

[0073] In addition, target 210 outputs a response signal in response to the request (S130).

[0074] In this example, it is assumed that target 230 has encountered some kind of anomaly and outputs a response signal (specifically, a response signal and an enable signal) as a response to the request (S210). In this case, selection device 100 will simultaneously obtain response signals from both target 210 and target 230.

[0075] In this case, among the two acquired response signals, the selection device 100, based on the target ID held in step S120, only outputs the response signal acquired from the target represented by that target ID to the host 400 (S220). Specifically, the selection device 100 only outputs the response signal and the enable signal acquired from the target 210 to the host 400.

[0076] Therefore, the host 400 only receives the response signal from the target 210, establishes a debugging connection between the host 400 and the target 210, and begins to debug the target 210 (S150).

[0077] Furthermore, the selection device 100 maintains the contention information (S230). For example, the detection circuit 130 causes the second register 140 to maintain the two enable signals output together with the two response signals as contention information.

[0078] Additionally, for example, if the selection device 100 receives only one response signal, and the target that outputs the response signal is not the target represented by the target ID, the response signal can be output to the host 400, or it can be left unoutput. Furthermore, at this time, the second register 140 or the like can hold the target ID representing the target and / or the enable signal output by the target that output the response signal.

[0079] <Processing steps of the selection device> Figure 6 This is a flowchart illustrating a specific example of the processing steps of the selection device 100 involved in the implementation method.

[0080] First, the selection device 100 retains the target ID output by the host 400 (S310).

[0081] Next, the selection device 100 obtains a response signal from at least one of the targets 210, 220 and 230 (S320).

[0082] Next, the selection device 100 determines whether the number of response signals acquired in step S320 is more than two (S330).

[0083] If it is determined that the number of acquired response signals is not more than two ("No" in S330), that is, if the number of acquired response signals is one, the selection device 100 outputs the acquired response signal to the host 400 (S340).

[0084] On the other hand, if it is determined that the number of acquired response signals is two or more ("Yes" in S330), that is, if it is determined that a competition state has occurred, the selection device 100, based on the target ID held in step S310, will only output the response signal of the target output represented by the target ID to the host 400 from the two or more acquired response signals (S350).

[0085] In addition, the selection device 100 may, for example, retain two or more enable signals acquired together with two or more response signals as contention information (S360).

[0086] Alternatively, step S330 may be omitted. In this case, for example, after step S320, the selection device 100 determines whether the target of the acquired response signal is the target represented by the target ID. For example, if the target is the target represented by the target ID, the selection device 100 forwards the acquired response signal to the host 400; if the target is not the target represented by the target ID, the selection device 100 does not forward the acquired response signal to the host 400.

[0087] <Representative Example> Figure 7 This is a flowchart illustrating the selection methods involved in the implementation. Specifically, Figure 7 This is a flowchart illustrating the basic processing steps of the selection method performed by the selection device 100. For example, the selection device 100 includes circuitry and registers, and the circuitry uses the registers to perform the following processing.

[0088] First, the selection device 100 holds identification information (first identification information) representing any one of the plurality of processors (S10). Specifically, the selection device 100 includes a first holding circuit, and the first holding circuit holds (stores) the first identification information.

[0089] Multiple processors, such as targets 210, 220, and 230 described above, are included. The first holding circuit, such as the first register 110 described above, is also included. Furthermore, the first identification information, such as the first target ID described above, is also included.

[0090] Next, the selection device 100 outputs only the data output from the processor represented by the first identification information to the debugger from among the more than one data output from one or more processors among a plurality of processors (S20).

[0091] The debugger is, for example, the host 400 mentioned above.

[0092] [Effects, etc.] As described above, the selection device 100 involved in the embodiment is a selection device connected to the host 400 and multiple targets 200. The host 400 is used to perform debugging on multiple targets 200 and has multiple connections with multiple targets 200. The selection device 100 includes: a first register 110, which holds a target ID (first target ID) representing any one of the multiple targets 200; and a selection circuit 120, which outputs only the response signal from the target 200 represented by the target ID to the host 400 from among more than one response signal output from one or more targets 200.

[0093] For example, when host 400 is debugging multiple targets 200, it establishes one-to-one communication with one of the targets 200. In this case, for example, to establish communication with the target 200 to be debugged, host 400 outputs (sends) the target ID representing that target 200 to that target 200. Here, in the case of multiple connections between host 400 and multiple targets 200, the target ID output by host 400 is obtained by each of the multiple targets 200. Based on the target ID, if the target ID represents itself, the multiple targets 200 output an acknowledgment signal to host 400; otherwise, they do not output an acknowledgment signal to host 400. Thus, one-to-one communication is established between host 400 and one target 200. In this system, which includes a selection device 100, multiple targets 200, and a host 400, if an unexpected fault occurs due to noise, or if two or more targets 200 are incorrectly assigned the same identifier, or if a fixed error in the output value occurs during power-off, or if one of the targets 200 operates according to a standard that does not support multi-point connection, or if a target 200 experiences an unexpected fault, the unexpected target 200 may also output a response signal to the host 400. In such cases, there is a possibility that the host 400 may not be able to perform debugging properly. Therefore, for example, if two or more targets 200 simultaneously output response signals in response to a debugging request output by the host 400 for subsequent debugging, resulting in a contention, the selection circuit 120, based on the target ID, outputs only the response signal obtained from the target 200 represented by the target ID to the host 400. This reduces the possibility that the host 400 may be unable to perform debugging due to receiving multiple response signals. Therefore, by selecting the device 100, the host 400 can easily and properly obtain the response signal from the target 200 that is being debugged, thereby reducing the possibility that the host 400 may not be able to properly perform debugging on the target 200.

[0094] In addition, for example, the selection circuit 120 and multiple targets 200 are located on the same chip.

[0095] Accordingly, the LSI300, which carries multiple targets, can be miniaturized, and the possibility that the host cannot properly perform debugging of the target 200 can be reduced.

[0096] In particular, while existing technologies such as wiring detection mechanisms can be used to establish debugging connections and detect faults when multiple connections are made externally to the LSI300, these mechanisms cannot be used when multiple connections are made internally to the LSI. Therefore, when multiple connections are made internally to the LSI, the host 400 may be unable to establish debugging connections with all targets 200 in the event of an anomaly (fault). Furthermore, it is difficult to determine the cause of the fault.

[0097] On the other hand, by using the selection device 100, even if multiple connections are made within the LSI 300, i.e., the selection circuit 120 and multiple targets 200 are located on the same chip, the debugger can easily and properly obtain the response signal from the target being debugged. Therefore, by using the selection device 100, even if the selection circuit 120 and multiple targets 200 are located on the same chip, the possibility that the host 400 cannot properly perform debugging of the target 200 can be reduced. Therefore, the selection device 100 is particularly useful for this structure where the selection circuit 120 and multiple targets are located on the same chip.

[0098] In addition, for example, the first register 110 holds the target ID contained in the data output from the host 400 to the multiple targets 200.

[0099] For example, when host 400 needs to perform debugging, it outputs debugging requests and target IDs to multiple targets 200. First register 110, for example, holds the target IDs that are being output at this time.

[0100] Accordingly, the selection device 100 can easily obtain the target ID.

[0101] In addition, for example, the selection device 100 has a port for receiving the target ID output to the first register 110.

[0102] Accordingly, the selection device 100 can easily obtain the target ID.

[0103] Furthermore, for example, the selection device 100 includes a second register 140 and a detection circuit 130. In the event of a contention state where response signals are output from two or more of the plurality of targets 200, the detection circuit 130 causes the second register 140 to retain contention information related to the contention state.

[0104] Therefore, in the event of a race condition, the cause of the race condition can be easily determined by analyzing the race information stored in the second register 140.

[0105] In addition, for example, competition information is the enable signal output by two or more targets 200 respectively.

[0106] Therefore, it is easy to identify two or more objectives 200 that trigger a competitive state.

[0107] In addition, for example, contention information is a second target ID representing more than two processors.

[0108] Therefore, it is easy to identify two or more objectives 200 that trigger a competitive state.

[0109] (Other implementation methods) As described above, the embodiments have been presented as examples of the technology involved in this disclosure. However, the technology involved in this disclosure is not limited thereto, and is also applicable to embodiments with appropriate modifications, substitutions, additions, omissions, etc. For example, the following variations are also included in one embodiment of this disclosure.

[0110] For example, the selection device 100 may not have the detection circuit 130.

[0111] Alternatively, for example, the selection device 100 may not have a second register 140.

[0112] Furthermore, for example, the LSI300 can have two or more target (processors).

[0113] Furthermore, for example, the LSI300 and host 400 can also be connected to multiple points outside the LSI300. Therefore, the LSI300 can also have the same number of ports connected to host 400 as the target number of the LSI300.

[0114] In addition, for example, the selection device 100 and multiple processors may be located on the same chip, but the selection device 100 and multiple processors may also be located on different chips.

[0115] Furthermore, the first holding circuit and the second holding circuit can be implemented by registers, for example, as long as they have the function of storing information, they can also be implemented by memory such as RAM (Random Access Memory).

[0116] Furthermore, for example, some or all of the functions of the selection device 100 involved in the above embodiments are typically implemented by an LSI 300 as an integrated circuit. These can be integrated into a single chip, or a portion or all of them can be integrated into a single chip. Moreover, integrated circuitry is not limited to LSIs; it can also be implemented using dedicated circuits or general-purpose processors. A post-programmable FPGA (Field Programmable Gate Array) or a reconfigurable processor capable of reconfiguring the connections or settings of the circuit cells within the LSI can also be used.

[0117] Furthermore, if an integrated circuit technology that replaces LSI has emerged due to advancements in semiconductor technology or other derived technologies, then such technology can certainly be used to integrate the various components included in the selection device 100.

[0118] Furthermore, for example, in the above embodiments, the processes performed by the specific processing unit can be executed by other processing units. Additionally, the order of multiple processes can be changed, and multiple processes can be executed in parallel.

[0119] Furthermore, this disclosure also includes methods obtained by applying various modifications to the embodiments that can be conceived by those skilled in the art, as well as methods implemented by arbitrarily combining the constituent elements and functions of the various embodiments without departing from the spirit of this disclosure.

[0120] (Postscript) The following describes the technology obtained from the disclosure of this specification and explains the effects obtained from the illustrated technology.

[0121] (Technology 1) A selection device connected to a debugger and a plurality of processors, the debugger being configured to perform debugging on the plurality of processors and being connected to the plurality of processors at multiple points, the selection device comprising: a first holding circuit for holding first identification information representing any one of the plurality of processors; and a selection circuit for outputting only the data output from the processor represented by the first identification information to the debugger from among more than one data output from one or more of the plurality of processors.

[0122] The selection device is, for example, the selection device 100 described above. The first holding circuit is, for example, the first register 110 described above. The selection circuit is, for example, the selection circuit 120 described above. The debugger is, for example, the host 400 described above. The multiple processors are, for example, the targets 210, 220, and 230 described above. The first identification information is, for example, the target ID (first target ID) described above, which indicates the processor that is the target of the debugger.

[0123] This reduces the likelihood that the debugger will be unable to perform debugging due to receiving multiple response signals. Consequently, it allows the debugger to easily and appropriately obtain data from the processor being debugged, thus reducing the possibility that the debugger will be unable to properly perform debugging of the processor.

[0124] (Technology 2) The selection device as described in Technology 1, wherein the selection circuit and the plurality of processors are disposed on the same chip.

[0125] Accordingly, it is possible to miniaturize electronic circuits equipped with multiple processors (such as the LSI300 mentioned above) and reduce the possibility that the debugger may not be able to properly perform debugging of the processor.

[0126] (Technology 3) The selection device as described in Technology 1 or 2, wherein the first holding circuit holds the first identification information contained in the data output from the debugger to the plurality of processors.

[0127] Accordingly, the selection device can easily obtain the first identification information.

[0128] (Technology 4) The selection device according to any one of Technologies 1 to 3, the selection device having a port for receiving the first identification information output to the first holding circuit.

[0129] Accordingly, the selection device can easily obtain the first identification information.

[0130] (Technology 5) The selection device according to any one of Technologies 1 to 4, the selection device comprising: a second holding circuit; and a detection circuit that, in the event of a contention state where two or more of the plurality of processors output data, causes the second holding circuit to hold contention information related to the contention state.

[0131] The second holding circuit is, for example, the second register 140 described above. The detection circuit is, for example, the detection circuit 130 described above.

[0132] Therefore, in the event of a race condition, a computer such as the host 400 described above can easily analyze the cause of the race condition by analyzing the race information held in the second holding circuit.

[0133] (Technology 6) The selection device as described in Technology 5, wherein the competition information is an enable signal output by each of the two or more processors.

[0134] Therefore, it is possible to easily identify two or more processors that trigger a race condition from the race information.

[0135] (Technology 7) The selection device as described in Technology 5 or 6, wherein the competition information is second identification information representing the two or more processors.

[0136] The second identification information is the aforementioned target ID (second target ID) representing the two or more processors that output data.

[0137] Therefore, it is possible to easily identify two or more processors that trigger a race condition from the race information.

[0138] (Technical 8) The selection device as claimed in any one of claims 5 to 7, wherein the debugger is connected to the second holding circuit in a communicable manner.

[0139] Accordingly, the debugger can read the contention information held in the second holding circuit.

[0140] (Technology 9) A selection method performed by a selection device connected to a debugger and a plurality of processors, the debugger being configured to perform debugging on the plurality of processors and being connected to the plurality of processors at multiple points, wherein in the selection method, first identification information representing any one of the plurality of processors is maintained, and among more than one data output from one or more of the plurality of processors, only the data output from the processor represented by the first identification information is output to the debugger.

[0141] Accordingly, the same effect as the selection device described in Technique 1 can be obtained.

[0142] Furthermore, these general or specific methods can be implemented by non-transitory recording media such as systems, methods, integrated circuits, computer programs, or computer-readable CD-ROMs, or by any combination of systems, methods, integrated circuits, computer programs, and recording media.

[0143] Industrial availability This disclosure can be applied to LSIs and the like that are equipped with multiple processors that are to be debugged.

[0144] Symbol Explanation 10. Debugging System 100 Selection Device 110 First Register 120 Selection Circuit 130 Detection Circuit 140 Second Register Targets: 200, 210, 220, 230 300 LSI 310 port section 400 host

Claims

1. A selection device connected to a debugger and a plurality of processors, the debugger being configured to perform debugging on the plurality of processors and having multiple connections to the plurality of processors. The selection device includes: A first holding circuit holds first identification information representing any one of the plurality of processors; and The selection circuit, from among more than one data output from one or more processors among the plurality of processors, outputs only the data output from the processor represented by the first identification information to the debugger.

2. The selection device as claimed in claim 1, The selection circuit and the plurality of processors are located on the same chip.

3. The selection device as described in claim 1, The first holding circuit holds the first identification information contained in the data output from the debugger to the plurality of processors.

4. The selection device as described in claim 1, The selection device has a port for receiving the first identification information output to the first holding circuit.

5. The selection device as claimed in claim 1, The selection device includes: The second holding circuit; and The detection circuit, in the event of a contention state where two or more of the plurality of processors output data, causes the second holding circuit to hold contention information related to the contention state.

6. The selection device as claimed in claim 5, The competition information refers to the enable signals output by each of the two or more processors.

7. The selection device as claimed in claim 5, The competition information is a second identification information representing the two or more processors.

8. The selection device as described in claim 5, The debugger is connected to the second holding circuit in a communicative manner.

9. A selection method, performed by a selection device connected to a debugger and a plurality of processors, the debugger being configured to perform debugging on the plurality of processors and having multiple connections to the plurality of processors. In the selection method, Maintain the first identification information representing any one of the plurality of processors. Of the more than one data output from one or more of the plurality of processors, only the data output from the processor represented by the first identification information is output to the debugger.

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