Pixel driving circuit and driving method thereof, display device

Abstract

A pixel driving circuit, a driving method thereof and a display device, wherein the pixel driving circuit comprises a driving sub-circuit, a first control sub-circuit and a second control sub-circuit. The driving sub-circuit is configured to provide a driving signal to a third node (N3) under the control of signals of a first node (N1) and a second node (N2). The first control sub-circuit can comprise a writing sub-circuit, a connecting sub-circuit, a storage sub-circuit and a voltage dividing sub-circuit. The writing sub-circuit is configured to provide a signal of a data signal terminal (Data) to a fifth node (N5) under the control of a signal of a first scan signal terminal (Gate1); the connecting sub-circuit is configured to connect the first node (N1) and the fifth node (N5) under the control of a signal of a second scan signal terminal (Gate2); the storage sub-circuit is configured to store a voltage difference between signals of the third node (N3) and the fifth node (N5); and the voltage dividing sub-circuit is configured to store a voltage difference between signals of the third node (N3), and a first signal terminal (VIN1). The second control sub-circuit is configured to provide a signal of a first power supply terminal (ELVDD) to the second node (N2) and connect the third node (N3) and a fourth node (N4) under the control of signals of a first light emitting signal terminal (EM1) and a second light emitting signal terminal (EM2). Through cooperation of the first control sub-circuit and the second control sub-circuit, a compensation process of the pixel driving circuit can be independent of a data writing process.

Description

Pixel driving circuit and its driving method, display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a pixel driving circuit and its driving method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices that offer advantages such as self-illumination, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous development of display technology, display devices using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a pixel driving circuit and driving method thereof, as well as a display device.

[0005] In a first aspect, this disclosure provides a pixel driving circuit, including: a driving sub-circuit, a first control sub-circuit, and a second control sub-circuit;

[0006] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node.

[0007] The first control sub-circuit is electrically connected to the first scan signal terminal, the second scan signal terminal, the data signal terminal, the first signal terminal, the first node, and the third node, respectively, and is configured to adjust the signals of the first node and the third node through the signals of the data signal terminal and the first signal terminal under the control of the signals of the first scan signal terminal and the second scan signal terminal.

[0008] The second control sub-circuit is electrically connected to the first light-emitting signal terminal, the second light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fourth node, respectively. It is configured to provide the signal from the first power supply terminal to the second node under the control of the signals from the first light-emitting signal terminal and the second light-emitting signal terminal, and to connect the third node and the fourth node.

[0009] In an exemplary embodiment, the first control sub-circuit includes: a write sub-circuit, a connection sub-circuit, a storage sub-circuit, and a voltage divider sub-circuit;

[0010] The writing sub-circuit is electrically connected to the first scan signal terminal, the data signal terminal, and the fifth node, respectively, and is configured to provide the data signal terminal to the fifth node under the control of the signal from the first scan signal terminal.

[0011] The connecting sub-circuit is electrically connected to the second scanning signal terminal, the first node, and the fifth node, respectively, and is configured to connect the first node and the fifth node under the control of the signal at the second scanning signal terminal;

[0012] The storage sub-circuit is electrically connected to the third node and the fifth node respectively, and is configured to store the voltage difference between the signals of the third node and the fifth node.

[0013] The voltage divider circuit is electrically connected to the third node and the first signal terminal respectively, and is configured to store the voltage difference between the signals of the third node and the first signal terminal.

[0014] In an exemplary embodiment, a third control sub-circuit is also included.

[0015] The third control sub-circuit is electrically connected to the first reset signal terminal, the second reset signal terminal, the second signal terminal, the third signal terminal, the first node, and the fourth node, respectively. It is configured to provide the signal from the second signal terminal to the first node and the signal from the third signal terminal to the fourth node under the control of the signals from the first reset signal terminal and the second reset signal terminal.

[0016] In an exemplary embodiment, the third control sub-circuit includes: a first reset sub-circuit and a second reset sub-circuit;

[0017] The first reset sub-circuit is electrically connected to the first reset signal terminal, the second signal terminal, and the first node, respectively, and is configured to provide the signal of the second signal terminal to the first node under the control of the signal of the first reset signal terminal;

[0018] The second reset sub-circuit is electrically connected to the second reset signal terminal, the third signal terminal, and the fourth node, respectively, and is configured to provide the signal from the third signal terminal to the fourth node under the control of the signal from the second reset signal terminal.

[0019] In an exemplary embodiment, it further includes: a third control sub-circuit;

[0020] The third control sub-circuit is electrically connected to the first reset signal terminal, the second reset signal terminal, the second signal terminal, the third signal terminal, the fourth node, and the fifth node, respectively. It is configured to provide the signal from the second signal terminal to the fifth node and the signal from the third signal terminal to the fourth node under the control of the signals from the first reset signal terminal and the second reset signal terminal.

[0021] In an exemplary embodiment, the third control sub-circuit includes: a first reset sub-circuit and a second reset sub-circuit;

[0022] The first reset sub-circuit is electrically connected to the first reset signal terminal, the second signal terminal, and the fifth node, respectively, and is configured to provide the second signal terminal to the fifth node under the control of the signal from the first reset signal terminal;

[0023] The second reset sub-circuit is electrically connected to the second reset signal terminal, the third signal terminal, and the fourth node, respectively, and is configured to provide the signal from the third signal terminal to the fourth node under the control of the signal from the second reset signal terminal.

[0024] In an exemplary embodiment, the communication sub-circuit includes a second transistor, and the writing sub-circuit includes a fourth transistor;

[0025] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the fifth node.

[0026] The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node.

[0027] In an exemplary embodiment, the storage sub-circuit includes a first capacitor, and the voltage divider sub-circuit includes a second capacitor;

[0028] The first terminal of the first capacitor is electrically connected to the fifth node, and the second terminal of the first capacitor is electrically connected to the third node.

[0029] The first terminal of the second capacitor is electrically connected to the first signal terminal, and the second terminal of the second capacitor is electrically connected to the third node.

[0030] In an exemplary embodiment, the first reset circuit includes a first transistor, and the second reset circuit includes a seventh transistor;

[0031] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the second signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0032] The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the third signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

[0033] In an exemplary embodiment, the first reset circuit includes a first transistor, and the second reset circuit includes a seventh transistor;

[0034] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the second signal terminal, and the second electrode of the first transistor is electrically connected to the fifth node.

[0035] The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the third signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

[0036] In an exemplary embodiment, it further includes: a third control sub-circuit, the driving sub-circuit including: a third transistor, the first control sub-circuit including: a second transistor, a fourth transistor, a first capacitor and a second capacitor, the second control sub-circuit including: a fifth transistor and a sixth transistor, and the third control sub-circuit including: a first transistor and a seventh transistor;

[0037] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the second signal terminal, and the second electrode of the first transistor is electrically connected to one of the first node and the fifth node.

[0038] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the fifth node.

[0039] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0040] The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node.

[0041] The control electrode of the fifth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0042] The control electrode of the sixth transistor is electrically connected to the second light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0043] The control electrode of the seventh transistor is electrically connected to the second reset signal terminal, the first electrode of the seventh transistor is electrically connected to the third signal terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node.

[0044] The first terminal of the first capacitor is electrically connected to the fifth node, and the second terminal of the first capacitor is electrically connected to the third node.

[0045] The first terminal of the second capacitor is electrically connected to the first signal terminal, and the second terminal of the second capacitor is electrically connected to the third node.

[0046] At least one of the first to the seventh transistors is an N-type transistor.

[0047] In an exemplary embodiment, the signal received by the second scanning signal terminal is the same as the signal received by the first light-emitting signal terminal.

[0048] In an exemplary embodiment, the pixel driving circuit is connected to the light-emitting device, and the light-emitting device is electrically connected to the fourth node and the second power supply terminal respectively.

[0049] The signal received by the first signal terminal is the same as the signal received by one of the following signal terminals: the first power terminal, the second power terminal, the second signal terminal, and the third signal terminal.

[0050] The signal received by the first signal terminal is the same as the signal received by the second signal terminal, or the signal received by the first signal terminal is the same as the signal received by the first power supply terminal.

[0051] Secondly, this disclosure also provides a display device having a display area and a non-display area located on at least one side of the display area, wherein the display area is provided with a plurality of the aforementioned pixel driving circuits.

[0052] In an exemplary embodiment, the non-display area is provided with a first shift register unit, a second shift register unit, a third shift register unit, a fourth shift register unit, and a fifth shift register unit;

[0053] The first shift register unit is electrically connected to the first scan signal terminal of the multiple pixel driving circuits and is configured to provide signals to the first scan signal terminal of the multiple pixel driving circuits. The second shift register unit is electrically connected to the second scan signal terminal and the first light emission signal terminal of the multiple pixel driving circuits and is configured to provide signals to the second scan signal terminal and the first light emission signal terminal of the multiple pixel driving circuits. The third shift register unit is electrically connected to the second light emission signal terminal of the multiple pixel driving circuits and is configured to provide signals to the second light emission signal terminal of the multiple pixel driving circuits. The fourth shift register unit is electrically connected to the first reset signal terminal of the multiple pixel driving circuits and is configured to provide signals to the first reset signal terminal of the multiple pixel driving circuits. The fifth shift register unit is electrically connected to the second reset signal terminal of the multiple pixel driving circuits and is configured to provide signals to the second reset signal terminal of the multiple pixel driving circuits.

[0054] In an exemplary embodiment, the time period during which the second shift register unit provides an effective level signal to the first light-emitting signal terminal and the second scan signal terminal connected to at least one pixel driving terminal circuit includes: a first time period and a second time period, wherein the first time period occurs before the second time period;

[0055] The time period during which the third shift register unit provides an effective level signal to the second light-emitting signal terminal connected to at least one pixel driving circuit includes: a third time period and a fourth time period, wherein the third time period occurs before the first time period and the fourth time period, and the second time period and the fourth time period at least partially overlap.

[0056] The time period during which the first shift register unit provides an effective level signal to the first scan signal terminal connected to at least one pixel driving circuit is a fifth time period, the fifth time period occurs between the first time period and the second time period, and the duration of the first time period is greater than the duration of the fifth time period;

[0057] The time period during which the fourth shift register unit provides an effective level signal to the first reset signal terminal connected to at least one pixel driving circuit is the sixth time period. The sixth time period overlaps at least partially with the first time period and the third time period, and the sixth time period occurs before the fifth time period, and the duration of the sixth time period is greater than the duration of the fifth time period.

[0058] The first time period is within the sixth time period, and the start time of the third time period is earlier than the start time of the sixth time period, while the end time of the third time period is within the sixth time period.

[0059] In an exemplary embodiment, the time period during which the fifth shift register unit provides an effective level signal to the second reset signal terminal connected to at least one pixel driving circuit includes a seventh time period and an eighth time period, wherein the seventh time period occurs before the eighth time period.

[0060] The seventh time period is located within the third time period and at least partially overlaps with the sixth time period; the eighth time period is located between the fifth time period and the fourth time period.

[0061] The duration of at least one of the seventh and eighth time periods is less than the duration of the sixth time period, and the duration of the first time period is greater than the duration of the eighth time period.

[0062] In an exemplary embodiment, the time period during which the fifth shift register unit provides an effective level signal to the second reset signal terminal connected to at least one pixel driving circuit is the seventh time period;

[0063] The seventh time period is located within the third time period and at least partially overlaps with the sixth time period, and the duration of the seventh time period is less than the duration of the sixth time period.

[0064] In an exemplary embodiment, the first shift register unit and the fifth shift register unit are the same shift register unit.

[0065] Thirdly, this disclosure also provides a method for driving a pixel driving circuit, configured to drive the aforementioned pixel driving circuit, the method comprising:

[0066] The driving sub-circuit provides driving signals to the third node under the control of the signals from the first and second nodes;

[0067] The first control sub-circuit, under the control of the signals from the first scan signal terminal and the second scan signal terminal, adjusts the signals of the first node and the third node through the signals from the data signal terminal and the first signal terminal.

[0068] The second control sub-circuit, under the control of the signals from the first and second light-emitting signal terminals, provides the signal from the first power supply terminal to the second node and connects the third and fourth nodes.

[0069] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0070] Overview of the attached figures

[0071] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0072] Figure 1 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0073] Figure 2 is a schematic diagram of the first control sub-circuit;

[0074] Figure 3 is the equivalent circuit diagram of the first control sub-circuit;

[0075] Figure 4 is a schematic diagram of a pixel driving circuit provided in an exemplary embodiment;

[0076] Figure 5 is a schematic diagram of the third control sub-circuit in the pixel driving circuit provided in Figure 4;

[0077] Figure 6 is the equivalent circuit diagram of the third control sub-circuit provided in Figure 5;

[0078] Figure 7 is a schematic diagram of the pixel driving circuit provided in another exemplary embodiment;

[0079] Figure 8 is a schematic diagram of the third control sub-circuit in the pixel driving circuit provided in Figure 7;

[0080] Figure 9 is the equivalent circuit diagram of the third control sub-circuit provided in Figure 8;

[0081] Figure 10 shows the equivalent circuit diagram of the driving sub-circuit and the second control sub-circuit;

[0082] Figure 11 is an equivalent circuit diagram of a pixel driving circuit;

[0083] Figure 12 shows the equivalent circuit diagram of another pixel driving circuit;

[0084] Figure 13 is a driving timing diagram of the pixel driving circuit provided in Figures 11 and 12.

[0085] Figure 14 is the second driving timing diagram of the pixel driving circuit provided in Figures 11 and 12;

[0086] Figure 15 is a schematic diagram of the structure of the display device provided in an embodiment of this disclosure;

[0087] Figure 16 is a schematic diagram of a planar structure of a display substrate;

[0088] Figure 17 is a schematic diagram of a planar structure of a display substrate;

[0089] Figure 18 is a schematic diagram of a planar structure of a display substrate;

[0090] Figure 19 is a schematic diagram of the structure of the non-display area.

[0091] Detailed Explanation

[0092] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0093] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0094] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0095] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0096] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0097] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0098] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0099] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0100] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0101] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0102] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0103] With the development of OLED display technology, oxide processes are frequently used in OLED display products due to their high uniformity. The compensation process of pixel driving circuits fabricated using oxide processes occurs during the data writing process, resulting in a short compensation time for the pixel driving circuit and reducing its reliability.

[0104] Figure 1 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure. As shown in Figure 1, the pixel driving circuit provided in an embodiment of this disclosure includes: a driving sub-circuit, a first control sub-circuit, and a second control sub-circuit.

[0105] As shown in Figure 1, the driving sub-circuit is electrically connected to the first node N1, the second node N2, and the third node N3, respectively, and is configured to provide a driving signal to the third node N3 under the control of the signals from the first node N1 and the second node N2. The first control sub-circuit is electrically connected to the first scan signal terminal Gate1, the second scan signal terminal Gate2, the data signal terminal Data, the first signal terminal VIN1, the first node N1, and the third node N3, respectively, and is configured to adjust the signals of the first node N1 and the third node N3 through the signals from the data signal terminal Data and the first signal terminal VIN1, under the control of the signals from the first scan signal terminal Gate1 and the second scan signal terminal Gate2. The second control sub-circuit is electrically connected to the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, the first power supply terminal ELVDD, the second node N2, the third node N3, and the fourth node N4, respectively, and is configured to provide the first power supply terminal ELVDD signal to the second node N2 under the control of the signals from the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2, and connect the third node N3 and the fourth node N4.

[0106] In an exemplary embodiment, the first signal terminal VIN1 can continuously provide a high-level signal or continuously provide a low-level signal. The signal at the first signal terminal VIN1 can be a DC signal.

[0107] In an exemplary embodiment, the first power supply terminal ELVDD can continuously provide a high-level signal, and the signal of the first power supply terminal ELVDD is a DC signal.

[0108] In an exemplary embodiment, the pixel driving circuit is configured to drive the light-emitting device EL to emit light, as shown in FIG1. ​​The light-emitting device EL is electrically connected to the fourth node N4 and the second power supply terminal ELVSS.

[0109] In an exemplary embodiment, the second power supply terminal ELVSS can continuously provide a low-level signal, and the signal of the second power supply terminal ELVSS is a DC signal.

[0110] In an exemplary embodiment, the light-emitting device EL may include a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together. Exemplarily, the anode of the light-emitting device EL is electrically connected to a fourth node N4, and the cathode of the light-emitting device EL is electrically connected to a second power supply terminal ELVSS.

[0111] In an exemplary embodiment, the light-emitting device EL may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0112] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0113] The pixel driving circuit provided in this disclosure, through the cooperation of the first control sub-circuit and the second control sub-circuit, enables the compensation process of the pixel driving circuit to be independent of the data writing process, thereby extending the compensation time of the pixel driving circuit and improving the reliability of the pixel driving circuit.

[0114] In an exemplary embodiment, FIG2 is a schematic diagram of the structure of the first control sub-circuit. As shown in FIG2, the first control sub-circuit may include: a write sub-circuit, a connection sub-circuit, a storage sub-circuit, and a voltage divider sub-circuit.

[0115] As shown in Figure 2, the write sub-circuit is electrically connected to the first scan signal terminal Gate1, the data signal terminal Data, and the fifth node N5, and is configured to provide the data signal terminal Data to the fifth node N5 under the control of the signal from the first scan signal terminal Gate1; the connect sub-circuit is electrically connected to the second scan signal terminal Gate2, the first node N1, and the fifth node N5, and is configured to connect the first node N1 and the fifth node N5 under the control of the signal from the second scan signal terminal Gate2; the storage sub-circuit is electrically connected to the third node N3 and the fifth node N5, and is configured to store the voltage difference between the signals from the third node N3 and the fifth node N5; the voltage divider sub-circuit is electrically connected to the third node N3 and the first signal terminal VIN1, and is configured to store the voltage difference between the signals from the third node N3 and the first signal terminal VIN1.

[0116] In an exemplary embodiment, Figure 3 is an equivalent circuit diagram of the first control sub-circuit. As shown in Figure 3, the connected sub-circuit in the first control sub-circuit includes a second transistor T2. The control terminal of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the second transistor T2 is electrically connected to the fifth node N5.

[0117] Figure 3 shows only one exemplary structure of the connected sub-circuit. Those skilled in the art will readily understand that the implementation of the connected sub-circuit is not limited to this.

[0118] In an exemplary embodiment, as shown in FIG3, the write sub-circuit in the first control sub-circuit includes a fourth transistor T4. The control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fifth node N5. The fourth transistor can be referred to as a data write transistor.

[0119] Figure 3 shows only one exemplary structure of the write sub-circuit, and those skilled in the art will readily understand that the implementation of the write sub-circuit is not limited to this.

[0120] In an exemplary embodiment, as shown in FIG3, the storage sub-circuit in the first control sub-circuit includes a first capacitor C1. The first terminal of the first capacitor C1 is electrically connected to the fifth node N5, and the second terminal of the first capacitor C1 is electrically connected to the third node N3.

[0121] Figure 3 shows only one exemplary structure of the storage sub-circuit. Those skilled in the art will readily understand that the implementation of the storage sub-circuit is not limited to this.

[0122] In an exemplary embodiment, as shown in FIG3, the voltage divider sub-circuit in the first control sub-circuit includes a second capacitor C2. The first terminal of the second capacitor C2 is electrically connected to the first signal terminal VIN1, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0123] Figure 3 shows only one exemplary structure of the voltage divider circuit. Those skilled in the art will readily understand that the implementation of the voltage divider circuit is not limited to this.

[0124] Figure 4 is a schematic diagram of a pixel driving circuit provided in an exemplary embodiment. As shown in Figure 4, the third control sub-circuit is electrically connected to the first reset signal terminal Reset1, the second reset signal terminal Reset2, the second signal terminal VIN2, the third signal terminal VIN3, the first node N1, and the fourth node N4, respectively. It is configured to provide the signal of the second signal terminal VIN2 to the first node N1 and the signal of the third signal terminal VIN3 to the fourth node N4 under the control of the signals of the first reset signal terminal Reset1 and the second reset signal terminal Reset2.

[0125] Figure 5 is a schematic diagram of the third control sub-circuit in the pixel driving circuit shown in Figure 4. As shown in Figure 5, the third control sub-circuit includes a first reset sub-circuit and a second reset sub-circuit. The first reset sub-circuit is electrically connected to the first reset signal terminal Reset1, the second signal terminal VIN2, and the first node N1, and is configured to provide the signal of the second signal terminal VIN2 to the first node N1 under the control of the signal of the first reset signal terminal Reset1. The second reset sub-circuit is electrically connected to the second reset signal terminal Reset2, the third signal terminal VIN3, and the fourth node N4, and is configured to provide the signal of the third signal terminal VIN3 to the fourth node N4 under the control of the signal of the second reset signal terminal Reset2.

[0126] Figure 6 is an equivalent circuit diagram of the third control sub-circuit provided in Figure 5. As shown in Figure 6, the first reset sub-circuit in the third control sub-circuit provided in Figure 5 includes a first transistor T1. The control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Reset1, the first electrode of the first transistor T1 is electrically connected to the second signal terminal VIN2, and the second electrode of the first transistor T1 is electrically connected to the first node N1. For example, the first transistor T1 can be referred to as a node reset transistor.

[0127] Figure 6 shows only one exemplary structure of the first reset circuit. Those skilled in the art will readily understand that the implementation of the first reset circuit is not limited to this.

[0128] In an exemplary embodiment, as shown in FIG6, the second reset sub-circuit in the third control sub-circuit provided in FIG5 includes a seventh transistor T7. The control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal Reset2, the first electrode of the seventh transistor T7 is electrically connected to the third signal terminal VIN3, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. Exemplarily, the seventh transistor T7 can be referred to as an anode reset transistor.

[0129] Figure 6 shows only one exemplary structure of the second reset circuit. Those skilled in the art will readily understand that the implementation of the second reset circuit is not limited to this.

[0130] Figure 7 is a schematic diagram of a pixel driving circuit provided in another exemplary embodiment. As shown in Figure 7, the third control sub-circuit is electrically connected to the first reset signal terminal Reset1, the second reset signal terminal Reset2, the second signal terminal VIN2, the third signal terminal VIN3, the fourth node N4, and the fifth node N5, respectively. It is configured to provide the signal of the second signal terminal VIN2 to the fifth node N5 and the signal of the third signal terminal VIN3 to the fourth node N4 under the control of the signals of the first reset signal terminal Reset1 and the second reset signal terminal Reset2.

[0131] Figure 8 is a schematic diagram of the third control sub-circuit in the pixel driving circuit provided in Figure 7. As shown in Figure 8, the third control sub-circuit includes a first reset sub-circuit and a second reset sub-circuit. The first reset sub-circuit is electrically connected to the first reset signal terminal Reset1, the second signal terminal VIN2, and the fifth node N5, and is configured to provide the signal of the second signal terminal VIN2 to the fifth node N5 under the control of the signal of the first reset signal terminal Reset1. The second reset sub-circuit is electrically connected to the second reset signal terminal Reset2, the third signal terminal VIN3, and the fourth node N4, and is configured to provide the signal of the third signal terminal VIN3 to the fourth node N4 under the control of the signal of the second reset signal terminal Reset2.

[0132] Figure 9 is an equivalent circuit diagram of the third control sub-circuit provided in Figure 8. As shown in Figure 9, the first reset sub-circuit in the third control sub-circuit provided in Figure 8 includes a first transistor T1. The control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Reset1, the first electrode of the first transistor T1 is electrically connected to the second signal terminal VIN2, and the second electrode of the first transistor T1 is electrically connected to the fifth node N5. For example, the first transistor T1 can be referred to as a node reset transistor.

[0133] Figure 9 shows only one exemplary structure of the first reset circuit. Those skilled in the art will readily understand that the implementation of the first reset circuit is not limited to this.

[0134] In an exemplary embodiment, as shown in FIG9, the second reset sub-circuit in the third control sub-circuit provided in FIG8 includes a seventh transistor T7. The control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal Reset2, the first electrode of the seventh transistor T7 is electrically connected to the third signal terminal VIN3, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. Exemplarily, the seventh transistor T7 can be referred to as an anode reset transistor.

[0135] Figure 9 shows only one exemplary structure of the second reset circuit. Those skilled in the art will readily understand that the implementation of the second reset circuit is not limited to this.

[0136] Figure 10 is an equivalent circuit diagram of the driving sub-circuit and the second control sub-circuit. As shown in Figure 10, in an exemplary embodiment, the driving sub-circuit may include a third transistor T3. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Exemplarily, the third transistor T3 may be referred to as the driving transistor.

[0137] Figure 10 shows only one exemplary structure of the driver sub-circuit. Those skilled in the art will readily understand that the implementation of the driver sub-circuit is not limited to this.

[0138] As shown in Figure 10, in an exemplary embodiment, the second control sub-circuit may include a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal ELVDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. Exemplarily, the fifth transistor T5 and the sixth transistor T6 may be referred to as light-emitting transistors (LEDs).

[0139] Figure 10 shows only one exemplary structure of the second control sub-circuit. Those skilled in the art will readily understand that the implementation of the second control sub-circuit is not limited to this.

[0140] Figure 11 is an equivalent circuit diagram of one pixel driving circuit, and Figure 12 is an equivalent circuit diagram of another pixel driving circuit. As shown in Figures 11 and 12, in the pixel driving circuit, the driving sub-circuit includes: a third transistor T3; the first control sub-circuit includes: a second transistor T2, a fourth transistor T4, a first capacitor C1, and a second capacitor C2; the second control sub-circuit includes: a fifth transistor T5 and a sixth transistor T6; and the third control sub-circuit includes: a first transistor T1 and a seventh transistor T7. Specifically, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Reset1, the first electrode of the first transistor T1 is electrically connected to the second signal terminal VIN2, and the second electrode of the first transistor T1 is electrically connected to one of the first nodes N1 and the fifth node N5; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the fifth node N5; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fifth node N5. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal ELVDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal Reset2, the first electrode of the seventh transistor T7 is electrically connected to the third signal terminal VIN3, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The first terminal of the first capacitor C1 is electrically connected to the fifth node N5, and the second terminal of the first capacitor C1 is electrically connected to the third node N3. The first terminal of the second capacitor C2 is electrically connected to the first signal terminal VIN1, and the second terminal of the second capacitor C2 is electrically connected to the third node N3. Figure 11 illustrates the connection between the second electrode of the first transistor T1 and the first node N1. Figure 12 illustrates the connection between the second electrode of the first transistor T1 and the fifth node N5.

[0141] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its on-state voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its off-state voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its on-state voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its off-state voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0142] In an exemplary embodiment, the N-type transistor can be an oxide thin-film transistor. The active layer of the oxide thin-film transistor is made of oxide semiconductor. Oxide thin-film transistors have advantages such as low leakage current, uniform film formation, good transistor hysteresis characteristics, and low manufacturing cost.

[0143] In an exemplary embodiment, in the pixel driving circuit provided in Figures 11 and 12, at least one of the first transistor T1 to the seventh transistor T7 is an N-type transistor. Exemplarily, all of the first transistor T1 to the seventh transistor T7 can be N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves product yield.

[0144] In an exemplary embodiment, the signal received by the second scanning signal terminal Gate2 is the same as the signal received by the first light-emitting signal terminal EM1. Exemplarily, the second scanning signal terminal Gate2 and the first light-emitting signal terminal EM1 can be connected to the same signal line; this disclosure does not impose any limitations on this.

[0145] In an exemplary embodiment, the signal received by the first signal terminal VIN1 may be the same as the signal received by one of the following signal terminals: the first power terminal ELVDD, the second power terminal ELVSS, the second signal terminal VIN2, and the third signal terminal VIN3. The signal line connected to the first signal terminal VIN1 may be the same signal line as the signal line connected to one of the following signal terminals: the first power terminal ELVDD, the second power terminal ELVSS, the second signal terminal VIN2, and the third signal terminal VIN3; or they may be different signal lines. This disclosure does not impose any limitations on this.

[0146] In an exemplary embodiment, the signal received by the first signal terminal VIN1 is the same as the signal received by the second signal terminal VIN2, which can reduce the voltage difference between the signals of the first node N1 and the third node N3 caused by different coupling effects of different pixel driving circuits, and can improve the reliability of the pixel driving circuit.

[0147] In an exemplary embodiment, at least two of the signals from the first signal terminal VIN1, the second signal terminal VIN2, and the first power supply terminal ELVDD have the same voltage value. This reduces the resistance of the signal lines connected to at least one of these terminals, further improving the display uniformity of the pixel driving circuit. Exemplarily, the signal from at least one of the first signal terminals VIN1 and VIN2 can also be other regulated signals.

[0148] In an exemplary embodiment, the signal received by the first signal terminal VIN1 is the same as the signal received by the first power supply terminal ELVDD. Exemplarily, when the signal received by the first signal terminal VIN1 is the same as the signal received by the first power supply terminal ELVDD, the first signal terminal VIN1 can be connected to the same signal line as the first power supply terminal ELVDD; this disclosure does not impose any limitations on this.

[0149] Figure 13 is the first driving timing diagram of the pixel driving circuit provided in Figures 11 and 12, and Figure 14 is the second driving timing diagram of the pixel driving circuit provided in Figures 11 and 12. Figures 13 and 14 are illustrated using the example of N-type transistors in the pixel driving circuit.

[0150] In an exemplary embodiment, as shown in Figures 13 and 14, the time periods during which the signals of the first light-emitting signal terminal EM1 and the second scanning signal terminal Gate2, connected to at least one pixel driving terminal circuit, are at an effective level include: a first time period t1 and a second time period t2, with the first time period t1 occurring before the second time period t2. The time periods during which the signal of the second light-emitting signal terminal EM2, connected to at least one pixel driving circuit, is at an effective level include: a third time period t3 and a fourth time period t4, with the third time period t3 occurring before the first time period t1 and the fourth time period t4, and the second time period t2 and the fourth time period t4 at least partially overlapping.

[0151] In an exemplary embodiment, as shown in Figures 13 and 14, the time period during which the signal of the first scanning signal terminal Gate1 connected to at least one pixel driving circuit is an effective level signal is the fifth time period t5. The fifth time period t5 occurs between the first time period t1 and the second time period t2, and the duration of the first time period t1 is greater than the duration of the fifth time period t5.

[0152] In an exemplary embodiment, as shown in Figures 13 and 14, the time period during which the signal of the first reset signal terminal Reset1 connected to at least one pixel driving circuit is an effective level signal is the sixth time period t6. The sixth time period t6 overlaps at least partially with the first time period t1 and the third time period t3, and the sixth time period t6 occurs before the fifth time period t5, and the duration of the sixth time period t6 is greater than the duration of the fifth time period t5.

[0153] In an exemplary embodiment, as shown in Figures 13 and 14, the first time period t1 is located within the sixth time period t6.

[0154] In an exemplary embodiment, as shown in Figures 13 and 14, the start time of the third time period t3 is earlier than the start time of the sixth time period t6, and the end time of the third time period t3 is within the sixth time period t6.

[0155] In an exemplary embodiment, as shown in FIG13, the time period during which the signal of the second reset signal terminal Reset2 connected to at least one pixel driving circuit is an effective level signal includes: a seventh time period t7 and an eighth time period t8, wherein the seventh time period t7 occurs before the eighth time period t8. The seventh time period t7 is located within the third time period t3 and at least partially overlaps with the sixth time period t6, and the eighth time period t8 is located between the fifth time period t5 and the fourth time period t4; the duration of at least one of the seventh time period t7 and the eighth time period t8 is less than the duration of the sixth time period t6, and the duration of the first time period t1 is greater than the duration of the eighth time period t8.

[0156] In an exemplary embodiment, as shown in FIG14, the time period during which the signal of the second reset signal terminal Reset2, to which at least one pixel driving circuit is connected, is an effective level signal is the seventh time period t7. The seventh time period t7 is located within the third time period t3 and at least partially overlaps with the sixth time period t6, and the duration of the seventh time period t7 is less than the duration of the sixth time period t6.

[0157] The exemplary embodiments of this disclosure are described below using the operation of the pixel driving circuit illustrated in FIG11. As shown in FIG11 and FIG13, the operation of the pixel driving circuit provided in FIG11 may include:

[0158] In the first stage (P11), the initialization stage, the signals at the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are low-level signals. The first transistor T1, the sixth transistor T6, and the seventh transistor T7 are turned on, while the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0159] The first transistor T1 is turned on, and the signal at the second signal terminal VIN2 is written to the first node N1, initializing the first node N1 and clearing its charge. The seventh transistor T7 is turned on, and the signal at the third signal terminal VIN3 is written to the fourth node N4, initializing the fourth node N4 and clearing its charge. The sixth transistor T6 is turned on, connecting the third node N3 and the fourth node N4. Under the influence of the first node N1 and the third node N3, the third transistor T3 is turned on, connecting the second node N2 and the third node N3, sequentially initializing the third node N3 and the second node N2, and clearing their charges.

[0160] In this phase, the voltage value V of the signal at the first node N1 N1 =Vinit1, the voltage value V of the signal at the second node N2. N2 =Vinit2, the voltage value of the signal at the third node N2; VN3 =Vinit2, the voltage value of the signal at the fourth node N4. N4 =Vinit2, where Vinit1 is the voltage value of the signal at the second signal terminal VIN2, and Vinit2 is the voltage value of the signal at the third signal terminal VIN3.

[0161] In the second stage (P12), the compensation stage, the signals of the first reset signal terminal Reset1, the second scan signal terminal Gate2, and the first light emission signal terminal EM1 are high-level signals, while the signals of the first scan signal terminal Gate1, the second reset signal terminal Reset2, and the second light emission signal terminal EM2 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0162] The first transistor T1 is turned on, and the signal at the second signal terminal VIN2 is continuously written to the first node N1, initializing the first node N1 and clearing its charge. The second transistor T2 is turned on, connecting the first node N1 to the fifth node N5, initializing the fifth node N5 and clearing its charge. The fifth transistor T5 is turned on, and the signal at the first power supply terminal ELVDD is written to the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3, until the voltage value V of the signal at the third node N3 is reached. N3 =Vinit1-Vth, where Vth is the threshold voltage of the third transistor T3.

[0163] In this phase, the voltage value V of the signal at the first node N1 N1 =Vinit1, the voltage value V of the signal at the second node N2. N2 =Vdd, the voltage value V of the signal at the third node N3.N3 =Vinit1-Vth, the voltage value V of the signal at the fifth node N5. N5 =Vinit1, where Vdd is the voltage value of the signal at the first power supply terminal ELVDD.

[0164] In the third stage (P13), the data writing stage, the signal at the first scan signal terminal (Gate1) is high, while the signals at the second scan signal terminal (Gate2), the first reset signal terminal (Reset1), the second reset signal terminal (Reset2), the first light emission signal terminal (EM1), and the second light emission signal terminal (EM2) are low. The data signal terminal (Data) writes the data signal. The fourth transistor (T4) is turned on, while the first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) are turned off.

[0165] The fourth transistor T4 is turned on, and the data signal at the data signal terminal Data is written to the fifth node N5. The voltage value of the signal at the fifth node N5 changes from Vinit1 in the previous stage to Vdata in this stage. The voltage value of the signal at the fifth node N5 has changed, where Vdata is the voltage value of the data signal. Under the action of the first capacitor C1 and the voltage division of the second capacitor C2, the voltage value of the signal at the third node N3 also changes. N3 =Vinit1-Vth+α(Vdata-Vinit1), where 0<α<1, α=C1 / (C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2. Since the third transistor T3 is turned on, the second node N2 and the third node N3 are connected.

[0166] In this stage, the voltage value V of the signal at the second node N2 N2 =Vinit1-Vth+α(Vdata-Vinit1), where V is the voltage value of the signal at the third node N3. N3 =Vinit1-Vth+α(Vdata-Vinit1), where V is the voltage value of the signal at the fifth node N5. N5 =Vdata.

[0167] In the fourth stage (P14), the effect elimination stage, the signal at the second reset signal terminal (Reset2) is a high-level signal, while the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the first reset signal terminal (Reset1), the first light emission signal terminal (EM1), and the second light emission signal terminal (EM2) are low-level signals. The seventh transistor (T7) is turned on, while the first transistor (T1), the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) are turned off.

[0168] When the seventh transistor T7 is turned on, the signal at the third signal terminal VIN3 is written to the fourth node N4 to initialize the fourth node N4 and clear the charge of the fourth node N4.

[0169] In this stage, the voltage value V of the signal at the fourth node N4 N4 =Vinit2.

[0170] In the fifth stage (P15), the light-emitting stage, the signals at the second scan signal terminal Gate2, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the first reset signal terminal Reset1, and the second reset signal terminal Reset2 are low-level signals. The second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned on, while the first transistor T1, the fourth transistor T4, and the seventh transistor T7 are turned off.

[0171] The second transistor T2 is turned on, connecting the first node N1 and the fifth node N5. The fifth transistor T5 and the sixth transistor T6 are turned on, allowing the power supply voltage output from the first power supply terminal ELVDD to provide driving current to the fourth node N4 (which is also the first terminal of the light-emitting device EL) through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6, thereby driving the light-emitting device EL to emit light.

[0172] In this phase, the voltage value V of the signal at the first node N1 N1 =(Vdata*C N5 +Vinit1*C N1 ) / (C N5 +C N1 The voltage value V of the signal at the second node N2. N2 =Vdd, the voltage value V of the signal at the third node N3. N3 =Vinit1-Vth+α(Vdata-Vinit1), where V is the voltage value of the signal at the fourth node. N4 =Voled + Vss, the voltage value V of the signal at the fifth node N5. N5 =(Vdata*C N5 +Vinit1*C N1 ) / (C N5 +C N1 ), where Vss is the voltage value of the signal at the second power supply terminal ELVSS, Voled is the voltage difference across the light-emitting device EL, and C N1 The coupling capacitance of the first node N1 is mainly the capacitance between the gate and source electrodes of the third transistor. C N5 The coupling capacitor of the fifth node N5 is mainly the first capacitor.

[0173] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode (i.e., the first node N1) and its second electrode (i.e., the third node N3). Since the voltage value V of the signal at the first node N1... N1 =(Vdata*C N5 +Vinit1*C N1 ) / (C N5 +C N1 The voltage value V of the signal at the third node N3. N3 =Vinit1-Vth+α(Vdata-Vinit1)

[0174] Therefore, the driving current I of the third transistor T3 is: I = K*(Vgs - Vth) 2 =K*(V N1 -V N3 -Vth) 2 =K*[(Vdata*C N5 +Vinit1*C N1 ) / (C N5 +C N1 )-Vinit1+Vth-α(Vdata-Vinit1)-Vth] 2 =K*[(Vdata*C N5 +Vinit1*C N1 ) / (C N5 +C N1 )-Vinit1-α(Vdata-Vinit1)] 2

[0175] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device EL, K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0176] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 in each pixel driving circuit is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product, and improving the display effect of the entire display product.

[0177] Due to manufacturing processes and other factors, the transistors in different pixel driving circuits may vary. Furthermore, the signal at the fourth node of the pixel driving circuit is coupled after the first to third stages, resulting in inconsistent voltage values ​​at the fourth node when the light-emitting device emits light from different pixel driving circuits. The existence of the fourth stage, P14, can eliminate this inconsistency in the voltage value of the fourth node signal when the light-emitting device emits light from different pixel driving circuits, thereby improving the reliability of the display substrate where the pixel driving circuit is located.

[0178] The exemplary embodiments of this disclosure are described below using the operation of the pixel driving circuit illustrated in FIG11. As shown in FIG11 and FIG14, the operation of the pixel driving circuit provided in FIG11 may include:

[0179] According to the driving timing provided in Figure 14, the pixel driving circuit provided in Figure 11 may include: a first stage P21, a second stage P22, a third stage P23, and a fourth stage P24. Specifically, the first stage P21 is the initialization stage, which is the same as the first stage P11 in the driving timing provided in Figure 13, and will not be described further here. The second stage P22 is the compensation stage, which is the same as the second stage P12 in the driving timing provided in Figure 13, and will not be described further here. The third stage P23 is the data writing stage, which is the same as the third stage P13 in the driving timing provided in Figure 13, and will not be described further here. The fourth stage P24 is the light emission stage, which is the same as the fifth stage P15 in the driving timing provided in Figure 13, and will not be described further here.

[0180] The exemplary embodiments of this disclosure are described below using the operation of the pixel driving circuit illustrated in FIG12. As shown in FIG12 and FIG13, the operation of the pixel driving circuit provided in FIG12 may include:

[0181] In the first stage (P11), the initialization stage, the signals at the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are low-level signals. The first transistor T1, the sixth transistor T6, and the seventh transistor T7 are turned on, while the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0182] The first transistor T1 is turned on, and the signal at the second signal terminal VIN2 is written to the fifth node N5, initializing the fifth node N5 and clearing its charge. The seventh transistor T7 is turned on, and the signal at the third signal terminal VIN3 is written to the fourth node N4, initializing the fourth node N4 and clearing its charge. The sixth transistor T6 is turned on, connecting the third node N3 and the fourth node N4. Under the influence of the first node N1 and the third node N3, the third transistor T3 is turned on, connecting the second node N2 and the third node N3, sequentially initializing the third node N3 and the second node N2, and clearing their charges.

[0183] In this stage, the voltage value V of the signal at the second node N2 N2 =Vinit2, the voltage value of the signal at the third node N2; VN3 =Vinit2, the voltage value of the signal at the fourth node N4. N4 =Vinit2, the voltage value V of the signal at the fifth node N5. N5 =Vinit1, where Vinit1 is the voltage value of the signal at the second signal terminal VIN2, and Vinit2 is the voltage value of the signal at the third signal terminal VIN3.

[0184] In the second stage (P12), the compensation stage, the signals of the first reset signal terminal Reset1, the second scan signal terminal Gate2, and the first light emission signal terminal EM1 are high-level signals, while the signals of the first scan signal terminal Gate1, the second reset signal terminal Reset2, and the second light emission signal terminal EM2 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0185] The first transistor T1 is turned on, and the signal at the second signal terminal VIN2 is continuously written to the fifth node N5, initializing the fifth node N5 and clearing its charge. The second transistor T2 is turned on, connecting the first node N1 and the fifth node N5, initializing the first node N1 and clearing its charge. The fifth transistor T5 is turned on, and the signal at the first power supply terminal ELVDD is written to the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3, until the voltage value V of the signal at the third node N3 is reached. N3 =Vinit1-Vth, where Vth is the threshold voltage of the third transistor T3.

[0186] In this phase, the voltage value V of the signal at the first node N1 N1 =Vinit1, the voltage value V of the signal at the second node N2. N2 =Vdd, the voltage value V of the signal at the third node N3. N3=Vinit1-Vth, the voltage value V of the signal at the fifth node N5. N5 =Vinit1, where Vdd is the voltage value of the signal at the first power supply terminal ELVDD.

[0187] In the third stage (P13), the data writing stage, the signal at the first scan signal terminal (Gate1) is high, while the signals at the second scan signal terminal (Gate2), the first reset signal terminal (Reset1), the second reset signal terminal (Reset2), the first light emission signal terminal (EM1), and the second light emission signal terminal (EM2) are low. The data signal terminal (Data) writes the data signal. The fourth transistor (T4) is turned on, while the first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) are turned off.

[0188] The fourth transistor T4 is turned on, and the data signal at the data signal terminal Data is written to the fifth node N5. The voltage value of the signal at the fifth node N5 changes from Vinit1 in the previous stage to Vdata in this stage. The voltage value of the signal at the fifth node N5 has changed, where Vdata is the voltage value of the data signal. Under the action of the first capacitor C1 and the voltage division of the second capacitor C2, the voltage value of the signal at the third node N3 also changes. N3 =Vinit1-Vth+α(Vdata-Vinit1), where 0<α<1, α=C1 / (C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2. Since the third transistor T3 is turned on, the second node N2 and the third node N3 are connected.

[0189] In this stage, the voltage value V of the signal at the second node N2 N2 =Vinit1-Vth+α(Vdata-Vinit1), where V is the voltage value of the signal at the third node N3. N3 =Vinit1-Vth+α(Vdata-Vinit1), where V is the voltage value of the signal at the fifth node N5. N5 =Vdata.

[0190] In the fourth stage (P14), the effect elimination stage, the signal at the second reset signal terminal (Reset2) is a high-level signal, while the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the first reset signal terminal (Reset1), the first light emission signal terminal (EM1), and the second light emission signal terminal (EM2) are low-level signals. The seventh transistor (T7) is turned on, while the first transistor (T1), the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) are turned off.

[0191] When the seventh transistor T7 is turned on, the signal at the third signal terminal VIN3 is written to the fourth node N4 to initialize the fourth node N4 and clear the charge of the fourth node N4.

[0192] In this stage, the voltage value V of the signal at the fourth node N4 N4 =Vinit2.

[0193] In the fifth stage (P15), the light-emitting stage, the signals at the second scan signal terminal Gate2, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the first reset signal terminal Reset1, and the second reset signal terminal Reset2 are low-level signals. The second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned on, while the first transistor T1, the fourth transistor T4, and the seventh transistor T7 are turned off.

[0194] The second transistor T2 is turned on, connecting the first node N1 and the fifth node N5. The fifth transistor T5 and the sixth transistor T6 are turned on, allowing the power supply voltage output from the first power supply terminal ELVDD to provide driving current to the fourth node N4 (which is also the first terminal of the light-emitting device EL) through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6, thereby driving the light-emitting device EL to emit light.

[0195] In this phase, the voltage value V of the signal at the first node N1 N1 =(Vdata*C N5 +Vinit1*C N1 ) / (C N5 +C N1 The voltage value V of the signal at the second node N2. N2 =Vdd, the voltage value V of the signal at the third node N3. N3 =Vinit1-Vth+α(Vdata-Vinit1), where V is the voltage value of the signal at the fourth node. N4 =Voled + Vss, the voltage value V of the signal at the fifth node N5. N5 =(Vdata*C N5 +Vinit1*C N1 ) / (C N5 +C N1 ), where Vss is the voltage value of the signal at the second power supply terminal ELVSS, Voled is the voltage difference across the light-emitting device EL, and C N1 The coupling capacitance of the first node N1 is mainly the capacitance between the gate and source electrodes of the third transistor. C N5 The coupling capacitor of the fifth node N5 is mainly the first capacitor.

[0196] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode (i.e., the first node N1) and its second electrode (i.e., the third node N3). Since the voltage value V of the signal at the first node N1... N1 =(Vdata*C N5 +Vinit1*C N1 ) / (C N5 +C N1 The voltage value V of the signal at the third node N3. N3 =Vinit1-Vth+α(Vdata-Vinit1)

[0197] Therefore, the driving current I of the third transistor T3 is: I = K*(Vgs - Vth) 2 =K*(V N1 -V N3 -Vth) 2 =K*[(Vdata*C N5 +Vinit1*C N1 ) / (C N5 +C N1 )-Vinit1+Vth-α(Vdata-Vinit1)-Vth] 2 =K*[(Vdata*C N5 +Vinit1*C N1 ) / (C N5 +C N1 )-Vinit1-α(Vdata-Vinit1)] 2

[0198] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device EL, K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0199] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 in each pixel driving circuit is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product, and improving the display effect of the entire display product.

[0200] Due to manufacturing processes and other factors, the transistors in different pixel driving circuits may vary. Furthermore, the signal at the fourth node of the pixel driving circuit is coupled after the first to third stages, resulting in inconsistent voltage values ​​at the fourth node when the light-emitting device emits light from different pixel driving circuits. The existence of the fourth stage, P14, can eliminate this inconsistency in the voltage value of the fourth node signal when the light-emitting device emits light from different pixel driving circuits, thereby improving the reliability of the display substrate where the pixel driving circuit is located.

[0201] The exemplary embodiments of this disclosure are described below using the operation of the pixel driving circuit illustrated in FIG12. As shown in FIG12 and FIG14, the operation of the pixel driving circuit provided in FIG12 may include:

[0202] According to the driving timing provided in Figure 14, the pixel driving circuit provided in Figure 12 may include: a first stage P21, a second stage P22, a third stage P23, and a fourth stage P24. Specifically, the first stage P21 is the initialization stage, which is the same as the first stage P11 in the driving timing provided in Figure 13, and will not be described further here. The second stage P22 is the compensation stage, which is the same as the second stage P12 in the driving timing provided in Figure 13, and will not be described further here. The third stage P23 is the data writing stage, which is the same as the third stage P13 in the driving timing provided in Figure 13, and will not be described further here. The fourth stage P24 is the light emission stage, which is the same as the fifth stage P15 in the driving timing provided in Figure 13, and will not be described further here.

[0203] As can be seen from the working process of the pixel driving circuit provided in Figures 11 and 12, the compensation stage in the pixel driving circuit provided in this embodiment is independent of the data writing stage, and the duration of the compensation stage depends on the duration of the first time period. The longer the duration of the first time period, the longer the compensation time of the pixel driving circuit. In addition, the driving current of the pixel driving circuit provided in this disclosure is independent of the threshold voltage and mobility of the driving transistor. That is to say, the compensation time of the pixel driving circuit provided in this disclosure is not limited by the data writing time, resolution, and the mobility and threshold voltage of the transistor, which improves the application range of the pixel driving circuit and also improves the brightness uniformity of the display substrate where the pixel driving circuit is located.

[0204] This disclosure also provides a method for driving a pixel driving circuit, configured to drive the pixel driving circuit provided in any of the foregoing embodiments. The method for driving a pixel driving circuit provided in this disclosure may include the following steps:

[0205] Step 100: The driving sub-circuit provides a driving signal to the third node under the control of the signals from the first and second nodes.

[0206] Step 200: Under the control of the signals from the first scan signal terminal and the second scan signal terminal, the first control sub-circuit adjusts the signals of the first node and the third node through the signals from the data signal terminal and the first signal terminal.

[0207] Step 300: Under the control of the signals from the first and second light-emitting signal terminals, the second control sub-circuit provides the signal from the first power supply terminal to the second node and connects the third and fourth nodes.

[0208] Figure 15 is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. As shown in Figure 15, an embodiment of the present disclosure also provides a display device having a display area AA and a non-display area BB located on at least one side of the display area AA. The display area AA is provided with a plurality of pixel driving circuits PX provided in any of the foregoing embodiments.

[0209] As shown in Figure 15, the display device may further include a timing controller, a gate driver, a data driver, and a pixel array. The timing controller is connected to both the data driver and the gate driver. The data driver is connected to multiple data signal lines (D1 to Dn), and the gate driver is connected to multiple gate lines (G1 to Gm). The pixel array may include multiple sub-pixels PX. At least one sub-pixel PX may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include the pixel driving circuit provided in any of the foregoing embodiments, and the pixel driving circuit may be connected to the gate lines and the data signal lines, respectively.

[0210] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, and can provide clock signals, start signals, etc. of specifications suitable for the gate driver to the gate driver.

[0211] In an exemplary embodiment, the data driver may use grayscale values ​​and control signals received from a timing controller to generate data voltages that will be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver may use a clock signal to sample grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-row basis, where n can be a natural number.

[0212] In an exemplary embodiment, the gate driver can generate scan signals to be provided to gate lines G1, G2, G3, ..., Gm by receiving clock signals, start signals, etc., from a timing controller. For example, the gate driver can sequentially provide drive signals with on-level pulses to gate lines G1 through Gm. For example, the gate driver can be configured as a shift register and can generate drive signals by sequentially transmitting start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number.

[0213] In an exemplary embodiment, the display device may include a display substrate. A gate driver may be directly disposed on the display substrate. For example, the gate driver may be disposed on the left bezel, or the right bezel, or both the left and right bezels of the display substrate. In an exemplary embodiment, the scan driving circuit and the light-emitting driving circuit may be formed together with the sub-pixels during the sub-pixel formation process.

[0214] In an exemplary embodiment, the data driver can be disposed on a separate chip or printed circuit board to connect to sub-pixels via signals on the display substrate. For example, the data driver can be formed on the bezel of the display substrate using chip-on-glass, chip-on-plastic, or chip-on-film methods. The timing controller can be disposed separately from or integrated with the data driver. However, this embodiment is not limited to this. In an exemplary embodiment, the data driver can be directly disposed on the display substrate.

[0215] Figure 16 is a schematic diagram of a planar structure of a display substrate (Figure 16-18), Figure 17 is a schematic diagram of a planar structure of a display substrate (Figure 17-18), and Figure 18 is a schematic diagram of a planar structure of a display substrate (Figure 18-19). As shown in Figures 16-18, the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light; or it may include: a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a fourth color light. Each of the first sub-pixel P1, second sub-pixel P2, third sub-pixel P3, and fourth sub-pixel P4 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, second sub-pixel P2, third sub-pixel P3, and fourth sub-pixel P4 are connected to the gate line and data signal line, respectively. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, third sub-pixel P3, and fourth sub-pixel P4 are connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0216] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light.

[0217] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel that emits red (R) light, the second sub-pixel P2 may be a blue sub-pixel that emits blue (B) light, the third sub-pixel P3 may be a green sub-pixel that emits green (G) light, and the fourth sub-pixel P4 may be a white sub-pixel that emits white (W) light.

[0218] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal.

[0219] In an exemplary embodiment, when a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement, and this disclosure is not limited thereto. Figure 16 illustrates an example of a pixel unit including three sub-pixels arranged horizontally side by side, and Figure 17 illustrates an example of a pixel unit including three sub-pixels arranged in a triangular arrangement.

[0220] In an exemplary embodiment, when a pixel unit comprises four sub-pixels, the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, in a diamond shape, or in a square, and this disclosure is not limited thereto. Figure 18 illustrates an example where a pixel unit comprises four sub-pixels, and the four sub-pixels are arranged in a square.

[0221] In an exemplary embodiment, FIG19 is a schematic diagram of the structure of the non-display area. As shown in FIG19, the non-display area may be provided with a first shift register unit 10, a second shift register unit 20, a third shift register unit 30, a fourth shift register unit 40, and a fifth shift register unit 50. The first shift register unit 10, the second shift register unit 20, the third shift register unit 30, the fourth shift register unit 40, and the fifth shift register unit 50 may be disposed in the gate driver. Specifically, the first shift register unit 10 is electrically connected to the first scan signal terminal Gate1, which is connected to multiple pixel driving circuits, and is configured to provide signals to the first scan signal terminal Gate1, which is connected to multiple pixel driving circuits. The second shift register unit 20 is electrically connected to the second scan signal terminal Gate2 and the first light emission signal terminal EM1, which are connected to multiple pixel driving circuits, and is configured to provide signals to the second scan signal terminal Gate2 and the first light emission signal terminal EM1, which are connected to multiple pixel driving circuits. The third shift register unit 30 is electrically connected to the second light emission signal terminal EM2, which is connected to multiple pixel driving circuits, and is configured to provide signals to the second light emission signal terminal EM2, which is connected to multiple pixel driving circuits. The fourth shift register unit 40 is electrically connected to the first reset signal terminal Reset1, which is connected to multiple pixel driving circuits, and is configured to provide signals to the first reset signal terminal Reset1, which is connected to multiple pixel driving circuits. The fifth shift register unit 50 is electrically connected to the second reset signal terminal Reset2, which is connected to multiple pixel driving circuits, and is configured to provide signals to the second reset signal terminal Reset2, which is connected to multiple pixel driving circuits.

[0222] In an exemplary embodiment, the time period during which the second shift register unit 20 provides an effective level signal to the first light emission signal terminal EM1 and the second scan signal terminal Gate2 connected to at least one pixel driving terminal circuit includes: a first time period and a second time period, wherein the first time period occurs before the second time period.

[0223] In an exemplary embodiment, the time period during which the third shift register unit 30 provides an effective level signal to the second light-emitting signal terminal EM2 connected to at least one pixel driving circuit includes: a third time period and a fourth time period, wherein the third time period occurs before the first time period and the fourth time period, and the second time period and the fourth time period at least partially overlap.

[0224] In an exemplary embodiment, the time period during which the first shift register unit 10 provides an effective level signal to the first scan signal terminal Gate1 connected to at least one pixel driving circuit is a fifth time period. The fifth time period occurs between the first time period and the second time period, and the duration of the first time period is greater than the duration of the fifth time period.

[0225] In an exemplary embodiment, the time period during which the fourth shift register unit 40 provides an effective level signal to the first reset signal terminal Reset1 connected to at least one pixel driving circuit is a sixth time period. The sixth time period overlaps at least partially with the first time period and the third time period, and the sixth time period occurs before the fifth time period, and the duration of the sixth time period is greater than the duration of the fifth time period.

[0226] In an exemplary embodiment, the first time period is within the sixth time period, and the start time of the third time period is earlier than the start time of the sixth time period, while the end time of the third time period is within the sixth time period.

[0227] In an exemplary embodiment, the time period during which the fifth shift register unit 50 provides an effective level signal to the second reset signal terminal Reset2 connected to at least one pixel driving circuit includes: a seventh time period and an eighth time period, wherein the seventh time period occurs before the eighth time period; the seventh time period is located within the third time period and at least partially overlaps with the sixth time period, and the eighth time period is located between the fifth time period and the fourth time period; the duration of at least one of the seventh and eighth time periods is less than the duration of the sixth time period, and the duration of the first time period is greater than the duration of the eighth time period.

[0228] In an exemplary embodiment, the time period during which the fifth shift register unit 50 provides an effective level signal to the second reset signal terminal Reset2 connected to at least one pixel driving circuit is a seventh time period; the seventh time period is located within the third time period and at least partially overlaps with the sixth time period, and the duration of the seventh time period is less than the duration of the sixth time period.

[0229] In an exemplary embodiment, the first shift register unit 10 and the fifth shift register unit 50 can be the same shift register unit. Having the first shift register unit 10 and the fifth shift register unit 50 as the same shift register unit can reduce the area occupied by the gate driver, enabling a narrow bezel in the display device.

[0230] In an exemplary embodiment, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. This embodiment of the invention is not limited thereto.

[0231] The accompanying drawings of the embodiments disclosed herein only involve the structures involved in the embodiments of this disclosure; other structures can be referred to in the general design.

[0232] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0233] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel driving circuit, comprising: Drive sub-circuit, first control sub-circuit, and second control sub-circuit; The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node. The first control sub-circuit is electrically connected to the first scan signal terminal, the second scan signal terminal, the data signal terminal, the first signal terminal, the first node, and the third node, respectively, and is configured to adjust the signals of the first node and the third node through the signals of the data signal terminal and the first signal terminal under the control of the signals of the first scan signal terminal and the second scan signal terminal. The second control sub-circuit is electrically connected to the first light-emitting signal terminal, the second light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fourth node, respectively. It is configured to provide the signal from the first power supply terminal to the second node under the control of the signals from the first light-emitting signal terminal and the second light-emitting signal terminal, and to connect the third node and the fourth node.

2. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit includes: a write sub-circuit, a connection sub-circuit, a storage sub-circuit, and a voltage divider sub-circuit; The writing sub-circuit is electrically connected to the first scan signal terminal, the data signal terminal, and the fifth node, respectively, and is configured to provide the data signal terminal to the fifth node under the control of the signal from the first scan signal terminal. The connecting sub-circuit is electrically connected to the second scanning signal terminal, the first node, and the fifth node, respectively, and is configured to connect the first node and the fifth node under the control of the signal at the second scanning signal terminal; The storage sub-circuit is electrically connected to the third node and the fifth node respectively, and is configured to store the voltage difference between the signals of the third node and the fifth node. The voltage divider circuit is electrically connected to the third node and the first signal terminal respectively, and is configured to store the voltage difference between the signals of the third node and the first signal terminal.

3. The pixel driving circuit according to claim 2 further includes: The third control sub-circuit, The third control sub-circuit is electrically connected to the first reset signal terminal, the second reset signal terminal, the second signal terminal, the third signal terminal, the first node, and the fourth node, respectively. It is configured to provide the signal from the second signal terminal to the first node and the signal from the third signal terminal to the fourth node under the control of the signals from the first reset signal terminal and the second reset signal terminal.

4. The pixel driving circuit according to claim 3, wherein, The third control sub-circuit includes: a first reset sub-circuit and a second reset sub-circuit; The first reset sub-circuit is electrically connected to the first reset signal terminal, the second signal terminal, and the first node, respectively, and is configured to provide the signal of the second signal terminal to the first node under the control of the signal of the first reset signal terminal; The second reset sub-circuit is electrically connected to the second reset signal terminal, the third signal terminal, and the fourth node, respectively, and is configured to provide the signal from the third signal terminal to the fourth node under the control of the signal from the second reset signal terminal.

5. The pixel driving circuit according to claim 2, further comprising: Third control sub-circuit; The third control sub-circuit is electrically connected to the first reset signal terminal, the second reset signal terminal, the second signal terminal, the third signal terminal, the fourth node, and the fifth node, respectively. It is configured to provide the signal from the second signal terminal to the fifth node and the signal from the third signal terminal to the fourth node under the control of the signals from the first reset signal terminal and the second reset signal terminal.

6. The pixel driving circuit according to claim 5, wherein, The third control sub-circuit includes: a first reset sub-circuit and a second reset sub-circuit; The first reset sub-circuit is electrically connected to the first reset signal terminal, the second signal terminal, and the fifth node, respectively, and is configured to provide the second signal terminal to the fifth node under the control of the signal from the first reset signal terminal; The second reset sub-circuit is electrically connected to the second reset signal terminal, the third signal terminal, and the fourth node, respectively, and is configured to provide the signal from the third signal terminal to the fourth node under the control of the signal from the second reset signal terminal.

7. The pixel driving circuit according to claim 2, wherein, The communication sub-circuit includes a second transistor, and the writing sub-circuit includes a fourth transistor; The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the fifth node. The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node.

8. The pixel driving circuit according to claim 2, wherein, The storage sub-circuit includes a first capacitor, and the voltage divider sub-circuit includes a second capacitor; The first terminal of the first capacitor is electrically connected to the fifth node, and the second terminal of the first capacitor is electrically connected to the third node. The first terminal of the second capacitor is electrically connected to the first signal terminal, and the second terminal of the second capacitor is electrically connected to the third node.

9. The pixel driving circuit according to claim 4, wherein, The first reset circuit includes a first transistor, and the second reset circuit includes a seventh transistor. The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the second signal terminal, and the second electrode of the first transistor is electrically connected to the first node. The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the third signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

10. The pixel driving circuit according to claim 6, wherein, The first reset circuit includes a first transistor, and the second reset circuit includes a seventh transistor. The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the second signal terminal, and the second electrode of the first transistor is electrically connected to the fifth node. The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the third signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

11. The pixel driving circuit according to claim 1, further comprising: The third control sub-circuit, the driving sub-circuit includes: a third transistor; the first control sub-circuit includes: a second transistor, a fourth transistor, a first capacitor and a second capacitor; the second control sub-circuit includes: a fifth transistor and a sixth transistor; the third control sub-circuit includes: a first transistor and a seventh transistor. The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the second signal terminal, and the second electrode of the first transistor is electrically connected to one of the first node and the fifth node. The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the fifth node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node. The control electrode of the fifth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the second light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node. The control electrode of the seventh transistor is electrically connected to the second reset signal terminal, the first electrode of the seventh transistor is electrically connected to the third signal terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node. The first terminal of the first capacitor is electrically connected to the fifth node, and the second terminal of the first capacitor is electrically connected to the third node. The first terminal of the second capacitor is electrically connected to the first signal terminal, and the second terminal of the second capacitor is electrically connected to the third node. At least one of the first to the seventh transistors is an N-type transistor.

12. The pixel driving circuit according to claim 1, wherein, The signal received by the second scanning signal terminal is the same as the signal received by the first light-emitting signal terminal.

13. The pixel driving circuit according to claim 11, wherein, The pixel driving circuit is connected to the light-emitting device, and the light-emitting device is electrically connected to the fourth node and the second power supply terminal respectively. The signal received by the first signal terminal is the same as the signal received by one of the following signal terminals: the first power terminal, the second power terminal, the second signal terminal, and the third signal terminal.

14. A display device having a display area and a non-display area located on at least one side of the display area, the display area being provided with a plurality of pixel driving circuits as described in any one of claims 1 to 13.

15. The display device according to claim 14, wherein, The non-display area is provided with a first shift register unit, a second shift register unit, a third shift register unit, a fourth shift register unit, and a fifth shift register unit; The first shift register unit is electrically connected to the first scan signal terminal of the multiple pixel driving circuits and is configured to provide signals to the first scan signal terminal of the multiple pixel driving circuits. The second shift register unit is electrically connected to the second scan signal terminal and the first light emission signal terminal of the multiple pixel driving circuits and is configured to provide signals to the second scan signal terminal and the first light emission signal terminal of the multiple pixel driving circuits. The third shift register unit is electrically connected to the second light emission signal terminal of the multiple pixel driving circuits and is configured to provide signals to the second light emission signal terminal of the multiple pixel driving circuits. The fourth shift register unit is electrically connected to the first reset signal terminal of the multiple pixel driving circuits and is configured to provide signals to the first reset signal terminal of the multiple pixel driving circuits. The fifth shift register unit is electrically connected to the second reset signal terminal of the multiple pixel driving circuits and is configured to provide signals to the second reset signal terminal of the multiple pixel driving circuits.

16. The display device according to claim 15, wherein, The time period during which the second shift register unit provides an effective level signal to the first light-emitting signal terminal and the second scanning signal terminal connected to at least one pixel driving terminal circuit includes: a first time period and a second time period, wherein the first time period occurs before the second time period; The time period during which the third shift register unit provides an effective level signal to the second light-emitting signal terminal connected to at least one pixel driving circuit includes: a third time period and a fourth time period, wherein the third time period occurs before the first time period and the fourth time period, and the second time period and the fourth time period at least partially overlap. The time period during which the first shift register unit provides an effective level signal to the first scan signal terminal connected to at least one pixel driving circuit is a fifth time period, the fifth time period occurs between the first time period and the second time period, and the duration of the first time period is greater than the duration of the fifth time period; The time period during which the fourth shift register unit provides an effective level signal to the first reset signal terminal connected to at least one pixel driving circuit is the sixth time period. The sixth time period overlaps at least partially with the first time period and the third time period, and the sixth time period occurs before the fifth time period, and the duration of the sixth time period is greater than the duration of the fifth time period. The first time period is within the sixth time period, and the start time of the third time period is earlier than the start time of the sixth time period, while the end time of the third time period is within the sixth time period.

17. The display device according to claim 16, wherein, The time period during which the fifth shift register unit provides an effective level signal to the second reset signal terminal connected to at least one pixel driving circuit includes: a seventh time period and an eighth time period, wherein the seventh time period occurs before the eighth time period; The seventh time period is located within the third time period and at least partially overlaps with the sixth time period; the eighth time period is located between the fifth time period and the fourth time period. The duration of at least one of the seventh and eighth time periods is less than the duration of the sixth time period, and the duration of the first time period is greater than the duration of the eighth time period.

18. The display device according to claim 16, wherein, The time period during which the fifth shift register unit provides an effective level signal to the second reset signal terminal connected to at least one pixel driving circuit is the seventh time period; The seventh time period is located within the third time period and at least partially overlaps with the sixth time period, and the duration of the seventh time period is less than the duration of the sixth time period.

19. The display device according to claim 18, wherein, The first shift register unit and the fifth shift register unit are the same shift register unit.

20. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as claimed in any one of claims 1 to 13, the method comprising: The driving sub-circuit provides driving signals to the third node under the control of the signals from the first and second nodes; The first control sub-circuit, under the control of the signals from the first scan signal terminal and the second scan signal terminal, adjusts the signals of the first node and the third node through the signals from the data signal terminal and the first signal terminal. The second control sub-circuit, under the control of the signals from the first and second light-emitting signal terminals, provides the signal from the first power supply terminal to the second node and connects the third and fourth nodes.

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