Pixel driving circuit, array substrate and display device

Abstract

A pixel driving circuit is provided. The pixel driving circuit includes a first reset transistor having a gate coupled to a respective first reset control signal line, a compensation transistor having a gate coupled to a respective second gate line, a first light emitting control transistor having a gate coupled to a respective first light emitting control signal line, and a second light emitting control transistor having a gate coupled to a respective second light emitting control signal line. The respective first reset control signal line and the respective second gate line are configured to receive different stages of output control signals from a first scan circuit. The respective first light emitting control signal line and the respective second light emitting control signal line are configured to receive different stages of output control signals from a second scan circuit.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to a pixel driving circuit, an array substrate, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor with a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the selected row of a pixel unit is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is then driven to emit light at a corresponding brightness. Summary of the Invention

[0003] On one hand, this disclosure provides a pixel driving circuit, including: a first reset transistor having a gate coupled to a corresponding first reset control signal line; a compensation transistor having a gate coupled to a corresponding second gate line; a first light-emitting control transistor having a gate coupled to a corresponding first light-emitting control signal line; and a second light-emitting control transistor having a gate coupled to a corresponding second light-emitting control signal line; wherein the corresponding first reset control signal line and the corresponding second gate line are configured to receive output control signals of different levels from a first scanning circuit; and the corresponding first light-emitting control signal line and the corresponding second light-emitting control signal line are configured to receive output control signals of different levels from a second scanning circuit.

[0004] Optionally, the corresponding second gate line is configured to receive an output control signal from the nth stage of the first scanning circuit; and the corresponding first reset control signal line is configured to receive an output control signal from the previous stage of the first scanning circuit.

[0005] Optionally, the corresponding first light emission control signal line is configured to receive an output control signal from the m-th stage of the second scanning circuit; and the corresponding second light emission control signal line is configured to receive an output control signal from the (m-1)-th stage of the second scanning circuit, where m is an integer greater than or equal to 2.

[0006] On the other hand, this disclosure provides an array substrate, including: the pixel driving circuit described herein; a first scanning circuit including a multi-level scanning unit cascaded in series; and a second scanning circuit including a multi-level scanning unit cascaded in series; wherein the first scanning circuit is configured to output an output control signal to a multi-row pixel driving circuit in the array substrate through the multi-level scanning unit; and the second scanning circuit is configured to output an output control signal to the multi-row pixel driving circuit in the array substrate through the multi-level scanning unit.

[0007] On the other hand, this disclosure provides an array substrate including a semiconductor material layer; wherein the semiconductor material layer includes: a plurality of first reset signal lines; and an active layer, a first electrode, and a second electrode of a plurality of transistors of a plurality of pixel driving circuits; wherein a corresponding first reset signal line among the plurality of first reset signal lines is connected to a first electrode of a first reset transistor of a pixel driving circuit in the same row; and the corresponding first reset signal line and the first electrode of the first reset transistor of the pixel driving circuit in the same row are integral structures.

[0008] Optionally, the array substrate further includes a first signal line layer located on the side of the semiconductor material layer away from the substrate; wherein the first signal line layer includes: a plurality of first light emission control signal lines; and a plurality of second light emission control signal lines.

[0009] Optionally, the array substrate further includes: a second gate metal layer located on the side of the semiconductor material layer away from the substrate; and a first signal line layer located on the side of the second gate metal layer away from the substrate; wherein the array substrate includes: a plurality of second reset signal lines; and a plurality of third reset signal lines; wherein the plurality of first reset signal lines are located on the semiconductor material layer; the plurality of second reset signal lines are located in at least one of the second gate metal layer or the first signal line layer; and the plurality of third reset signal lines are located in at least one of the first signal line layer or the second gate metal layer.

[0010] Optionally, the array substrate further includes: a second signal line layer located on the side of the semiconductor material layer away from the substrate; and an anode layer located on the side of the second signal line layer away from the substrate; wherein the second signal line layer includes: a plurality of second voltage supply lines; and a plurality of data lines; wherein the plurality of second voltage supply lines include a first line, a second line, and a third line; the first line, the second line, and the third line are configured to provide reference voltage signals to three adjacent columns of pixel driving circuits, respectively; the first line includes a body, a first ring, and a second ring; the array substrate includes a first opening and a second opening extending through the first line; the first ring includes a first branch at least partially surrounding the first opening; and the second ring includes a second branch at least partially surrounding the second opening.

[0011] Optionally, the orthographic projection of the first anode on the substrate overlaps with the orthographic projection of a portion of the body of the first line on the substrate, overlaps with the orthographic projection of a portion of the first ring of the first line on the substrate, overlaps with the orthographic projection of a portion of the first data line among the plurality of data lines on the substrate, and overlaps with the orthographic projection of a portion of the second line on the substrate.

[0012] Optionally, the array substrate further includes: a storage capacitor including a second capacitor electrode; and a corresponding first gate line; wherein a portion of the corresponding first gate line's orthographic projection on the substrate overlaps with the orthographic projection on the substrate of at least a portion of the second electrode of the semiconductor material layer including the second transistor and / or at least a portion of the second electrode of the first reset transistor; the orthographic projection of a portion of the second capacitor electrode of the storage capacitor on the substrate at least partially overlaps with the orthographic projection on the substrate of the portion of the corresponding first gate line, and overlaps with the portion of the semiconductor material layer including at least the second electrode of the second transistor and / or at least the portion of the second electrode of the first reset transistor on the substrate. The orthographic projections on the substrate at least partially overlap; the orthographic projection of a portion of the corresponding second gate line on the substrate overlaps with the orthographic projections of at least a portion of the second electrode of the semiconductor material layer including the second transistor and / or at least a portion of the second electrode of the first reset transistor on the substrate; and the orthographic projection of a portion of the second capacitor electrode of the storage capacitor on the substrate at least partially overlaps with the orthographic projection of a portion of the corresponding second gate line on the substrate, and at least partially overlaps with the orthographic projections of at least a portion of the second electrode of the semiconductor material layer including the second transistor and / or at least a portion of the second electrode of the first reset transistor on the substrate.

[0013] Optionally, the array substrate further includes: a first gate metal layer located on the side of the semiconductor material layer away from the substrate; and a second gate metal layer located on the side of the first gate metal layer away from the substrate; wherein the first gate metal layer includes a plurality of second light emission control signal lines; and the second gate metal layer includes a plurality of first light emission control signal lines.

[0014] Optionally, the array substrate further includes a first signal line layer located on the side of the second gate metal layer away from the substrate; wherein the first signal line layer includes a second node connection line; the pixel driving circuit in the plurality of pixel driving circuits includes a third reset transistor; the second node connection line is connected to the second electrode of the first light-emitting control transistor and to the second electrode of the third reset transistor; the orthographic projection of the second node connection line on the substrate partially overlaps with the orthographic projection of the corresponding first light-emitting control signal line in the plurality of first light-emitting control signal lines on the substrate, and partially overlaps with the orthographic projection of the corresponding second light-emitting control signal line in the plurality of second light-emitting control signal lines on the substrate.

[0015] Optionally, the array substrate further includes: a first gate metal layer located on the side of the semiconductor material layer away from the substrate; a second gate metal layer located on the side of the first gate metal layer away from the substrate; and a first signal line layer located on the side of the second gate metal layer away from the substrate; wherein the first gate metal layer includes a third gate pad; the pixel driving circuit in the plurality of pixel driving circuits includes a first light-emitting control transistor; the third gate pad includes the gate of the first light-emitting control transistor; the second gate metal layer includes a plurality of first light-emitting control signal lines; the first signal line layer includes a light-emitting control signal connection pad; the light-emitting control signal connection pad is connected to the third gate pad and connected to the corresponding first light-emitting control signal line; and the orthographic projection of the light-emitting control signal connection pad on the substrate does not overlap with the orthographic projection of the semiconductor material layer on the substrate.

[0016] Optionally, the array substrate further includes a second gate metal layer located on the side of the semiconductor material layer away from the substrate; wherein the second gate metal layer includes a plurality of first light-emitting control signal lines; wherein the pixel driving circuit of the plurality of pixel driving circuits includes a first light-emitting control transistor and a driving transistor; wherein the portion of the semiconductor material layer having a first electrode of the first light-emitting control transistor, an active layer, a second electrode, and a first electrode of the driving transistor has a U-shaped form; the orthographic projection of a corresponding first light-emitting control signal line among the plurality of first light-emitting control signal lines on the substrate at least partially overlaps with the orthographic projection of the bottom of the U-shaped form on the substrate; and the bottom of the U-shaped form includes at least a portion of the second electrode of the third transistor.

[0017] Optionally, the array substrate further includes: a second gate metal layer located on the side of the semiconductor material layer away from the substrate; and a first signal line layer located on the side of the second gate metal layer away from the substrate; wherein the first signal line layer includes a second node connection line; the pixel driving circuit in the plurality of pixel driving circuits includes a first light-emitting control transistor, a third reset transistor, and a driving transistor; the second node connection line is connected to the second electrode of the first light-emitting control transistor and to the second electrode of the third reset transistor; the orthographic projection of the second node connection line on the substrate does not overlap with the orthographic projection of the corresponding first light-emitting control signal line among the plurality of first light-emitting control signal lines on the substrate; the orthographic projection of at least a portion of the second electrode of the first light-emitting control transistor and / or at least a portion of the first electrode of the driving transistor in the semiconductor material layer on the substrate at least partially overlaps with the orthographic projection of the corresponding first light-emitting control signal line on the substrate.

[0018] Optionally, the second gate metal layer further includes a second capacitor electrode of a storage capacitor; the orthographic projection of a portion of the corresponding first light-emitting control signal line on the substrate overlaps with the orthographic projection of at least a portion of the second electrode of the semiconductor material layer including the third transistor and / or at least a portion of the first electrode of the driving transistor on the substrate; and the orthographic projection of a portion of the second capacitor electrode of the storage capacitor on the substrate at least partially overlaps with the orthographic projection of the portion of the corresponding first light-emitting control signal line on the substrate, and at least partially overlaps with the orthographic projection of at least said portion of the second electrode of the semiconductor material layer including the third transistor and / or at least said portion of the first electrode of the driving transistor on the substrate.

[0019] Optionally, the array substrate further includes: a second signal line layer located on the side of the semiconductor material layer away from the substrate; and an anode layer located on the side of the second signal line layer away from the substrate; wherein the second signal line layer includes: a plurality of second voltage supply lines; a plurality of data lines; and a plurality of third voltage supply lines; wherein the plurality of second voltage supply lines include a first line, a second line, and a third line; the first line, the second line, and the third line are configured to provide reference voltage signals to three adjacent columns of pixel driving circuits, respectively; the orthographic projection of the first anode on the substrate overlaps with the orthographic projection of a portion of the first line on the substrate, overlaps with the orthographic projection of a portion of a corresponding third voltage supply line among the plurality of third voltage supply lines on the substrate, overlaps with the orthographic projection of a portion of the first data line among the plurality of data lines on the substrate, and overlaps with the orthographic projection of a portion of the second line on the substrate.

[0020] Optionally, the array substrate further includes a light-shielding layer; wherein, the pixel driving circuit in the plurality of pixel driving circuits includes a first reset transistor; the first reset transistor is a dual-gate transistor, and the active layer of the first reset transistor includes two channel portions spaced apart from each other by a first intermediate portion; the first intermediate portion connects the two channel portions of the active layer of the first reset transistor; the semiconductor material layer includes a first protrusion portion protruding from a first main line away from the semiconductor material layer; the first protrusion portion includes at least a portion of the first intermediate portion; the light-shielding layer includes a light-shielding member; the light-shielding member includes a third protrusion portion protruding from a second main line away from the light-shielding member; and the orthographic projection of the third protrusion portion on the substrate covers the orthographic projection of the first protrusion portion on the substrate.

[0021] Optionally, the array substrate further includes: a light-shielding layer; and a first gate metal layer located on the side of the semiconductor material layer away from the light-shielding layer; wherein the pixel driving circuit in the plurality of pixel driving circuits includes a compensation transistor; wherein the first gate metal layer includes a second gate pad; the second gate pad includes the gate of the compensation transistor; the compensation transistor is a dual-gate transistor, and the active layer of the compensation transistor includes two channel portions spaced apart from each other by a second intermediate portion; the second intermediate portion connects the two channel portions of the active layer of the compensation transistor; the semiconductor material layer includes a second protruding portion protruding from a first main line away from the semiconductor material layer; the second protruding portion includes at least a portion of the second intermediate portion; the light-shielding layer includes a light-shielding member; the orthographic projection of the light-shielding member on the substrate covers the orthographic projection of the second protruding portion on the substrate; the second gate pad includes two portions of the gate of the compensation transistor, the two portions of the gate being spaced apart from each other by a connecting portion; and the orthographic projection of the connecting portion on the substrate and the orthographic projection of the light-shielding member on the substrate do not substantially overlap.

[0022] On the other hand, this disclosure provides a display device including the array substrate described herein, and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0025] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0026] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0027] Figure 3A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0028] Figure 3B It is shown Figure 3A A schematic diagram of the arrangement of pixel driving circuits in a portion of an array substrate depicted in the figure.

[0029] Figure 4A It is shown Figure 3A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure.

[0030] Figure 4B It is shown Figure 3A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0031] Figure 4C It is shown Figure 3A A schematic diagram of the structure of the first gate metal layer in a portion of the array substrate depicted in the figure.

[0032] Figure 4D It is shown Figure 3A A schematic diagram of the structure of the second gate metal layer in a portion of the array substrate depicted in the figure.

[0033] Figure 4E It is shown Figure 3A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure.

[0034] Figure 4F It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0035] Figure 4G It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure.

[0036] Figure 4H It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure.

[0037] Figure 4I It is shown Figure 3A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure.

[0038] Figure 4J It is shown Figure 3A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram.

[0039] Figure 4K It is shown Figure 3A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure.

[0040] Figure 5 It is along Figure 3A A cross-sectional view of line A-A' in the diagram.

[0041] Figure 6A This is a schematic diagram illustrating the structure of the second signal line layer and the anode layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0042] Figure 6B This is a schematic diagram illustrating the structure of a second signal line layer and a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0043] Figure 6C This is a schematic diagram illustrating the structure of a first planarization layer, a second signal line layer, and a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0044] Figure 6D This is a schematic diagram illustrating the structure of a semiconductor material layer, a second gate metal layer, a corresponding first gate line, and a corresponding second gate line in a portion of an array substrate according to some embodiments of the present disclosure.

[0045] Figure 6E This is a schematic diagram illustrating the structure of a second capacitor electrode in an array substrate according to some embodiments of the present disclosure.

[0046] Figure 7A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0047] Figure 7B It is shown Figure 7A A schematic diagram of the arrangement of pixel driving circuits in a portion of an array substrate depicted in the figure.

[0048] Figure 8A It is shown Figure 7A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure.

[0049] Figure 8B It is shown Figure 7A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0050] Figure 8C It is shown Figure 7A A schematic diagram of the structure of the first gate metal layer in a portion of the array substrate depicted in the figure.

[0051] Figure 8D It is shown Figure 7A A schematic diagram of the structure of the second gate metal layer in a portion of the array substrate depicted in the figure.

[0052] Figure 8E It is shown Figure 7A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure.

[0053] Figure 8F It is shown Figure 7A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0054] Figure 8G It is shown Figure 7A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure.

[0055] Figure 8H It is shown Figure 7A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure.

[0056] Figure 8I It is shown Figure 7A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure.

[0057] Figure 8J It is shown Figure 7A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram.

[0058] Figure 8K It is shown Figure 7A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure.

[0059] Figure 9A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0060] Figure 9B It is shown Figure 9A A schematic diagram of the arrangement of pixel driving circuits in a portion of an array substrate depicted in the figure.

[0061] Figure 10A It is shown Figure 9A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure.

[0062] Figure 10B It is shown Figure 9A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0063] Figure 10C It is shown Figure 9A A schematic diagram of the structure of the first gate metal layer in a portion of the array substrate depicted in the figure.

[0064] Figure 10D It is shown Figure 9A A schematic diagram of the structure of the second gate metal layer in a portion of the array substrate depicted in the figure.

[0065] Figure 10E It is shown Figure 9A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure.

[0066] Figure 10F It is shown Figure 9AA schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0067] Figure 10G It is shown Figure 9A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure.

[0068] Figure 10H It is shown Figure 9A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure.

[0069] Figure 10I It is shown Figure 9A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure.

[0070] Figure 10J It is shown Figure 9A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram.

[0071] Figure 10K It is shown Figure 9A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure.

[0072] Figure 11A This is a schematic diagram illustrating the structure of a semiconductor material layer and a light-emitting control signal connection pad in a portion of an array substrate according to some embodiments of the present disclosure.

[0073] Figure 11B It is shown Figure 10A A schematic diagram of the structure of a semiconductor material layer and a corresponding first light-emitting control signal line in a portion of an array substrate.

[0074] Figure 11C It is shown Figure 8A A schematic diagram of the structure of a semiconductor material layer and a corresponding first light-emitting control signal line in a portion of an array substrate.

[0075] Figure 12A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0076] Figure 12B It is shown Figure 12A A schematic diagram of the arrangement of pixel driving circuits in a portion of an array substrate depicted in the figure.

[0077] Figure 13A It is shown Figure 12A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure.

[0078] Figure 13B It is shown Figure 12A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0079] Figure 13C It is shown Figure 12A A schematic diagram of the structure of the first gate metal layer in a portion of the array substrate depicted in the figure.

[0080] Figure 13D It is shown Figure 12A A schematic diagram of the structure of the second gate metal layer in a portion of the array substrate depicted in the figure.

[0081] Figure 13E It is shown Figure 12A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure.

[0082] Figure 13F It is shown Figure 12A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0083] Figure 13G It is shown Figure 12A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure.

[0084] Figure 13H It is shown Figure 12A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure.

[0085] Figure 13I It is shown Figure 12A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure.

[0086] Figure 13J It is shown Figure 12A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram.

[0087] Figure 13K It is shown Figure 12A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure.

[0088] Figure 14 It is shown Figure 13A The diagram depicts a portion of an array substrate containing a semiconductor material layer, a second gate metal layer, a second node connection line, and a corresponding first light-emitting control signal line.

[0089] Figure 15A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0090] Figure 15BIt is shown Figure 15A A schematic diagram of the arrangement of pixel driving circuits in a portion of an array substrate depicted in the figure.

[0091] Figure 16A It is shown Figure 15A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure.

[0092] Figure 16B It is shown Figure 15A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0093] Figure 16C It is shown Figure 15A A schematic diagram of the structure of the first gate metal layer in a portion of the array substrate depicted in the figure.

[0094] Figure 16D It is shown Figure 15A A schematic diagram of the structure of the second gate metal layer in a portion of the array substrate depicted in the figure.

[0095] Figure 16E It is shown Figure 15A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure.

[0096] Figure 16F It is shown Figure 15A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0097] Figure 16G It is shown Figure 15A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure.

[0098] Figure 16H It is shown Figure 15A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure.

[0099] Figure 16I It is shown Figure 15A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure.

[0100] Figure 16J It is shown Figure 15A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram.

[0101] Figure 16K It is shown Figure 15A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure.

[0102] Figure 17AThis is a schematic diagram illustrating the structure of the second signal line layer and the anode layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0103] Figure 17B This is a schematic diagram illustrating the structure of a second signal line layer and a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0104] Figure 17C This is a schematic diagram illustrating the structure of a first planarization layer, a second signal line layer, and a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0105] Figure 18A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0106] Figure 18B It is shown Figure 18A A schematic diagram of the arrangement of pixel driving circuits in a portion of an array substrate depicted in the figure.

[0107] Figure 19A It is shown Figure 18A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure.

[0108] Figure 19B It is shown Figure 18A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0109] Figure 19C It is shown Figure 18A A schematic diagram of the structure of the first gate metal layer in a portion of the array substrate depicted in the figure.

[0110] Figure 19D It is shown Figure 18A A schematic diagram of the structure of the second gate metal layer in a portion of the array substrate depicted in the figure.

[0111] Figure 19E It is shown Figure 18A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure.

[0112] Figure 19F It is shown Figure 18A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0113] Figure 19G It is shown Figure 18A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure.

[0114] Figure 19H It is shown Figure 18A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure.

[0115] Figure 19I It is shown Figure 18A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure.

[0116] Figure 19J It is shown Figure 18A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram.

[0117] Figure 19K It is shown Figure 18A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure.

[0118] Figure 20A It is shown Figure 18A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0119] Figure 20B It is shown Figure 18A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0120] Figure 20C It is shown Figure 18A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure.

[0121] Figure 20D It is shown Figure 18A A schematic diagram of the structure of the second gate pad in a portion of the array substrate depicted in the figure.

[0122] Figure 20E It is shown Figure 18A A schematic diagram of the structure of the semiconductor material layer, the light-shielding layer, and the second gate pad in a portion of the array substrate depicted in the diagram. Specific Implementation

[0123] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0124] This disclosure provides, in particular, a pixel driving circuit, an array substrate, and a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a pixel driving circuit. In some embodiments, the pixel driving circuit includes: a first reset transistor having a gate coupled to a corresponding first reset control signal line; a compensation transistor having a gate coupled to a corresponding second gate line; a first light-emitting control transistor having a gate coupled to a corresponding first light-emitting control signal line; and a second light-emitting control transistor having a gate coupled to a corresponding second light-emitting control signal line. Optionally, the corresponding first reset control signal line and the corresponding second gate line are configured to receive different levels of output control signals from a first scan circuit. Optionally, the corresponding first light-emitting control signal line and the corresponding second light-emitting control signal line are configured to receive different levels of output control signals from a second scan circuit.

[0125] Various suitable pixel driving circuits can be used in the array substrate of this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is an 8T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate of this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0126] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1 The array substrate includes an array of sub-pixels Sp. Each sub-pixel includes electronic components such as a light-emitting element. In one example, the light-emitting element is driven by a respective pixel driving circuit PDC. The array substrate includes multiple first gate lines GL1, multiple second gate lines GL2, multiple data lines DL, multiple first voltage supply lines (e.g., each first voltage supply line Vdd), and multiple second voltage supply lines (e.g., each second voltage supply line Vss). Each sub-pixel Sp is driven to emit light by the respective pixel driving circuit PDC. In one example, a high voltage signal (e.g., VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via each high voltage supply line Vdd; a low voltage signal (e.g., VSS signal) is input to the cathode of the light-emitting element via a low voltage supply line. The voltage difference between the high voltage signal (e.g., VDD signal) and the low voltage signal (e.g., VSS signal) is the driving voltage ΔV that drives the light-emitting element to emit light.

[0127] Figure 2AThis is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2A In some embodiments, the pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first reset transistor Tr1 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of a fourth transistor T4 and the anode of the light-emitting element LE; a third reset transistor Tr3 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to the first electrode of the driving transistor Td; the first transistor T1 (e.g., A data write transistor has a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of a driving transistor Td; a second transistor T2 (e.g., a compensation transistor) has a gate connected to a corresponding second gate line GL2 among a plurality of second gate lines, a first electrode connected to a first capacitor electrode Ce1 of a storage capacitor Cst and a gate of a driving transistor Td, and a second electrode connected to a second electrode of a driving transistor Td; a third transistor T3 has a gate connected to a corresponding first light emission control signal line em1 among a plurality of first light emission control signal lines, a first electrode connected to a corresponding first voltage supply line Vdd among a plurality of first voltage supply lines, and a second electrode connected to a first electrode of a driving transistor Td and a second electrode of a first transistor T1; and a fourth transistor T4 has a gate connected to a corresponding second light emission control signal line em2 among a plurality of second light emission control signal lines, a first electrode connected to a second electrode of a driving transistor Td and a second electrode of a second transistor T2, and a second electrode connected to the anode of a light-emitting element LE and a second electrode of a second reset transistor Tr2. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0128] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a first transistor T1), a compensation transistor (e.g., a second transistor T2), two light-emitting control transistors (e.g., a third transistor T3 and a fourth transistor T4), and three reset transistors (e.g., a first reset transistor Tr1, a second reset transistor Tr2, and a third reset transistor Tr3).

[0129] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, wherein the first terminal and the second terminal are connected to the active layer of the transistor. The direction of current flow through the transistor can be configured from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flow through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0130] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, the first electrode of the second transistor T2, and the second electrode of the first reset transistor Tr1. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the second transistor T2, and the first electrode of the fourth transistor T4. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the second reset transistor Tr2, and the anode of the light-emitting element LE.

[0131] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes each first sub-pixel, each second sub-pixel, and each third sub-pixel. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array of the form S1-S2-S3, where S1 represents each first sub-pixel, S2 represents each second sub-pixel, and S3 represents each third sub-pixel. In another example, the S1-S2-S3 form is a C1-C2-C3 form, where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, and C3 represents each third sub-pixel of a third color. In another example, the C1-C2-C3 form is an RGB form, where each first sub-pixel is a red sub-pixel, each second sub-pixel is a green sub-pixel, and each third sub-pixel is a blue sub-pixel.

[0132] In another example, the array of multiple sub-pixels includes a repeating array of the form S1-S2-S3-S4, where S1 represents each first sub-pixel, S2 represents each second sub-pixel, S3 represents each third sub-pixel, and S4 represents each fourth sub-pixel. In another example, the S1-S2-S3-S4 form is C1-C2-C3-C4, where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, C3 represents each third sub-pixel of a third color, and C4 represents each fourth sub-pixel of a fourth color. In yet another example, the S1-S2-S3-S4 form is C1-C2-C3-C2', where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, C3 represents each third sub-pixel of a third color, and C2' represents each fourth sub-pixel of a second color. In another example, the C1-C2-C3-C2' form is RGBG, where each first subpixel is a red subpixel, each second subpixel is a green subpixel, each third subpixel is a blue subpixel, and each fourth subpixel is a green subpixel.

[0133] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a driving transistor Td, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a storage capacitor Cst.

[0134] In an alternative embodiment, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a driving transistor Td, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a storage capacitor Cst.

[0135] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. (See also...) Figure 2A All transistors are p-type transistors, such as polysilicon transistors. For p-type transistors, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0136] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2A and Figure 2B During one frame of an image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light emission sub-stage t3. In the initial sub-stage t0, a cutoff reset control signal is provided to the gate of the first reset transistor Tr1 via the corresponding first reset control signal line rst1, causing the first reset transistor Tr1 to turn off. A cutoff reset control signal is provided to the gates of the second reset transistor Tr2 and the third reset transistor Tr3 via the corresponding second reset control signal line rst2, causing the second reset transistor Tr2 and the third reset transistor Tr3 to turn off. In the initial sub-stage t0, cutoff signals are provided to the corresponding first gate line GL1 and the corresponding second gate line GL2, thus turning off the first transistor T1 and the second transistor T2.

[0137] In reset phase t1, a reset control signal is provided to the gate of the first reset transistor Tr1 via the first reset control signal line rst1, turning on the first reset transistor Tr1. This allows the initialization voltage signal from the corresponding first reset signal line Vint1 to be transmitted from the first electrode of the first reset transistor Tr1 to its second electrode, and then to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high-voltage signal from the corresponding first voltage supply line Vdd. Due to the increased voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in reset phase t1. In reset phase t1, cutoff signals are provided to the corresponding first gate line GL1 and the corresponding second gate line GL2, thus turning off the first transistor T1 and the second transistor T2. A high-voltage signal is provided to the corresponding first light-emitting control signal line em1 to turn off the third transistor T3, and a high-voltage signal is provided to the corresponding second light-emitting control signal line em2 to turn off the fourth transistor T4.

[0138] During the data write sub-stage t2, the cutoff reset control signal is again provided to the gate of the first reset transistor Tr1 via the corresponding first reset control signal line rst1, causing the first reset transistor Tr1 to turn off. The corresponding first gate line GL1 and the corresponding second gate line GL2 are provided with conduction signals, thus turning on the first transistor T1 and the second transistor T2. The second electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the first electrode of the second transistor T2. Because the second transistor T2 is turned on during the data write sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thus putting the driving transistor Td in diode connection mode. The first transistor T1 is turned on during the data write sub-stage t2. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and then transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. Node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Because only the PN junction between the gate of the driving transistor Td and the first electrode is active, the voltage level of the first node N1 gradually increases to (Vdata + Vth) during the data writing sub-stage t2, where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. A high voltage signal is provided to the corresponding first light-emitting control signal line em1 to turn off the third transistor T3, and a high voltage signal is provided to the corresponding second light-emitting control signal line em2 to turn off the fourth transistor T4.

[0139] In data writing sub-stage t2, the turn-on reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, causing the second reset transistor Tr2 to turn on. This allows the initialization voltage signal from the corresponding second reset signal line Vint2 to be transmitted from the first electrode of the second reset transistor Tr2 to the second electrode, and then to node N4. The anode of the light-emitting element LE is initialized. The turn-on reset control signal is provided to the gate of the third reset transistor Tr3 via the corresponding second reset control signal line rst2, causing the third reset transistor Tr3 to turn on. This allows the initialization voltage signal from the corresponding second reset signal line Vint2 to be transmitted from the first electrode of the third reset transistor Tr3 to the second electrode, and then to node N2. Node N2 is initialized.

[0140] In the light-emitting phase t3, the cutoff reset control signal is again provided to the gate of the first reset transistor Tr1 through the corresponding first reset control signal line rst1, causing the first reset transistor Tr1 to turn off. The corresponding first gate line GL1 and the corresponding second gate line GL2 are provided with cutoff signals, thus turning off the first transistor T1 and the second transistor T2. The corresponding first light-emitting control signal line em1 is provided with a low voltage signal to turn on the third transistor T3, and the corresponding second light-emitting control signal line em2 is provided with a low voltage signal to turn on the fourth transistor T4. In the light-emitting phase t3, the voltage level of the first node N1 is maintained at (Vdata + Vth), the driving transistor Td is turned on by this voltage level, and it operates in the saturation region. A path is formed through the third transistor T3, the driving transistor Td, the fourth transistor T4, and the light-emitting element LE. The driving transistor Td generates a driving current for driving the light-emitting element LE to emit light. The voltage level at node N3, connected to the second electrode of the driving transistor Td, is equal to the emission voltage of the light-emitting element LE.

[0141] In some embodiments, the corresponding first reset control signal line rst1 and the corresponding second gate line GL2 are configured to receive output control signals of different levels from the first scan circuit. In some embodiments, the corresponding second gate line GL2 is configured to receive the output control signal of the nth level from the first scan circuit, and the corresponding first reset control signal line rst1 is configured to receive the output control signal of the previous level from the first scan circuit. In one example, the corresponding first reset control signal line rst1 is configured to receive the output control signal of the (n-5)th level from the first scan circuit, where n is an integer greater than or equal to 6.

[0142] In some embodiments, the corresponding first light emission control signal line em1 and the corresponding second light emission control signal line em2 are configured to receive output control signals of different levels from the second scanning circuit. In some embodiments, the corresponding first light emission control signal line em1 is configured to receive the m-th level output control signal from the second scanning circuit, and the corresponding second light emission control signal line em2 is configured to receive the (m-1)-th level output control signal from the second scanning circuit, where m is an integer greater than or equal to 2.

[0143] In some embodiments, the array substrate further includes a first scanning circuit comprising a series-cascaded multi-level scanning unit. In some embodiments, the first scanning circuit is configured to output an output control signal to a multi-row pixel driving circuit in the array substrate via the multi-level scanning unit. In some embodiments, the nth level scanning unit of the first scanning circuit is configured to output an output control signal to the gate of the second transistor T2 in the pixel driving circuit via a corresponding second gate line GL2, and the preceding level scanning unit of the first scanning circuit is configured to output an output control signal to the gate of the first reset transistor Tr1 in the pixel driving circuit via a corresponding first reset control signal line rst1. In one example, the (n-5)th level scanning unit of the first scanning circuit is configured to output an output control signal to the gate of the first reset transistor Tr1 in the pixel driving circuit via a corresponding first reset control signal line rst1, where n is an integer greater than or equal to 6. When both the second transistor T2 and the first reset transistor Tr1 are turned on, the voltage at the third node N3 is reset, thereby providing a uniform bias state to the driving transistor Td.

[0144] In some embodiments, the array substrate further includes a second scanning circuit, which includes a series-cascaded multi-level scanning unit. In some embodiments, the second scanning circuit is configured to output an output control signal to a multi-row pixel driving circuit in the array substrate through the multi-level scanning unit. In some embodiments, the m-th level scanning unit of the second scanning circuit is configured to output an output control signal to the gate of the first light-emitting control transistor T3 in the pixel driving circuit through a corresponding first light-emitting control signal line em1, and the (m-1)-th level scanning unit of the second scanning circuit is configured to output an output control signal to the gate of the second light-emitting control transistor T4 in the pixel driving circuit through a corresponding second light-emitting control signal line em2, where m is an integer greater than or equal to 2.

[0145] Figure 3A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 3B It is shown Figure 3A A schematic diagram of the arrangement of pixel driving circuits in a portion of an array substrate depicted in the figure. Figure 4A It is shown Figure 3A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure. Figure 4B It is shown Figure 3A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 4C It is shown Figure 3A A schematic diagram of the structure of the first gate metal layer in a portion of the array substrate depicted in the figure. Figure 4D It is shown Figure 3AA schematic diagram of the structure of the second gate metal layer in a portion of the array substrate depicted in the figure. Figure 4E It is shown Figure 3A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure. Figure 4F It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure. Figure 4G It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure. Figure 4H It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure. Figure 4I It is shown Figure 3A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure. Figure 4J It is shown Figure 3A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram. Figure 4K It is shown Figure 3A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure. Figure 5 It is along Figure 3A A cross-sectional view of line A-A' in the diagram. Figure 3A , Figure 3B , Figures 4A to 4K ,and Figure 5 A portion of an array substrate is depicted having three adjacent pixel driving circuits arranged in a row, the three adjacent pixel driving circuits including PDC1, PDC2 and PDC3.

[0146] Reference Figure 3A , Figure 3B , Figures 4A to 4K ,and Figure 5In some embodiments, the array substrate includes a substrate BS, a light-shielding layer LSL on the substrate BS, a buffer layer BUF on the side of the light-shielding layer LSL away from the substrate BS, a semiconductor material layer SML on the side of the buffer layer BUF away from the substrate BS, a gate insulating layer GI on the side of the semiconductor material layer SML away from the substrate BS, a first gate metal layer Gate1 on the side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN on the side of the first gate metal layer Gate1 away from the gate insulating layer GI, a second gate metal layer Gate2 on the side of the insulating layer IN away from the first gate metal layer Gate1, and a second gate metal layer Ga... The interlayer dielectric layer ILD located on the side of te2 away from the insulating layer IN, the first signal line layer SD1 located on the side of the interlayer dielectric layer ILD away from the second gate metal layer Gate2, the first planarization layer PLN1 located on the side of the first signal line layer SD1 away from the interlayer dielectric layer ILD, the second signal line layer SD2 located on the side of the first planarization layer PLN1 away from the first signal line layer SD1, the second planarization layer PLN2 located on the side of the second signal line layer SD2 away from the first planarization layer PLN1, the anode layer ADL located on the side of the second planarization layer PLN2 away from the second signal line layer SD2, and the pixel definition layer PDL located on the side of the anode layer ADL away from the second planarization layer PLN2.

[0147] Reference Figure 2A , Figure 3A , Figure 3B and Figure 4A In some embodiments, the light-shielding layer LSL includes a light-shielding element LS.

[0148] Reference Figure 2A , Figure 3A , Figure 3B and Figure 4BIn some embodiments, the semiconductor material layer SML includes an active layer of at least a plurality of transistors of a pixel driving circuit, the plurality of transistors including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td. Optionally, the semiconductor material layer SML also includes at least corresponding portions of the first electrodes of the plurality of transistors of the pixel driving circuit, the plurality of transistors including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the semiconductor material layer SML also includes at least corresponding portions of the second electrodes of the plurality of transistors of the pixel driving circuit, the plurality of transistors including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the semiconductor material layer SML includes an active layer of multiple transistors for a pixel driving circuit, a first electrode, and a second electrode. The multiple transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td. Various suitable semiconductor materials can be used to fabricate the semiconductor material layer SML. Examples of semiconductor materials used to fabricate the semiconductor material layer SML include silicon-based semiconductor materials such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0149] Figure 4B The transistors are labeled with markings indicating components of each of the multiple transistors (T1, T2, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0150] Optionally, the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, ACTr3, and ACTd), the first electrodes (S1, S2, S3, S4, Sr1, Sr2, Sr3, and Sd), and the second electrodes (D1, D2, D3, D4, Dr1, Dr2, Dr3, and Dd) of each transistor (T1, T2, T3, T4, Tr1, Tr2, Tr3, and Td) are located on the same layer.

[0151] In some embodiments, at least a portion of the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, ACTr3, and ACTd) of the plurality of transistors (T1, T2, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, Sr3, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, Dr3, and Dd) are integral structures.

[0152] In some embodiments, the semiconductor material layer SML further includes a plurality of first reset signal lines (e.g., individual first reset signal lines Vint1). In some embodiments, the corresponding first reset signal line Vint1 is connected to the first electrode of the first reset transistor of the pixel driving circuit in the same row. In some embodiments, the corresponding first reset signal line Vint1, the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, ACTr3, and ACTd) of the plurality of transistors (T1, T2, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, Sr3, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, Dr3, and Dd) are an integral structure. In some embodiments, the corresponding first reset signal line Vint1, the active layers of the transistors in the pixel driving circuit in the same row, the first electrode, and the second electrode are an integral structure.

[0153] Reference Figure 2A , Figure 3A , Figure 3B and Figure 4C In some embodiments, the first gate metal layer Gate1 includes a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a first capacitor electrode Ce1 of the storage capacitor Cst, a first gate pad GEP1, a second gate pad GEP2, a third gate pad GEP3, a fourth gate pad GEP4, and a fifth gate pad GEP5.

[0154] Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first gate metal layer Gate1. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the respective second reset control signal line rst2, the first capacitor electrode Ce1 of the storage capacitor Cst, the first gate pad GEP1, the second gate pad GEP2, the third gate pad GEP3, the fourth gate pad GEP4, and the fifth gate pad GEP5 are located in the same layer.

[0155] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, when the respective second reset control signal lines rst2 and the first capacitor electrode Ce1 are formed by one or more steps of the same patterning process on the same material layer, the respective second reset control signal lines rst2 and the first capacitor electrode Ce1 are located in the same layer. In another example, multiple second reset signal lines rst2 and first capacitor electrodes Ce1 can be formed in the same layer by simultaneously performing the steps of forming the respective second reset control signal lines rst2 and the steps of forming the first capacitor electrode Ce1. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0156] In some embodiments, the first gate pad GEP1 includes the gate G1 of the first transistor T1 in the pixel driving circuit. In some embodiments, the second gate pad GEP2 includes the gate G2 of the second transistor T2 in the pixel driving circuit. In some embodiments, the third gate pad GEP3 includes the gate G3 of the third transistor T3 in the pixel driving circuit. In some embodiments, the fourth gate pad GEP4 includes the gate G4 of the fourth transistor T4 in the pixel driving circuit. In some embodiments, the fifth gate pad GEP5 includes the gate Gr1 of the first reset transistor Tr1 in the pixel driving circuit. The first gate pad GEP1 is connected to a corresponding first gate line GL1 among a plurality of first gate lines. The second gate pad GEP2 is connected to a corresponding second gate line GL2 among a plurality of second gate lines. The third gate pad GEP3 is connected to a corresponding first light emission control signal line em1 among a plurality of first light emission control signal lines. The fourth gate pad GEP4 is connected to a corresponding second light emission control signal line em2 among a plurality of second light emission control signal lines. The fifth gate pad GEP5 is connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines.

[0157] Reference Figure 2A, Figure 3A , Figure 3B and Figure 4D In some embodiments, the second gate metal layer Gate2 includes a plurality of second reset signal lines (e.g., individual second reset signal lines Vint2) and a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the second gate metal layer Gate2. For example, a conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of second reset signal lines and the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0158] Figure 4E The image depicts vias extending through the interlayer dielectric layer (ILD).

[0159] Reference Figure 2A , Figure 3A , Figure 3B and Figure 4F In some embodiments, the first signal line layer SD1 includes a plurality of first reset control signal lines (e.g., each first reset control signal line rst1), a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of first gate lines (e.g., each first gate line GL1), a plurality of second gate lines (e.g., each second gate line GL2), a plurality of first light emission control signal lines (e.g., each first light emission control signal line em1), a plurality of second light emission control signal lines (e.g., each second light emission control signal line em2), a plurality of third reset signal lines (e.g., each third reset signal line Vint3), a plurality of first voltage supply lines (e.g., each first voltage supply line Vdd1), a first node connection line Cln1, a data signal connection pad DCP, a relay electrode RE, and a reset signal connection pad Cli.

[0160] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer SD1. For example, the conductive material can be deposited on the substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the first signal line layer comprises a plurality of sublayers stacked together. In one example, the first signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure.

[0161] Optionally, multiple first reset control signal lines (e.g., each first reset control signal line rst1), multiple second reset control signal lines (e.g., each second reset control signal line rst2), multiple first gate lines (e.g., each first gate line GL1), multiple second gate lines (e.g., each second gate line GL2), multiple first light emission control signal lines (e.g., each first light emission control signal line em1), multiple second light emission control signal lines (e.g., each second light emission control signal line em2), multiple third reset signal lines (e.g., each third reset signal line Vint3), multiple first voltage supply lines (e.g., each first voltage supply line Vdd1), a first node connection line Cln1, a data signal connection pad DCP, a relay electrode RE, and a reset signal connection pad Cli are located on the same layer.

[0162] In some embodiments, the first node connection line Cln1 in the pixel driving circuit connects multiple components of the pixel driving circuit to the first node N1. (Refer to...) Figure 5 The first node connection line Cln1 is connected to the first capacitor electrode Ce1 through the first via v1, and to the second transistor T2 (e.g., connected to the second electrode D2 of the second transistor T2) through the second via v2. Optionally, the first node connection line Cln1 corresponds to Figure 2A The first node N1 is depicted in the diagram.

[0163] Reference Figure 2A , Figure 3A , Figure 3B , Figure 4C , Figure 4D , Figure 4F and Figure 5In some embodiments, the second capacitor electrode Ce2 is absent from the via region H. Optionally, except for the via region H in which the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 onto the substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers and extends beyond the orthographic projection of the first capacitor electrode Ce1 onto the substrate BS. Optionally, the first via v1 extends through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0164] Reference Figure 4A , Figure 4F , Figure 4H and Figure 5 In the pixel driving circuit, the data signal connection pad DCP connects the corresponding data line DL to the first electrode S1 of the first transistor T1, and the data signal provided by the corresponding data line DL is transmitted to the first electrode S1 of the first transistor T1 through the signal connection pad DCP.

[0165] Reference Figure 4A , Figure 4F , Figure 4H and Figure 5 The relay electrode RE connects the anode connection pad ACP to the second electrode D4 of the fourth transistor T4 in the pixel driving circuit. The anode connection pad ACP is also connected to the anode of the light-emitting element.

[0166] Reference Figure 3A , Figure 3B Figure 3D, Figure 3I Figure 4A and Figure 4B The reset signal connection line Cli connects the corresponding second reset signal line Vint2 to the first electrode Sr2 of the second reset transistor Tr2 in the pixel driving circuit, thereby providing a reset signal to the first electrode Sr2 of the second reset transistor Tr2 in the pixel driving circuit.

[0167] In some embodiments, the reset signal connection line Cli in at least one pixel driving circuit is also connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines in the second signal line layer SD2.

[0168] In some embodiments, the relay electrode RE is connected to the second electrode of the fourth transistor and the second electrode of the second reset transistor, and is also connected to the anode connection pad.

[0169] Figure 4G The image depicts vias extending through the first planarization layer PLN1.

[0170] Reference Figure 2A, Figure 3A , Figure 3B ,and Figure 4H In some embodiments, the second signal line layer SD2 includes a plurality of second voltage supply lines (e.g., each second voltage supply line Vdd2), a plurality of data lines (e.g., each data line DL), a plurality of fourth reset signal lines (e.g., each fourth reset signal line Vint4), and an anode connection pad ACP.

[0171] In some embodiments, a plurality of first voltage supply lines and a plurality of second voltage supply lines are configured to provide a first reference voltage signal. In one example, the first reference voltage signal is a constant voltage signal, such as a high reference voltage signal.

[0172] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer SD2. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer SD2 include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the second signal line layer comprises multiple sublayers stacked together. In one example, the second signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple second voltage supply lines (e.g., individual second voltage supply lines Vdd2), multiple data lines (e.g., individual data lines DL), multiple fourth reset signal lines (e.g., individual fourth reset signal lines Vint4), and an anode connection pad ACP are located in the same layer.

[0173] In some embodiments, a plurality of first voltage supply lines are configured to provide a first reference voltage signal. In one example, the first reference voltage signal is a constant voltage signal, such as a high reference voltage signal.

[0174] Figure 4I The image depicts vias extending through the second planarization layer PLN2.

[0175] Reference Figure 2A , Figure 3A , Figure 3B and Figure 4J In some embodiments, the anode layer ADL includes multiple anodes AD.

[0176] Reference Figure 2A , Figure 3A , Figure 3B and Figure 4K In some embodiments, the array substrate includes a plurality of sub-pixel openings SA extending through the pixel defining layer PDL.

[0177] In some embodiments, refer to Figure 2A , Figure 3A , Figure 3B , Figures 4A to 4K ,as well as Figure 5 Multiple first reset signal lines are located in the semiconductor material layer SML. In some embodiments, a corresponding first reset signal line Vint1 of the multiple first reset signal lines is connected to the first electrode of the first reset transistor of the pixel driving circuit in the same row. In some embodiments, the corresponding first reset signal line Vint1 and the first electrode of the first reset transistor of the pixel driving circuit in the same row are integral structures. In some embodiments, the corresponding first reset signal line Vint1, the active layer of the multiple transistors in the pixel driving circuit, at least a portion of the first electrode, and at least a portion of the second electrode are integral structures. In some embodiments, the corresponding first reset signal line Vint1, at least a portion of the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, ACTr3, and ACTd) of all transistors (T1, T2, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, Sr3, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, Dr3, and Dd) are integral structures. The inventors of this disclosure have discovered that by providing multiple first reset signal lines in the semiconductor material layer SML, the need to form vias in the array substrate is eliminated.

[0178] In some embodiments, a plurality of first light emission control signal lines and a plurality of second light emission control signal lines are located in a first signal line layer SD1. The first signal line layer SD1 is made of a conductive material with relatively low resistance, so that when the plurality of first light emission control signal lines and the plurality of second light emission control signal lines are formed in the first signal line layer SD1, they have relatively low resistance.

[0179] In some embodiments, a plurality of first reset signal lines are located in the semiconductor material layer SML, a plurality of second reset signal lines are located in the second gate metal layer Gate2, and a plurality of third reset signal lines are located in the first signal line layer SD1.

[0180] Figure 6A This is a schematic diagram illustrating the structure of the second signal line layer and the anode layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 6B This is a schematic diagram illustrating the structure of a second signal line layer and a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 6A , Figure 6B , Figure 2A , Figure 3A , Figure 3B , Figures 4A to 4K ,as well as Figure 5 In some embodiments, at least one of the plurality of second voltage supply lines includes a body MB and a ring LP. In some embodiments, the array substrate includes an opening AP extending through at least one second voltage supply line, wherein the ring LP includes a branch BH at least partially surrounding the opening AP. In some embodiments, the branch BH extends along a second direction DR2; the body MB, the opening AP, and the branch BH are arranged along a first direction DR1, which is different from the second direction DR2. In one example, the first direction DR1 and the second direction DR2 are perpendicular to each other. In some embodiments, the plurality of second voltage supply lines are arranged along the first direction DR1. In some embodiments, the plurality of data lines are arranged along the first direction DR1. In some embodiments, the plurality of fourth reset signal lines are arranged along the first direction DR1.

[0181] In some embodiments, the array substrate includes three of a plurality of second voltage supply lines, including a first line Vdd2-1, a second line Vdd2-2, and a third line Vdd2-3. In some embodiments, the first line Vdd2-1, the second line Vdd2-2, and the third line Vdd2-3 are configured to provide reference voltage signals to three adjacent columns of pixel driving circuits, respectively. In some embodiments, the first line Vdd2-1 includes a loop LP, while the second line Vdd2-2 and the third line Vdd2-3 do not include loops.

[0182] In some embodiments, the orthographic projection of the first anode AD1 onto the substrate at least partially overlaps with the orthographic projection of the first line Vdd2-1 onto the substrate, and at least partially overlaps with the orthographic projection of the second line Vdd2-2 onto the substrate. Optionally, the orthographic projection of the first anode AD1 onto the substrate does not overlap with the orthographic projection of the third line Vdd2-3 onto the substrate. Optionally, the first anode AD1 is the anode in a sub-pixel configured to receive a reference voltage signal from the first line Vdd2-1.

[0183] In some embodiments, the orthographic projection of the second anode AD2 onto the substrate at least partially overlaps with the orthographic projection of the first line Vdd2-1 onto the substrate, and at least partially overlaps with the orthographic projection of the second line Vdd2-2 onto the substrate. Optionally, the orthographic projection of the second anode AD2 onto the substrate does not overlap with the orthographic projection of the third line Vdd2-3 onto the substrate. Optionally, the second anode AD2 is the anode in a sub-pixel configured to receive a reference voltage signal from the second line Vdd2-2.

[0184] In some embodiments, the orthographic projection of the third anode AD3 onto the substrate at least partially overlaps with the orthographic projection of the third line Vdd2-3 onto the substrate. Optionally, the orthographic projection of the third anode AD3 onto the substrate does not overlap with the orthographic projection of the first line Vdd2-1 onto the substrate, and does not overlap with the orthographic projection of the second line Vdd2-2 onto the substrate. Optionally, the third anode AD3 is the anode in a sub-pixel configured to receive a reference voltage signal from the third line Vdd2-3.

[0185] In some embodiments, the first line Vdd2-1 includes a body MB, a first ring LP1, and a second ring LP2. In some embodiments, the array substrate includes a first opening AP1 and a second opening AP2 extending through the first line Vdd2-1. Optionally, the first ring LP1 includes a first branch BH1 that at least partially surrounds the first opening AP1. Optionally, the second ring LP2 includes a second branch BH2 that at least partially surrounds the second opening AP2.

[0186] In some embodiments, the first branch BH1 and the second branch BH2 extend along the second direction DR2; the body MB, the first opening AP1, and the first branch BH1 are arranged along the first direction DR1; the body MB, the second opening AP2, and the second branch BH are arranged along the first direction DR1, and the first direction DR1 and the second direction DR2 are different from each other. In one example, the first direction DR1 and the second direction DR2 are perpendicular to each other. In some embodiments, a plurality of second voltage supply lines are arranged along the first direction DR1. In some embodiments, a plurality of data lines are arranged along the first direction DR1. In some embodiments, a plurality of fourth reset signal lines are arranged along the first direction DR1.

[0187] In some embodiments, the orthographic projection of the first anode AD1 on the substrate overlaps with the orthographic projection of a portion of the body MB of the first line Vdd2-1 on the substrate, overlaps with the orthographic projection of a portion of the first ring LP1 of the first line Vdd2-1 on the substrate, overlaps with the orthographic projection of a portion of the first data line DL1 among a plurality of data lines on the substrate, and overlaps with the orthographic projection of a portion of the second line Vdd2-2 on the substrate.

[0188] In some embodiments, the orthographic projections of a portion of the body MB of the first line Vdd2-1, a portion of the first ring LP1 of the first line Vdd2-1, a portion of the first data line DL1 among a plurality of data lines, and a portion of the second line Vdd2-2 on the substrate are substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) uniformly distributed relative to the orthographic projection of the first anode AD1 on the substrate.

[0189] In some embodiments, the orthographic projection of the second anode AD2 on the substrate overlaps with the orthographic projection of a portion of the body MB of the first line Vdd2-1 on the substrate, overlaps with the orthographic projection of a portion of the second ring LP2 of the first line Vdd2-1 on the substrate, overlaps with the orthographic projection of a portion of the first data line DL1 among a plurality of data lines on the substrate, and overlaps with the orthographic projection of a portion of the second line Vdd2-2 on the substrate.

[0190] In some embodiments, the orthographic projections of a portion of the body MB of the first line Vdd2-1, a portion of the second ring LP2 of the first line Vdd2-1, a portion of the first data line DL1 among a plurality of data lines, and a portion of the second line Vdd2-2 on the substrate are substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) uniformly distributed relative to the orthographic projection of the second anode AD2 on the substrate.

[0191] In some embodiments, the orthographic projection of the third anode AD3 on the substrate overlaps with the orthographic projection of a portion of the second data line DL2 among the plurality of data lines on the substrate, overlaps with the orthographic projection of a portion of the third line Vdd2-3 on the substrate, and overlaps with the orthographic projection of a portion of the third data line DL3 among the plurality of data lines on the substrate.

[0192] In some embodiments, the orthographic projections of a portion of the second data line DL2, a portion of the third line Vdd2-3, and a portion of the third data line DL3 are substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) of the orthographic projection of the third anode AD3 on the substrate are substantially uniformly distributed relative to the orthographic projection of the third anode AD3 on the substrate.

[0193] The inventors of this disclosure have discovered that the uniformity of the anode in a display panel can adversely affect image display. For example, color shift can be caused by anode tilt. This disclosure reveals that the signal line beneath the anode can significantly influence the degree of anode tilt. In one example, a signal line is positioned on one side beneath the anode, while no signal line is present on the other side. This results in an uneven surface of the planarization layer above the signal line. This uneven surface of the planarization layer, in turn, causes the anode above the planarization layer to tilt. For example, the presence of a signal line beneath the left portion of the planarization layer results in an uneven surface of the planarization layer, which in turn causes the anode above the planarization layer to tilt to the right. The tilted anode reflects more light towards the right side of the display panel. In a display panel, anodes associated with sub-pixels of different colors have different tilt angles, so light reflected by the anodes in sub-pixels of different colors is reflected at different angles to different colors of light. The cumulative effect of this problem leads to color shift at large viewing angles.

[0194] In this disclosure, by making the orthographic projection of a portion of the body MB of the first line Vdd2-1, a portion of the first ring LP1 of the first line Vdd2-1, a portion of the first data line DL1 among a plurality of data lines, and a portion of the second line Vdd2-2 on the substrate substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) of the orthographic projection of the first anode AD1 on the substrate, the array substrate achieves a uniform surface of the planarization layer below the first anode AD1.

[0195] By ensuring that the orthographic projections of a portion of the main body MB of the first line Vdd2-1, a portion of the second ring LP2 of the first line Vdd2-1, a portion of the first data line DL1 among the plurality of data lines, and a portion of the second line Vdd2-2 on the substrate are substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) uniform relative to the orthographic projection of the second anode AD2 on the substrate, the array substrate achieves a uniform surface for the planarization layer beneath the second anode AD2. Therefore, color shift problems can be mitigated.

[0196] By ensuring that the orthographic projections of a portion of the second data line DL2, a portion of the third data line Vdd2-3, and a portion of the third data line DL3 are substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) onto the substrate relative to the orthographic projection of the third anode AD3, the array substrate achieves a uniform surface for the planarization layer beneath the third anode AD3. Therefore, color shift issues can be mitigated.

[0197] In some embodiments, the array substrate includes a plurality of sub-pixel openings extending through the pixel defining layer (PDL), including a first sub-pixel opening SA1, a second sub-pixel opening SA2, and a third sub-pixel opening SA3. In some embodiments, the first sub-pixel opening SA1 exposes a portion of a first anode AD1, the second sub-pixel opening SA2 exposes a portion of a second anode AD2, and the third sub-pixel opening SA3 exposes a portion of a third anode AD3. Optionally, the first sub-pixel opening SA1 is a sub-pixel opening within a sub-pixel configured to receive a reference voltage signal from a first line Vdd2-1. Optionally, the second sub-pixel opening SA2 is a sub-pixel opening within a sub-pixel configured to receive a reference voltage signal from a second line Vdd2-2. Optionally, the third sub-pixel opening SA3 is a sub-pixel opening within a sub-pixel configured to receive a reference voltage signal from a third line Vdd2-3.

[0198] In some embodiments, the orthographic projection of the first sub-pixel opening SA1 on the substrate overlaps with the orthographic projection of a portion of the body MB of the first line Vdd2-1 on the substrate, overlaps with the orthographic projection of a portion of the first ring LP1 of the first line Vdd2-1 on the substrate, overlaps with the orthographic projection of a portion of the first data line DL1 among a plurality of data lines on the substrate, and overlaps with the orthographic projection of a portion of the second line Vdd2-2 on the substrate.

[0199] In some embodiments, the orthographic projections of a portion of the main body MB of the first line Vdd2-1, a portion of the first ring LP1 of the first line Vdd2-1, a portion of the first data line DL1 among a plurality of data lines, and a portion of the second line Vdd2-2 on the substrate are substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) uniformly distributed relative to the orthographic projection of the first sub-pixel opening SA1 on the substrate.

[0200] In some embodiments, the orthographic projection of the second sub-pixel opening SA2 on the substrate overlaps with the orthographic projection of a portion of the body MB of the first line Vdd2-1 on the substrate, overlaps with the orthographic projection of a portion of the second ring LP2 of the first line Vdd2-1 on the substrate, overlaps with the orthographic projection of a portion of the first data line DL1 among a plurality of data lines on the substrate, and overlaps with the orthographic projection of a portion of the second line Vdd2-2 on the substrate.

[0201] In some embodiments, the orthographic projections of a portion of the main body MB of the first line Vdd2-1, a portion of the second ring LP2 of the first line Vdd2-1, a portion of the first data line DL1 among a plurality of data lines, and a portion of the second line Vdd2-2 on the substrate are substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) uniformly distributed relative to the orthographic projection of the second sub-pixel opening SA2 on the substrate.

[0202] In some embodiments, the orthographic projection of the third sub-pixel opening SA3 on the substrate overlaps with the orthographic projection of a portion of the second data line DL2 among the plurality of data lines on the substrate, overlaps with the orthographic projection of a portion of the third line Vdd2-3 on the substrate, and overlaps with the orthographic projection of a portion of the third data line DL3 among the plurality of data lines on the substrate.

[0203] In some embodiments, the orthographic projections of a portion of the second data line DL2, a portion of the third line Vdd2-3, and a portion of the third data line DL3 are substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) of the orthographic projection of the third sub-pixel opening SA3 on the substrate are substantially uniformly distributed relative to the orthographic projection of the third sub-pixel opening SA3 on the substrate.

[0204] Figure 6C This is a schematic diagram illustrating the structure of a first planarization layer, a second signal line layer, and a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure. In some embodiments, the orthographic projection of a via extending through the first planarization layer onto the substrate substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) does not overlap with the orthographic projection of a plurality of sub-pixel openings onto the substrate. By having this structure, the inventors of the present disclosure have found that the array substrate achieves a uniform surface of the planarization layer below the anode. Therefore, color shift problems can be mitigated.

[0205] In some embodiments, the array substrate includes a plurality of third vias v3 extending through a first planarization layer. Each of the plurality of second voltage supply lines extends through a corresponding third via v3 to connect to a corresponding first voltage supply line among the plurality of first voltage supply lines. In some embodiments, the orthographic projections of the plurality of third vias v3 onto the substrate do not substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) overlap with the orthographic projections of the plurality of sub-pixel openings onto the substrate.

[0206] In some embodiments, the array substrate includes a plurality of fourth vias v4 extending through a first planarization layer. Each of the plurality of data lines extends through a corresponding fourth via v4 to connect to a data connection pad. In some embodiments, the orthographic projections of the plurality of fourth vias v4 onto the substrate do not substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) overlap with the orthographic projections of the plurality of sub-pixel openings onto the substrate.

[0207] Figure 6D This is a schematic diagram illustrating the structure of a semiconductor material layer, a second gate metal layer, a first gate line, and a second gate line in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 6D In some embodiments, a portion of the second capacitor electrode Ce2 is configured to shield at least a portion of the semiconductor material layer including the second electrode D2 of the second transistor and / or at least a portion of the second electrode Dr1 of the first reset transistor from the influence of the corresponding first gate line GL1 and / or the corresponding second gate line GL2. The inventors of this disclosure have found that this structure prevents the corresponding first gate line GL1 and / or the corresponding second gate line GL2 from interfering with the first node N1 (e.g., at least a portion of the semiconductor material layer including the second electrode D2 of the second transistor and / or at least a portion of the second electrode Dr1 of the first reset transistor). The capacitance between the portion of the second capacitor electrode Ce2 and the first node N1 stabilizes the voltage of the first node N1.

[0208] In some embodiments, the orthographic projection of a portion of the corresponding first gate line GL1 on the substrate overlaps with the orthographic projection of at least a portion of the second electrode D2 of the semiconductor material layer including the second transistor and / or at least a portion of the second electrode Dr1 of the first reset transistor on the substrate; the orthographic projection of a portion of the second capacitor electrode Ce2 of the storage capacitor on the substrate at least partially overlaps with the orthographic projection of a portion of the corresponding first gate line GL1 on the substrate, and at least partially overlaps with the orthographic projection of at least a portion of the second electrode D2 of the semiconductor material layer including the second transistor and / or at least a portion of the second electrode Dr1 of the first reset transistor on the substrate.

[0209] In some embodiments, the orthographic projection of a portion of the corresponding second gate line GL2 on the substrate overlaps with the orthographic projection of at least a portion of the second electrode D2 of the semiconductor material layer including the second transistor and / or at least a portion of the second electrode Dr1 of the first reset transistor on the substrate; the orthographic projection of a portion of the second capacitor electrode Ce2 of the storage capacitor on the substrate at least partially overlaps with the orthographic projection of a portion of the corresponding second gate line GL2 on the substrate, and at least partially overlaps with the orthographic projection of at least a portion of the second electrode D2 of the semiconductor material layer including the second transistor and / or at least a portion of the second electrode Dr1 of the first reset transistor on the substrate.

[0210] Figure 6E This is a schematic diagram illustrating the structure of a second capacitor electrode in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 6E In some embodiments, the second capacitor electrode includes a main portion MP and an extension portion ET extending away from the main portion MP. In some embodiments, the extension portion ET first extends away from the main portion MP along a second direction DR2, then extends along a first direction DR1, and then extends along the second direction DR2. In some embodiments, the extension portion ET includes a first portion P1, a second portion P2, and a third portion P3, wherein the first portion P1 is connected to the main portion MP, and the second portion P2 connects the first portion P1 to the third portion P3. In some embodiments, the first portion P1 extends away from the main portion MP along the second direction DR2, the second portion P2 extends along the first direction DR1, and the third portion P3 extends away from the main portion MP along the second direction DR2.

[0211] In some embodiments, the orthographic projection of a portion of the corresponding first gate line GL1 on the substrate overlaps with the orthographic projection of at least a portion of the second electrode D2 of the semiconductor material layer including the second transistor and / or at least a portion of the second electrode Dr1 of the first reset transistor on the substrate; the orthographic projection of the third portion P3 on the substrate at least partially overlaps with the orthographic projection of a portion of the corresponding first gate line GL1 on the substrate, and at least partially overlaps with the orthographic projection of at least a portion of the second electrode D2 of the semiconductor material layer including the second transistor and / or at least a portion of the second electrode Dr1 of the first reset transistor on the substrate.

[0212] In some embodiments, the orthographic projection of a portion of the corresponding second gate line GL2 on the substrate overlaps with the orthographic projection of at least a portion of the second electrode D2 of the semiconductor material layer including the second transistor and / or at least a portion of the second electrode Dr1 of the first reset transistor on the substrate; the orthographic projection of the third portion P3 on the substrate at least partially overlaps with the orthographic projection of a portion of the corresponding second gate line GL2 on the substrate, and at least partially overlaps with the orthographic projection of at least a portion of the second electrode D2 of the semiconductor material layer including the second transistor and / or at least a portion of the second electrode Dr1 of the first reset transistor on the substrate.

[0213] Figure 7A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 7B It is shown Figure 7A A schematic diagram of the arrangement of pixel driving circuits in a portion of an array substrate depicted in the figure. Figure 8A It is shown Figure 7A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure. Figure 8B It is shown Figure 7A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 8C It is shown Figure 7A A schematic diagram of the structure of the first gate metal layer in a portion of the array substrate depicted in the figure. Figure 8D It is shown Figure 7A A schematic diagram of the structure of the second gate metal layer in a portion of the array substrate depicted in the figure. Figure 8E It is shown Figure 7A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure. Figure 8F It is shown Figure 7A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure. Figure 8G It is shown Figure 7A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure. Figure 8H It is shown Figure 7A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure. Figure 8I It is shown Figure 7A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure. Figure 8J It is shown Figure 7A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram. Figure 8K It is shown Figure 7A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure. Figure 7A , Figure 7B ,as well as Figures 8A to 8K A portion of an array substrate is depicted having three adjacent pixel driving circuits arranged in a row, the three adjacent pixel driving circuits including PDC1, PDC2 and PDC3.

[0214] Reference Figure 2A , Figure 7A , Figure 7B and Figure 8A In some embodiments, the light-shielding layer includes a light-shielding element LS.

[0215] Reference Figure 2A , Figure 7A , Figure 7B and Figure 8BIn some embodiments, the semiconductor material layer includes an active layer of at least a plurality of transistors of a pixel driving circuit, the plurality of transistors including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td. Optionally, the semiconductor material layer also includes at least corresponding portions of the first electrodes of the plurality of transistors of the pixel driving circuit, the plurality of transistors including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the semiconductor material layer also includes at least corresponding portions of the second electrodes of the plurality of transistors of the pixel driving circuit, the plurality of transistors including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the semiconductor material layer includes an active layer of multiple transistors for a pixel driving circuit, a first electrode, and a second electrode. The multiple transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td. Various suitable semiconductor materials can be used to fabricate the semiconductor material layer. Examples of semiconductor materials used to fabricate the semiconductor material layer include silicon-based semiconductor materials such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0216] Figure 8B The transistors are labeled with markings indicating components of each of the multiple transistors (T1, T2, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0217] Optionally, the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, ACTr3, and ACTd), the first electrodes (S1, S2, S3, S4, Sr1, Sr2, Sr3, and Sd), and the second electrodes (D1, D2, D3, D4, Dr1, Dr2, Dr3, and Dd) of each transistor (T1, T2, T3, T4, Tr1, Tr2, Tr3, and Td) are located on the same layer.

[0218] In some embodiments, at least a portion of the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, and ACTd) of the plurality of transistors (T1, T2, T3, T4, Tr1, Tr2, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, and Dd) are integral structures.

[0219] In some embodiments, the semiconductor material layer further includes a plurality of first reset signal lines (e.g., individual first reset signal lines Vint1). In some embodiments, the corresponding first reset signal line Vint1 is connected to the first electrode of the first reset transistor of the pixel driving circuit in the same row. In some embodiments, the corresponding first reset signal line Vint1, the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, and ACTd) of the plurality of transistors (T1, T2, T3, T4, Tr1, Tr2, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, and Dd) are integral structures.

[0220] Reference Figure 2A , Figure 7A , Figure 7B and Figure 8C In some embodiments, the first gate metal layer includes a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of second light emission control signal lines (e.g., each second light emission control signal line em2), a first capacitor electrode Ce1 of the storage capacitor Cst, a first gate pad GEP1, a second gate pad GEP2, a third gate pad GEP3, and a fifth gate pad GEP5.

[0221] Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first gate metal layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first gate metal layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, each of the plurality of second reset control signal lines rst2, each of the plurality of second light emission control signal lines em2, the first capacitor electrode Ce1 of the storage capacitor Cst, the first gate pad GEP1, the second gate pad GEP2, the third gate pad GEP3, and the fifth gate pad GEP5 are located in the same layer.

[0222] In some embodiments, the first gate pad GEP1 includes the gate G1 of the first transistor T1 in the pixel driving circuit. In some embodiments, the second gate pad GEP2 includes the gate G2 of the second transistor T2 in the pixel driving circuit. In some embodiments, the third gate pad GEP3 includes the gate G3 of the third transistor T3 in the pixel driving circuit. In some embodiments, the fifth gate pad GEP5 includes the gate Gr1 of the first reset transistor Tr1 in the pixel driving circuit. The first gate pad GEP1 is connected to a corresponding first gate line GL1 among a plurality of first gate lines. The second gate pad GEP2 is connected to a corresponding second gate line GL2 among a plurality of second gate lines. The third gate pad GEP3 is connected to a corresponding first light emission control signal line em1 among a plurality of first light emission control signal lines. The fifth gate pad GEP5 is connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines.

[0223] Reference Figure 2A , Figure 7A , Figure 7B and Figure 8D In some embodiments, the second gate metal layer includes a plurality of second reset signal lines (e.g., each second reset signal line Vint2), a plurality of first light emission control signal lines (e.g., each first light emission control signal line em1), and a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the second gate metal layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second gate metal layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of second reset signal lines, the plurality of first light emission control signal lines, and the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0224] Figure 8E The image depicts vias extending through the interlayer dielectric layer.

[0225] Reference Figure 2A , Figure 7A , Figure 7B and Figure 8F In some embodiments, the first signal line layer includes a plurality of first reset control signal lines (e.g., each first reset control signal line rst1), a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of first gate lines (e.g., each first gate line GL1), a plurality of second gate lines (e.g., each second gate line GL2), a plurality of third reset signal lines (e.g., each third reset signal line Vint3), a plurality of first voltage supply lines (e.g., each first voltage supply line Vdd1), a first node connection line Cln1, a second node connection line Cln2, a light emission control signal connection pad LEP, a data signal connection pad DCP, a relay electrode RE, and a reset signal connection pad Cli.

[0226] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the first signal line layer comprises a plurality of sublayers stacked together. In one example, the first signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure.

[0227] Optionally, multiple first reset control signal lines (e.g., each first reset control signal line rst1), multiple second reset control signal lines (e.g., each second reset control signal line rst2), multiple first gate lines (e.g., each first gate line GL1), multiple second gate lines (e.g., each second gate line GL2), multiple third reset signal lines (e.g., each third reset signal line Vint3), multiple first voltage supply lines (e.g., each first voltage supply line Vdd1), first node connection line Cln1, second node connection line Cln2, light emission control signal connection pad LEP, data signal connection pad DCP, relay electrode RE, and reset signal connection pad Cli are located on the same layer.

[0228] In some embodiments, a first node connection line Cln1 in the pixel driving circuit connects multiple components of the pixel driving circuit to a first node N1. In some embodiments, the first node connection line Cln1 is connected to a first capacitor electrode Ce1 via a first via v1 and to a second transistor T2 (e.g., to a second electrode D2 of the second transistor T2) via a second via v2. Optionally, the first node connection line Cln1 corresponds to... Figure 2A The node N1 is depicted in the diagram.

[0229] In some embodiments, the second node connection line Cln2 in the pixel driving circuit connects multiple components of the pixel driving circuit to the second node N2. In some embodiments, the second node connection line Cln2 is connected to the second electrode of the third transistor and also to the second electrode of the third reset transistor. Optionally, the second node connection line Cln2 corresponds to... Figure 2A The second node N2 is depicted in the diagram.

[0230] Reference Figure 8A , Figure 8F , Figure 8H In the pixel driving circuit, the data signal connection pad DCP connects the corresponding data line DL to the first electrode S1 of the first transistor T1, and the data signal provided by the corresponding data line DL is transmitted to the first electrode S1 of the first transistor T1 through the signal connection pad DCP.

[0231] Reference Figure 8A , Figure 8F , Figure 8H The relay electrode RE connects the anode connection pad ACP to the second electrode D4 of the fourth transistor T4 in the pixel driving circuit. The anode connection pad ACP is also connected to the anode of the light-emitting element.

[0232] Reference Figure 7A , Figure 7B Figure 7D, Figure 7I Figure 8A and Figure 8B The reset signal connection line Cli connects the corresponding second reset signal line Vint2 to the first electrode Sr2 of the second reset transistor Tr2 in the pixel driving circuit, thereby providing a reset signal to the first electrode Sr2 of the second reset transistor Tr2 in the pixel driving circuit.

[0233] In some embodiments, the reset signal connection line Cli in at least one pixel driving circuit is also connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines in the second signal line layer.

[0234] In some embodiments, the light emission control signal connection pad LEP is connected to the third gate pad GEP3 and to the corresponding first light emission control signal line em1.

[0235] In some embodiments, the relay electrode RE is connected to the second electrode of the fourth transistor and the second electrode of the second reset transistor, and is also connected to the anode connection pad.

[0236] Figure 8G The image depicts a via extending through the first planarization layer.

[0237] Reference Figure 2A , Figure 7A , Figure 7B and Figure 8H In some embodiments, the second signal line layer includes a plurality of second voltage supply lines (e.g., each second voltage supply line Vdd2), a plurality of data lines (e.g., each data line DL), a plurality of fourth reset signal lines (e.g., each fourth reset signal line Vint4), and an anode connection pad ACP.

[0238] In some embodiments, a plurality of first voltage supply lines and a plurality of second voltage supply lines are configured to provide a first reference voltage signal. In one example, the first reference voltage signal is a constant voltage signal, such as a high reference voltage signal.

[0239] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the second signal line layer comprises multiple sublayers stacked together. In one example, the second signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple second voltage supply lines (e.g., each second voltage supply line Vdd2), multiple data lines (e.g., each data line DL), multiple fourth reset signal lines (e.g., each fourth reset signal line Vint4), and an anode connection pad ACP are located in the same layer.

[0240] In some embodiments, a plurality of first voltage supply lines are configured to provide a first reference voltage signal. In one example, the first reference voltage signal is a constant voltage signal, such as a high reference voltage signal.

[0241] Figure 8I The image depicts vias extending through the first planarization layer PLN1.

[0242] Reference Figure 2A , Figure 7A , Figure 7B and Figure 8JIn some embodiments, the anode layer includes multiple anodes (ADs).

[0243] Reference Figure 2A , Figure 7A , Figure 7B and Figure 8K In some embodiments, the array substrate includes a plurality of sub-pixel openings SA extending through the pixel defining layer PDL.

[0244] In some embodiments, refer to Figure 2A , Figure 7A , Figure 7B , Figures 8A to 8K Multiple first reset signal lines are located in a semiconductor material layer. In some embodiments, a corresponding first reset signal line Vint1 of the multiple first reset signal lines is connected to the first electrode of the first reset transistor of the pixel driving circuit in the same row. In some embodiments, the corresponding first reset signal line Vint1 and the first electrode of the first reset transistor of the pixel driving circuit in the same row are integral structures. In some embodiments, the corresponding first reset signal line Vint1, the active layer of the multiple transistors in the pixel driving circuit, at least a portion of the first electrode, and at least a portion of the second electrode are integral structures. In some embodiments, the corresponding first reset signal line Vint1, the active layer (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, and ACTd) of all transistors (T1, T2, T3, T4, Tr1, Tr2, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, and Dd) are integral structures. The inventors of this disclosure have discovered that by providing a plurality of first reset signal lines in a semiconductor material layer, the need to form vias in the array substrate is eliminated.

[0245] In some embodiments, a plurality of first light-emitting control signal lines are located in a second gate metal layer, and a plurality of second light-emitting control signal lines are located in a first gate metal layer. By providing a plurality of first light-emitting control signal lines in the second gate metal layer and a plurality of second light-emitting control signal lines in the first gate metal layer, the first signal line layer can have a lower wiring density (e.g., reduced from 29.84% to 27.98%). The inventors of this disclosure have found that this structure prevents short circuits in the wiring of the first signal line layer.

[0246] In some embodiments, a plurality of first reset signal lines are located in a semiconductor material layer, a plurality of second reset signal lines are located in a second gate metal layer, and a plurality of third reset signal lines are located in a first signal line layer.

[0247] Figure 9AThis is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 9B It is shown Figure 9A A schematic diagram of the arrangement of pixel driving circuits in a portion of an array substrate depicted in the figure. Figure 10A It is shown Figure 9A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure. Figure 10B It is shown Figure 9A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 10C It is shown Figure 9A A schematic diagram of the structure of the first gate metal layer in a portion of the array substrate depicted in the figure. Figure 10D It is shown Figure 9A A schematic diagram of the structure of the second gate metal layer in a portion of the array substrate depicted in the figure. Figure 10E It is shown Figure 9A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure. Figure 10F It is shown Figure 9A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure. Figure 10G It is shown Figure 9A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure. Figure 10H It is shown Figure 9A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure. Figure 10I It is shown Figure 9A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure. Figure 10J It is shown Figure 9A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram. Figure 10K It is shown Figure 9A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure. Figure 9A , Figure 9B ,as well as Figures 10A to 10K A portion of an array substrate is depicted having three adjacent pixel driving circuits arranged in a row, the three adjacent pixel driving circuits including PDC1, PDC2 and PDC3.

[0248] Reference Figure 2A , Figure 9A , Figure 9B and Figure 10A In some embodiments, the light-shielding layer includes a light-shielding element LS.

[0249] Reference Figure 2A , Figure 9A , Figure 9B and Figure 10BIn some embodiments, the semiconductor material layer includes an active layer of at least a plurality of transistors of a pixel driving circuit, the plurality of transistors including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td. Optionally, the semiconductor material layer also includes at least corresponding portions of the first electrodes of the plurality of transistors of the pixel driving circuit, the plurality of transistors including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the semiconductor material layer also includes at least corresponding portions of the second electrodes of the plurality of transistors of the pixel driving circuit, the plurality of transistors including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the semiconductor material layer includes an active layer of multiple transistors for a pixel driving circuit, a first electrode, and a second electrode. The multiple transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td. Various suitable semiconductor materials can be used to fabricate the semiconductor material layer. Examples of semiconductor materials used to fabricate the semiconductor material layer include silicon-based semiconductor materials such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0250] Figure 10B The transistors are labeled with markings indicating components of each of the multiple transistors (T1, T2, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0251] Optionally, the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, ACTr3, and ACTd), the first electrodes (S1, S2, S3, S4, Sr1, Sr2, Sr3, and Sd), and the second electrodes (D1, D2, D3, D4, Dr1, Dr2, Dr3, and Dd) of each transistor (T1, T2, T3, T4, Tr1, Tr2, Tr3, and Td) are located on the same layer.

[0252] In some embodiments, at least a portion of the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, and ACTd) of the plurality of transistors (T1, T2, T3, T4, Tr1, Tr2, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, and Dd) are integral structures.

[0253] In some embodiments, the semiconductor material layer further includes a plurality of first reset signal lines (e.g., individual first reset signal lines Vint1). In some embodiments, the corresponding first reset signal line Vint1 is connected to the first electrode of the first reset transistor of the pixel driving circuit in the same row. In some embodiments, the corresponding first reset signal line Vint1, the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, and ACTd) of the plurality of transistors (T1, T2, T3, T4, Tr1, Tr2, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, and Dd) are integral structures.

[0254] Reference Figure 2A , Figure 9A , Figure 9B and Figure 10C In some embodiments, the first gate metal layer includes a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of second light emission control signal lines (e.g., each second light emission control signal line em2), a first capacitor electrode Ce1 of the storage capacitor Cst, a first gate pad GEP1, a second gate pad GEP2, a third gate pad GEP3, and a fifth gate pad GEP5.

[0255] Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first gate metal layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first gate metal layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, each of the plurality of second reset control signal lines rst2, each of the plurality of second light emission control signal lines em2, the first capacitor electrode Ce1 of the storage capacitor Cst, the first gate pad GEP1, the second gate pad GEP2, the third gate pad GEP3, and the fifth gate pad GEP5 are located in the same layer.

[0256] In some embodiments, the first gate pad GEP1 includes the gate G1 of the first transistor T1 in the pixel driving circuit. In some embodiments, the second gate pad GEP2 includes the gate G2 of the second transistor T2 in the pixel driving circuit. In some embodiments, the third gate pad GEP3 includes the gate G3 of the third transistor T3 in the pixel driving circuit. In some embodiments, the fifth gate pad GEP5 includes the gate Gr1 of the first reset transistor Tr1 in the pixel driving circuit. The first gate pad GEP1 is connected to a corresponding first gate line GL1 among a plurality of first gate lines. The second gate pad GEP2 is connected to a corresponding second gate line GL2 among a plurality of second gate lines. The third gate pad GEP3 is connected to a corresponding first light emission control signal line em1 among a plurality of first light emission control signal lines. The fifth gate pad GEP5 is connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines.

[0257] Reference Figure 2A , Figure 9A , Figure 9B and Figure 10D In some embodiments, the second gate metal layer includes a plurality of second reset signal lines (e.g., each second reset signal line Vint2), a plurality of first light emission control signal lines (e.g., each first light emission control signal line em1), and a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the second gate metal layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second gate metal layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of second reset signal lines, the plurality of first light emission control signal lines, and the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0258] Figure 10E The image depicts vias extending through the interlayer dielectric layer.

[0259] Reference Figure 2A , Figure 9A , Figure 9B and Figure 10F In some embodiments, the first signal line layer includes a plurality of first reset control signal lines (e.g., each first reset control signal line rst1), a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of first gate lines (e.g., each first gate line GL1), a plurality of second gate lines (e.g., each second gate line GL2), a plurality of third reset signal lines (e.g., each third reset signal line Vint3), a plurality of first voltage supply lines (e.g., each first voltage supply line Vdd1), a first node connection line Cln1, a second node connection line Cln2, a light emission control signal connection pad LEP, a data signal connection pad DCP, a relay electrode RE, and a reset signal connection pad Cli.

[0260] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the first signal line layer comprises a plurality of sublayers stacked together. In one example, the first signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure.

[0261] Optionally, multiple first reset control signal lines (e.g., each first reset control signal line rst1), multiple second reset control signal lines (e.g., each second reset control signal line rst2), multiple first gate lines (e.g., each first gate line GL1), multiple second gate lines (e.g., each second gate line GL2), multiple third reset signal lines (e.g., each third reset signal line Vint3), multiple first voltage supply lines (e.g., each first voltage supply line Vdd1), first node connection line Cln1, second node connection line Cln2, light emission control signal connection pad LEP, data signal connection pad DCP, relay electrode RE, and reset signal connection pad Cli are located on the same layer.

[0262] In some embodiments, a first node connection line Cln1 in the pixel driving circuit connects multiple components of the pixel driving circuit to a first node N1. In some embodiments, the first node connection line Cln1 is connected to a first capacitor electrode Ce1 via a first via v1 and to a second transistor T2 (e.g., to a second electrode D2 of the second transistor T2) via a second via v2. Optionally, the first node connection line Cln1 corresponds to... Figure 2A The node N1 is depicted in the diagram.

[0263] In some embodiments, the second node connection line Cln2 in the pixel driving circuit connects multiple components of the pixel driving circuit to the second node N2. In some embodiments, the second node connection line Cln2 is connected to the second electrode of the third transistor and also to the second electrode of the third reset transistor. Optionally, the second node connection line Cln2 corresponds to... Figure 2A The second node N2 is depicted in the diagram.

[0264] Reference Figure 10A , Figure 10F , Figure 10H In the pixel driving circuit, the data signal connection pad DCP connects the corresponding data line DL to the first electrode S1 of the first transistor T1, and the data signal provided by the corresponding data line DL is transmitted to the first electrode S1 of the first transistor T1 through the signal connection pad DCP.

[0265] Reference Figure 10A , Figure 10F , Figure 10H The relay electrode RE connects the anode connection pad ACP to the second electrode D4 of the fourth transistor T4 in the pixel driving circuit. The anode connection pad ACP is also connected to the anode of the light-emitting element.

[0266] Reference Figure 9A , Figure 9B Figure 9D, Figure 9I Figure 10A and Figure 10B The reset signal connection line Cli connects the corresponding second reset signal line Vint2 to the first electrode Sr2 of the second reset transistor Tr2 in the pixel driving circuit, thereby providing a reset signal to the first electrode Sr2 of the second reset transistor Tr2 in the pixel driving circuit.

[0267] In some embodiments, the reset signal connection line Cli in at least one pixel driving circuit is also connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines in the second signal line layer.

[0268] In some embodiments, the light emission control signal connection pad LEP is connected to the third gate pad GEP3 and to the corresponding first light emission control signal line em1.

[0269] In some embodiments, the relay electrode RE is connected to the second electrode of the fourth transistor and the second electrode of the second reset transistor, and is also connected to the anode connection pad.

[0270] Figure 10G The image depicts a via extending through the first planarization layer.

[0271] Reference Figure 2A , Figure 9A , Figure 9B and Figure 10H In some embodiments, the second signal line layer includes a plurality of second voltage supply lines (e.g., each second voltage supply line Vdd2), a plurality of data lines (e.g., each data line DL), a plurality of fourth reset signal lines (e.g., each fourth reset signal line Vint4), and an anode connection pad ACP.

[0272] In some embodiments, a plurality of first voltage supply lines and a plurality of second voltage supply lines are configured to provide a first reference voltage signal. In one example, the first reference voltage signal is a constant voltage signal, such as a high reference voltage signal.

[0273] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the second signal line layer comprises multiple sublayers stacked together. In one example, the second signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple second voltage supply lines (e.g., each second voltage supply line Vdd2), multiple data lines (e.g., each data line DL), multiple fourth reset signal lines (e.g., each fourth reset signal line Vint4), and an anode connection pad ACP are located in the same layer.

[0274] In some embodiments, a plurality of first voltage supply lines are configured to provide a first reference voltage signal. In one example, the first reference voltage signal is a constant voltage signal, such as a high reference voltage signal.

[0275] Figure 10I The image depicts vias extending through the first planarization layer PLN1.

[0276] Reference Figure 2A , Figure 9A , Figure 9B and Figure 10JIn some embodiments, the anode layer includes multiple anodes (ADs).

[0277] Reference Figure 2A , Figure 9A , Figure 9B and Figure 10K In some embodiments, the array substrate includes a plurality of sub-pixel openings SA extending through the pixel defining layer PDL.

[0278] In some embodiments, refer to Figure 2A , Figure 9A , Figure 9B , Figures 10A to 10K Multiple first reset signal lines are located in a semiconductor material layer. In some embodiments, a corresponding first reset signal line Vint1 of the multiple first reset signal lines is connected to the first electrode of the first reset transistor of the pixel driving circuit in the same row. In some embodiments, the corresponding first reset signal line Vint1 and the first electrode of the first reset transistor of the pixel driving circuit in the same row are integral structures. In some embodiments, the corresponding first reset signal line Vint1, the active layer of the multiple transistors in the pixel driving circuit, at least a portion of the first electrode, and at least a portion of the second electrode are integral structures. In some embodiments, the corresponding first reset signal line Vint1, the active layer (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, and ACTd) of all transistors (T1, T2, T3, T4, Tr1, Tr2, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, and Dd) are integral structures. The inventors of this disclosure have discovered that by providing a plurality of first reset signal lines in a semiconductor material layer, the need to form vias in the array substrate is eliminated.

[0279] In some embodiments, a plurality of first light-emitting control signal lines are located in a second gate metal layer, and a plurality of second light-emitting control signal lines are located in a first gate metal layer. By providing a plurality of first light-emitting control signal lines in the second gate metal layer and a plurality of second light-emitting control signal lines in the first gate metal layer, the first signal line layer can have a lower wiring density (e.g., reduced from 29.84% to 27.98%). The inventors of this disclosure have found that this structure prevents short circuits in the wiring of the first signal line layer.

[0280] In some embodiments, a plurality of first reset signal lines are located in a semiconductor material layer, a plurality of second reset signal lines are located in a second gate metal layer, and a plurality of third reset signal lines are located in a first signal line layer.

[0281] Figure 11AThis is a schematic diagram illustrating the structure of a semiconductor material layer and a light-emitting control signal connection pad in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 11A In some embodiments, the orthographic projection of the light-emitting control signal connection pad (LEP) on the substrate does not overlap with the orthographic projection of the semiconductor material layer on the substrate. This structure minimizes the parasitic capacitance between the LEP and the third node (e.g., the first electrode S4 of the fourth transistor). In some embodiments, the orthographic projection of the LEP on the substrate does not overlap with the orthographic projection of the fourth transistor on the substrate. In some embodiments, the orthographic projection of the LEP on the substrate does not overlap with the orthographic projection of the third node on the substrate.

[0282] Figure 11B It is shown Figure 10A A schematic diagram of the structure of a semiconductor material layer and a corresponding first light-emitting control signal line in a portion of an array substrate. Figure 11C It is shown Figure 8A A schematic diagram depicting the structure of a semiconductor material layer and a corresponding first light-emitting control signal line in a portion of an array substrate. (Refer to...) Figure 11B and Figure 11C ,and Figure 8A Compared to the array substrate depicted in the image, Figure 10A The overlap area between the orthographic projection of each first light-emitting control signal line em1 in the array substrate depicted in the diagram and the orthographic projection of the semiconductor material layer on the substrate is reduced. In some embodiments, with Figure 8A Compared to the array substrate depicted in the image, Figure 10A The overlap area between the orthographic projections of each of the first light-emitting control signal lines em1 in the array substrate depicted in the diagram and the orthographic projection of the third node on the substrate substrate is reduced. In some embodiments, with Figure 8A Compared to the array substrate depicted in the image, Figure 10A The overlap area between the orthographic projection of each first light-emitting control signal line em1 in the array substrate depicted in the diagram and the orthographic projection of the first electrode S4 of the fourth transistor on the substrate is reduced. The inventors of this disclosure have found that this structure effectively minimizes the parasitic capacitance between the light-emitting control signal connection pad LEP and the third node (e.g., the first electrode S4 of the fourth transistor).

[0283] In some embodiments, refer to Figure 11BThe portion of the semiconductor material layer having a first electrode S3 of a third transistor, an active layer ACT3, a second electrode D3, and a first electrode Sd of a driving transistor has a U-shaped shape. In some embodiments, the orthographic projection of the corresponding first light-emitting control signal line em1 on the substrate at least partially overlaps with the orthographic projection of the bottom of the U-shaped shape on the substrate. Optionally, the bottom of the U-shaped shape includes at least a portion of the second electrode D3 of the third transistor.

[0284] Figure 12A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 12B It is shown Figure 12A A schematic diagram of the arrangement of pixel driving circuits in a portion of an array substrate depicted in the figure. Figure 13A It is shown Figure 12A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure. Figure 13B It is shown Figure 12A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 13C It is shown Figure 12A A schematic diagram of the structure of the first gate metal layer in a portion of the array substrate depicted in the figure. Figure 13D It is shown Figure 12A A schematic diagram of the structure of the second gate metal layer in a portion of the array substrate depicted in the figure. Figure 13E It is shown Figure 12A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure. Figure 13F It is shown Figure 12A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure. Figure 13G It is shown Figure 12A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure. Figure 13H It is shown Figure 12A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure. Figure 13I This is an explanation Figure 12A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure. Figure 13J It is shown Figure 12A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram. Figure 13K It is shown Figure 12A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure. Figure 12A , Figure 12B ,as well as Figures 13A to 13KA portion of an array substrate is depicted having three adjacent pixel driving circuits arranged in a row, the three adjacent pixel driving circuits including PDC1, PDC2 and PDC3.

[0285] Reference Figure 2A , Figure 12A , Figure 12B and Figure 13A In some embodiments, the light-shielding layer includes a light-shielding element LS.

[0286] Reference Figure 2A , Figure 12A , Figure 12B and Figure 13B In some embodiments, the semiconductor material layer includes an active layer of at least a plurality of transistors of a pixel driving circuit, the plurality of transistors including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td. Optionally, the semiconductor material layer also includes at least corresponding portions of the first electrodes of the plurality of transistors of the pixel driving circuit, the plurality of transistors including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the semiconductor material layer also includes at least corresponding portions of the second electrodes of the plurality of transistors of the pixel driving circuit, the plurality of transistors including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the semiconductor material layer includes an active layer of multiple transistors for a pixel driving circuit, a first electrode, and a second electrode. The multiple transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td. Various suitable semiconductor materials can be used to fabricate the semiconductor material layer. Examples of semiconductor materials used to fabricate the semiconductor material layer include silicon-based semiconductor materials such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0287] Figure 13BThe transistors are labeled with markings indicating components of each of the multiple transistors (T1, T2, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0288] Optionally, the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, ACTr3, and ACTd), the first electrodes (S1, S2, S3, S4, Sr1, Sr2, Sr3, and Sd), and the second electrodes (D1, D2, D3, D4, Dr1, Dr2, Dr3, and Dd) of each transistor (T1, T2, T3, T4, Tr1, Tr2, Tr3, and Td) are located on the same layer.

[0289] In some embodiments, at least a portion of the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, and ACTd) of the plurality of transistors (T1, T2, T3, T4, Tr1, Tr2, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, and Dd) are integral structures.

[0290] In some embodiments, the semiconductor material layer further includes a plurality of first reset signal lines (e.g., individual first reset signal lines Vint1). In some embodiments, the corresponding first reset signal line Vint1 is connected to the first electrode of the first reset transistor of the pixel driving circuit in the same row. In some embodiments, the corresponding first reset signal line Vint1, the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, and ACTd) of the plurality of transistors (T1, T2, T3, T4, Tr1, Tr2, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, and Dd) are integral structures.

[0291] Reference Figure 2A , Figure 12A , Figure 12B and Figure 13C In some embodiments, the first gate metal layer includes a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of second light emission control signal lines (e.g., each second light emission control signal line em2), a first capacitor electrode Ce1 of the storage capacitor Cst, a first gate pad GEP1, a second gate pad GEP2, a third gate pad GEP3, and a fifth gate pad GEP5.

[0292] Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first gate metal layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first gate metal layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, each of the plurality of second reset control signal lines rst2, each of the plurality of second light emission control signal lines em2, the first capacitor electrode Ce1 of the storage capacitor Cst, the first gate pad GEP1, the second gate pad GEP2, the third gate pad GEP3, and the fifth gate pad GEP5 are located in the same layer.

[0293] In some embodiments, the first gate pad GEP1 includes the gate G1 of the first transistor T1 in the pixel driving circuit. In some embodiments, the second gate pad GEP2 includes the gate G2 of the second transistor T2 in the pixel driving circuit. In some embodiments, the third gate pad GEP3 includes the gate G3 of the third transistor T3 in the pixel driving circuit. In some embodiments, the fifth gate pad GEP5 includes the gate Gr1 of the first reset transistor Tr1 in the pixel driving circuit. The first gate pad GEP1 is connected to a corresponding first gate line GL1 among a plurality of first gate lines. The second gate pad GEP2 is connected to a corresponding second gate line GL2 among a plurality of second gate lines. The third gate pad GEP3 is connected to a corresponding first light emission control signal line em1 among a plurality of first light emission control signal lines. The fifth gate pad GEP5 is connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines.

[0294] Reference Figure 2A , Figure 12A , Figure 12B and Figure 13D In some embodiments, the second gate metal layer includes a plurality of second reset signal lines (e.g., individual second reset signal lines Vint2) and a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the second gate metal layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second gate metal layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of second reset signal lines and the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0295] Figure 13E The image depicts vias extending through the interlayer dielectric layer.

[0296] Reference Figure 2A , Figure 12A , Figure 12B and Figure 13FIn some embodiments, the first signal line layer includes a plurality of first reset control signal lines (e.g., each first reset control signal line rst1), a plurality of first light emission control signal lines (e.g., each first light emission control signal line em1), a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of first gate lines (e.g., each first gate line GL1), a plurality of second gate lines (e.g., each second gate line GL2), a plurality of third reset signal lines (e.g., each third reset signal line Vint3), a plurality of first voltage supply lines (e.g., each first voltage supply line Vdd1), a first node connection line Cln1, a second node connection line Cln2, a data signal connection pad DCP, a relay electrode RE, and a reset signal connection pad Cli.

[0297] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the first signal line layer comprises a plurality of sublayers stacked together. In one example, the first signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure.

[0298] Optionally, multiple first reset control signal lines (e.g., each first reset control signal line rst1), multiple second reset control signal lines (e.g., each second reset control signal line rst2), multiple first light emission control signal lines (e.g., each first light emission control signal line em1), multiple first gate lines (e.g., each first gate line GL1), multiple second gate lines (e.g., each second gate line GL2), multiple third reset signal lines (e.g., each third reset signal line Vint3), multiple first voltage supply lines (e.g., each first voltage supply line Vdd1), first node connection line Cln1, second node connection line Cln2, data signal connection pad DCP, relay electrode RE, and reset signal connection pad Cli are located on the same layer.

[0299] In some embodiments, a first node connection line Cln1 in the pixel driving circuit connects multiple components of the pixel driving circuit to a first node N1. In some embodiments, the first node connection line Cln1 is connected to a first capacitor electrode Ce1 via a first via v1 and to a second transistor T2 (e.g., to a second electrode D2 of the second transistor T2) via a second via v2. Optionally, the first node connection line Cln1 corresponds to... Figure 2AThe node N1 is depicted in the diagram.

[0300] In some embodiments, the second node connection line Cln2 in the pixel driving circuit connects multiple components of the pixel driving circuit to the second node N2. In some embodiments, the second node connection line Cln2 is connected to the second electrode of the third transistor and also to the second electrode of the third reset transistor. Optionally, the second node connection line Cln2 corresponds to... Figure 2A The second node N2 is depicted in the diagram.

[0301] Reference Figure 13A , Figure 13F , Figure 13H In the pixel driving circuit, the data signal connection pad DCP connects the corresponding data line DL to the first electrode S1 of the first transistor T1, and the data signal provided by the corresponding data line DL is transmitted to the first electrode S1 of the first transistor T1 through the signal connection pad DCP.

[0302] Reference Figure 13A , Figure 13F , Figure 13H The relay electrode RE connects the anode connection pad ACP to the second electrode D4 of the fourth transistor T4 in the pixel driving circuit. The anode connection pad ACP is also connected to the anode of the light-emitting element.

[0303] Reference Figure 12A , Figure 12B Figure 12D, Figure 12I Figure 13A and Figure 13B The reset signal connection line Cli connects the corresponding second reset signal line Vint2 to the first electrode Sr2 of the second reset transistor Tr2 in the pixel driving circuit, thereby providing a reset signal to the first electrode Sr2 of the second reset transistor Tr2 in the pixel driving circuit.

[0304] In some embodiments, the reset signal connection line Cli in at least one pixel driving circuit is also connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines in the second signal line layer.

[0305] In some embodiments, the relay electrode RE is connected to the second electrode of the fourth transistor and the second electrode of the second reset transistor, and is also connected to the anode connection pad.

[0306] Figure 13G The image depicts a via extending through the first planarization layer.

[0307] Reference Figure 2A , Figure 12A , Figure 12B and Figure 13HIn some embodiments, the second signal line layer includes a plurality of second voltage supply lines (e.g., each second voltage supply line Vdd2), a plurality of data lines (e.g., each data line DL), a plurality of fourth reset signal lines (e.g., each fourth reset signal line Vint4), and an anode connection pad ACP.

[0308] In some embodiments, a plurality of first voltage supply lines and a plurality of second voltage supply lines are configured to provide a first reference voltage signal. In one example, the first reference voltage signal is a constant voltage signal, such as a high reference voltage signal.

[0309] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the second signal line layer comprises multiple sublayers stacked together. In one example, the second signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple second voltage supply lines (e.g., each second voltage supply line Vdd2), multiple data lines (e.g., each data line DL), multiple fourth reset signal lines (e.g., each fourth reset signal line Vint4), and an anode connection pad ACP are located in the same layer.

[0310] In some embodiments, a plurality of first voltage supply lines are configured to provide a first reference voltage signal. In one example, the first reference voltage signal is a constant voltage signal, such as a high reference voltage signal.

[0311] Figure 13I The image depicts vias extending through the first planarization layer PLN1.

[0312] Reference Figure 2A , Figure 12A , Figure 12B and Figure 13J In some embodiments, the anode layer includes multiple anodes (ADs).

[0313] Reference Figure 2A , Figure 12A , Figure 12B and Figure 13K In some embodiments, the array substrate includes a plurality of sub-pixel openings SA extending through the pixel defining layer PDL.

[0314] In some embodiments, refer to Figure 2A , Figure 12A , Figure 12B , Figures 13A to 13K Multiple first reset signal lines are located in a semiconductor material layer. In some embodiments, a corresponding first reset signal line Vint1 of the multiple first reset signal lines is connected to the first electrode of the first reset transistor of the pixel driving circuit in the same row. In some embodiments, the corresponding first reset signal line Vint1 and the first electrode of the first reset transistor of the pixel driving circuit in the same row are integral structures. In some embodiments, the corresponding first reset signal line Vint1, the active layer of the multiple transistors in the pixel driving circuit, at least a portion of the first electrode, and at least a portion of the second electrode are integral structures. In some embodiments, the corresponding first reset signal line Vint1, the active layer (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, and ACTd) of all transistors (T1, T2, T3, T4, Tr1, Tr2, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, and Dd) are integral structures. The inventors of this disclosure have discovered that by providing a plurality of first reset signal lines in a semiconductor material layer, the need to form vias in the array substrate is eliminated.

[0315] In some embodiments, a plurality of first light-emitting control signal lines are located in a first signal line layer, and a plurality of second light-emitting control signal lines are located in a first gate metal layer. By providing a plurality of first light-emitting control signal lines in the first signal line layer and a plurality of second light-emitting control signal lines in the first gate metal layer, the first signal line layer can have a lower wiring density (e.g., reduced from 29.84% to 27.98%). The inventors of this disclosure have found that this structure prevents short circuits in the wiring of the first signal line layer.

[0316] In some embodiments, a plurality of first reset signal lines are located in a semiconductor material layer, a plurality of second reset signal lines are located in a second gate metal layer, and a plurality of third reset signal lines are located in a first signal line layer.

[0317] Figure 14 It is shown Figure 13A This is a schematic diagram depicting the structure of a semiconductor material layer, a second gate metal layer, a second node connection line, and a corresponding first light-emitting control signal line in a portion of an array substrate. (Refer to...) Figures 13A to 13K ,as well as Figure 14In some embodiments, the orthographic projection of the second node connection line Cln2 on the substrate does not overlap with the orthographic projection of the first light-emitting control signal line em1 on the substrate. In some embodiments, the orthographic projection of at least a portion of the second electrode D3 of the semiconductor material layer including the third transistor and / or at least a portion of the first electrode Sd of the driving transistor on the substrate at least partially overlaps with the orthographic projection of the corresponding first light-emitting control signal line em1 on the substrate. Optionally, at least a portion of the second electrode D3 of the semiconductor material layer including the third transistor and / or at least a portion of the first electrode Sd of the driving transistor intersects with the corresponding first light-emitting control signal line em1.

[0318] In some embodiments, the corresponding first light-emitting control signal line em1 has a tortuous shape to avoid the second node connection line Cln2.

[0319] In some embodiments, a portion of the second capacitor electrode Ce2 of the storage capacitor is configured to shield at least a portion of the second electrode D3 of the semiconductor material layer, including the third transistor, and / or at least a portion of the first electrode Sd of the driving transistor, from the influence of the corresponding first light-emitting control signal line em1. The inventors of this disclosure have discovered that this structure prevents the corresponding first light-emitting control signal line em1 from interfering with the second node N2 (e.g., at least a portion of the second electrode D3 of the semiconductor material layer, including the third transistor, and / or at least a portion of the first electrode Sd of the driving transistor). The capacitance between the portion of the second capacitor electrode Ce2 and the second node N2 stabilizes the voltage of the second node N2. At low frequencies, the leakage time is prolonged, thereby preventing voltage changes at the N1 / N2 node from accelerating leakage.

[0320] In some embodiments, the orthographic projection of a portion of the corresponding first light-emitting control signal line em1 on the substrate overlaps with the orthographic projection of at least a portion of the second electrode D3 of the semiconductor material layer including the third transistor and / or at least a portion of the first electrode Sd of the driving transistor on the substrate; the orthographic projection of a portion of the second capacitor electrode Ce2 of the storage capacitor on the substrate at least partially overlaps with the orthographic projection of a portion of the corresponding first light-emitting control signal line em1 on the substrate, and at least partially overlaps with the orthographic projection of at least a portion of the second electrode D3 of the semiconductor material layer including the third transistor and / or at least a portion of the first electrode Sd of the driving transistor on the substrate.

[0321] In some embodiments, the corresponding second gate line GL2 has a zigzag shape; and the corresponding first reset control signal line rst1 has a zigzag shape. By having a zigzag shape, the space between the corresponding second gate line GL2 and the corresponding first reset control signal line rst1 can be increased, thereby reducing the parasitic capacitance between the corresponding second gate line GL2 and the corresponding first reset control signal line rst1.

[0322] Figure 15A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 15B It is shown Figure 15A A schematic diagram of the arrangement of pixel driving circuits in a portion of an array substrate depicted in the figure. Figure 16A It is shown Figure 15A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure. Figure 16B It is shown Figure 15A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 16C It is shown Figure 15A A schematic diagram of the structure of the first gate metal layer in a portion of the array substrate depicted in the figure. Figure 16D It is shown Figure 15A A schematic diagram of the structure of the second gate metal layer in a portion of the array substrate depicted in the figure. Figure 16E It is shown Figure 15A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure. Figure 16F It is shown Figure 15A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure. Figure 16G It is shown Figure 15A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure. Figure 16H It is shown Figure 15A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure. Figure 16I This is an explanation Figure 15A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure. Figure 16J It is shown Figure 15A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram. Figure 16K It is shown Figure 15A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure. Figure 15A , Figure 15B ,as well as Figures 16A to 16K A portion of an array substrate is depicted having three adjacent pixel driving circuits arranged in a row, the three adjacent pixel driving circuits including PDC1, PDC2 and PDC3.

[0323] Reference Figure 2A , Figure 15A , Figure 15B and Figure 16A In some embodiments, the light-shielding layer includes a light-shielding element LS.

[0324] Reference Figure 2A , Figure 15A , Figure 15B and Figure 16B In some embodiments, the semiconductor material layer includes an active layer of at least a plurality of transistors of a pixel driving circuit, the plurality of transistors including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td. Optionally, the semiconductor material layer also includes at least corresponding portions of the first electrodes of the plurality of transistors of the pixel driving circuit, the plurality of transistors including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the semiconductor material layer also includes at least corresponding portions of the second electrodes of the plurality of transistors of the pixel driving circuit, the plurality of transistors including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the semiconductor material layer includes an active layer of multiple transistors for a pixel driving circuit, a first electrode, and a second electrode. The multiple transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td. Various suitable semiconductor materials can be used to fabricate the semiconductor material layer. Examples of semiconductor materials used to fabricate the semiconductor material layer include silicon-based semiconductor materials such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0325] Figure 16BThe transistors are labeled with markings indicating components of each of the multiple transistors (T1, T2, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0326] Optionally, the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, ACTr3, and ACTd), the first electrodes (S1, S2, S3, S4, Sr1, Sr2, Sr3, and Sd), and the second electrodes (D1, D2, D3, D4, Dr1, Dr2, Dr3, and Dd) of each transistor (T1, T2, T3, T4, Tr1, Tr2, Tr3, and Td) are located on the same layer.

[0327] In some embodiments, at least a portion of the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, and ACTd) of the plurality of transistors (T1, T2, T3, T4, Tr1, Tr2, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, and Dd) are integral structures.

[0328] In some embodiments, the semiconductor material layer further includes a plurality of first reset signal lines (e.g., individual first reset signal lines Vint1). In some embodiments, the corresponding first reset signal line Vint1 is connected to the first electrode of the first reset transistor of the pixel driving circuit in the same row. In some embodiments, the corresponding first reset signal line Vint1, the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, and ACTd) of the plurality of transistors (T1, T2, T3, T4, Tr1, Tr2, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, and Dd) are integral structures.

[0329] Reference Figure 2A , Figure 15A , Figure 15B and Figure 16C In some embodiments, the first gate metal layer includes a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of second light emission control signal lines (e.g., each second light emission control signal line em2), a first capacitor electrode Ce1 of the storage capacitor Cst, a first gate pad GEP1, a second gate pad GEP2, a third gate pad GEP3, and a fifth gate pad GEP5.

[0330] Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first gate metal layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first gate metal layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, each of the plurality of second reset control signal lines rst2, each of the plurality of second light emission control signal lines em2, the first capacitor electrode Ce1 of the storage capacitor Cst, the first gate pad GEP1, the second gate pad GEP2, the third gate pad GEP3, and the fifth gate pad GEP5 are located in the same layer.

[0331] In some embodiments, the first gate pad GEP1 includes the gate G1 of the first transistor T1 in the pixel driving circuit. In some embodiments, the second gate pad GEP2 includes the gate G2 of the second transistor T2 in the pixel driving circuit. In some embodiments, the third gate pad GEP3 includes the gate G3 of the third transistor T3 in the pixel driving circuit. In some embodiments, the fifth gate pad GEP5 includes the gate Gr1 of the first reset transistor Tr1 in the pixel driving circuit. The first gate pad GEP1 is connected to a corresponding first gate line GL1 among a plurality of first gate lines. The second gate pad GEP2 is connected to a corresponding second gate line GL2 among a plurality of second gate lines. The third gate pad GEP3 is connected to a corresponding first light emission control signal line em1 among a plurality of first light emission control signal lines. The fifth gate pad GEP5 is connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines.

[0332] Reference Figure 2A , Figure 15A , Figure 15B and Figure 16D In some embodiments, the second gate metal layer includes a plurality of second reset signal lines (e.g., individual second reset signal lines Vint2) and a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the second gate metal layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second gate metal layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of second reset signal lines and the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0333] Figure 16E The image depicts vias extending through the interlayer dielectric layer.

[0334] Reference Figure 2A , Figure 15A , Figure 15B and Figure 16FIn some embodiments, the first signal line layer includes a plurality of first reset control signal lines (e.g., each first reset control signal line rst1), a plurality of first light emission control signal lines (e.g., each first light emission control signal line em1), a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of first gate lines (e.g., each first gate line GL1), a plurality of second gate lines (e.g., each second gate line GL2), a plurality of third reset signal lines (e.g., each third reset signal line Vint3), a plurality of first voltage supply lines (e.g., each first voltage supply line Vdd1), a first node connection line Cln1, a second node connection line Cln2, a data signal connection pad DCP, a relay electrode RE, and a reset signal connection pad Cli.

[0335] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the first signal line layer comprises a plurality of sublayers stacked together. In one example, the first signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure.

[0336] Optionally, multiple first reset control signal lines (e.g., each first reset control signal line rst1), multiple second reset control signal lines (e.g., each second reset control signal line rst2), multiple first light emission control signal lines (e.g., each first light emission control signal line em1), multiple first gate lines (e.g., each first gate line GL1), multiple second gate lines (e.g., each second gate line GL2), multiple third reset signal lines (e.g., each third reset signal line Vint3), multiple first voltage supply lines (e.g., each first voltage supply line Vdd1), first node connection line Cln1, second node connection line Cln2, data signal connection pad DCP, relay electrode RE, and reset signal connection pad Cli are located on the same layer.

[0337] In some embodiments, a first node connection line Cln1 in the pixel driving circuit connects multiple components of the pixel driving circuit to a first node N1. In some embodiments, the first node connection line Cln1 is connected to a first capacitor electrode Ce1 via a first via v1 and to a second transistor T2 (e.g., to a second electrode D2 of the second transistor T2) via a second via v2. Optionally, the first node connection line Cln1 corresponds to... Figure 2AThe node N1 is depicted in the diagram.

[0338] In some embodiments, the second node connection line Cln2 in the pixel driving circuit connects multiple components of the pixel driving circuit to the second node N2. In some embodiments, the second node connection line Cln2 is connected to the second electrode of the third transistor and also to the second electrode of the third reset transistor. Optionally, the second node connection line Cln2 corresponds to... Figure 2A The second node N2 is depicted in the diagram.

[0339] Reference Figure 16A , Figure 16F , Figure 16H In the pixel driving circuit, the data signal connection pad DCP connects the corresponding data line DL to the first electrode S1 of the first transistor T1, and the data signal provided by the corresponding data line DL is transmitted to the first electrode S1 of the first transistor T1 through the signal connection pad DCP.

[0340] Reference Figure 16A , Figure 16F , Figure 16H The relay electrode RE connects the anode connection pad ACP to the second electrode D4 of the fourth transistor T4 in the pixel driving circuit. The anode connection pad ACP is also connected to the anode of the light-emitting element.

[0341] Reference Figure 15A , Figure 15B Figure 15D, Figure 15I Figure 16A and Figure 16B The reset signal connection line Cli connects the corresponding second reset signal line Vint2 to the first electrode Sr2 of the second reset transistor Tr2 in the pixel driving circuit, thereby providing a reset signal to the first electrode Sr2 of the second reset transistor Tr2 in the pixel driving circuit.

[0342] In some embodiments, the reset signal connection line Cli in at least one pixel driving circuit is also connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines in the second signal line layer.

[0343] In some embodiments, the relay electrode RE is connected to the second electrode of the fourth transistor and the second electrode of the second reset transistor, and is also connected to the anode connection pad.

[0344] Figure 16G The image depicts a via extending through the first planarization layer.

[0345] Reference Figure 2A , Figure 15A , Figure 15B and Figure 16HIn some embodiments, the second signal line layer includes a plurality of second voltage supply lines (e.g., each second voltage supply line Vdd2), a plurality of third voltage supply lines (e.g., each third voltage supply line Vss), a plurality of data lines (e.g., each data line DL), a plurality of fourth reset signal lines (e.g., each fourth reset signal line Vint4), and an anode connection pad ACP.

[0346] In some embodiments, a plurality of first voltage supply lines and a plurality of second voltage supply lines are configured to provide a first reference voltage signal. In one example, the first reference voltage signal is a constant voltage signal, such as a high reference voltage signal. In some embodiments, a plurality of third voltage supply lines are configured to provide a second reference voltage signal. In one example, the second reference voltage signal is a constant voltage signal, such as a low reference voltage signal. In some embodiments, the first reference voltage signal has a voltage level higher than that of the second reference voltage signal.

[0347] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the second signal line layer comprises multiple sublayers stacked together. In one example, the second signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple second voltage supply lines (e.g., each second voltage supply line Vdd2), multiple data lines (e.g., each data line DL), multiple fourth reset signal lines (e.g., each fourth reset signal line Vint4), and an anode connection pad ACP are located in the same layer.

[0348] In some embodiments, a plurality of first voltage supply lines are configured to provide a first reference voltage signal. In one example, the first reference voltage signal is a constant voltage signal, such as a high reference voltage signal.

[0349] Figure 16I The image depicts vias extending through the first planarization layer PLN1.

[0350] Reference Figure 2A , Figure 15A , Figure 15B and Figure 16J In some embodiments, the anode layer includes multiple anodes (ADs).

[0351] Reference Figure 2A , Figure 15A, Figure 15B and Figure 16K In some embodiments, the array substrate includes a plurality of sub-pixel openings SA extending through the pixel defining layer PDL.

[0352] In some embodiments, refer to Figure 2A , Figure 15A , Figure 15B , Figures 16A to 16K Multiple first reset signal lines are located in a semiconductor material layer. In some embodiments, a corresponding first reset signal line Vint1 of the multiple first reset signal lines is connected to the first electrode of the first reset transistor of the pixel driving circuit in the same row. In some embodiments, the corresponding first reset signal line Vint1 and the first electrode of the first reset transistor of the pixel driving circuit in the same row are integral structures. In some embodiments, the corresponding first reset signal line Vint1, the active layer of the multiple transistors in the pixel driving circuit, at least a portion of the first electrode, and at least a portion of the second electrode are integral structures. In some embodiments, the corresponding first reset signal line Vint1, the active layer (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, and ACTd) of all transistors (T1, T2, T3, T4, Tr1, Tr2, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, and Dd) are integral structures. The inventors of this disclosure have discovered that by providing a plurality of first reset signal lines in a semiconductor material layer, the need to form vias in the array substrate is eliminated.

[0353] In some embodiments, a plurality of first light-emitting control signal lines are located in a first signal line layer, and a plurality of second light-emitting control signal lines are located in a first gate metal layer. By providing a plurality of first light-emitting control signal lines in the first signal line layer and a plurality of second light-emitting control signal lines in the first gate metal layer, the first signal line layer can have a lower wiring density (e.g., reduced from 29.84% to 27.98%). The inventors of this disclosure have found that this structure prevents short circuits in the wiring of the first signal line layer.

[0354] In some embodiments, a plurality of first reset signal lines are located in a semiconductor material layer, a plurality of second reset signal lines are located in a second gate metal layer, and a plurality of third reset signal lines are located in a first signal line layer.

[0355] Figure 17A This is a schematic diagram illustrating the structure of the second signal line layer and the anode layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 17BThis is a schematic diagram illustrating the structure of a second signal line layer and a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 17C This is a schematic diagram illustrating the structure of a first planarization layer, a second signal line layer, and a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 17A , Figure 17B , Figure 17C , Figure 2A , Figure 15A , Figure 15B ,as well as Figures 16A to 16K In some embodiments, the array substrate includes three adjacent second voltage supply lines among a plurality of second voltage supply lines, including a first line Vdd2-1, a second line Vdd2-2, and a third line Vdd2-3. In some embodiments, the first line Vdd2-1, the second line Vdd2-2, and the third line Vdd2-3 are configured to provide reference voltage signals to three adjacent columns of pixel driving circuits, respectively.

[0356] In some embodiments, a corresponding third voltage supply line Vss extends along the second direction DR2; a first line Vdd2-1 extends along the second direction DR2; a second line Vdd2-2 extends along the second direction DR2; and a third line Vdd2-3 extends along the second direction DR2. In some embodiments, the first line Vdd2-1, the corresponding third voltage supply line Vss, the second line Vdd2-2, and the third line Vdd2-3 are arranged along the first direction DR1, which is different from the second direction DR2. In one example, the first direction DR1 and the second direction DR2 are perpendicular to each other. In some embodiments, a plurality of second voltage supply lines are arranged along the first direction DR1. In some embodiments, a plurality of data lines are arranged along the first direction DR1. In some embodiments, a plurality of fourth reset signal lines are arranged along the first direction DR1.

[0357] In some embodiments, the orthographic projection of the first anode AD1 onto the substrate at least partially overlaps with the orthographic projection of the first line Vdd2-1 onto the substrate, and at least partially overlaps with the orthographic projection of the second line Vdd2-2 onto the substrate. Optionally, the orthographic projection of the first anode AD1 onto the substrate does not overlap with the orthographic projection of the third line Vdd2-3 onto the substrate. Optionally, the first anode AD1 is the anode in a sub-pixel configured to receive a reference voltage signal from the first line Vdd2-1.

[0358] In some embodiments, the orthographic projection of the second anode AD2 onto the substrate at least partially overlaps with the orthographic projection of the first line Vdd2-1 onto the substrate, and at least partially overlaps with the orthographic projection of the second line Vdd2-2 onto the substrate. Optionally, the orthographic projection of the second anode AD2 onto the substrate does not overlap with the orthographic projection of the third line Vdd2-3 onto the substrate. Optionally, the second anode AD2 is the anode in a sub-pixel configured to receive a reference voltage signal from the second line Vdd2-2.

[0359] In some embodiments, the orthographic projection of the third anode AD3 onto the substrate at least partially overlaps with the orthographic projection of the third line Vdd2-3 onto the substrate. Optionally, the orthographic projection of the third anode AD3 onto the substrate does not overlap with the orthographic projection of the first line Vdd2-1 onto the substrate, and does not overlap with the orthographic projection of the second line Vdd2-2 onto the substrate. Optionally, the third anode AD3 is the anode in a sub-pixel configured to receive a reference voltage signal from the third line Vdd2-3.

[0360] In some embodiments, the orthographic projection of the first anode AD1 on the substrate overlaps with the orthographic projection of a portion of the first line Vdd2-1 on the substrate, overlaps with the orthographic projection of a portion of the corresponding third voltage supply line Vss on the substrate, overlaps with the orthographic projection of a portion of the first data line DL1 among a plurality of data lines on the substrate, and overlaps with the orthographic projection of a portion of the second line Vdd2-2 on the substrate.

[0361] In some embodiments, the orthographic projections of a portion of the first line Vdd2-1, a portion of the corresponding third voltage supply line Vss, a portion of the first data line DL1 among a plurality of data lines, and a portion of the second line Vdd2-2 on the substrate are substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) uniformly distributed relative to the orthographic projection of the first anode AD1 on the substrate.

[0362] In some embodiments, the orthographic projection of the second anode AD2 on the substrate overlaps with the orthographic projection of a portion of the first line Vdd2-1 on the substrate, overlaps with the orthographic projection of a portion of the corresponding third voltage supply line Vss on the substrate, overlaps with the orthographic projection of a portion of the first data line DL1 among a plurality of data lines on the substrate, and overlaps with the orthographic projection of a portion of the second line Vdd2-2 on the substrate.

[0363] In some embodiments, the orthographic projections of a portion of the first line Vdd2-1, a portion of the corresponding third voltage supply line Vss, a portion of the first data line DL1 among a plurality of data lines, and a portion of the second line Vdd2-2 on the substrate are substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) uniformly distributed relative to the orthographic projection of the second anode AD2 on the substrate.

[0364] In some embodiments, the orthographic projection of the third anode AD3 on the substrate overlaps with the orthographic projection of a portion of the second data line DL2 among the plurality of data lines on the substrate, overlaps with the orthographic projection of a portion of the third line Vdd2-3 on the substrate, and overlaps with the orthographic projection of a portion of the third data line DL3 among the plurality of data lines on the substrate.

[0365] In some embodiments, the orthographic projections of a portion of the second data line DL2, a portion of the third line Vdd2-3, and a portion of the third data line DL3 are substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) of the orthographic projection of the third anode AD3 on the substrate are substantially uniformly distributed relative to the orthographic projection of the third anode AD3 on the substrate.

[0366] The inventors of this disclosure have discovered that the uniformity of the anode in a display panel can adversely affect image display. For example, color shift can be caused by anode tilt. This disclosure reveals that the signal line beneath the anode can significantly influence the degree of anode tilt. In one example, a signal line is positioned on one side beneath the anode, while no signal line is present on the other side. This results in an uneven surface of the planarization layer above the signal line. This uneven surface of the planarization layer, in turn, causes the anode above the planarization layer to tilt. For example, the presence of a signal line beneath the left portion of the planarization layer results in an uneven surface of the planarization layer, which in turn causes the anode above the planarization layer to tilt to the right. The tilted anode reflects more light towards the right side of the display panel. In a display panel, anodes associated with sub-pixels of different colors have different tilt angles, so light reflected by the anodes in sub-pixels of different colors is reflected at different angles to different colors of light. The cumulative effect of this problem leads to color shift at large viewing angles.

[0367] In this disclosure, by making the orthographic projection of a portion of the first line Vdd2-1, a portion of the corresponding third voltage supply line Vss, a portion of the first data line DL1 among a plurality of data lines, and a portion of the second line Vdd2-2 on the substrate substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) on the substrate relative to the orthographic projection of the first anode AD1 on the substrate, the array substrate achieves a uniform surface of the planarization layer below the first anode AD1.

[0368] By ensuring that the orthographic projections of a portion of the first line Vdd2-1, a portion of the corresponding third voltage supply line Vss, a portion of the first data line DL1 among the plurality of data lines, and a portion of the second line Vdd2-2 on the substrate are substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) uniform on the substrate relative to the orthographic projection of the second anode AD2, the array substrate achieves a uniform surface for the planarization layer beneath the second anode AD2. Therefore, color shift problems can be mitigated.

[0369] By ensuring that the orthographic projections of a portion of the second data line DL2, a portion of the third data line Vdd2-3, and a portion of the third data line DL3 are substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) onto the substrate relative to the orthographic projection of the third anode AD3, the array substrate achieves a uniform surface for the planarization layer beneath the third anode AD3. Therefore, color shift issues can be mitigated.

[0370] Figure 18A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 18B It is shown Figure 18A A schematic diagram of the arrangement of pixel driving circuits in a portion of an array substrate depicted in the figure. Figure 19A It is shown Figure 18A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure. Figure 19B It is shown Figure 18A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 19C It is shown Figure 18A A schematic diagram of the structure of the first gate metal layer in a portion of the array substrate depicted in the figure. Figure 19D It is shown Figure 18AA schematic diagram of the structure of the second gate metal layer in a portion of the array substrate depicted in the figure. Figure 19E It is shown Figure 18A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure. Figure 19F It is shown Figure 18A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure. Figure 19G It is shown Figure 18A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure. Figure 19H It is shown Figure 18A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure. Figure 19I It is shown Figure 18A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure. Figure 19J It is shown Figure 18A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram. Figure 19K It is shown Figure 18A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure. Figure 18A , Figure 18B ,as well as Figures 19A to 19K A portion of an array substrate is depicted having three adjacent pixel driving circuits arranged in a row, the three adjacent pixel driving circuits including PDC1, PDC2 and PDC3.

[0371] Reference Figure 2A , Figure 18A , Figure 18B and Figure 19A In some embodiments, the light-shielding layer includes a light-shielding element LS.

[0372] Reference Figure 2A , Figure 18A , Figure 18B and Figure 19BIn some embodiments, the semiconductor material layer includes an active layer of at least a plurality of transistors of a pixel driving circuit, the plurality of transistors including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td. Optionally, the semiconductor material layer also includes at least corresponding portions of the first electrodes of the plurality of transistors of the pixel driving circuit, the plurality of transistors including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the semiconductor material layer also includes at least corresponding portions of the second electrodes of the plurality of transistors of the pixel driving circuit, the plurality of transistors including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the semiconductor material layer includes an active layer of multiple transistors for a pixel driving circuit, a first electrode, and a second electrode. The multiple transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td. Various suitable semiconductor materials can be used to fabricate the semiconductor material layer. Examples of semiconductor materials used to fabricate the semiconductor material layer include silicon-based semiconductor materials such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0373] Figure 19B The transistors are labeled with markings indicating components of each of the multiple transistors (T1, T2, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0374] Optionally, the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, ACTr3, and ACTd), the first electrodes (S1, S2, S3, S4, Sr1, Sr2, Sr3, and Sd), and the second electrodes (D1, D2, D3, D4, Dr1, Dr2, Dr3, and Dd) of each transistor (T1, T2, T3, T4, Tr1, Tr2, Tr3, and Td) are located on the same layer.

[0375] In some embodiments, at least a portion of the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, and ACTd) of the plurality of transistors (T1, T2, T3, T4, Tr1, Tr2, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, and Dd) are integral structures.

[0376] In some embodiments, the semiconductor material layer further includes a plurality of first reset signal lines (e.g., individual first reset signal lines Vint1). In some embodiments, the corresponding first reset signal line Vint1 is connected to the first electrode of the first reset transistor of the pixel driving circuit in the same row. In some embodiments, the corresponding first reset signal line Vint1, the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, and ACTd) of the plurality of transistors (T1, T2, T3, T4, Tr1, Tr2, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, and Dd) are integral structures.

[0377] Reference Figure 2A , Figure 18A , Figure 18B and Figure 19C In some embodiments, the first gate metal layer includes a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of second light emission control signal lines (e.g., each second light emission control signal line em2), a first capacitor electrode Ce1 of the storage capacitor Cst, a first gate pad GEP1, a second gate pad GEP2, a third gate pad GEP3, and a fifth gate pad GEP5.

[0378] Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first gate metal layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first gate metal layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, each of the plurality of second reset control signal lines rst2, each of the plurality of second light emission control signal lines em2, the first capacitor electrode Ce1 of the storage capacitor Cst, the first gate pad GEP1, the second gate pad GEP2, the third gate pad GEP3, and the fifth gate pad GEP5 are located in the same layer.

[0379] In some embodiments, the first gate pad GEP1 includes the gate G1 of the first transistor T1 in the pixel driving circuit. In some embodiments, the second gate pad GEP2 includes the gate G2 of the second transistor T2 in the pixel driving circuit. In some embodiments, the third gate pad GEP3 includes the gate G3 of the third transistor T3 in the pixel driving circuit. In some embodiments, the fifth gate pad GEP5 includes the gate Gr1 of the first reset transistor Tr1 in the pixel driving circuit. The first gate pad GEP1 is connected to a corresponding first gate line GL1 among a plurality of first gate lines. The second gate pad GEP2 is connected to a corresponding second gate line GL2 among a plurality of second gate lines. The third gate pad GEP3 is connected to a corresponding first light emission control signal line em1 among a plurality of first light emission control signal lines. The fifth gate pad GEP5 is connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines.

[0380] Reference Figure 2A , Figure 18A , Figure 18B and Figure 19D In some embodiments, the second gate metal layer includes a plurality of second reset signal lines (e.g., individual second reset signal lines Vint2) and a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the second gate metal layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second gate metal layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of second reset signal lines and the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0381] Figure 19E The image depicts vias extending through the interlayer dielectric layer.

[0382] Reference Figure 2A , Figure 18A , Figure 18B and Figure 19F In some embodiments, the first signal line layer includes a plurality of first reset control signal lines (e.g., each first reset control signal line rst1), a plurality of first light emission control signal lines (e.g., each first light emission control signal line em1), a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of first gate lines (e.g., each first gate line GL1), a plurality of second gate lines (e.g., each second gate line GL2), a plurality of third reset signal lines (e.g., each third reset signal line Vint3), a plurality of first voltage supply lines (e.g., each first voltage supply line Vdd1), a first node connection line Cln1, a second node connection line Cln2, a data signal connection pad DCP, a relay electrode RE, and a reset signal connection pad Cli.

[0383] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the first signal line layer comprises a plurality of sublayers stacked together. In one example, the first signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure.

[0384] Optionally, multiple first reset control signal lines (e.g., each first reset control signal line rst1), multiple second reset control signal lines (e.g., each second reset control signal line rst2), multiple first light emission control signal lines (e.g., each first light emission control signal line em1), multiple first gate lines (e.g., each first gate line GL1), multiple second gate lines (e.g., each second gate line GL2), multiple third reset signal lines (e.g., each third reset signal line Vint3), multiple first voltage supply lines (e.g., each first voltage supply line Vdd1), first node connection line Cln1, second node connection line Cln2, data signal connection pad DCP, relay electrode RE, and reset signal connection pad Cli are located on the same layer.

[0385] In some embodiments, a first node connection line Cln1 in the pixel driving circuit connects multiple components of the pixel driving circuit to a first node N1. In some embodiments, the first node connection line Cln1 is connected to a first capacitor electrode Ce1 via a first via v1 and to a second transistor T2 (e.g., to a second electrode D2 of the second transistor T2) via a second via v2. Optionally, the first node connection line Cln1 corresponds to... Figure 2A The node N1 is depicted in the diagram.

[0386] In some embodiments, the second node connection line Cln2 in the pixel driving circuit connects multiple components of the pixel driving circuit to the second node N2. In some embodiments, the second node connection line Cln2 is connected to the second electrode of the third transistor and also to the second electrode of the third reset transistor. Optionally, the second node connection line Cln2 corresponds to... Figure 2A The second node N2 is depicted in the diagram.

[0387] Reference Figure 19A , Figure 19F , Figure 19H In the pixel driving circuit, the data signal connection pad DCP connects the corresponding data line DL to the first electrode S1 of the first transistor T1, and the data signal provided by the corresponding data line DL is transmitted to the first electrode S1 of the first transistor T1 through the signal connection pad DCP.

[0388] Reference Figure 19A , Figure 19F , Figure 19H The relay electrode RE connects the anode connection pad ACP to the second electrode D4 of the fourth transistor T4 in the pixel driving circuit. The anode connection pad ACP is also connected to the anode of the light-emitting element.

[0389] Reference Figure 18A , Figure 18B Figure 18D, Figure 18I Figure 19A and Figure 19B The reset signal connection line Cli connects the corresponding second reset signal line Vint2 to the first electrode Sr2 of the second reset transistor Tr2 in the pixel driving circuit, thereby providing a reset signal to the first electrode Sr2 of the second reset transistor Tr2 in the pixel driving circuit.

[0390] In some embodiments, the reset signal connection line Cli in at least one pixel driving circuit is also connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines in the second signal line layer.

[0391] In some embodiments, the relay electrode RE is connected to the second electrode of the fourth transistor and the second electrode of the second reset transistor, and is also connected to the anode connection pad.

[0392] Figure 19G The image depicts a via extending through the first planarization layer.

[0393] Reference Figure 2A , Figure 18A , Figure 18B and Figure 19H In some embodiments, the second signal line layer includes a plurality of second voltage supply lines (e.g., each second voltage supply line Vdd2), a plurality of third voltage supply lines (e.g., each third voltage supply line Vss), a plurality of data lines (e.g., each data line DL), a plurality of fourth reset signal lines (e.g., each fourth reset signal line Vint4), and an anode connection pad ACP.

[0394] In some embodiments, a plurality of first voltage supply lines and a plurality of second voltage supply lines are configured to provide a first reference voltage signal. In one example, the first reference voltage signal is a constant voltage signal, such as a high reference voltage signal. In some embodiments, a plurality of third voltage supply lines are configured to provide a second reference voltage signal. In one example, the second reference voltage signal is a constant voltage signal, such as a low reference voltage signal. In some embodiments, the first reference voltage signal has a voltage level higher than that of the second reference voltage signal.

[0395] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the second signal line layer comprises multiple sublayers stacked together. In one example, the second signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple second voltage supply lines (e.g., each second voltage supply line Vdd2), multiple data lines (e.g., each data line DL), multiple fourth reset signal lines (e.g., each fourth reset signal line Vint4), and an anode connection pad ACP are located in the same layer.

[0396] In some embodiments, a plurality of first voltage supply lines are configured to provide a first reference voltage signal. In one example, the first reference voltage signal is a constant voltage signal, such as a high reference voltage signal.

[0397] Figure 19I The image depicts vias extending through the first planarization layer PLN1.

[0398] Reference Figure 2A , Figure 18A , Figure 18B and Figure 19J In some embodiments, the anode layer includes multiple anodes (ADs).

[0399] Reference Figure 2A , Figure 18A , Figure 18B and Figure 19K In some embodiments, the array substrate includes a plurality of sub-pixel openings SA extending through the pixel defining layer PDL.

[0400] In some embodiments, refer to Figure 2A , Figure 18A , Figure 18B , Figures 19A to 19K Multiple first reset signal lines are located in a semiconductor material layer. In some embodiments, a corresponding first reset signal line Vint1 of the multiple first reset signal lines is connected to the first electrode of the first reset transistor of the pixel driving circuit in the same row. In some embodiments, the corresponding first reset signal line Vint1 and the first electrode of the first reset transistor of the pixel driving circuit in the same row are integral structures. In some embodiments, the corresponding first reset signal line Vint1, the active layer of the multiple transistors in the pixel driving circuit, at least a portion of the first electrode, and at least a portion of the second electrode are integral structures. In some embodiments, the corresponding first reset signal line Vint1, the active layer (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, and ACTd) of all transistors (T1, T2, T3, T4, Tr1, Tr2, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S2, S3, S4, Sr1, Sr2, and Sd), and at least a portion of the second electrode (D1, D2, D3, D4, Dr1, Dr2, and Dd) are integral structures. The inventors of this disclosure have discovered that by providing a plurality of first reset signal lines in a semiconductor material layer, the need to form vias in the array substrate is eliminated.

[0401] In some embodiments, a plurality of first light-emitting control signal lines are located in a first signal line layer, and a plurality of second light-emitting control signal lines are located in a first gate metal layer. By providing a plurality of first light-emitting control signal lines in the first signal line layer and a plurality of second light-emitting control signal lines in the first gate metal layer, the first signal line layer can have a lower wiring density (e.g., reduced from 29.84% to 27.98%). The inventors of this disclosure have found that this structure prevents short circuits in the wiring of the first signal line layer.

[0402] In some embodiments, a plurality of first reset signal lines are located in a semiconductor material layer, a plurality of second reset signal lines are located in a second gate metal layer, and a plurality of third reset signal lines are located in a first signal line layer.

[0403] Figure 20A It is shown Figure 18A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 20B It is shown Figure 18A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 20C It is shown Figure 18A A diagram illustrating the structure of the light-shielding layer in a portion of the array substrate depicted in the image. Figure 20D It is shown Figure 18A A schematic diagram of the structure of the second gate pad in a portion of the array substrate depicted in the figure. Figure 20E It is shown Figure 18A A schematic diagram of the structure of the semiconductor material layer, the light-shielding layer, and the second gate pad in a portion of the array substrate depicted in the diagram.

[0404] In some embodiments, the first reset transistor is a dual-gate transistor, and the active layer ACTr1 of the first reset transistor includes two channel portions spaced apart from each other by a first intermediate portion IP1. The first intermediate portion IP1 connects the two portions of the active layer ACTr1 of the first reset transistor.

[0405] Reference Figures 20A to 20E In some embodiments, the semiconductor material layer includes a first protrusion P1 that protrudes away from a first main line ML1 of the semiconductor material layer. In some embodiments, the first protrusion P1 includes at least a portion of a first intermediate portion IP1.

[0406] In some embodiments, the second transistor is a dual-gate transistor, and the active layer ACT2 of the second transistor includes two channel portions spaced apart from each other by a second intermediate portion IP2. The second intermediate portion IP2 connects the two portions of the active layer ACT2 of the second transistor.

[0407] Reference Figures 20A to 20E In some embodiments, the semiconductor material layer includes a second protrusion P2 that protrudes away from the first main line ML1 of the semiconductor material layer. In some embodiments, the second protrusion P2 includes at least a portion of a second intermediate portion IP2.

[0408] In some embodiments, the light-shielding member LS includes a third protrusion P3 that protrudes away from the second main line ML2 of the light-shielding member LS. In some embodiments, the orthographic projection of the third protrusion P3 on the substrate covers the orthographic projection of the first protrusion P1 on the substrate. The inventors of this disclosure have discovered that by providing the first protrusion P1 and the third protrusion P3, the capacitance with the first intermediate portion IP1 can be enhanced, and the voltage level at that portion can be stabilized.

[0409] In some embodiments, the orthogonal projection of the light-shielding member LS on the substrate covers the orthogonal projection of the second protrusion P2 on the substrate. The inventors of this disclosure have discovered that by providing the second protrusion P2, the capacitance with the second intermediate portion IP2 can be enhanced, the voltage level at that portion can be stabilized, and the leakage current of the second transistor can be reduced, thereby improving low-frequency performance and reducing bright spot defects.

[0410] In some embodiments, the second gate pad GEP2 comprises two portions of the gate G2 of the second transistor, the two portions of the gate G2 being spaced apart from each other by a connection portion CP. In some embodiments, the orthographic projection of the connection portion CP onto the substrate and the orthographic projection of the light-shielding member LS onto the substrate are substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) non-overlapping. The inventors of this disclosure have discovered that by making the orthographic projection of the connection portion CP onto the substrate substantially non-overlapping with the orthographic projection of the light-shielding member LS onto the substrate, the load on the second gate pad GEP2 can be reduced.

[0411] On the other hand, the present invention provides a display device comprising an array substrate manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0412] On the other hand, this disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a first reset transistor having a gate coupled to a corresponding first reset control signal line; forming a compensation transistor having a gate coupled to a corresponding second gate line; forming a first light-emitting control transistor having a gate coupled to a corresponding first light-emitting control signal line; and forming a second light-emitting control transistor having a gate coupled to a corresponding second light-emitting control signal line. Optionally, the corresponding first reset control signal line and the corresponding second gate line are configured to receive different levels of output control signals from a first scan circuit. Optionally, the corresponding first light-emitting control signal line and the corresponding second light-emitting control signal line are configured to receive different levels of output control signals from a second scan circuit.

[0413] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms 'the invention, the present invention,' etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of 'first,' 'second,' etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A pixel driving circuit, comprising: A first reset transistor has a gate coupled to a corresponding first reset control signal line; A compensation transistor having a gate coupled to a corresponding second gate line; A first light-emitting control transistor has a gate coupled to a corresponding first light-emitting control signal line; as well as The second light-emitting control transistor has a gate coupled to a corresponding second light-emitting control signal line; The corresponding first reset control signal line and the corresponding second gate line are configured to receive different levels of output control signals from the first scan circuit; as well as The corresponding first light emission control signal line and the corresponding second light emission control signal line are configured to receive different levels of output control signals from the second scanning circuit.

2. The pixel driving circuit according to claim 1, wherein, The corresponding second gate line is configured to receive the output control signal from the nth stage of the first scanning circuit; as well as The corresponding first reset control signal line is configured to receive an output control signal from the previous stage of the first scanning circuit.

3. The pixel driving circuit according to claim 1, wherein, The corresponding first light emission control signal line is configured to receive the output control signal of the mth stage from the second scanning circuit; as well as The corresponding second light emission control signal line is configured to receive the output control signal of the (m-1)th stage from the second scanning circuit, where m is an integer greater than or equal to 2.

4. An array substrate, comprising: Pixel driving circuit according to any one of claims 1 to 3; The first scanning circuit includes a series-cascaded multi-stage scanning unit; as well as The second scanning circuit includes a series-cascaded multi-stage scanning unit; The first scanning circuit is configured to output an output control signal to a multi-row pixel driving circuit in the array substrate through the multi-level scanning unit. as well as The second scanning circuit is configured to output an output control signal to a multi-row pixel driving circuit in the array substrate through the multi-level scanning unit.

5. An array substrate, comprising a semiconductor material layer; in, The semiconductor material layer includes: Multiple first reset signal lines; and The active layer, first electrode, and second electrode of multiple transistors in a multiple pixel driving circuit; Wherein, a corresponding first reset signal line among the plurality of first reset signal lines is connected to the first electrode of the first reset transistor of the pixel driving circuit in the same row; and The corresponding first reset signal line and the first electrode of the first reset transistor of the pixel driving circuit in the same row are integral structures.

6. The array substrate according to claim 5 further includes a first signal line layer, which is located on the side of the semiconductor material layer away from the substrate. in, The first signal line layer includes: Multiple first light emission control signal lines; and Multiple second light-emitting control signal lines.

7. The array substrate according to claim 5, further comprising: The second gate metal layer is located on the side of the semiconductor material layer away from the substrate. as well as The first signal line layer is located on the side of the second gate metal layer away from the substrate. The array substrate includes: Multiple second reset signal lines; and Multiple third reset signal lines; The plurality of first reset signal lines are located in the semiconductor material layer; The plurality of second reset signal lines are located in at least one of the second gate metal layer or the first signal line layer; and The plurality of third reset signal lines are located in at least one of the first signal line layer or the second gate metal layer.

8. The array substrate according to claim 5, further comprising: The second signal line layer is located on the side of the semiconductor material layer away from the substrate. as well as An anode layer is located on the side of the second signal line layer away from the substrate. The second signal line layer includes: Multiple second voltage supply lines; and Multiple data cables; The plurality of second voltage supply lines include a first line, a second line, and a third line; The first line, the second line, and the third line are configured to provide reference voltage signals to the three adjacent pixel driving circuits, respectively. The first line includes a main body, a first ring, and a second ring; The array substrate includes a first opening and a second opening extending through the first line; The first ring includes a first branch that at least partially surrounds the first opening; and The second ring includes a second branch that at least partially surrounds the second opening.

9. The array substrate according to claim 8, wherein, The orthographic projection of the first anode on the substrate overlaps with the orthographic projection of a portion of the body of the first line on the substrate, overlaps with the orthographic projection of a portion of the first ring of the first line on the substrate, overlaps with the orthographic projection of a portion of the first data line among the plurality of data lines on the substrate, and overlaps with the orthographic projection of a portion of the second line on the substrate.

10. The array substrate according to claim 5, further comprising: Storage capacitor including the second capacitor electrode; as well as Corresponding to the first gate line; Wherein, the orthographic projection of a portion of the corresponding first gate line on the substrate overlaps with the orthographic projection of at least a portion of the second electrode of the semiconductor material layer including the second transistor and / or at least a portion of the second electrode of the first reset transistor on the substrate; The orthographic projection of a portion of the second capacitor electrode of the storage capacitor on the substrate at least partially overlaps with the orthographic projection of a portion of the corresponding first gate line on the substrate, and at least partially overlaps with the orthographic projection of at least a portion of the second electrode of the semiconductor material layer including the second transistor and / or at least a portion of the second electrode of the first reset transistor on the substrate. The orthographic projection of a portion of the corresponding second gate line on the substrate overlaps with the orthographic projection of at least a portion of the second electrode of the semiconductor material layer including the second transistor and / or at least a portion of the second electrode of the first reset transistor on the substrate; and The orthographic projection of a portion of the second capacitor electrode of the storage capacitor on the substrate at least partially overlaps with the orthographic projection of a portion of the corresponding second gate line on the substrate, and at least partially overlaps with the orthographic projection of at least a portion of the second electrode of the semiconductor material layer including the second transistor and / or at least a portion of the second electrode of the first reset transistor on the substrate.

11. The array substrate according to claim 5, further comprising: The first gate metal layer is located on the side of the semiconductor material layer away from the substrate. as well as A second gate metal layer is located on the side of the first gate metal layer away from the substrate. The first gate metal layer includes a plurality of second light-emitting control signal lines; and The second gate metal layer includes a plurality of first light emission control signal lines.

12. The array substrate according to claim 11, further comprising a first signal line layer located on the side of the second gate metal layer away from the substrate; in, The first signal line layer includes a second node connection line; The pixel driving circuit in the plurality of pixel driving circuits includes a third reset transistor; The second node connection line is connected to the second electrode of the first light-emitting control transistor and also to the second electrode of the third reset transistor; The orthographic projection of the second node connection line on the substrate partially overlaps with the orthographic projection of the corresponding first light emission control signal line among the plurality of first light emission control signal lines on the substrate, and also partially overlaps with the orthographic projection of the corresponding second light emission control signal line among the plurality of second light emission control signal lines on the substrate.

13. The array substrate according to claim 5, further comprising: The first gate metal layer is located on the side of the semiconductor material layer away from the substrate. A second gate metal layer is located on the side of the first gate metal layer away from the substrate. as well as The first signal line layer is located on the side of the second gate metal layer away from the substrate. The first gate metal layer includes a third gate pad; The pixel driving circuit in the plurality of pixel driving circuits includes a first light-emitting control transistor; The third gate pad includes the gate of the first light-emitting control transistor; The second gate metal layer includes a plurality of first light emission control signal lines; The first signal line layer includes a light emission control signal connection pad; The light emission control signal connection pad is connected to the third gate pad and to the corresponding first light emission control signal line; as well as The orthographic projection of the light-emitting control signal pad on the substrate does not overlap with the orthographic projection of the semiconductor material layer on the substrate.

14. The array substrate according to claim 5, further comprising a second gate metal layer located on the side of the semiconductor material layer away from the substrate; in, The second gate metal layer includes a plurality of first light emission control signal lines; The pixel driving circuit in the plurality of pixel driving circuits includes a first light-emitting control transistor and a driving transistor; The portion of the semiconductor material layer having the first electrode of the first light-emitting control transistor, the active layer, the second electrode, and the first electrode of the driving transistor has a U-shaped shape. The orthographic projection of a corresponding first light-emitting control signal line among the plurality of first light-emitting control signal lines on the substrate at least partially overlaps with the orthographic projection of the bottom of the U-shaped form on the substrate; and The bottom of the U-shape includes at least a portion of the second electrode of the third transistor.

15. The array substrate according to claim 5, further comprising: The second gate metal layer is located on the side of the semiconductor material layer away from the substrate. as well as The first signal line layer is located on the side of the second gate metal layer away from the substrate. The first signal line layer includes a second node connection line; The pixel driving circuit in the plurality of pixel driving circuits includes a first light-emitting control transistor, a third reset transistor, and a driving transistor. The second node connection line is connected to the second electrode of the first light-emitting control transistor and also to the second electrode of the third reset transistor; The orthographic projection of the second node connection line on the substrate does not overlap with the orthographic projection of the corresponding first light emission control signal line among the plurality of first light emission control signal lines on the substrate. The orthographic projection of at least a portion of the second electrode of the first light-emitting control transistor and / or at least a portion of the first electrode of the driving transistor on the substrate of the semiconductor material layer at least partially overlaps with the orthographic projection of the corresponding first light-emitting control signal line on the substrate.

16. The array substrate according to claim 15, wherein, The second gate metal layer also includes a second capacitor electrode for storing the capacitor; The orthographic projection of a portion of the corresponding first light-emitting control signal line on the substrate overlaps with the orthographic projection of at least a portion of the second electrode of the semiconductor material layer including the third transistor and / or at least a portion of the first electrode of the driving transistor on the substrate. as well as The orthographic projection of a portion of the second capacitor electrode of the storage capacitor on the substrate at least partially overlaps with the orthographic projection of a portion of the corresponding first light-emitting control signal line on the substrate, and at least partially overlaps with the orthographic projection of at least a portion of the second electrode of the semiconductor material layer including the third transistor and / or at least a portion of the first electrode of the driving transistor on the substrate.

17. The array substrate according to claim 5, further comprising: The second signal line layer is located on the side of the semiconductor material layer away from the substrate. as well as An anode layer is located on the side of the second signal line layer away from the substrate. The second signal line layer includes: Multiple secondary voltage supply lines; Multiple data cables; and Multiple third voltage supply lines; The plurality of second voltage supply lines include a first line, a second line, and a third line; The first line, the second line, and the third line are configured to provide reference voltage signals to the three adjacent pixel driving circuits, respectively. The orthographic projection of the first anode on the substrate overlaps with the orthographic projection of a portion of the first line on the substrate, overlaps with the orthographic projection of a portion of a corresponding third voltage supply line among the plurality of third voltage supply lines on the substrate, overlaps with the orthographic projection of a portion of the first data line among the plurality of data lines on the substrate, and overlaps with the orthographic projection of a portion of the second line on the substrate.

18. The array substrate according to claim 5, further comprising a light-shielding layer; in, The pixel driving circuit in the plurality of pixel driving circuits includes a first reset transistor; The first reset transistor is a dual-gate transistor, and the active layer of the first reset transistor includes two channel portions spaced apart from each other by a first intermediate portion; The first intermediate portion connects the two channel portions of the active layer of the first reset transistor; The semiconductor material layer includes a first protruding portion that protrudes from a first main line away from the semiconductor material layer; The first protruding portion includes at least a portion of the first intermediate portion; The light-shielding layer includes a light-shielding component; The light-shielding member includes a third protruding portion that protrudes from the second main line of the light-shielding member; as well as The orthographic projection of the third protrusion onto the substrate covers the orthographic projection of the first protrusion onto the substrate.

19. The array substrate according to claim 5, further comprising: Light-shielding layer; as well as A first gate metal layer is located on the side of the semiconductor material layer away from the light-shielding layer; The pixel driving circuit in the plurality of pixel driving circuits includes a compensation transistor; The first gate metal layer includes a second gate pad; The second gate pad includes the gate of the compensation transistor; The compensation transistor is a dual-gate transistor, and the active layer of the compensation transistor includes two channel portions spaced apart from each other by a second intermediate portion. The second intermediate portion connects the two channel portions of the active layer of the compensation transistor; The semiconductor material layer includes a second protruding portion that protrudes from a first main line away from the semiconductor material layer; The second protruding portion includes at least a portion of the second intermediate portion; The light-shielding layer includes a light-shielding component; The orthogonal projection of the light-shielding member on the substrate covers the orthogonal projection of the second protruding portion on the substrate. The second gate pad includes two portions of the gate of the compensation transistor, the two portions of the gate being spaced apart from each other by a connecting portion; and The orthographic projection of the connecting portion on the substrate and the orthographic projection of the light-shielding member on the substrate do not substantially overlap.

20. A display device comprising an array substrate according to any one of claims 4 to 19, and one or more integrated circuits connected to the array substrate.

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