Pixel circuit, driving method and display device

Abstract

A pixel circuit, a driving method and a display device. The pixel circuit comprises a driving circuit (10), a compensation control circuit (11), a on-off control circuit (12) and a first reset circuit (13); the display period of the pixel circuit comprises a refresh frame (FS); the refresh frame (FS) comprises a data writing stage (S14) and a refresh light emitting stage (S17); the refresh frame (FS) further comprises at least one of a first control stage (S15) and a second control stage (S10); the first control stage (S15) is arranged between the data writing stage (S14) and the refresh light emitting stage (S17), and the second control stage (S10) is arranged between the data writing stage (S14) and the refresh light emitting stage (S17); the first reset circuit (13) writes a voltage signal provided by a first initial voltage terminal (I1) into a control node (NC) under the control of a first reset control signal in the first control stage (S15); the on-off control circuit (GP) is used for controlling the communication between the control terminal of the driving circuit (10) and the control node (NC) under the control of a second scanning signal in the second control stage (S10), thereby improving the horizontal stripe and low frequency flicker phenomenon.

Description

Pixel circuits, driving methods, and display devices Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a pixel circuit, driving method, and display device. Background Technology

[0002] With diverse application needs, the market demand for low-refresh-rate display screens is becoming increasingly urgent. During reliability testing of related display products, prolonged circuit bias and high temperatures can cause a shift in the characteristics of oxide transistors. Slight changes in threshold voltage can lead to changes in luminous current, especially at low brightness and low grayscale, where this problem is more severe and horizontal stripe defects are prone to occur during reliability testing. Summary of the Invention

[0003] In one aspect, embodiments of this disclosure provide a pixel circuit, including a driving circuit, a compensation control circuit, an on / off control circuit, and a first reset circuit;

[0004] The compensation control circuit is electrically connected to the first scanning end, the first end of the driving circuit, and the control node, respectively, and is used to control the connection or disconnection between the first end of the driving circuit and the control node under the control of the first scanning signal provided by the first scanning end.

[0005] The on / off control circuit is electrically connected to the second scanning terminal, the control terminal of the driving circuit and the control node respectively, and is used to control the connection or disconnection between the control terminal of the driving circuit and the control node under the control of the second scanning signal provided by the second scanning terminal.

[0006] The first reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal, and the control node, respectively, and is used to control the connection or disconnection between the first initial voltage terminal and the control node under the control of the first reset control signal provided by the first reset control terminal;

[0007] The display cycle of the pixel circuit includes a refresh frame; the refresh frame includes a data writing phase and a refresh light emission phase;

[0008] The refresh frame further includes at least one of a first control phase and a second control phase;

[0009] The first control phase is set between the data writing phase and the refresh emission phase, and the second control phase is set between the data writing phase and the refresh emission phase;

[0010] The first reset circuit is used to write the voltage signal provided by the first initial voltage terminal into the control node under the control of the first reset control signal during the first control phase.

[0011] The on / off control circuit is used, during the second control phase, under the control of the second scanning signal, to control the connection between the control terminal of the drive circuit and the control node.

[0012] Optionally, the refresh frame includes the second control phase; the display cycle further includes a hold frame; the hold frame includes a third control phase and a hold-light phase set sequentially.

[0013] The on / off control circuit is used in the third control phase to control the connection between the control terminal of the drive circuit and the control node under the control of the second scanning signal.

[0014] Optionally, the refresh frame includes the first control phase; the refresh frame also includes a first reset phase set before the data writing phase;

[0015] The first initial voltage terminal is used to provide a first initial voltage during the first reset phase and a second first initial voltage during the first control phase.

[0016] The first reset circuit is used to write a first initial voltage into the control node under the control of a first reset control signal during the first reset phase, and to write a second initial voltage into the control node under the control of a first reset control signal during the first control phase.

[0017] The first initial voltage is different from the second initial voltage.

[0018] Optionally, the driving circuit includes a p-type transistor as the driving transistor;

[0019] The voltage value of the first initial voltage is less than the voltage value of the second initial voltage.

[0020] Optionally, the first initial voltage has a value of -3V; the second initial voltage has a value of -0.5V.

[0021] Optionally, the refresh frame includes the first control phase, the first reset circuit includes a first transistor; the gate of the first transistor is electrically connected to the first reset control terminal, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the control node.

[0022] During the first control phase, the first transistor is not fully turned on under the control of the first reset control signal.

[0023] Optionally, the refresh frame may further include a first reset phase set before the data writing phase;

[0024] During the first reset phase, the first transistor is fully turned on under the control of the first reset control signal;

[0025] The first transistor is an n-type transistor; during the first reset phase, the potential of the first reset control signal is greater than the potential of the first reset control signal during the first control phase; or,

[0026] The first transistor is a p-type transistor. During the first reset phase, the potential of the first reset control signal is lower than the potential of the first reset control signal during the first control phase.

[0027] Optionally, the first transistor is an n-type transistor; in the first reset phase, the potential of the first reset control signal is 7V; in the first control phase, the potential of the first reset control signal is 1V. Optionally, the refresh frame includes the first control phase; the display cycle further includes a hold frame, which includes a fourth control phase and a hold-light phase set sequentially.

[0028] The first reset circuit is also used in the fourth control phase to write the voltage signal provided by the first initial voltage terminal into the control node under the control of the first reset control signal.

[0029] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element and a second reset circuit;

[0030] The refresh frame further includes a fifth control phase disposed between the data writing phase and the refresh illumination phase; the hold frame further includes a sixth control phase disposed before the hold illumination phase;

[0031] The second reset circuit is electrically connected to the second reset control terminal, the first electrode of the light-emitting element, and the second initial voltage terminal, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal in the fifth control stage and the sixth control stage.

[0032] Optionally, the driving circuit further includes a second reset circuit; the refresh frame further includes a fifth control phase disposed between the data writing phase and the refresh light emission phase; the holding frame further includes a sixth control phase disposed before the holding light emission phase;

[0033] The second reset circuit is electrically connected to the second reset control terminal, the first electrode of the light-emitting element, and the second initial voltage terminal, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal during the fifth control stage and the sixth control stage.

[0034] Optionally, the start time of the second control phase is set before the start time of the fifth control phase, and the start time of the third control phase is set before the start time of the sixth control phase; or,

[0035] The start time of the fifth control stage is set before the start time of the second control stage, and the start time of the sixth control stage is set before the start time of the third control stage.

[0036] Optionally, the pixel circuit further includes a data writing circuit; the display cycle further includes a conduction phase; the conduction phase includes the data writing phase, and the end time of the conduction phase is later than the end time of the data writing phase;

[0037] The data writing circuit is electrically connected to the second scanning terminal, the data line and the second terminal of the driving circuit, respectively, and is used to write the data voltage on the data line to the second terminal of the driving circuit under the control of the second scanning signal provided by the second scanning terminal during the data writing stage.

[0038] The compensation control circuit is used to control the connection between the first end of the drive circuit and the control node under the control of the first scan signal during the conduction phase.

[0039] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, a third reset circuit, a first energy storage circuit, and a second energy storage circuit;

[0040] The third reset circuit is electrically connected to the second reset control terminal, the third initial voltage terminal, and the second terminal of the drive circuit, respectively, and is used to control the connection or disconnection between the third initial voltage terminal and the second terminal of the drive circuit under the control of the second reset control signal provided by the second reset control terminal;

[0041] The first energy storage circuit is electrically connected to the control terminal of the drive circuit to maintain the potential of the control terminal of the drive circuit.

[0042] The second energy storage circuit is electrically connected to the control node and is used to maintain the potential of the control node;

[0043] The compensation control circuit includes oxide transistors, and the on / off control circuit includes low-temperature polysilicon transistors.

[0044] In a second aspect, embodiments of this disclosure provide a driving method applied to the aforementioned pixel circuit, wherein the display cycle of the pixel circuit includes a refresh frame; the refresh frame includes a data writing phase and a refresh light emission phase;

[0045] The refresh frame includes at least one of a first control phase and a second control phase; the first control phase is disposed between the data writing phase and the refresh emission phase, and the second control phase is disposed between the data writing phase and the refresh emission phase;

[0046] The driving method includes:

[0047] During the first control phase, the first reset circuit, under the control of the first reset control signal, writes the voltage signal provided by the first initial voltage terminal into the control node;

[0048] In the second control phase, the on / off control circuit connects the control terminal of the drive circuit with the control node under the control of the second scanning signal.

[0049] Optionally, the refresh frame includes the second control phase; the display cycle further includes a hold frame; the hold frame includes a third control phase and a hold-light phase set sequentially.

[0050] The driving method further includes:

[0051] In the third control phase, the on / off control circuit, under the control of the second scanning signal, controls the connection between the control terminal of the drive circuit and the control node.

[0052] Optionally, the refresh frame includes the first control phase; the refresh frame further includes a first reset phase set before the data writing phase; the driving method further includes:

[0053] During the first reset phase, the first initial voltage terminal provides a first initial voltage, and the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the control node.

[0054] During the first control phase, the first initial voltage terminal provides a second first initial voltage, and the first reset circuit, under the control of the first reset control signal, writes the second first initial voltage into the control node.

[0055] The first initial voltage is different from the second initial voltage.

[0056] Optionally, the refresh frame includes the first control phase; the driving method further includes:

[0057] During the first control phase, the potential of the first reset control signal is adjusted to control the transistors included in the first reset circuit to not be fully turned on.

[0058] The refresh frame further includes a first reset phase set before the data writing phase; the driving method further includes:

[0059] During the first reset phase, the first reset circuit, under the control of the first reset control signal, controls the transistors included in the first reset circuit to be fully turned on.

[0060] The first reset circuit includes an n-type transistor. During the first reset phase, the potential of the first reset control signal is greater than the potential of the first reset control signal during the first control phase; or...

[0061] The first reset circuit includes a p-type transistor. During the first reset phase, the potential of the first reset control signal is lower than that during the first control phase.

[0062] Optionally, the refresh frame includes the first control phase; the display cycle further includes a hold frame, which includes a fourth control phase and a hold-light phase set sequentially; the driving method further includes:

[0063] In the fourth control phase, the first reset circuit, under the control of the first reset control signal, writes the voltage signal provided by the first initial voltage terminal into the control node.

[0064] The driving circuit further includes a second reset circuit; the refresh frame further includes a fifth control phase disposed between the data writing phase and the refresh light emission phase; the holding frame further includes a sixth control phase disposed before the holding light emission phase; the driving method further includes:

[0065] In the fifth and sixth control phases, the second reset circuit, under the control of the second reset control signal, writes the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element.

[0066] In a third aspect, embodiments of this disclosure provide a display device including the pixel circuit described above. Attached Figure Description

[0067] Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0068] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0069] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0070] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0071] Figure 5 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0072] Figure 6 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;

[0073] Figure 7 is a brightness waveform curve of at least one embodiment of the pixel circuit shown in Figure 5;

[0074] Figure 8A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;

[0075] Figure 8B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;

[0076] Figure 8C is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;

[0077] Figure 9A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;

[0078] Figure 9B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;

[0079] Figure 9C is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;

[0080] Figure 10A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;

[0081] Figure 10B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;

[0082] Figure 10C is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;

[0083] Figure 11 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;

[0084] Figure 12 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;

[0085] Figure 13 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;

[0086] Figure 14 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;

[0087] Figure 15 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;

[0088] Figure 16 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0089] Figure 17 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 16. Detailed Implementation

[0090] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0091] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0092] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0093] The pixel circuit described in this embodiment includes a driving circuit, a compensation control circuit, an on / off control circuit, and a first reset circuit;

[0094] The compensation control circuit is electrically connected to the first scanning end, the first end of the driving circuit, and the control node, respectively, and is used to control the connection or disconnection between the first end of the driving circuit and the control node under the control of the first scanning signal provided by the first scanning end.

[0095] The on / off control circuit is electrically connected to the second scanning terminal, the control terminal of the driving circuit and the control node respectively, and is used to control the connection or disconnection between the control terminal of the driving circuit and the control node under the control of the second scanning signal provided by the second scanning terminal.

[0096] The first reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal, and the control node, respectively, and is used to control the connection or disconnection between the first initial voltage terminal and the control node under the control of the first reset control signal provided by the first reset control terminal;

[0097] The display cycle of the pixel circuit includes a refresh frame; the refresh frame includes a data writing phase and a refresh light emission phase that are set sequentially.

[0098] The refresh frame further includes at least one of a first control phase and a second control phase;

[0099] The first control phase is set between the data writing phase and the refresh emission phase, and the second control phase is set between the data writing phase and the refresh emission phase;

[0100] The first reset circuit is used to write the voltage signal provided by the first initial voltage terminal into the control node under the control of the first reset control signal during the first control phase.

[0101] The on / off control circuit is used, during the second control phase, under the control of the second scanning signal, to control the connection between the control terminal of the drive circuit and the control node.

[0102] In the pixel circuit described in this embodiment, the transistor included in the on / off control circuit can be an LTPS (Low Temperature Polycrystalline Silicon) transistor, and the transistor included in the compensation control circuit can be an oxide transistor. The LTPS transistor in the on / off control circuit isolates the gate of the driving transistor in the driving circuit from the oxide transistor in the compensation control circuit. Since the backplane process for low temperature polycrystalline silicon is relatively mature and has good process stability, the characteristics of the LTPS transistor in the on / off control circuit are relatively stable. The pixel circuit described in this embodiment includes an on / off control circuit, which can set the transistor in the on / off control circuit to turn off before the transistor in the compensation control circuit. This eliminates the influence of characteristic differences of the transistor in the compensation control circuit on the light-emitting current, removes the influence of gate potential changes in the driving transistor caused by characteristic shifts in the oxide transistor during the reliability process, and thus improves the horizontal stripe defects during the reliability process.

[0103] In related technologies, during the light-emitting stage, due to the high potential of the control node, it continuously leaks current to the first node (the first node is the node electrically connected to the control terminal of the driving circuit) within one frame, thus causing flickering.

[0104] In at least one embodiment of this disclosure, the refresh frame includes the second control phase; the display cycle may further include a hold frame; the hold frame may include a third control phase and a hold-light phase set sequentially.

[0105] The on / off control circuit is used in the third control phase to control the connection between the control terminal of the drive circuit and the control node under the control of the second scanning signal.

[0106] Based on the above problems, in at least one embodiment of this disclosure,

[0107] According to one specific implementation, a first control stage can be set between the data writing stage and the refresh light emission stage; in the first control stage, the first reset circuit, under the control of the first reset control signal, writes the voltage signal provided by the first initial voltage terminal into the control node to pull down the potential of the control node, reduce the leakage current from the control node to the first node, which is conducive to maintaining the potential of the first node and improving the flickering phenomenon.

[0108] According to another specific embodiment, a second control stage can be set between the data writing stage and the refresh light emission stage; a third control stage can be set within the holding frame and before the holding light emission stage; in the second control stage included in the refresh frame and the third control stage included in the holding frame, the on / off control circuit controls the connection between the control terminal of the driving circuit and the control node under the control of the second scan signal, so that the leakage current between the control node and the first node is consistent in the refresh light emission stage and the holding light emission stage, thereby improving the flickering phenomenon.

[0109] As shown in FIG1, the pixel circuit described in at least one embodiment of the present disclosure may include a driving circuit 10, a compensation control circuit 11, an on / off control circuit 12, and a first reset circuit 13.

[0110] The compensation control circuit 11 is electrically connected to the first scanning terminal GN, the first terminal of the driving circuit 10, and the control node NC, respectively, and is used to control the connection or disconnection between the first terminal of the driving circuit 10 and the control node NC under the control of the first scanning signal provided by the first scanning terminal GN.

[0111] The on / off control circuit 12 is electrically connected to the second scanning end GP, the control end of the driving circuit 10 and the control node NC respectively, and is used to control the connection or disconnection between the control end of the driving circuit 10 and the control node NC under the control of the second scanning signal provided by the second scanning end GP.

[0112] The first reset circuit 13 is electrically connected to the first reset control terminal RN, the first initial voltage terminal I1 and the control node NC respectively, and is used to control the connection or disconnection between the first initial voltage terminal I1 and the control node NC under the control of the first reset control signal provided by the first reset control terminal RN.

[0113] The first node N1 is electrically connected to the control terminal of the drive circuit 10.

[0114] In at least one embodiment of this disclosure, the refresh frame includes the first control phase; the refresh frame also includes a first reset phase set before the data writing phase;

[0115] The first initial voltage terminal is used to provide a first initial voltage during the first reset phase and a second first initial voltage during the first control phase.

[0116] The first reset circuit is used to write a first initial voltage into the control node under the control of a first reset control signal during the first reset phase, and to write a second initial voltage into the control node under the control of a first reset control signal during the first control phase.

[0117] The first initial voltage is different from the second initial voltage.

[0118] In specific implementation, when the refresh frame includes a first control phase, a first reset phase can be set within the refresh frame before the data writing phase. In the first reset phase, the first initial voltage terminal provides a first initial voltage, and in the first control phase, the first initial voltage terminal provides a second first initial voltage. The voltage values ​​of the first and second first initial voltages are not equal. In the first reset phase, under the control of the first reset control signal, the first reset circuit writes the first initial voltage to the control node. In the first control phase, under the control of the first reset control signal, the first reset circuit writes the second initial voltage to the control node, so that during the refresh and light-emitting phase, the potential of the control node is not much different from the potential of the first node, reducing leakage current from the control node to the first node and improving flickering. Under this premise, in the first reset phase, when the on / off control circuit controls the connection between the control terminal of the driving circuit and the control node under the control of the second scan signal, the first initial voltage can be written to the first node, so that the driving transistors included in the driving circuit can be fully turned on at the start of the data writing phase.

[0119] Optionally, the driving circuit includes a p-type transistor as the driving transistor;

[0120] The voltage value of the first initial voltage is less than the voltage value of the second initial voltage.

[0121] In a specific implementation, when the driving transistor is a p-type transistor, the voltage value of the first initial voltage can be less than the voltage value of the second initial voltage.

[0122] In at least one embodiment of this disclosure, the refresh frame includes the first control phase; the first reset circuit includes a first transistor; the gate of the first transistor is electrically connected to the first reset control terminal, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the control node.

[0123] During the first control phase, the first transistor is not fully turned on under the control of the first reset control signal.

[0124] In practical implementation, the potential of the first reset control signal can be adjusted in the first control stage so that the first transistor is not fully turned on, thereby reducing the pull-down of the NC potential and achieving a balance between the NC potential and the N1 potential as much as possible. This reduces the leakage current from NC to N1 and helps to improve the flickering phenomenon.

[0125] In at least one embodiment of this disclosure, the refresh frame further includes a first reset phase set prior to the data writing phase;

[0126] During the first reset phase, the first transistor is fully turned on under the control of the first reset control signal.

[0127] In practice, during the first reset phase, the first transistor can be fully turned on by adjusting the potential of the first reset control signal, so as to facilitate the reset of the control node's potential.

[0128] Optionally, the first transistor is an n-type transistor; during the first reset phase, the potential of the first reset control signal is greater than the potential of the first reset control signal during the first control phase; or, the first transistor is a p-type transistor; during the first reset phase, the potential of the first reset control signal is less than the potential of the first reset control signal during the first control phase.

[0129] In specific implementation, when the first transistor is an n-type transistor or an oxide transistor, during the first reset phase, the potential of the first reset control signal can be greater than the potential of the first reset control signal during the first control phase, so as to control the first transistor to be fully turned on during the first reset phase and not fully turned on during the first control phase.

[0130] In specific implementation, when the first transistor is a p-type transistor or an LTPS (low-temperature polysilicon) transistor, during the first reset phase, the potential of the first reset control signal can be lower than the potential of the first reset control signal during the first control phase, so as to control the first transistor to be fully turned on during the first reset phase and not fully turned on during the first control phase.

[0131] In at least one embodiment of this disclosure, the refresh frame includes the first control phase; the display cycle further includes a hold frame, and the hold frame further includes a fourth control phase and a hold-light phase set sequentially.

[0132] The first reset circuit is also used in the fourth control phase to write the voltage signal provided by the first initial voltage terminal into the control node under the control of the first reset control signal.

[0133] In specific implementation, when the refresh frame includes a first control stage, a fourth control stage can be set in the holding frame before the holding light-emitting stage. In the fourth control stage, the first reset circuit, under the control of the first reset control signal, writes the voltage signal provided by the first initial voltage terminal into the control node so that the potential of the control node remains consistent during the refresh light-emitting stage and the holding light-emitting stage, so that the leakage current between the control node and the first node is consistent, which helps to improve the flickering phenomenon.

[0134] As shown in Figure 2, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure further includes a light-emitting element E1 and a second reset circuit 21.

[0135] The second reset circuit 21 is electrically connected to the second reset control terminal RP, the first electrode of the light-emitting element E1, and the second initial voltage terminal I2, respectively. It is used to control the connection or disconnection between the first electrode of the light-emitting element E1 and the second initial voltage terminal I2 under the control of the second reset control signal provided by the second reset control terminal RP.

[0136] The refresh frame further includes a fifth control phase disposed between the data writing phase and the refresh illumination phase; the hold frame further includes a sixth control phase disposed before the hold illumination phase;

[0137] The second reset circuit 21 is used, under the control of the second reset control signal in the fifth control phase and the sixth control phase, to write the second initial voltage provided by the second initial voltage terminal I2 into the first pole of the light-emitting element E1.

[0138] In specific implementation, a fifth control stage can be set between the data writing stage and the refresh light emission stage within the refresh frame, and a sixth control stage can be set before the hold light emission stage within the hold frame. In the fifth control stage and the sixth control stage, under the control of the second reset control signal, the second reset circuit 21 writes the second initial voltage provided by the second initial voltage terminal I2 into the first electrode of the light emission element E1 to reset the potential of the first electrode of the light emission element E1, which helps to clear the residual charge of the first electrode of the light emission element E1.

[0139] In at least one embodiment of this disclosure, the refresh frame further includes the second control phase; the hold frame further includes the third control phase;

[0140] The driving circuit further includes a second reset circuit; the refresh frame further includes a fifth control phase disposed between the data writing phase and the refresh light emission phase; the holding frame further includes a sixth control phase disposed before the holding light emission phase;

[0141] The second reset circuit is electrically connected to the second reset control terminal, the first electrode of the light-emitting element, and the second initial voltage terminal, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal during the fifth control stage and the sixth control stage.

[0142] In specific implementation, when the refresh frame further includes the second control stage and the holding frame further includes the third control stage, a fifth control stage can be set between the data writing stage and the refresh light emission stage in the refresh frame, and a sixth control stage can be set before the holding light emission stage in the holding frame. In the fifth control stage and the sixth control stage, under the control of the second reset control signal, the second reset circuit writes the second initial voltage provided by the second initial voltage terminal into the first electrode of the light emission element to reset the potential of the first electrode of the light emission element, which helps to clear the residual charge of the first electrode of the light emission element.

[0143] Optionally, the start time of the second control phase is set before the start time of the fifth control phase, and the start time of the third control phase is set before the start time of the sixth control phase; or,

[0144] The start time of the fifth control stage is set before the start time of the second control stage, and the start time of the sixth control stage is set before the start time of the third control stage.

[0145] In at least one embodiment of this disclosure, as shown in FIG3, based on at least one embodiment of the pixel circuit shown in FIG2, the pixel circuit further includes a data writing circuit 31; the display cycle further includes a conduction phase; the conduction phase includes the data writing phase, and the end time of the conduction phase is later than the end time of the data writing phase.

[0146] The data writing circuit 31 is electrically connected to the second scanning terminal PG, the data line DL and the second terminal of the driving circuit 10, respectively, and is used to write the data voltage Vdata on the data line DL into the second terminal of the driving circuit 10 under the control of the second scanning signal provided by the second scanning terminal PG during the data writing stage.

[0147] The compensation control circuit 11 is used to control the first terminal of the drive circuit 10 to connect with the control node NC under the control of the first scan signal during the conduction phase.

[0148] In specific implementation, within the refresh frame, before the refresh light emission stage, the transistors included in the on / off control circuit can be set to turn off before the transistors included in the compensation control circuit. This eliminates the influence of the characteristic differences of the transistors included in the compensation control circuit on the light emission current, removes the influence of the gate potential change of the driving transistor caused by the characteristic shift of the oxide transistor during the reliability process, and thus improves the horizontal stripe defects during the reliability process.

[0149] The pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, a third reset circuit, a first energy storage circuit, and a second energy storage circuit;

[0150] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal, and the second terminal of the driving circuit, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second terminal of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control terminal;

[0151] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the first terminal of the driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the first terminal of the driving circuit and the first electrode of the light-emitting element under the control of the light-emitting control signal;

[0152] The third reset circuit is electrically connected to the second reset control terminal, the third initial voltage terminal, and the second terminal of the drive circuit, respectively, and is used to control the connection or disconnection between the third initial voltage terminal and the second terminal of the drive circuit under the control of the second reset control signal provided by the second reset control terminal;

[0153] The first energy storage circuit is electrically connected to the control terminal of the drive circuit to maintain the potential of the control terminal of the drive circuit.

[0154] The second energy storage circuit is electrically connected to the control node and is used to maintain the potential of the control node.

[0155] In a specific implementation, the pixel circuit may further include a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, a third reset circuit, a first energy storage circuit, and a second energy storage circuit.

[0156] Under the control of the light emission control signal, the first light emission control circuit controls the connection or disconnection between the power supply voltage terminal and the second terminal of the driving circuit; under the control of the light emission control signal, the second light emission control circuit controls the connection or disconnection between the first terminal of the driving circuit and the first electrode of the light emission element; under the control of the second reset control signal, the third reset circuit controls the writing of the third initial voltage to the second terminal of the driving circuit to improve the hysteresis phenomenon.

[0157] As shown in Figure 4, based on at least one embodiment of the pixel circuit shown in Figure 3, the pixel circuit of at least one embodiment of this disclosure further includes a first light-emitting control circuit 41, a second light-emitting control circuit 42, a third reset circuit 43, a first energy storage circuit 44, and a second energy storage circuit 45.

[0158] The first light-emitting control circuit 41 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal VDD, and the second terminal of the driving circuit 10, respectively. It is used to control the connection or disconnection between the power supply voltage terminal VDD and the second terminal of the driving circuit 10 under the control of the light-emitting control signal provided by the light-emitting control terminal EM during the refresh light-emitting stage and the light-emitting maintenance stage.

[0159] The second light-emitting control circuit 42 is electrically connected to the light-emitting control terminal EM, the first terminal of the driving circuit 10, and the first electrode of the light-emitting element E1, respectively. It is used to control the connection or disconnection between the first terminal of the driving circuit 10 and the first electrode of the light-emitting element E1 under the control of the light-emitting control signal during the refresh light-emitting stage and the light-emitting maintenance stage.

[0160] The third reset circuit 43 is electrically connected to the second reset control terminal RP, the third initial voltage terminal I3 and the first terminal of the drive circuit 10, respectively, and is used to control the connection or disconnection between the third initial voltage terminal I3 and the first terminal of the drive circuit 10 under the control of the second reset control signal provided by the second reset control terminal RP.

[0161] The first energy storage circuit 44 is electrically connected to the control terminal of the drive circuit 10 to maintain the potential of the control terminal of the drive circuit 10.

[0162] The second energy storage circuit 45 is electrically connected to the control node NC and is used to maintain the potential of the control node NC.

[0163] As shown in Figure 5, based on at least one embodiment of the pixel circuit shown in Figure 4,

[0164] The first reset circuit includes a first transistor T1;

[0165] The gate of the first transistor T1 is electrically connected to the first reset control terminal RN, the source of the first transistor T1 is electrically connected to the first initial voltage terminal I1, and the drain of the first transistor T1 is electrically connected to the control node NC.

[0166] The compensation control circuit includes a second transistor T2;

[0167] The gate of T2 is electrically connected to the first scan terminal GN, the source of T2 is electrically connected to the control node NC, and the drain of T2 is electrically connected to the third node N3.

[0168] The driving circuit includes a driving transistor T3;

[0169] The gate of T3 is electrically connected to the first node N1, the source of T3 is electrically connected to the second node N2, and the drain of T3 is electrically connected to the third node N3.

[0170] The data writing circuit includes a fourth transistor T4;

[0171] The gate of T4 is electrically connected to the second scan terminal GP, the source of T4 is electrically connected to the data line DL, and the drain of T4 is electrically connected to the second node N2.

[0172] The first light-emitting control circuit includes a fifth transistor T5, and the second light-emitting control circuit includes a sixth transistor T6; the light-emitting element is an organic light-emitting diode O1.

[0173] The gate of T5 is electrically connected to the light-emitting control terminal EM, the source of T5 is electrically connected to the power supply voltage terminal VDD, and the drain of T5 is electrically connected to the second node N2.

[0174] The gate of T6 is electrically connected to the light-emitting control terminal EM, the source of T6 is electrically connected to the third node N3, the drain of T6 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0175] The second reset circuit includes a seventh transistor T7;

[0176] The gate of T7 is electrically connected to the second reset control terminal RP, the source of T7 is electrically connected to the second initial voltage terminal I2, and the drain of T7 is electrically connected to the anode of O1.

[0177] The third reset circuit includes an eighth transistor T8;

[0178] The gate of T8 is electrically connected to the second reset control terminal RP, the source of T8 is electrically connected to the third initial voltage terminal I3, and the drain of T8 is electrically connected to the second node N2.

[0179] The on / off control circuit includes a ninth transistor T9;

[0180] The gate of T9 is electrically connected to the second scan terminal GP, the source of T9 is electrically connected to the first node N1, and the drain of T9 is electrically connected to the control node NC.

[0181] The first energy storage circuit includes a storage capacitor Cst, and the second energy storage circuit includes a first capacitor C1.

[0182] The first terminal of Cst is electrically connected to N1, and the second terminal of Cst is electrically connected to VDD.

[0183] The first terminal of C1 is electrically connected to NC, and the second terminal of Cst is electrically connected to VDD.

[0184] In at least one embodiment of the pixel circuit shown in Figure 5, T1 and T2 are oxide transistors, T3-T9 are LTPS transistors, T1 and T2 are n-type transistors, and T3-T9 are p-type transistors.

[0185] As shown in Figure 6, when at least one embodiment of the pixel circuit shown in Figure 5 is in operation, the display cycle of the pixel circuit may include a refresh frame FS and a hold frame FB; the refresh frame includes a first first stage S11, a first reset stage S12, a first third stage S13, a data writing stage S14, a first control stage S15, a fifth control stage S16, and a refresh light emission stage S17, which are set sequentially; the hold frame may include a sixth control stage S26 and a hold light emission stage S27, which are set sequentially.

[0186] In S11, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, and T1, T2, and T4-T9 are turned off.

[0187] In S12, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T9 and T7 are both turned on, T1 is turned on, I1 provides a first initial voltage Vinit1 to NC, Vinit1 is written to N1 through T9, and the second initial voltage Vinit2 provided by I1 is written to the anode of O1 through T7, clearing the residual charge on the anode of O1;

[0188] In S13, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 and T2 are both turned on, I1 provides Vinit1 to NC, N3 is connected to NC to reset the potential of N3 through Vinit1;

[0189] In S14, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T4 is turned on, T2 is turned on, T9 is turned on, N1 and N3 are connected, DL provides data voltage Vdata to N2, and Vdata is stored in Cst;

[0190] At the start of S14, T3 is turned on and charges Cst through Vdata to change the potential of N1 until the potential of N1 becomes Vdata+Vth. Then T3 is turned off to perform data voltage writing and threshold voltage compensation, where Vth is the threshold voltage of T3.

[0191] In S15, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 is turned on, and Vinit1 is written to NC to lower the potential of NC before the refresh light emission stage S17, so that the potential of N1 is not much different from the potential of NC during the refresh light emission stage S17, thereby reducing the leakage current from NC to N1 and improving the flickering phenomenon.

[0192] In S16, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0193] In S17, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light; in S17, the light-emitting current Io1 of O1 is equal to K×(Vdd-Vdata)2; K is a current coefficient related to the process and design, and Vdd is the voltage value of the power supply voltage signal provided by the power supply voltage terminal VDD.

[0194] In S26, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0195] In S27, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0196] As shown in Figure 6, during the refresh frame, in S12, GP provides a low voltage signal, T4 and T9 are turned on, and the initial voltage Vinit1 provided by I1 resets the potential of N1 through T1 and T9. When GP provides a high voltage signal, T4 and T9 are turned off. T9, as an LTPS transistor, is affected by the potential of N1 and the gate bias before the first turn-on. The gate bias is fixed, but the potential of N1 is related to the data voltage of the previous refresh frame. Therefore, the characteristics of T9 are still affected by the previous refresh frame. During the refresh frame, after T9 is turned on for the first time, the potential of N1 is reset to Vinit1. Regardless of whether the gate voltage of T9 is high or low, the voltage of N1 is still affected by the previous refresh frame. The voltage level is relatively fixed, whether it is high or low. After the first on and off, the influence of the previous refresh frame data voltage on the characteristics of T9 can be eliminated. When T9 is turned on for the second time, the potential of N1 is reset to Vinit1 again. The two consecutive reset actions can better eliminate the influence of the previous refresh frame data voltage on the characteristics of T9, thereby improving image retention and low grayscale image quality. In addition, in S12, the potential of N1 is reset to Vinit1. Since T2 is off, the potential of N2 remains Vinit3. The gate-source voltage of T3 is Vinit1-Vint3. The characteristics of T3 are also reset, thereby improving image retention.

[0197] In at least one embodiment shown in Figure 6, S15 and S16 can be interchanged, that is, S16 can be set between S14 and S15; or, S15 and S16 can be the same time period. In at least one embodiment shown in Figure 6, the conduction phase can include a first third phase S13 and a data writing phase S14;

[0198] Before the refresh light emission stage S17, T9 is cut off before T2, which eliminates the influence of the characteristic difference of the second transistor on the light emission current in the circuit, removes the influence of the gate potential change of the driving transistor caused by the characteristic offset of the oxide transistor during the reliability process, and thus improves the horizontal stripe defect in the reliability process.

[0199] As shown in the brightness waveform curve in Figure 7, when the working timing shown in Figure 6 is used, the leakage direction of N1 is reversed, and N1 leaks current to NC, so that the brightness gradually increases.

[0200] In Figure 7, the horizontal axis represents time in seconds, and the vertical axis represents brightness in nits.

[0201] As shown in Figure 8A, at least one embodiment of the pixel circuit shown in Figure 5 operates as follows:

[0202] The display cycle of the pixel circuit may include a refresh frame FS; the refresh frame FS includes a first first stage S11, a first reset stage S12, a first third stage S13, a data writing stage S14, a first control stage S15, a fifth control stage S16, and a refresh light emission stage S17, which are set sequentially.

[0203] In S11, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, and T1, T2, and T4-T9 are turned off.

[0204] In S12, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T9 and T1 are turned on, I1 provides the first initial voltage Vinit11 to NC, and Vinit1 is written to N1 through T9; the voltage value of the first initial voltage Vinit11 can be -3V;

[0205] In S13, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 and T2 are both turned on, I1 provides Vinit1 to NC, and N3 is connected to NC;

[0206] In S14, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T4 is on, T2 is on, T9 is on, N1 and N3 are connected, and DL provides the data voltage Vdata to N2.

[0207] At the start of S14, T3 is turned on and charges Cst through Vdata to change the potential of N1 until the potential of N1 becomes Vdata+Vth. Then T3 is turned off to perform data voltage writing and threshold voltage compensation, where Vth is the threshold voltage of T3.

[0208] In S15, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 is turned on, and I1 writes the second first initial voltage Vinit21 into NC to pull down the potential of NC before the refresh light emission stage S17, so that the potential of N1 is not much different from the potential of NC during the refresh light emission stage S17, reducing the leakage current from NC to N1 and helping to improve the flickering phenomenon; the voltage value of the second first initial voltage Vinit21 is -0.5V;

[0209] In S16, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0210] In S17, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0211] When the working timing shown in Figure 8A is adopted, I1 dynamically provides the first initial voltage. In the first reset phase S12, I1 provides the first initial voltage Vinit11 to NC, and the voltage value of the first initial voltage Vinit11 can be -3V. In the first control phase S15, I1 writes the second initial voltage Vinit21 into NC, and the voltage value of the second initial voltage Vinit21 is -0.5V, so that during the refresh light emission phase, the potential of the control node NC is not much different from the potential of the first node N1, reducing the leakage current of the control node NC to the first node N1 and helping to improve the flickering phenomenon. Under this premise, in the first reset phase S12, when T9 is turned on and the control node N1 is connected to the control node NC, the first initial voltage Vinit11 can be written into the first node N1, so that the driving transistor T3 can be fully turned on at the beginning of the data writing phase.

[0212] In at least one embodiment of the pixel circuit shown in Figure 5, during operation, in the first reset phase S12, the voltage value of the first initial voltage Vinit11 can be -3V; in the first control phase S15, the voltage value of the second initial voltage Vinit21 can be -0.5V.

[0213] In specific implementation, when the driving transistor is a p-type transistor, the voltage value of the first initial voltage Vinit11 can be less than the voltage value of the second initial voltage Vinit21.

[0214] Among them, the voltage value of Vinit11 can be greater than or equal to -3.5V and less than or equal to -2V, and the voltage value of Vinit21 can be greater than or equal to -1V and less than or equal to 0V; for example, the voltage value of Vinit11 can be equal to -3.5V, -3V, -2.5V or -2V, and the voltage value of Vinit21 can be equal to -1V, -0.8V, -0.5V, -0.2V or 0V.

[0215] In at least one embodiment shown in Figure 8A, S15 and S16 can be interchanged, that is, S16 can be set between S14 and S15; or, S15 and S16 can be the same time period.

[0216] The difference between at least one embodiment shown in Figure 8B and at least one embodiment shown in Figure 8A is that S15 and S16 are interchanged.

[0217] As shown in Figure 8B, the refresh frame FS includes the first first stage S11, the first reset stage S12, the first third stage S13, the data writing stage S14, the fifth control stage S16, the first control stage S15, and the refresh and light emission stage S17, which are set sequentially.

[0218] The difference between the at least one embodiment shown in Figure 8C and the at least one embodiment shown in Figure 8A is that S15 and the fifth control stage are in the same time period;

[0219] In at least one embodiment shown in FIG8C, the refresh frame FS includes a first first stage S11, a first reset stage S12, a first third stage S13, a data writing stage S14, a first control stage S15, and a refresh and light emission stage S17, which are set sequentially.

[0220] In the first control phase S15, RN provides a high voltage signal, T1 is turned on, and I1 writes the second initial voltage Vinit21 into NC; RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis phenomenon of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0221] As shown in Figure 9A, at least one embodiment of the pixel circuit shown in Figure 5 operates as follows:

[0222] The display cycle of the pixel circuit may include a refresh frame FS and a hold frame FB; the refresh frame includes a first first stage S11, a first reset stage S12, a first third stage S13, a data writing stage S14, a first control stage S15, a fifth control stage S16 and a refresh light emission stage S17 set sequentially; the hold frame may include a sixth control stage S26 and a hold light emission stage S27 set sequentially.

[0223] In S11, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, and T1, T2, and T4-T9 are turned off.

[0224] In S12, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T9 and T7 are both turned on, T1 is turned on, I1 provides a first initial voltage Vinit1 to NC, Vinit1 is written to N1 through T9, and the second initial voltage Vinit2 provided by I1 is written to the anode of O1 through T7, clearing the residual charge on the anode of O1;

[0225] In S13, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 and T2 are both turned on, I1 provides Vinit1 to NC, and N3 is connected to NC;

[0226] In S14, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T4 is on, T2 is on, T9 is on, N1 and N3 are connected, and DL provides the data voltage Vdata to N2.

[0227] At the start of S14, T3 is turned on and charges Cst through Vdata to change the potential of N1 until the potential of N1 becomes Vdata+Vth. Then T3 is turned off to perform data voltage writing and threshold voltage compensation, where Vth is the threshold voltage of T3.

[0228] In S15, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 is turned on, and Vinit1 is written to NC to lower the potential of NC before the refresh light emission stage S17, so that the potential of N1 is not much different from the potential of NC during the refresh light emission stage S17, thereby reducing the leakage current from NC to N1 and improving the flickering phenomenon.

[0229] In S15, the voltage value of the first reset control signal provided by RN can be adjusted so that T1 is not fully turned on, thereby reducing the force of pulling down the potential of NC and achieving a balance between the potential of NC and the potential of N1 as much as possible.

[0230] In S16, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0231] In S17, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0232] In at least one embodiment of this disclosure, the data writing phase S14 lasts for 1 hour (one-line scan time);

[0233] The data writing phase S14 lasts for a short period of time. After the data writing phase S14 ends, GN still provides a high voltage signal. When T2 is turned on, threshold voltage compensation can continue through parasitic capacitance until the potential of N1 becomes Vdata+Vth.

[0234] In at least one embodiment shown in Figure 9A, S15 and S16 can be interchanged, that is, S16 can be set between S14 and S15; or, S15 and S16 can be the same time period.

[0235] The difference between at least one embodiment shown in Figure 9B and at least one embodiment shown in Figure 9A is that S15 and S16 are interchanged.

[0236] As shown in Figure 9B, the refresh frame FS includes the first first stage S11, the first reset stage S12, the first third stage S13, the data writing stage S14, the fifth control stage S16, the first control stage S15, and the refresh and light emission stage S17, which are set sequentially.

[0237] The difference between the at least one embodiment shown in Figure 9C and the at least one embodiment shown in Figure 9A is that S15 and the fifth control stage are in the same time period;

[0238] In at least one embodiment shown in FIG9C, the refresh frame FS includes a first first stage S11, a first reset stage S12, a first third stage S13, a data writing stage S14, a first control stage S15, and a refresh and light emission stage S17, which are set sequentially.

[0239] In the first control phase S15, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RP provides a high voltage signal, T1 is turned on, and Vinit1 is written to NC to lower the potential of NC before the refresh light emission phase S17, so that the potential of N1 is not much different from the potential of NC during the refresh light emission phase S17, thereby reducing the leakage current from NC to N1 and improving the flickering phenomenon.

[0240] In S15, the voltage value of the first reset control signal provided by RN can be adjusted so that T1 is not fully turned on, thereby reducing the force of pulling down the potential of NC and achieving a balance between the potential of NC and the potential of N1 as much as possible.

[0241] In S15, RP provides a low voltage signal, T8 turns on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 turns on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0242] As shown in Figure 9A, at least one embodiment of the pixel circuit shown in Figure 5 operates as follows:

[0243] In S12 and S13, RN can provide a 7V voltage signal to control T1 to be fully turned on; in S15, RN can provide a 1V voltage signal to control T1 to be partially turned on.

[0244] In the first reset phase S12, the potential of the first reset control signal provided by RN is greater than the potential of the first reset control signal in the first control phase S15.

[0245] In specific implementation, in the first stage S11 and the first reset stage S12, the potential of the first reset control signal provided by RN can be greater than or equal to 6V and less than or equal to 8V. In the first control stage S15, the potential of the first reset control signal provided by RN can be greater than or equal to 0.5V and less than or equal to 2V.

[0246] For example, in the first first stage S11 and the first reset stage S12, the potential of the first reset control signal provided by RN can be 6V, 6.5V, 7V, 7.5V or 8V, and in the first control stage S15, the potential of the first reset control signal provided by RN can be 0.5V, 1V, 1.5V or 2V.

[0247] As shown in Figure 10A, when at least one embodiment of the pixel circuit shown in Figure 5 is in operation, the display cycle of the pixel circuit may include a refresh frame FS and a hold frame FB; the refresh frame includes a first first stage S11, a first reset stage S12, a first third stage S13, a data writing stage S14, a first control stage S15, a fifth control stage S16, and a refresh light emission stage S17, which are set sequentially; the hold frame may include a fourth control stage S25, a sixth control stage S26, and a hold light emission stage S27, which are set sequentially.

[0248] In S11, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, and T1, T2, and T4-T9 are turned off.

[0249] In S12, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T9 and T7 are both turned on, T1 is turned on, I1 provides a first initial voltage Vinit1 to NC, Vinit1 is written to N1 through T9, and the second initial voltage Vinit2 provided by I1 is written to the anode of O1 through T7, clearing the residual charge on the anode of O1;

[0250] In S13, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 and T2 are both turned on, I1 provides Vinit1 to NC, and N3 is connected to NC;

[0251] In S14, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T4 is on, T2 is on, T9 is on, N1 and N3 are connected, and DL provides the data voltage Vdata to N2.

[0252] At the start of S14, T3 is turned on and charges Cst through Vdata to change the potential of N1 until the potential of N1 becomes Vdata+Vth. Then T3 is turned off to perform data voltage writing and threshold voltage compensation, where Vth is the threshold voltage of T3.

[0253] In S15, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 is turned on, and Vinit1 is written to NC to lower the potential of NC before the refresh light emission stage S17, so that the potential of N1 is not much different from the potential of NC during the refresh light emission stage S17, thereby reducing the leakage current from NC to N1 and improving the flickering phenomenon.

[0254] In S16, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0255] In S17, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light;

[0256] In S25, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 is turned on, and Vinit1 is written to NC to lower the potential of NC before the refresh light emission stage S17, so that the potential of N1 is not much different from the potential of NC during the refresh light emission stage S17, thereby reducing the leakage current from NC to N1 and improving the flickering phenomenon.

[0257] In S26, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0258] In S27, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0259] As shown in Figure 10A, in at least one embodiment shown in Figure 5, during operation, a fourth control stage S25 is added to the guarantee frame. In the fourth control stage S25, T1 is turned on by RN so that the potential of NC is consistent in the refresh light emission stage included in the refresh frame and the hold light emission stage included in the hold frame, which is equivalent to turning 1Hz into 120 120Hz, each 1s / 120, by pulling down the potential of N1 by NC.

[0260] In at least one embodiment shown in Figure 10A, S15 and S16 can be interchanged, that is, S16 can be set between S14 and S15; or, S15 and S16 can be the same time period.

[0261] S25 and S26 can be interchanged, that is, S26 can be set between S24 and S25; or, S25 and S26 can be the same time period.

[0262] As shown in Figure 10B, when at least one embodiment of the pixel circuit shown in Figure 5 is in operation, the refresh frame may include a first first stage S11, a first reset stage S12, a first third stage S13, a data writing stage S14, a fifth control stage S16, a first control stage S15, and a refresh light emission stage S17, which are set sequentially; the hold frame may include a sixth control stage S26, a fourth control stage S25, and a hold light emission stage S27, which are set sequentially.

[0263] As shown in Figure 10C, when at least one embodiment of the pixel circuit shown in Figure 5 is in operation, the refresh frame may include a first first stage S11, a first reset stage S12, a first third stage S13, a data writing stage S14, a first control stage S15, and a refresh light emission stage S17 set sequentially; the hold frame may include a fourth control stage S25 and a hold light emission stage S27 set sequentially.

[0264] In S15, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, T1 is turned on, and Vinit1 is written to NC to lower the potential of NC before the refresh light emission stage S17, so that the potential of N1 is not much different from the potential of NC during the refresh light emission stage S17, thereby reducing the leakage current from NC to N1 and improving the flickering phenomenon.

[0265] In S15, RP provides a low voltage signal, T8 turns on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; when T7 turns on, I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0266] In S25, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, T1 is turned on, and Vinit1 is written to NC to lower the potential of NC before the refresh light emission stage S17, so that the potential of N1 is not much different from the potential of NC during the refresh light emission stage S17, thereby reducing the leakage current from NC to N1 and improving the flickering phenomenon.

[0267] In S25, RP provides a low voltage signal, T8 turns on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 turns on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0268] As shown in Figure 11, at least one embodiment shown in Figure 5 is in operation.

[0269] The display cycle of the pixel circuit may include a refresh frame FS and a hold frame FB; the refresh frame includes a first first stage S11, a first reset stage S12, a first third stage S13, a data writing stage S14, a first control stage S15, a fifth control stage S16 and a refresh light emission stage S17 set sequentially; the hold frame may include a sixth control stage S26 and a hold light emission stage S27 set sequentially.

[0270] In S11, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, and T1, T2, and T4-T9 are turned off.

[0271] In S12, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T9 and T7 are both turned on, T1 is turned on, I1 provides the first initial voltage Vinit11 to NC, Vinit1 is written to N1 through T9, and the second initial voltage Vinit2 provided by I1 is written to the anode of O1 through T7 to clear the residual charge on the anode of O1; the voltage value of the first initial voltage Vinit11 can be -3V;

[0272] In S12, T1 can be fully turned on by adjusting the voltage value of the first reset control signal provided by RN;

[0273] In S13, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 and T2 are both turned on, I1 provides Vinit1 to NC, and N3 is connected to NC;

[0274] In S14, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T4 is on, T2 is on, T9 is on, N1 and N3 are connected, and DL provides the data voltage Vdata to N2.

[0275] At the start of S14, T3 is turned on and charges Cst through Vdata to change the potential of N1 until the potential of N1 becomes Vdata+Vth. Then T3 is turned off to perform data voltage writing and threshold voltage compensation, where Vth is the threshold voltage of T3.

[0276] In S15, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 is turned on, and I1 writes the second first initial voltage Vinit21 into NC to pull down the potential of NC before the refresh light emission stage S17, so that the potential of N1 is not much different from the potential of NC during the refresh light emission stage S17, reducing the leakage current from NC to N1 and helping to improve the flickering phenomenon; the voltage value of the second first initial voltage Vinit21 is -0.5V;

[0277] In S15, the voltage value of the first reset control signal provided by RN can be adjusted so that T1 is not fully turned on, thereby reducing the force of pulling down the potential of NC and achieving a balance between the potential of NC and the potential of N1 as much as possible.

[0278] In S16, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0279] In S17, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light;

[0280] The holding frame may include a sixth control stage S26 and a light-holding stage S27 set sequentially.

[0281] In S26, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0282] In S27, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0283] When the working timing shown in Figure 11 is adopted, I1 dynamically provides a first initial voltage. In the first reset phase S12, I1 provides a first initial voltage Vinit11 to NC, and the voltage value of the first initial voltage Vinit11 can be -3V. In the first control phase S15, I1 writes a second initial voltage Vinit21 to NC, and the voltage value of the second initial voltage Vinit21 is -0.5V, so that during the refresh light emission phase, the potential of the control node NC is not much different from the potential of the first node N1, reducing the leakage current of the control node NC to the first node N1 and helping to improve the flickering phenomenon. Under this premise, in the first reset phase S12, when T9 is turned on and the control node N1 is connected to the control node NC, the first initial voltage Vinit11 can be written to the first node N1, so that the driving transistor T3 can be fully turned on at the beginning of the data writing phase. In the holding frame, I1 provides a second initial voltage Vinit21.

[0284] As shown in Figure 12, at least one embodiment shown in Figure 5 is in operation.

[0285] The display cycle of the pixel circuit may include a refresh frame FS and a hold frame FB; the refresh frame includes a first first stage S11, a first reset stage S12, a first third stage S13, a data writing stage S14, a second control stage S10, a fifth control stage S16, and a refresh light emission stage S17, which are set sequentially; the hold frame may include a third control stage S20, a sixth control stage S26, and a hold light emission stage S27, which are set sequentially.

[0286] In S11, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, and T1, T2, and T4-T9 are turned off.

[0287] In S12, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T9 and T7 are both turned on, T1 is turned on, I1 provides a first initial voltage Vinit1 to NC, Vinit1 is written to N1 through T9, and the second initial voltage Vinit2 provided by I1 is written to the anode of O1 through T7, clearing the residual charge on the anode of O1;

[0288] In S13, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 and T2 are both turned on, I1 provides Vinit1 to NC, and N3 is connected to NC;

[0289] In S14, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T4 is on, T2 is on, T9 is on, N1 and N3 are connected, and DL provides the data voltage Vdata to N2.

[0290] At the start of S14, T3 is turned on and charges Cst through Vdata to change the potential of N1 until the potential of N1 becomes Vdata+Vth. Then T3 is turned off to perform data voltage writing and threshold voltage compensation, where Vth is the threshold voltage of T3.

[0291] In S10, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, and RP provides a high voltage signal. T9 is turned on to control the connection between NC and N1, so as to keep the potential of NC consistent with the potential of N1, which helps to improve the flickering phenomenon.

[0292] In S16, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0293] In S17, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light;

[0294] In S20, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, and RP provides a high voltage signal. T9 is turned on to control the connection between NC and N1, so as to keep the potential of NC consistent with the potential of N1, which helps to improve the flickering phenomenon.

[0295] In S26, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0296] In S27, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0297] As shown in Figure 12, in at least one embodiment shown in Figure 5, a second control stage and a third control stage can be added before the refresh light emission stage and the hold light emission stage during operation. In the second control stage S10 and the third control stage S20, GP provides a low voltage signal to increase the number of downward pulses. When 120Hz is used, it is equivalent to making the potential of NC consistent with the potential of N1 every 8.3ms, which is equivalent to turning the 1Hz leakage time into 120 times the 120Hz leakage time. Every 8.3ms, the potential of N1 is pulled down by NC, which helps to improve the flickering phenomenon.

[0298] In practice, flickering can be improved by pulling down the potential of N1 by NC 120 times every 8.3ms within 1 second.

[0299] In at least one embodiment shown in Figure 12, S10 can be interchanged with S16, that is, S16 can be set between S14 and S10; or, S10 and S16 can be the same time period.

[0300] S20 and S26 can be interchanged, that is, S26 can be set between S24 and S20; or, S20 and S26 can be the same time period.

[0301] As shown in Figure 13, at least one embodiment shown in Figure 5 is in operation.

[0302] The display cycle of the pixel circuit may include a refresh frame FS and a hold frame FB; the refresh frame includes a first first stage S11, a first reset stage S12, a first third stage S13, a data writing stage S14, a fifth control stage S16, a second control stage S10, and a refresh light emission stage S17 set sequentially; the hold frame may include a sixth control stage S26, a third control stage S20, and a hold light emission stage S27 set sequentially.

[0303] In S11, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, and T1, T2, and T4-T9 are turned off.

[0304] In S12, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T9 and T7 are both turned on, T1 is turned on, I1 provides a first initial voltage Vinit1 to NC, Vinit1 is written to N1 through T9, and the second initial voltage Vinit2 provided by I1 is written to the anode of O1 through T7, clearing the residual charge on the anode of O1;

[0305] In S13, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 and T2 are both turned on, I1 provides Vinit1 to NC, and N3 is connected to NC;

[0306] In S14, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T4 is on, T2 is on, T9 is on, N1 and N3 are connected, and DL provides the data voltage Vdata to N2.

[0307] At the start of S14, T3 is turned on and charges Cst through Vdata to change the potential of N1 until the potential of N1 becomes Vdata+Vth. Then T3 is turned off to perform data voltage writing and threshold voltage compensation, where Vth is the threshold voltage of T3.

[0308] In S16, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0309] In S10, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, and RP provides a high voltage signal. T9 is turned on to control the connection between NC and N1, so as to keep the potential of NC consistent with the potential of N1, which helps to improve the flickering phenomenon.

[0310] In S17, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light;

[0311] In S26, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0312] In S20, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, and RP provides a high voltage signal. T9 is turned on to control the connection between NC and N1, so as to keep the potential of NC consistent with the potential of N1, which helps to improve the flickering phenomenon.

[0313] In S27, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0314] As shown in Figure 13, in at least one embodiment shown in Figure 5, a second control stage and a third control stage can be added before the refresh light-emitting stage and the hold light-emitting stage during operation. In the second control stage S10 and the third control stage S20, GP provides a low voltage signal to increase the number of downward pulses. When 120Hz is used, it is equivalent to making the potential of NC consistent with the potential of N1 every 8.3ms, which is equivalent to turning the 1Hz leakage time into 120 times the 120Hz leakage time. Every 8.3ms, the potential of N1 is pulled down by NC, which helps to improve the flickering phenomenon.

[0315] As shown in Figure 14, at least one embodiment shown in Figure 5 is in operation.

[0316] The display cycle of the pixel circuit may include a refresh frame FS and a hold frame FB; the refresh frame includes a first first stage S11, a first reset stage S12, a first third stage S13, a data writing stage S14, a first control stage S15, a second control stage S10, a fifth control stage S16, and a refresh light emission stage S17, which are set sequentially; the hold frame may include a fourth control stage S25, a third control stage S20, a sixth control stage S26, and a hold light emission stage S27, which are set sequentially.

[0317] In S11, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, and T1, T2, and T4-T9 are turned off.

[0318] In S12, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T9 and T7 are both turned on, T1 is turned on, I1 provides a first initial voltage Vinit1 to NC, Vinit1 is written to N1 through T9, and the second initial voltage Vinit2 provided by I1 is written to the anode of O1 through T7, clearing the residual charge on the anode of O1;

[0319] In S13, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 and T2 are both turned on, I1 provides Vinit1 to NC, and N3 is connected to NC;

[0320] In S14, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T4 is on, T2 is on, T9 is on, N1 and N3 are connected, and DL provides the data voltage Vdata to N2.

[0321] At the start of S14, T3 is turned on and charges Cst through Vdata to change the potential of N1 until the potential of N1 becomes Vdata+Vth. Then T3 is turned off to perform data voltage writing and threshold voltage compensation, where Vth is the threshold voltage of T3.

[0322] In S15, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 is turned on, and Vinit1 is written to NC to lower the potential of NC before the refresh light emission stage S17, so that the potential of N1 is not much different from the potential of NC during the refresh light emission stage S17, thereby reducing the leakage current from NC to N1 and improving the flickering phenomenon.

[0323] In S10, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, and RP provides a high voltage signal. T9 is turned on to control the connection between NC and N1, so as to keep the potential of NC consistent with the potential of N1, which helps to improve the flickering phenomenon.

[0324] In S16, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0325] In S17, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light;

[0326] In S25, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 is turned on, and Vinit1 is written to NC to lower the potential of NC before the refresh light emission stage S17, so that the potential of N1 is not much different from the potential of NC during the refresh light emission stage S17, thereby reducing the leakage current from NC to N1 and improving the flickering phenomenon.

[0327] In S20, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, and RP provides a high voltage signal. T9 is turned on to control the connection between NC and N1, so as to keep the potential of NC consistent with the potential of N1, which helps to improve the flickering phenomenon.

[0328] In S26, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0329] In S27, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0330] As shown in Figure 15, at least one embodiment shown in Figure 5 is in operation.

[0331] The display cycle of the pixel circuit may include a refresh frame FS and a hold frame FB; the refresh frame includes a first first stage S11, a first reset stage S12, a first third stage S13, a data writing stage S14, a first control stage S15, a second control stage S10, a fifth control stage S16, and a refresh light emission stage S17, which are set sequentially; the hold frame may include a fourth control stage S25, a third control stage S20, a sixth control stage S26, and a hold light emission stage S27, which are set sequentially.

[0332] In S11, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, and T1, T2, and T4-T9 are turned off.

[0333] In S12, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T9 and T7 are both turned on, T1 is turned on, I1 provides the first initial voltage Vinit11 to NC, Vinit1 is written to N1 through T9, and the second initial voltage Vinit2 provided by I1 is written to the anode of O1 through T7 to clear the residual charge on the anode of O1; the voltage value of the first initial voltage Vinit11 can be -3V;

[0334] In S12, the potential of the first reset control signal provided by RN can be adjusted to control T1 to be fully turned on;

[0335] In S13, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 and T2 are both turned on, I1 provides Vinit1 to NC, and N3 is connected to NC;

[0336] In S14, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T4 is on, T2 is on, T9 is on, N1 and N3 are connected, and DL provides the data voltage Vdata to N2.

[0337] At the start of S14, T3 is turned on and charges Cst through Vdata to change the potential of N1 until the potential of N1 becomes Vdata+Vth. Then T3 is turned off to perform data voltage writing and threshold voltage compensation, where Vth is the threshold voltage of T3.

[0338] In S15, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T1 is turned on, and I1 writes the second first initial voltage Vinit21 into NC to pull down the potential of NC before the refresh light emission stage S17, so that the potential of N1 is not much different from the potential of NC during the refresh light emission stage S17, reducing the leakage current from NC to N1 and helping to improve the flickering phenomenon; the voltage value of the second first initial voltage Vinit21 is -0.5V;

[0339] In S15, by lowering the voltage value of the first reset control signal provided by RN, T1 is not fully turned on, thus weakening the pull-down of NC's potential and achieving a balance between NC's potential and N1's potential as much as possible.

[0340] In S10, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, and RP provides a high voltage signal. T9 is turned on to control the connection between NC and N1, so as to keep the potential of NC consistent with the potential of N1, which helps to improve the flickering phenomenon.

[0341] In S16, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0342] In S17, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light;

[0343] In S25, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, and I1 writes the second first initial voltage Vinit21 into NC to pull down the potential of NC before the refresh light emission stage S17, so that the potential of N1 is not much different from the potential of NC during the refresh light emission stage S17, thereby reducing the leakage current from NC to N1 and improving the flickering phenomenon.

[0344] In S15, by lowering the voltage value of the first reset control signal provided by RN, T1 is not fully turned on, thus weakening the pull-down of NC's potential and achieving a balance between NC's potential and N1's potential as much as possible.

[0345] In S20, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a low voltage signal, and RP provides a high voltage signal. T9 is turned on to control the connection between NC and N1, so as to keep the potential of NC consistent with the potential of N1, which helps to improve the flickering phenomenon.

[0346] In S26, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a low voltage signal, T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3; T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0347] In S27, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0348] In practical implementation, the increasing downward pulses of the second scan signal provided by GP and the increasing upward pulses of the first reset signal provided by RN can be determined according to the time adjustment situation. For example, when the display frequency is 120Hz, if the potential of N1 is pulled by NC every 16.6ms, the flickering requirement of the display panel can be met. Then the number of increasing downward pulses of the second scan signal provided by GP and the number of increasing upward pulses of the first reset signal provided by RN can be halved to save some power consumption.

[0349] The difference between at least one embodiment of the pixel circuit shown in FIG16 of this disclosure and at least one embodiment of the pixel circuit shown in FIG5 of this disclosure is as follows: T1 is a p-type transistor.

[0350] As shown in Figure 17, at least one embodiment of the pixel circuit shown in Figure 16 operates as follows:

[0351] The display cycle of the pixel circuit may include a refresh frame FS and a hold frame FB; the refresh frame includes a first first stage S11, a first reset stage S12, a first third stage S13, a data writing stage S14, a first control stage S15, a fifth control stage S16 and a refresh light emission stage S17 set sequentially; the hold frame may include a sixth control stage S26 and a hold light emission stage S27 set sequentially.

[0352] In S11, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, and T1, T2, and T4-T9 are turned off.

[0353] In S12, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a low voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T9 and T7 are both turned on, T1 is turned on, I1 provides a first initial voltage Vinit1 to NC, Vinit1 is written to N1 through T9, and the second initial voltage Vinit2 provided by I1 is written to the anode of O1 through T7, clearing the residual charge on the anode of O1;

[0354] In S13, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, RP provides a high voltage signal, T1 and T2 are both turned on, I1 provides Vinit1 to NC, and N3 is connected to NC;

[0355] In S14, EM provides a high voltage signal, GN provides a high voltage signal, GP provides a low voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T4 is on, T2 is on, T9 is on, N1 and N3 are connected, and DL provides the data voltage Vdata to N2.

[0356] At the start of S14, T3 is turned on and charges Cst through Vdata to change the potential of N1 until the potential of N1 becomes Vdata+Vth. Then T3 is turned off to perform data voltage writing and threshold voltage compensation, where Vth is the threshold voltage of T3.

[0357] In S15, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a low voltage signal, and RP provides a high voltage signal. T1 is turned on, and Vinit1 is written to NC to lower the potential of NC before the refresh light emission stage S17, so that the potential of N1 is not much different from the potential of NC during the refresh light emission stage S17, thereby reducing the leakage current from NC to N1 and improving the flickering phenomenon.

[0358] In S15, the voltage value of the first reset control signal provided by RN can be adjusted so that T1 is not fully turned on, thereby reducing the force of pulling down the potential of NC and achieving a balance between the potential of NC and the potential of N1 as much as possible.

[0359] In S16, EM provides a high voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, and RP provides a low voltage signal. T8 is turned on, and I3 writes the third initial voltage Vinit3 into N2 to improve the hysteresis of T3. T7 is turned on, and I2 writes the second initial voltage Vinit2 into the anode of O1 to clear the residual charge on the anode of O1.

[0360] In S17, EM provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, RN provides a high voltage signal, RP provides a high voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0361] In at least one embodiment shown in Figures 16 and 17, the first transistor is a p-type transistor. In the first reset stage S12, the potential of the first reset control signal is lower than that in the first control stage S15. In the first control stage S15, the potential of the first reset control signal is adjusted so that the first transistor T1 is not fully turned on, thereby reducing the pull-down of the NC potential and achieving a balance between the NC potential and the N1 potential as much as possible. This reduces the leakage current from NC to N1 and helps to improve the flickering phenomenon.

[0362] The driving method described in this embodiment is applied to the pixel circuit described above, wherein the display cycle of the pixel circuit includes a refresh frame; the refresh frame includes a data writing phase and a refresh light emission phase;

[0363] The refresh frame includes at least one of a first control phase and a second control phase; the first control phase is disposed between the data writing phase and the refresh emission phase, and the second control phase is disposed between the data writing phase and the refresh emission phase;

[0364] The driving method includes:

[0365] During the first control phase, the first reset circuit, under the control of the first reset control signal, writes the voltage signal provided by the first initial voltage terminal into the control node;

[0366] In the second control phase, the on / off control circuit connects the control terminal of the drive circuit with the control node under the control of the second scanning signal.

[0367] In at least one embodiment of this disclosure, the refresh frame includes the second control phase; the display cycle further includes a hold frame; the hold frame includes a third control phase and a hold-light phase set sequentially.

[0368] The driving method further includes:

[0369] In the third control phase, the on / off control circuit, under the control of the second scanning signal, controls the connection between the control terminal of the drive circuit and the control node.

[0370] In at least one embodiment of this disclosure, the refresh frame includes the first control phase; the refresh frame further includes a first reset phase set before the data writing phase; the driving method further includes:

[0371] During the first reset phase, the first initial voltage terminal provides a first initial voltage, and the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the control node.

[0372] During the first control phase, the first initial voltage terminal provides a second first initial voltage, and the first reset circuit, under the control of the first reset control signal, writes the second first initial voltage into the control node.

[0373] The first initial voltage is different from the second initial voltage.

[0374] In at least one embodiment of this disclosure, the refresh frame includes the first control phase; the driving method further includes:

[0375] During the first control phase, the potential of the first reset control signal is adjusted to control the transistors included in the first reset circuit to not be fully turned on.

[0376] The refresh frame further includes a first reset phase set before the data writing phase; the driving method further includes:

[0377] During the first reset phase, the first reset circuit, under the control of the first reset control signal, controls the transistors included in the first reset circuit to be fully turned on.

[0378] The first reset circuit includes an n-type transistor. During the first reset phase, the potential of the first reset control signal is greater than the potential of the first reset control signal during the first control phase; or...

[0379] The first reset circuit includes a p-type transistor. During the first reset phase, the potential of the first reset control signal is lower than that during the first control phase.

[0380] In at least one embodiment of this disclosure, the refresh frame includes the first control phase; the display cycle further includes a hold frame, the hold frame including a fourth control phase and a hold-light phase set sequentially; the driving method further includes:

[0381] In the fourth control phase, the first reset circuit, under the control of the first reset control signal, writes the voltage signal provided by the first initial voltage terminal into the control node.

[0382] The driving circuit further includes a second reset circuit; the refresh frame further includes a fifth control phase disposed between the data writing phase and the refresh light emission phase; the holding frame further includes a sixth control phase disposed before the holding light emission phase; the driving method further includes:

[0383] In the fifth and sixth control phases, the second reset circuit, under the control of the second reset control signal, writes the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element.

[0384] The display device described in this disclosure includes the pixel circuit described above.

[0385] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, comprising a driving circuit, a compensation control circuit, an on / off control circuit, and a first reset circuit; The compensation control circuit is electrically connected to the first scanning end, the first end of the driving circuit, and the control node, respectively, and is used to control the connection or disconnection between the first end of the driving circuit and the control node under the control of the first scanning signal provided by the first scanning end. The on / off control circuit is electrically connected to the second scanning terminal, the control terminal of the driving circuit and the control node respectively, and is used to control the connection or disconnection between the control terminal of the driving circuit and the control node under the control of the second scanning signal provided by the second scanning terminal. The first reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal, and the control node, respectively, and is used to control the connection or disconnection between the first initial voltage terminal and the control node under the control of the first reset control signal provided by the first reset control terminal; The display cycle of the pixel circuit includes refresh frames; The refresh frame includes a data writing phase and a refresh and light emission phase; The refresh frame further includes at least one of a first control phase and a second control phase; The first control phase is set between the data writing phase and the refresh emission phase, and the second control phase is set between the data writing phase and the refresh emission phase; The first reset circuit is used to write the voltage signal provided by the first initial voltage terminal into the control node under the control of the first reset control signal during the first control phase. The on / off control circuit is used, during the second control phase, under the control of the second scanning signal, to control the connection between the control terminal of the drive circuit and the control node.

2. The pixel circuit as described in claim 1, wherein, The refresh frame includes the second control phase; the display cycle also includes a hold frame; the hold frame includes a third control phase and a hold-light phase set sequentially. The on / off control circuit is used in the third control phase to control the connection between the control terminal of the drive circuit and the control node under the control of the second scanning signal.

3. The pixel circuit as described in claim 1, wherein, The refresh frame includes the first control phase; the refresh frame also includes a first reset phase set before the data writing phase; The first initial voltage terminal is used to provide a first initial voltage during the first reset phase and a second first initial voltage during the first control phase. The first reset circuit is used to write a first initial voltage into the control node under the control of a first reset control signal during the first reset phase, and to write a second initial voltage into the control node under the control of a first reset control signal during the first control phase. The first initial voltage is different from the second initial voltage.

4. The pixel circuit as described in claim 3, wherein, The driving circuit includes a p-type driving transistor; The voltage value of the first initial voltage is less than the voltage value of the second initial voltage.

5. The pixel circuit as described in claim 4, wherein, The first initial voltage has a value of -3V; the second initial voltage has a value of -0.5V.

6. The pixel circuit as described in claim 1, wherein, The refresh frame includes the first control phase, and the first reset circuit includes a first transistor; the gate of the first transistor is electrically connected to the first reset control terminal, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the control node. During the first control phase, the first transistor is not fully turned on under the control of the first reset control signal.

7. The pixel circuit as described in claim 6, wherein, The refresh frame also includes a first reset phase set before the data writing phase; During the first reset phase, the first transistor is fully turned on under the control of the first reset control signal; The first transistor is an n-type transistor; During the first reset phase, the potential of the first reset control signal is greater than that during the first control phase. or, The first transistor is a p-type transistor. During the first reset phase, the potential of the first reset control signal is lower than the potential of the first reset control signal during the first control phase.

8. The pixel circuit as described in claim 7, wherein, The first transistor is an n-type transistor; in the first reset phase, the potential of the first reset control signal is 7V; in the first control phase, the potential of the first reset control signal is 1V.

9. The pixel circuit according to any one of claims 1 to 8, wherein, The refresh frame includes the first control phase; the display cycle also includes a hold frame, which includes a fourth control phase and a hold-light phase set sequentially. The first reset circuit is also used in the fourth control phase to write the voltage signal provided by the first initial voltage terminal into the control node under the control of the first reset control signal.

10. The pixel circuit as claimed in claim 9, wherein, It also includes a light-emitting element and a second reset circuit; The refresh frame further includes a fifth control phase disposed between the data writing phase and the refresh illumination phase; the hold frame further includes a sixth control phase disposed before the hold illumination phase; The second reset circuit is electrically connected to the second reset control terminal, the first electrode of the light-emitting element, and the second initial voltage terminal, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal in the fifth control stage and the sixth control stage.

11. The pixel circuit as claimed in claim 2, wherein, The driving circuit further includes a second reset circuit; the refresh frame further includes a fifth control phase disposed between the data writing phase and the refresh light emission phase; the holding frame further includes a sixth control phase disposed before the holding light emission phase; The second reset circuit is electrically connected to the second reset control terminal, the first electrode of the light-emitting element, and the second initial voltage terminal, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal during the fifth control stage and the sixth control stage.

12. The pixel circuit as claimed in claim 11, wherein, The start time of the second control phase is set before the start time of the fifth control phase, and the start time of the third control phase is set before the start time of the sixth control phase; or, The start time of the fifth control stage is set before the start time of the second control stage, and the start time of the sixth control stage is set before the start time of the third control stage.

13. The pixel circuit according to any one of claims 1 to 8, wherein, The pixel circuit further includes a data writing circuit; the display cycle further includes a conduction phase; the conduction phase includes the data writing phase, and the end time of the conduction phase is later than the end time of the data writing phase; The data writing circuit is electrically connected to the second scanning terminal, the data line and the second terminal of the driving circuit, respectively, and is used to write the data voltage on the data line to the second terminal of the driving circuit under the control of the second scanning signal provided by the second scanning terminal during the data writing stage. The compensation control circuit is used to control the connection between the first end of the drive circuit and the control node under the control of the first scan signal during the conduction phase.

14. The pixel circuit according to any one of claims 1 to 8, wherein, It also includes a light-emitting element, a third reset circuit, a first energy storage circuit, and a second energy storage circuit; The third reset circuit is electrically connected to the second reset control terminal, the third initial voltage terminal, and the second terminal of the drive circuit, respectively, and is used to control the connection or disconnection between the third initial voltage terminal and the second terminal of the drive circuit under the control of the second reset control signal provided by the second reset control terminal; The first energy storage circuit is electrically connected to the control terminal of the drive circuit to maintain the potential of the control terminal of the drive circuit. The second energy storage circuit is electrically connected to the control node and is used to maintain the potential of the control node; The compensation control circuit includes oxide transistors, and the on / off control circuit includes low-temperature polysilicon transistors.

15. A driving method applied to a pixel circuit as described in any one of claims 1 to 14, wherein the display cycle of the pixel circuit includes a refresh frame; the refresh frame includes a data writing phase and a refresh emission phase; The refresh frame includes at least one of a first control phase and a second control phase; the first control phase is disposed between the data writing phase and the refresh emission phase, and the second control phase is disposed between the data writing phase and the refresh emission phase; The driving method includes: During the first control phase, the first reset circuit, under the control of the first reset control signal, writes the voltage signal provided by the first initial voltage terminal into the control node; In the second control phase, the on / off control circuit connects the control terminal of the drive circuit with the control node under the control of the second scanning signal.

16. The driving method as described in claim 15, wherein, The refresh frame includes the second control phase; the display cycle also includes a hold frame; the hold frame includes a third control phase and a hold-light phase set sequentially. The driving method further includes: In the third control phase, the on / off control circuit, under the control of the second scanning signal, controls the connection between the control terminal of the drive circuit and the control node.

17. The driving method as described in claim 15, wherein, The refresh frame includes the first control phase; the refresh frame also includes a first reset phase set before the data writing phase; the driving method further includes: During the first reset phase, the first initial voltage terminal provides a first initial voltage, and the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the control node. During the first control phase, the first initial voltage terminal provides a second first initial voltage, and the first reset circuit, under the control of the first reset control signal, writes the second first initial voltage into the control node. The first initial voltage is different from the second initial voltage.

18. The driving method as described in claim 15, wherein, The refresh frame includes the first control phase; the driving method further includes: During the first control phase, the potential of the first reset control signal is adjusted to control the transistors included in the first reset circuit to not be fully turned on. The refresh frame further includes a first reset phase set before the data writing phase; the driving method further includes: During the first reset phase, the first reset circuit, under the control of the first reset control signal, controls the transistors included in the first reset circuit to be fully turned on. The first reset circuit includes an n-type transistor. During the first reset phase, the potential of the first reset control signal is greater than the potential of the first reset control signal during the first control phase; or... The first reset circuit includes a p-type transistor. During the first reset phase, the potential of the first reset control signal is lower than that during the first control phase.

19. The driving method as described in claim 15, wherein, The refresh frame includes the first control phase; the display cycle also includes a hold frame, which includes a fourth control phase and a hold-light phase set sequentially; the driving method further includes: In the fourth control phase, the first reset circuit, under the control of the first reset control signal, writes the voltage signal provided by the first initial voltage terminal into the control node. The driving circuit further includes a second reset circuit; the refresh frame further includes a fifth control phase disposed between the data writing phase and the refresh light emission phase; the holding frame further includes a sixth control phase disposed before the holding light emission phase; the driving method further includes: In the fifth and sixth control phases, the second reset circuit, under the control of the second reset control signal, writes the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element.

20. A display device comprising a pixel circuit as claimed in any one of claims 1 to 14.

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