Storage system and operating method thereof, controller

Abstract

Embodiments of the present disclosure disclose a storage system and an operating method thereof, and a controller. The storage system comprises a controller and a memory device coupled to the controller, the memory device comprising a plurality of storage cell rows, each of the storage cell rows comprising a plurality of storage cells; the controller is configured to: determine one of the plurality of row addresses as a row hammer address based on count data corresponding to each of the plurality of row addresses that have been cached; generate an adjacent row address adjacent to the row hammer address based on the row hammer address; wherein the target storage cell row pointed to by the adjacent row address is adjacent to the storage cell row pointed to by the row hammer address; and send the adjacent row address and a row hammer refresh operation command to the memory device; wherein the row hammer refresh operation command is used to instruct to perform a row hammer refresh operation on the target storage cell row.

Description

Storage system and its operation method, controller Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory system and its operating method and controller. Background Technology

[0002] Memory devices are classified into volatile memory and non-volatile memory based on whether they retain stored data when power is off. Volatile memory, which loses data when power is off, can include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0003] Dynamic random access memory (DRAM) requires periodic refreshing to maintain the data stored in the memory cells. Furthermore, if the same row address in DRAM is accessed continuously and frequently, the accumulated number of accesses may cause the data stored in adjacent rows to flip, a phenomenon generally known as the row hammer effect. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a storage system is provided, comprising: a controller and a memory device coupled to the controller, the memory device including a plurality of memory cell rows, the memory cell rows including a plurality of memory cells; the controller being configured to: determine one of the cached plurality of row addresses as a row hammer address based on count data corresponding to each of the row addresses in the cached plurality of row addresses; generate an adjacent row address adjacent to the row hammer address based on the row hammer address; wherein the target memory cell row pointed to by the adjacent row address is adjacent to the memory cell row pointed to by the row hammer address; and send the adjacent row address and a row hammer refresh operation command to the memory device; wherein the row hammer refresh operation command is used to instruct a row hammer refresh operation to be performed on the target memory cell row.

[0005] According to a second aspect of the present disclosure, a method for operating a storage system is provided, comprising: determining one of the cached row addresses as a row hammer address based on counting data corresponding to each of the cached row addresses; generating an adjacent row address adjacent to the row hammer address based on the row hammer address; wherein the target storage cell row pointed to by the adjacent row address is adjacent to the storage cell row pointed to by the row hammer address; and sending the adjacent row address and a row hammer refresh operation command to a memory device in the storage system; wherein the row hammer refresh operation command is used to instruct a row hammer refresh operation to be performed on the target storage cell row among the plurality of storage cell rows of the memory device.

[0006] According to a third aspect of the present disclosure, a controller is provided, the controller being coupled to a memory device, the memory device including a plurality of memory cell rows, the memory cell rows including a plurality of memory cells; the controller is configured to: determine one of the cached plurality of row addresses as a row hammer address based on count data corresponding to each of the row addresses in the cached plurality of row addresses; generate an adjacent row address adjacent to the row hammer address based on the row hammer address; wherein the target memory cell row pointed to by the adjacent row address is adjacent to the memory cell row pointed to by the row hammer address; and send the adjacent row address and a row hammer refresh operation command to the memory device; wherein the row hammer refresh operation command is used to instruct a row hammer refresh operation to be performed on the target memory cell row.

[0007] In this embodiment, the controller, based on the count data corresponding to each row address in a cached set of row addresses, determines one of the cached row addresses as the row hammer address and further generates adjacent row addresses. The controller then sends the adjacent row addresses and a row hammer refresh operation command to the memory device. The row hammer refresh operation command instructs the execution of a row hammer refresh operation on the target memory cell row pointed to by the adjacent row address, where the target memory cell row is adjacent to the memory cell row pointed to by the row hammer address. Thus, by having the controller find the row hammer address and generate the adjacent row address, the traditional passive prevention within DRAM is transformed into proactive prevention by the controller. This proactively prevents the potential occurrence of row hammer errors in DRAM and avoids row hammer problems, thereby reducing the likelihood of row hammer issues occurring in the memory device and improving data reliability. Attached Figure Description

[0008] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0009] Figure 1 is a schematic diagram of a system according to an embodiment of the present disclosure.

[0010] Figures 2A and 2B are schematic diagrams illustrating a memory device according to embodiments of the present disclosure.

[0011] Figure 3 is a schematic diagram of a row hammer effect in a storage array according to an embodiment of the present disclosure.

[0012] Figure 4 is a schematic diagram illustrating a refresh process according to an embodiment of the present disclosure.

[0013] Figure 5 is a schematic diagram of a storage system according to an embodiment of the present disclosure.

[0014] Figure 6 is a flowchart illustrating an operation method of a storage system according to an embodiment of the present disclosure.

[0015] Figure 7 is an operation flowchart of a storage system according to an embodiment of the present disclosure.

[0016] Figure 8 is a schematic diagram illustrating a controller sending adjacent row addresses and row hammer refresh operation commands to a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0017] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0018] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described herein.

[0019] The present disclosure will be described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0020] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0021] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0022] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0023] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0024] Figure 1 is a schematic diagram of a system according to an embodiment of the present disclosure, and Figures 2A and 2B are schematic diagrams of a memory device according to an embodiment of the present disclosure.

[0025] Referring to FIG1, system 1 may include a host and a storage system 30. In this embodiment of the present disclosure, system 1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory device therein.

[0026] The host device can be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The storage system 30 has one or more memory devices 20 and a controller 10. The host device can be configured to send data to or receive data from the memory device 20. The controller 10 is coupled to both the memory device 20 and the host device and is configured to control the memory device 20. The controller 10 can manage the data stored in the memory device 20 and communicate with the host device.

[0027] The controller 10 can be configured to control the operation of the memory device 20, such as read, write, and refresh operations. In some embodiments, the controller 10 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory device 20. The controller 10 can also perform any other suitable function, such as formatting the memory device 20.

[0028] In some specific embodiments, the controller 10 and one or more memory devices 20 can be integrated into various types of storage devices. For example, the controller 10 can be integrated into the northbridge of a computer motherboard or directly into the computer CPU, and multiple memory devices 20 can be integrated into a memory module. In other words, the storage system 30 can be implemented and packaged into different types of terminal electronic products.

[0029] Controller 10 can send data to or receive data from the host, and can send commands (CMD) and addresses (ADDR) to the memory device 20. Controller 10 may include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 can receive commands (CMD) and addresses (ADDR) from the host. The command generator 110 can generate access commands, refresh commands, etc., by decoding the commands (CMD) received from the host, and can provide access commands and refresh commands to the memory device 20 through the device interface 130. An access command may be a signal instructing the memory device 20 to write or read data by accessing a row of the memory array 210 corresponding to the address ADDR. A refresh command may instruct the memory array 210 of the memory device 20 to perform a data refresh operation.

[0030] The address generator 120 in the controller 10 can generate the row and column addresses to be accessed in the memory array 210 by decoding the address ADDR received from the host interface 140. Furthermore, the memory device 20 can generate addresses of the memory banks to be accessed when the memory array 210 includes multiple banks.

[0031] Furthermore, the controller 10 can control memory device operations such as writing and reading by providing various signals to the memory device 20 via the device interface 130. For example, the controller 10 can provide a write command to the memory device 20. The write command is used to instruct the memory device 20 to perform a write operation to store data in the memory device 20. The memory device 20 can be random access memory (RAM), such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc.

[0032] Referring to Figures 1, 2A, and 2B, the memory device 20 includes a memory array 210 and peripheral circuitry 220. The memory array 210 includes multiple memory banks; as an example, Figure 2B shows 16 memory banks, namely Bank0 to Bank15. Each memory bank includes multiple memory blocks, each memory block includes multiple rows of memory cells and multiple columns of memory cells, each row of memory cells is coupled to a corresponding word line, and each column of memory cells is coupled to a corresponding bit line.

[0033] The peripheral circuitry 220 may include: control circuitry corresponding to each memory block, such as a sensing amplifier (SA) 230 and a word-line driver (WLD); control circuitry corresponding to each memory bank, such as a row decoder 240 and a column decoder 250; and control circuitry corresponding to all memory banks, such as a data input / output buffer 260, a command buffer, a command decoder, an address buffer, and a mode register.

[0034] The peripheral circuit 220 can write data to or read data from the storage array 210 based on the command CMD and address ADDR received from the controller 10, or it can provide the row decoder 240 and column decoder 230 with the control signal CTRL for refreshing the storage cells included in the storage array 210. In other words, the peripheral circuit 220 can perform all operations to process the data in the storage array 210.

[0035] Referring to FIG2A, the memory device includes at least one DRAM chip, each DRAM chip including a memory array 210, the memory array 210 including a plurality of memory cells 201 arranged in an array, each memory cell 201 including a transistor T and a capacitor C. The main working principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells are arranged in an array, which can be regarded as a typical mesh structure. The memory array uses rows and columns to specify addresses. By specifying the intersection of the rows and columns (by specifying the row address and column address of the DRAM), the controller can independently access each memory cell in the DRAM chip and perform read, write or refresh operations on the data stored therein.

[0036] Figure 3 is a schematic diagram of a row hammer effect in a storage array according to an embodiment of the present disclosure. Referring to Figure 3, the storage array includes multiple rows of storage cells, each row of storage cells being coupled to a corresponding word line. When a row of storage cells is accessed rapidly and continuously over a period of time, a data flipping error may occur on a storage cell row physically adjacent to the accessed row. The continuously accessed storage cell row is typically called the aggressor row, and its physical address is the row hammer address. The storage cell row physically adjacent to the aggressor row that may experience a data flipping error is called the victim row, and its physical address is the adjacent row address. It should be noted that each row address corresponds to a word line. By accessing a target row address among multiple row addresses, the word line corresponding to the target row address can be selected or activated.

[0037] To address the row hammer effect, each DRAM device has a target process parameter based on its manufacturing process and storage density. For example, without refreshing rows of memory cells in DRAM, if the number of consecutive accesses to a particular row is less than the defined target parameter, the data stored in physically adjacent rows is safe and reliable. Conversely, if the number of consecutive accesses to a row is greater than or equal to the target parameter, data flipping errors may occur in physically adjacent rows, a phenomenon commonly known as row hammer errors. If a refresh operation is performed on physically adjacent rows before the number of consecutive accesses reaches the target parameter, data flipping errors in adjacent rows can be avoided, thus preventing row hammer errors and the row hammer problem. In practical applications, the target parameters may be the same or different for different DRAM manufacturers. Target parameters are typically set by DRAM manufacturers during the development and design phases. The size of the target parameters can be related to factors such as the process technology used in DRAM production, the DRAM capacity, and the die size.

[0038] DRAM refreshes are typically performed row-by-row. Within a refresh cycle, multiple refresh commands are sent to the memory device to perform a refresh operation on all memory arrays. For example, the controller sends a refresh command to the memory device, which then refreshes the memory cells pointed to by several row addresses across all memory banks based on the refresh command. By continuously sending refresh commands, all memory banks can be refreshed. The refresh cycle depends on the DRAM specifications and is typically measured in milliseconds. For example, if the DRAM refresh cycle is 64 milliseconds, then all memory arrays in the memory device need to be refreshed every 64 milliseconds.

[0039] Figure 4 is a schematic diagram illustrating a refresh operation according to an embodiment of the present disclosure. Referring to Figure 4, the refresh operation mainly includes two parts: the first part is a normal refresh operation (Normal REF) performed to maintain the data stored in the DRAM memory cells. Typically, a normal refresh operation refreshes several rows of memory cells pointed to by row addresses. For example, a normal refresh is performed on the four rows of memory cells pointed to by row addresses within each sub-bank. The second part is a row hammer refresh (RH REF) operation performed to prevent potential row hammer errors in the DRAM. For example, a row hammer refresh is performed on the two rows of memory cells pointed to by row addresses within each sub-bank. In this embodiment, the memory bank may include multiple sub-banks, and each sub-bank includes at least one memory block.

[0040] In the refresh operation of the above technical solution, since the DRAM passively receives the refresh command sent by the controller, the handling of the row hammer problem (e.g., finding the row address corresponding to the invading row and the row address corresponding to the victim row) is performed by the circuit inside the DRAM. Furthermore, due to the limited hardware resources inside the DRAM, the potential probability of row hammer errors in the DRAM is relatively high, and it is also difficult to completely avoid the risk of the row hammer effect.

[0041] Furthermore, the row hammer effect, caused by the high-density arrangement of current DRAM memory cells, exists in all next-generation DRAM devices (e.g., DDR, LPDDR, GDDR, HBM, etc.). The row hammer effect is a security vulnerability, a common problem in all next-generation DRAM devices. By rapidly and consecutively accessing memory cell rows pointed to by the same row address, data in adjacent memory cell rows can be flipped, thereby altering the stored data. Powerful attacks exploiting the row hammer effect can bypass current security mechanisms, leading to system corruption, loss of control, and memory damage.

[0042] Based on one or more of the above-mentioned technical problems, this disclosure provides a storage system.

[0043] Figure 5 is a schematic diagram of a storage system according to an embodiment of the present disclosure. Referring to Figure 5, the storage system 300 includes a memory device 320, which includes, but is not limited to, DRAM. The memory device 320 may include a plurality of memory cell rows, and each memory cell row includes a plurality of memory cells. The memory device 320, memory cell rows, and memory cells can be referred to the relevant descriptions of the memory device 20, memory cell rows, and memory cells 201 in Figures 2A and 2B, respectively.

[0044] The storage system 300 also includes a controller 310, and the memory device 320 is coupled to the controller 310. The controller 310 can provide various signals to the memory device 320 through the device interface 130 shown in FIG. 1 to control operations such as writing and reading. For example, the controller 310 can send at least one of a command signal CMD, a clock signal CLK, and a data signal DQ / data strobe signal DQS to the memory device 320 through the device interface 130 shown in FIG. 1. The controller 310 can also receive the data signal DQ / data strobe signal DQS sent by the memory device 320 through the device interface 130 shown in FIG. 1. It should be noted that the data signal DQ / data strobe signal DQS is a synchronization signal; for example, the controller 310 synchronously sends the data signal DQ and the data strobe signal DQS to the memory device 320.

[0045] In some embodiments, the controller 310 is configured to: determine one of the cached row addresses as a row hammer address based on the count data corresponding to each row address in the cached plurality of row addresses; generate an adjacent row address adjacent to the row hammer address based on the row hammer address; wherein the target memory cell row pointed to by the adjacent row address is adjacent to the memory cell row pointed to by the row hammer address; and send the adjacent row address and a row hammer refresh operation command to the memory device 320; wherein the row hammer refresh operation command is used to instruct the target memory cell row to perform a row hammer refresh operation.

[0046] In this embodiment, the controller 310 can cache corresponding row addresses based on received access requests from the host or based on multiple access commands or refresh commands sent to the memory device 320. Specifically, the controller 310 can cache multiple row addresses and record count data corresponding to each cached row address. When any one of the recorded count data reaches a target parameter, the row address corresponding to the count data reaching the target parameter is determined as the row hammer address, and an adjacent row address adjacent to the row hammer address is generated. Then, the adjacent row address and a row hammer refresh operation command are sent to the memory device 320. As an example, the controller 310 can send a row hammer activation command and a precharge command to the memory device 320 to perform a row hammer refresh operation on the target memory cell row. It is understood that the row hammer refresh operation command includes a row hammer activation command and a precharge command.

[0047] In other words, the controller 310 can find the row hammer address and further generate adjacent row addresses by using the count data corresponding to each cached row address. It then sends the adjacent row addresses and the row hammer refresh operation command to the memory device 320, thereby performing a row hammer refresh operation on the target memory cell row pointed to by the adjacent row address. Thus, by having the controller 310 find the row hammer address and generate adjacent row addresses, the traditional passive prevention within the DRAM is transformed into active prevention by the controller 310. This proactively prevents the potential for row hammer errors in the DRAM and avoids row hammer problems, reducing the likelihood of row hammer problems occurring in the memory device 320 and improving data reliability.

[0048] In some embodiments, the controller 310 is further configured to: send a plurality of activation commands to the memory device 320; wherein an activation command is used to indicate the activation of a target row address; and randomly latch at least one target row address corresponding to an activation command based on a generated random number.

[0049] In this embodiment of the disclosure, the controller 310 can send multiple activation commands to the memory device 320. As an example, the controller 310 can generate an access command based on a received access request from the host and send it to the memory device 320. The access request may include at least one of a read request and a write request. As another example, the controller 310 can internally generate an access command or a refresh command and send it to the memory device 320. In both examples, the access command or refresh command may include an activation command and other operation commands, such as a read command, a write command, etc.

[0050] The memory device 320 can activate the corresponding target row address in response to each activation command. For example, the row decoder 240 in FIG2A can decode the row address to activate the target row address, and the word line driver can provide the word line drive voltage to the word line corresponding to the target row address based on the target row address. It should be noted that the target row addresses indicated by the activation commands can be the same or different, and multiple activation commands can be sent to the memory device 320 continuously or intermittently. This disclosure does not impose any special restrictions on this.

[0051] The controller 310 can also generate random numbers and latch at least one target row address corresponding to an activation command based on the generated random numbers. For ease of understanding, the following example will be provided with a random number of N, a number of activation commands of M, and both N and M being integers greater than 1.

[0052] As an example, if N ≤ M < k*N, where k is an integer greater than 1, the controller 310 can latch the target row address corresponding to the Nth activation command, the target row address corresponding to the 2Nth activation command, and the target row address corresponding to the (k-1)th activation command, respectively. It should be noted that when k is 2, the controller 310 can latch only the target row address corresponding to the Nth activation command.

[0053] Furthermore, if the M activation commands are sent in multiple transmissions, for example, in two transmissions where the first transmission sends M1 activation commands and the second transmission sends M2 activation commands, where M1 and M2 are both integers greater than 1, and M1 < N ≤ M1 + M2 ≤ M, the controller 310 can, in the case of the first transmission of M1 activation commands, not latch the target row address, and if, in the case of the second transmission, the sum of the sequence number of a certain activation command and M1 is an integer multiple of the random number N, then the controller 310 can latch the target row address corresponding to that activation command.

[0054] It is understood that in this embodiment of the present disclosure, multiple activation commands can be sent to the memory device 320 in multiple installments. The controller 310 can accumulate the number of activation commands sent in multiple installments, and when the number of accumulated activation commands is an integer multiple of a random number, latch the target row address corresponding to the activation command.

[0055] In this embodiment of the disclosure, the controller 310 generates random numbers and latches at least one target row address corresponding to an activation command based on the generated random numbers, thereby increasing the randomness of the target row address latch. This can prevent hackers or other users with restricted access from using the row hammer effect to carry out row hammer attacks, which is beneficial to improving the reliability of data and the security and stability of the storage system 300.

[0056] In some embodiments, as shown in FIG5, the controller 310 includes a random number generation circuit 311; the random number generation circuit 311 is configured to generate random numbers based on the power-on of the storage system 300.

[0057] In this embodiment of the disclosure, the random number generation circuit 311 can generate any random number during the power-on initialization process of the storage system 300 or after the storage system 300 has completed power-on initialization. The random number can be an integer greater than 1. In addition, the random number generation circuit 311 can also update the generated random number. The updated random number can be the same as or different from the original random number.

[0058] As an example, the updated random number is different from the original random number. For instance, the original random number is N1, and the updated random number is N2. Both N1 and N2 are integers greater than 1 and are different. Before the random number N1 is updated, the controller 310 can latch the target line address corresponding to the activation command if the number of accumulated activation commands is an integer multiple of N1. After the random number N1 is updated to N2, the controller 310 can latch the target line address corresponding to the activation command if the number of accumulated activation commands is an integer multiple of N2. This makes the latching of the target line address more random, meaning the controller 310 does not follow a fixed pattern to latch the target line address, thus preventing hackers or other users with restricted access from finding a fixed pattern in the controller 310's prevention of line hammer attacks. This avoids hackers or other users with restricted access from using fixed patterns to launch line hammer attacks.

[0059] In some embodiments, referring to FIG5, the controller 310 further includes a power-on circuit 318, which is coupled to a random number generation circuit 311. The power-on circuit 318 is configured to generate a random number control signal upon power-on of the storage system 300; wherein the random number control signal is used to indicate the generation of random numbers. The random number generation circuit 311 can receive the random number control signal generated by the power-on circuit 318 and generate random numbers. The power-on circuit 318 can also perform a power-on initialization operation upon power-on of the storage system 300.

[0060] In some embodiments, the random number generation circuit 311 includes a plurality of random number generation sub-circuits and a random number operation circuit, wherein the plurality of random number generation sub-circuits are all coupled to the random number operation circuit; the random number generation sub-circuits are configured to generate an initial random number based on the power-on of the storage system 300; the random number operation circuit is configured to perform operations on the initial random number generated by each random number generation sub-circuit to generate a random number.

[0061] In this embodiment, each random number generation subcircuit can generate an initial random number during the power-on initialization process of the storage system 300 or after the storage system 300 has completed power-on initialization. The initial random numbers generated by any two random number generation subcircuits can be the same or different. The random number operation circuit performs operations on the initial random numbers generated by each random number generation subcircuit to obtain a random number. These operations can include addition, subtraction, multiplication, division, or other operations. Furthermore, the random number generation subcircuit can also update the generated initial random number to update the random number.

[0062] In some embodiments, referring to FIG5, the controller 310 further includes a row address latch circuit 312, which is coupled to a random number generation circuit 311; the row address latch circuit 312 is configured to latch at least one target row address corresponding to an activation command based on the generated random number; wherein the count of activation commands corresponding to the latched target row address is an integer multiple of the random number.

[0063] In this embodiment of the disclosure, the row address latch circuit 312 can temporarily store the target row address corresponding to the activation command whose count is an integer multiple of the random number, provided that the number of accumulated activation commands is an integer multiple of the random number (i.e., the count of activation commands is an integer multiple of the random number). In other words, the row address latch circuit 312 can randomly latch one or more target row addresses based on random numbers, increasing the randomness of the target row address latch. The row address latch circuit 312 includes any latch that can implement row address latching.

[0064] As an example, the row address latch circuit 312 can latch the target row address corresponding to the Nth activation command, the target row address corresponding to the 2Nth activation command, and the target row address corresponding to the (k-1)th activation command, respectively. It should be noted that when k is 2, the row address latch circuit 312 can latch only the target row address corresponding to the Nth activation command.

[0065] In some embodiments, as shown in FIG5, the controller 310 further includes a row address counting circuit 313, which is coupled to a row address latching circuit 312; the row address counting circuit 313 is configured to increase the count data corresponding to the latched target row address based on the latched target row address being hit.

[0066] In this embodiment of the disclosure, the row address counting circuit 313 can record the count data corresponding to each cached row address, and increment the count data corresponding to the latched target row address by 1 when the latched target row address is hit. A latched target row address hit indicates that the latched target row address exists among the multiple cached row addresses.

[0067] In some embodiments, the row address latch circuit 312 is further configured to: compare the latched target row address with multiple cached row addresses and generate a comparison result; wherein the comparison result is used to indicate whether the latched target row address is hit.

[0068] In this embodiment of the disclosure, the row address latch circuit 312 can also compare the latched target row address with multiple cached row addresses to generate a comparison result. If the comparison result indicates that the latched target row address exists among the multiple cached row addresses, it means that the latched target row address in the row address latch circuit 312 has been hit, and the row address counting circuit 313 can increment the count data corresponding to the latched target row address, for example, by incrementing the count data corresponding to the latched target row address by 1; conversely, if the comparison result indicates that the latched target row address does not exist among the multiple cached row addresses, it means that the latched target row address has not been hit, and it is necessary to further determine whether the missed target row address (i.e., the target row address latched in the row address latch circuit 312) should be cached.

[0069] Taking the latching of the target row address corresponding to the Nth activation command as an example, if the target row address corresponding to the Nth activation command is hit, the row address counting circuit 313 will increment the count data corresponding to the hit target row address by 1; otherwise, if the target row address corresponding to the Nth activation command is not hit, it is necessary to further determine whether to cache the target row address corresponding to the Nth activation command.

[0070] It should be noted that if the row address latching circuit 312 latches the same target row address multiple times, and the target row address exists among the multiple cached row addresses, then the row address counting circuit 313 needs to increment the count data corresponding to the target row address by 1 each time the target row address is latched.

[0071] In some embodiments, referring to FIG5, the controller 310 further includes a row address cache circuit 314, which is coupled to the row address latch circuit 312 and the row address counting circuit 313 respectively. The row address cache circuit 314 is configured to determine whether to cache the latched target row address based on a missed latch. The row address counting circuit 313 is further configured to increase the count data corresponding to the cached target row address based on the cached latched target row address.

[0072] In this embodiment, the row address caching circuit 314 can cache multiple row addresses, which are the aforementioned cached row addresses. If the target row address latched by the row address latching circuit 312 is not cached, the row address caching circuit 314 can determine whether to cache the missed target row address. If the row address caching circuit 314 caches the missed target row address, that is, when the missed target row address is cached for the first time in the row address caching circuit 314, the row address counting circuit 313 can set the count data corresponding to the missed target row address to 1.

[0073] In some embodiments, the row address cache circuit 314 is specifically configured to cache the latched target row address based on the fact that the latched target row address is not hit and the cache capacity of the row address cache circuit 314 is sufficient.

[0074] In this embodiment of the disclosure, when the target row address latched by the row address latching circuit 312 fails to cache, the row address caching circuit 314 can determine whether to cache the failed target row address based on whether the current cache capacity is sufficient. Specifically, if the current cache capacity of the row address caching circuit 314 is sufficient, the failed target row address can be cached; conversely, if the current cache capacity of the row address caching circuit 314 is insufficient, it is necessary to further determine whether cache capacity management can be performed to cache the failed target row address.

[0075] It should be noted that if the current cache capacity is greater than or equal to the capacity required for the target row address where a cache miss occurred, then the current cache capacity is sufficient; conversely, if the current cache capacity is less than the capacity required for the target row address where a cache miss occurred, then the current cache capacity is insufficient. The current cache capacity = total capacity of the row address cache circuit 314 - total capacity of the data already cached in the row address cache circuit 314. It should be understood that the total capacity of the data already cached in the row address cache circuit 314 is less than or equal to the total capacity of the row address cache circuit 314.

[0076] In some embodiments, the row address caching circuit 314 is specifically configured to: determine the count data corresponding to each row address already cached in the row address caching circuit 314 based on the target row address being missed and the cache capacity of the row address caching circuit 314 not being met; and delete the row address with the smallest corresponding count data among the cached row addresses based on the fact that the count data corresponding to at least one of the cached row addresses is less than or equal to a first preset threshold, and cache the latched target row address.

[0077] In this embodiment of the disclosure, when the latched target row address is not hit and the cache capacity of the row address cache circuit 314 is insufficient, the row address cache circuit 314 can determine whether to perform cache capacity management, for example, by deleting at least one cached row address to increase the cache capacity. Specifically, the row address cache circuit 314 can determine the count data corresponding to each cached row address through the row address counting circuit 313. If the count data corresponding to at least one row address is less than or equal to a first preset threshold, it indicates that the access frequency of the row address is relatively small, and the possibility that the storage cell row pointed to by the row address is an intrusive row is small. Therefore, the row address with the smallest count data can be deleted to increase the cache capacity, so that the cache capacity after deleting the row address is sufficient, thereby realizing the caching of the missed target row address.

[0078] In some embodiments, the row address caching circuit 314 is specifically configured to: determine the target row address not to be cached based on the fact that the count data corresponding to each cached row address is greater than a first preset threshold.

[0079] In this embodiment, if the count data corresponding to each cached row address is greater than a first preset threshold, it indicates that the access count of each cached row address is relatively large, and the cached row addresses are likely to be intrusive rows. However, since the latched target row address is not hit (the corresponding historical count is 0 or not counted), it indicates that the access count of the hit target row address is less than the access count of each cached row address, and the storage unit row pointed to by the hit target row address is less likely to be an intrusive row. Therefore, the hit target row address can be left uncached.

[0080] As an example, the row address cache circuit 314 can sort the count data corresponding to each cached row address and find whether the smallest count data in the sorted order is less than or equal to a first preset threshold. If the smallest count data in the sorted order is greater than the first preset threshold, it indicates that the count data corresponding to each cached row address is greater than the first preset threshold. Conversely, if the smallest count data in the sorted order is less than or equal to the first preset threshold, it indicates that at least one cached row address can be deleted.

[0081] Of course, in other examples, the row address caching circuit 314 can also sequentially compare the count data corresponding to each cached row address with a first preset threshold to determine whether to delete at least one cached row address. It should be noted that the count data corresponding to each cached row address can be the same or different; for example, the count data corresponding to the first cached row address and the count data corresponding to the second cached row address can be the same or different.

[0082] As an example, the first preset threshold can be any integer from 0 to 16, such as 0, 2, 3, 5, 10, 12, or 16. In practical applications, the first preset threshold can be reasonably set according to the actual situation, and this disclosure does not impose any special restrictions on it.

[0083] In some embodiments, the controller 310 further includes a row hammer refresh operation command generation circuit 315, which is coupled to the row address cache circuit 314 and the row address counting circuit 313 respectively. The row hammer refresh operation command generation circuit 315 is configured to generate a row hammer refresh operation command based on the count data corresponding to one of the cached row addresses being greater than or equal to a second preset threshold. The second preset threshold is greater than a first preset threshold.

[0084] In this embodiment of the present disclosure, the row hammer refresh operation command generation circuit 315 can determine the row address corresponding to the count data that reaches the second preset threshold as the row hammer address when any one of the count data among the recorded multiple count data reaches the second preset threshold (i.e., the target parameter), and generate adjacent row addresses based on the row hammer address, thereby generating the row hammer refresh operation command. The adjacent row addresses and the row hammer refresh operation command can be sent to the memory device 320 through the command output circuit 316 or the device interface 130 shown in FIG1.

[0085] As an example, the second preset threshold can be any integer from 0 to 128. For example, the second preset threshold can be 0, 5, 10, 20, 50, 100, or 128. In practical applications, the second preset threshold can be reasonably set according to the actual situation, and this disclosure does not impose any special restrictions on it.

[0086] In some embodiments, the controller 310 further includes a command output circuit 316, which is coupled to a row hammer refresh operation command generation circuit 315; the command output circuit 316 is configured to: complete the data transmission operation based on the memory bank to which the target memory cell row belongs, and output a row hammer refresh operation command.

[0087] In this embodiment, the command output circuit 316 is used to output the row hammer refresh operation command generated by the row hammer refresh operation command generation circuit 315. Specifically, before sending the adjacent row address and generating the row hammer refresh operation command to the memory device 320, the controller 310 may first confirm whether the memory bank to which the target memory cell row belongs is currently performing a data transmission operation. If the memory bank to which the target memory cell row belongs has completed the data transmission operation, the command output circuit 316 outputs the row hammer refresh operation command to the memory device 320. The data transmission operation includes at least one of a read operation and a write operation.

[0088] It should be noted that the command output circuit 316 can also output other operation commands. The command output circuit 316 can form part of the device interface 130 shown in FIG1, or the command output circuit 316 and the device interface 130 shown in FIG1 can be two separate circuits in the controller. This disclosure does not have any special limitations in this regard.

[0089] In some embodiments, the command output circuit 316 is further configured to delay outputting a row hammer refresh operation command based on the fact that the memory bank to which the target memory cell row belongs is performing a data transfer operation.

[0090] In this embodiment of the present disclosure, if the memory bank to which the target memory cell row belongs is performing a data transmission operation, the command output circuit 316 delays the output of the row hammer refresh operation command to the memory device 320. For example, the row hammer refresh operation command is output after a certain period of time.

[0091] In some embodiments, the controller 310 further includes a determination circuit 317 coupled to a command output circuit 316; the determination circuit 317 is configured to determine whether the memory bank to which the target memory cell row belongs is performing a data transfer operation.

[0092] In this embodiment of the present disclosure, the judgment circuit 317 can determine the state of the memory bank to which the target memory cell row belongs and generate a judgment result. If the judgment result indicates that the memory bank to which the target memory cell row belongs has completed the data transmission operation, it means that the row hammer refresh operation can be performed on the target memory cell row at present, so the command output circuit 316 outputs the row hammer refresh operation command; otherwise, if the judgment result indicates that the memory bank to which the target memory cell row belongs is performing the data transmission operation, it means that it is necessary to wait for the memory bank to which the target memory cell row belongs to complete the data transmission operation, so the command output circuit 316 delays the output of the row hammer refresh operation command.

[0093] In some embodiments, the command output circuit 316 is coupled to the random number generation circuit 311; the command output circuit 316 is further configured to output a plurality of refresh commands during a refresh cycle; wherein the refresh commands are used to instruct at least one of the plurality of memory cell rows to perform a refresh operation; the random number generation circuit 311 is further configured to update the generated random number based on the output refresh commands.

[0094] In this embodiment of the disclosure, the command output circuit 316 can output multiple refresh commands (e.g., the normal refresh command shown in FIG4) during a refresh cycle. The memory device 320 performs a refresh operation on at least one of the multiple memory cell rows based on the refresh commands. The refresh operation is typically performed row by row, that is, data is rewritten by activating the memory cell row indicated by the refresh command to maintain the data stored in the DRAM memory cell. When the command output circuit 316 outputs a refresh command, the random number generation circuit 311 can update the generated random number, for example, update the random number N1 to N2.

[0095] In some embodiments, the command output circuit 316 is coupled to the row address cache circuit 314; the row address cache circuit 314 is further configured to delete the cached row address based on the output refresh command; the row address counting circuit 313 is further configured to reset the counting data corresponding to the cached row address.

[0096] In this embodiment of the disclosure, when a refresh command is output, the row address cache circuit 314 can delete the cached row addresses. For example, if the controller 310 sends multiple refresh commands to the memory device 320 during a refresh cycle to refresh all memory cell rows once, the row address cache circuit 314 can delete all cached row addresses. Furthermore, the row address counting circuit 313 can reset the counting data corresponding to the cached row addresses, for example, by resetting the counting data corresponding to all deleted row addresses to 0 or deleting the counting data corresponding to all row addresses.

[0097] In some embodiments, the row hammer refresh operation command includes a row hammer activation command and a precharge command; wherein, the row hammer activation command is used to instruct an activation operation to be performed on the row address corresponding to the target storage cell row, and the precharge command is used to instruct a precharge operation to be performed on the column address corresponding to the selected storage cell among a plurality of storage cells in the target storage cell row.

[0098] In this embodiment of the present disclosure, the memory device 320 can activate the row address corresponding to the target memory cell row in response to the row hammer activation command. For example, the row decoder 240 in FIG2A can decode the row address to activate the row address corresponding to the target memory cell row, and the word line driver can provide the word line driving voltage to the word line coupled to the target memory cell row based on the row address corresponding to the target memory cell row to complete the activation operation.

[0099] The memory device 320 can also precharge the column address corresponding to the target memory cell row in response to a precharge command. For example, the column decoder 250 in FIG2A can decode the column address to select the column address corresponding to the target memory cell row, and the bit line driver can provide a precharge voltage to the bit line coupled to the target memory cell row based on the column address corresponding to the target memory cell row to complete the precharge operation.

[0100] This disclosure provides a storage system including a controller and a memory device coupled to the controller. The memory device includes multiple rows of memory cells, and each row of memory cells includes multiple memory cells. The controller is configured to: determine a row address as a row hammer address based on count data corresponding to each row address in a cached plurality of row addresses; generate adjacent row addresses based on the row hammer address; wherein the target memory cell row pointed to by the adjacent row address is adjacent to the memory cell row pointed to by the row hammer address; and send the adjacent row address and a row hammer refresh operation command to the memory device; wherein the row hammer refresh operation command is used to instruct the target memory cell row to perform a row hammer refresh operation. Thus, firstly, by having the controller find the row hammer address and generate adjacent row addresses, the traditional passive prevention within DRAM is transformed into proactive prevention by the controller. This proactively prevents potential row hammer errors in DRAM and avoids their occurrence, reducing the likelihood of row hammer problems in memory devices and improving data reliability. Secondly, the increased randomness of target row address latching prevents hackers or other users with restricted access from exploiting security vulnerabilities to launch row hammer attacks, further improving data reliability and the security and stability of the storage system. Thirdly, the entire process of row address latching, counting, and caching is fully automated by the controller hardware, requiring minimal software intervention or changes to any software processes, and has no impact on external systems or the use and operation of the controller. Fourthly, by using a row hammer refresh operation command combining row hammer activation and precharge commands to prevent DRAM row hammer problems, instead of using conventional refresh commands, DRAM utilization efficiency and flexibility can be improved.

[0101] Based on the above storage system, this disclosure provides an operation method for the storage system.

[0102] Figure 6 is a schematic flowchart illustrating an operation method of a storage system according to an embodiment of the present disclosure. It should be noted that the steps shown in Figure 6 are not exclusive, and other steps may be performed before, after, or between any step shown in the operation; the order of the steps shown in Figure 6 can be adjusted according to actual needs. Referring to Figure 6, the operation method includes at least the following steps:

[0103] S410: Based on the count data corresponding to each row address in the cached multiple row addresses, determine one of the cached multiple row addresses as the row hammer address;

[0104] S420: Based on the row hammer address, generate adjacent row addresses that are adjacent to the row hammer address; wherein, the target memory cell row pointed to by the adjacent row address is adjacent to the memory cell row pointed to by the row hammer address;

[0105] S430: Send the adjacent row address and row hammer refresh operation command to the memory device in the storage system; wherein, the row hammer refresh operation command is used to instruct the target memory cell row among the multiple memory cell rows of the memory device to perform a row hammer refresh operation.

[0106] In some embodiments, the above operation method further includes: sending a plurality of activation commands to a memory device; wherein an activation command is used to indicate the activation of a target row address; and randomly latching at least one target row address corresponding to an activation command based on a generated random number.

[0107] In some embodiments, the above operation method further includes: generating a random number based on the power-on of the storage system; latching at least one target row address corresponding to an activation command based on the generated random number; wherein the count of activation commands corresponding to the latched target row address is an integer multiple of the random number; and incrementing the count data corresponding to the latched target row address based on a hit of the latched target row address.

[0108] In some embodiments, the above operation method further includes: determining whether to cache the latched target row address based on a missed latch target row address; and increasing the count data corresponding to the cached target row address based on the cached latched target row address.

[0109] In some embodiments, determining whether to cache the latched target row address based on a missed latched target row address includes: caching the latched target row address based on a missed latched target row address and the cache capacity of the row address caching circuit being sufficient.

[0110] In some embodiments, determining whether to cache the latched target row address based on a missed latched target row address includes: determining the count data corresponding to each cached row address based on a missed latched target row address and the insufficient cache capacity of the row address caching circuit; deleting the row address with the smallest corresponding count data among the cached row addresses based on the fact that the count data corresponding to at least one of the cached row addresses is less than or equal to a first preset threshold, and caching the latched target row address.

[0111] In some embodiments, the above-mentioned determination of whether to cache the latched target row address based on the missing latched target row address further includes: determining not to cache the latched target row address based on the fact that the count data corresponding to each cached row address is greater than a first preset threshold.

[0112] In some embodiments, the above operation method further includes: generating a row hammer refresh operation command based on the fact that the count data corresponding to one of the cached row addresses is greater than or equal to a second preset threshold; wherein the second preset threshold is greater than a first preset threshold.

[0113] In some embodiments, the above operation method further includes: completing the data transmission operation based on the storage bank to which the target storage cell row belongs, and outputting a row hammer refresh operation command.

[0114] In some embodiments, the above operation method further includes: delaying the output of the row hammer refresh operation command based on the fact that the storage bank to which the target storage cell row belongs is performing a data transfer operation.

[0115] In some embodiments, the above operation method further includes: determining whether the storage bank to which the target storage cell row belongs is currently performing a data transfer operation.

[0116] In some embodiments, the above operation method further includes: outputting a plurality of refresh commands during a refresh cycle; wherein the refresh commands are used to instruct at least one of the plurality of storage cell rows to perform a refresh operation; and updating the generated random number based on the output refresh commands.

[0117] In some embodiments, the above operation method further includes: deleting the cached row address based on the output refresh command; and resetting the count data corresponding to the cached row address.

[0118] In some embodiments, the row hammer refresh operation command includes a row hammer activation command and a precharge command; wherein, the row hammer activation command is used to instruct an activation operation to be performed on the row address corresponding to the target storage cell row, and the precharge command is used to instruct a precharge operation to be performed on the column address corresponding to the selected storage cell among a plurality of storage cells in the target storage cell row.

[0119] In this embodiment, the operation method of the storage system can be executed by the controller in any of the foregoing embodiments of the storage system. The technical effects achievable by the storage systems in the foregoing embodiments can also be achieved by the operation method of this storage system, and will not be elaborated upon here. Regarding the operation methods in the above embodiments, the specific implementation methods of each step have been described in detail in the relevant storage system embodiments, and will not be elaborated upon here.

[0120] Figure 7 is an operation flowchart of a storage system according to an embodiment of the present disclosure. To facilitate understanding of the above operation method, the operation method of the storage system provided in the embodiment of the present disclosure will be described exemplarily below with reference to Figures 5 and 7.

[0121] Referring to Figure 7, in step S501: the storage system is powered on. Specifically, the power-on circuit 318 in Figure 5 can perform a power-on initialization operation based on the power-on of the storage system, and generate a random number control signal and send it to the random number generation circuit in Figure 5.

[0122] In step S502: a random number is generated. Specifically, the random number generation circuit in Figure 5 generates a random number based on the received random number control signal and sends it to the row address latch circuit in Figure 5. The random number is an integer greater than 1.

[0123] In step S503: it is determined whether the controller sends an activation command or a refresh command to the memory device. Specifically, if the controller does not send an activation command or a refresh command to the memory device, the process returns to step 503, that is, continues to wait for an activation command or a refresh command; otherwise, if the controller sends an activation command or a refresh command to the memory device, step S504 is executed.

[0124] In step S504: it is determined whether the controller sent an activation command. Specifically, if the controller sent a refresh command instead of an activation command, then step S505 is executed; otherwise, if the controller sent an activation command, then step S506 is executed.

[0125] In step S505: Update the row addresses and counts. Specifically, when a refresh command is output, the row address cache circuit 314 in FIG5 can delete the cached row addresses. For example, if the controller 310 in FIG5 sends multiple refresh commands to the memory device 320 in FIG5 during the refresh cycle to refresh all memory cell rows once, the row address cache circuit 314 in FIG5 can delete all cached row addresses. The row address counting circuit 313 in FIG5 can reset the count data corresponding to the cached row addresses and update the count data. For example, it can reset the count data corresponding to all deleted row addresses to 0 or delete the count data corresponding to all row addresses. The random number generation circuit 311 in FIG5 can also update the generated random numbers.

[0126] In step S506: it is determined whether to latch the target row address corresponding to at least one activation command. Specifically, if the count of the current activation command is an integer multiple of the random number, then the row address latching circuit 312 in Figure 5 latches the target row address; otherwise, if the count of the current activation command is not an integer multiple of the random number, then the row address latching circuit 312 in Figure 5 does not latch the target row address and returns to step 503 to continue waiting for the next activation command or refresh command.

[0127] In step S507: It is determined whether the latched target row address has been hit. Specifically, if the latched target row address exists among the multiple row addresses cached by the row address cache circuit 314 in Figure 5, it indicates that the latched target row address has been hit and step S510 is executed; otherwise, if the latched target row address does not exist among the multiple row addresses cached by the row address cache circuit 314 in Figure 5, it indicates that the latched target row address has been hit and step S508 is executed.

[0128] In step S508: Determine whether to cache the missed target row address. Specifically, if the cache capacity of the row address caching circuit 314 in Figure 5 is sufficient, then the missed target row address is cached and step S509 is executed; if the cache capacity of the row address caching circuit 314 in Figure 5 is insufficient, but the count data corresponding to at least one of the cached row addresses is less than or equal to the first preset threshold, then the row address with the smallest corresponding count data among the cached row addresses is deleted and step S509 is executed; if the cache capacity of the row address caching circuit 314 in Figure 5 is insufficient, and the count data corresponding to each of the cached row addresses is greater than the first preset threshold, then the latched target row address is not cached, and the process returns to step 503 to continue waiting for the next activation command or refresh command.

[0129] In step S509: Update the cached row address. Specifically, if the row address cache circuit 314 in Figure 5 caches a target row address that has not been hit, the cached row address in the row address cache circuit 314 can be updated, and step S510 can be executed.

[0130] In step S510: the row address count is incremented by 1. Specifically, if the latched target row address is hit, the row address counting circuit 313 in Figure 5 can increment the count data corresponding to the hit target row address by 1; if the row address caching circuit 314 in Figure 5 caches the target row address that was not hit for the first time, the row address counting circuit 313 in Figure 5 can set the count data corresponding to the cached target row address to 1.

[0131] In step S511: it is determined whether the row address count has reached the second preset threshold. Specifically, if the count data corresponding to one of the cached row addresses is greater than or equal to the second preset threshold, the row address is determined to be the row hammer address, and adjacent row addresses are generated based on the row hammer address. The row hammer refresh operation command generation circuit 315 in Figure 5 can generate the row hammer refresh operation command and execute step S512; otherwise, if the count data corresponding to each of the cached row addresses is less than the second preset threshold, the process returns to step 503 and continues to wait for the next activation command or refresh command.

[0132] In step S512: It is determined whether the current memory bank is currently performing a data transmission operation. If the current memory bank is performing a data transmission operation, the command output circuit 316 in Figure 5 outputs the row hammer refresh operation command with a delay; otherwise, if the current memory bank has completed the data transmission operation, step S513 is executed. The current memory bank is the memory bank to which the target memory cell row belongs, and the target memory cell row is adjacent to the memory cell row pointed to by the row hammer address.

[0133] In step S513: A row hammer activation command is sent. Specifically, the command output circuit 316 in Figure 5 outputs a row hammer refresh operation command, which includes a row hammer activation command. The row hammer activation command is used to instruct the row address corresponding to the target memory cell row to perform an activation operation. After the activation operation is completed, step S514 is executed.

[0134] In step S514: A precharge command is sent. The row hammer refresh operation command also includes a precharge command, which instructs the column address corresponding to the selected memory cell among multiple memory cells in the target memory cell row to perform a precharge operation. After the precharge operation is completed, step S515 is executed.

[0135] In step S515: Update the row address and count. Specifically, after completing the row hammer refresh operation for the target storage cell row, the row address cache circuit 314 in Figure 5 can delete the row hammer address and update the cached row address. The row address counting circuit 313 in Figure 5 can delete the count data corresponding to the row hammer address. After completing the row hammer refresh operation, continue to wait for the next activation command or refresh command.

[0136] Understandably, by repeatedly executing steps 501 to S515, the controller can handle row hammer problems. That is, the controller finds the row hammer address and generates adjacent row addresses, shifting from passive prevention within the traditional DRAM to active prevention by the controller. This proactively prevents the potential occurrence of row hammer errors in DRAM and avoids the occurrence of row hammer problems, thereby reducing the likelihood of row hammer problems in the memory device and improving data reliability.

[0137] Figure 8 is a schematic diagram illustrating a controller sending adjacent row addresses and row hammer refresh operation commands to a memory device according to an embodiment of the present disclosure.

[0138] Referring to FIG8, the controller 610 sends the adjacent row address RH Row Addr and the row hammer refresh operation command to the memory device 620; wherein, the row hammer refresh operation command includes the row hammer activation command ACT and the precharge command PREPb.

[0139] Specifically, the memory device 620 can perform an activation operation on the target memory cell row pointed to by an adjacent row address based on the row hammer activation command ACT, wherein the activated target memory cell row and the memory cell row pointed to by the row hammer address are adjacent. After the activation operation is completed, the memory device 620 can also perform a precharge operation on the column address corresponding to the target memory cell row based on the precharge command PREPb.

[0140] As an example, controller 610 generates two adjacent row addresses RH Row addr based on the row hammer address. The two adjacent row addresses RH Row addr can be (Aggressor Row Address+1) and (Aggressor Row Address-1), respectively.

[0141] The controller 610 sends a first row hammer activation command ACT and a first adjacent row address (Aggressor Row Address+1) to the memory device 620 to activate (or enable) the first adjacent row address (Aggressor Row Address+1). After activating the first adjacent row address (Aggressor Row Address+1), the controller 610 sends a first precharge command PREPB to disable the first adjacent row address (Aggressor Row Address+1), thereby completing the row hammer refresh of the first target memory cell row pointed to by the first adjacent row address (Aggressor Row Address+1).

[0142] The controller 610 sends a second row hammer activation command ACT and a second adjacent row address (Aggressor Row Address-1) to the memory device 620 to activate (or enable) the second adjacent row address (Aggressor Row Address-1). After activating the second adjacent row address (Aggressor Row Address-1), the controller 610 sends a second precharge command PREPB to disable the second adjacent row address (Aggressor Row Address-1), thereby completing the row hammer refresh of the second target memory cell row pointed to by the second adjacent row address (Aggressor Row Address-1).

[0143] In other examples, row hammer refresh of the second target storage cell row can be performed first, followed by row hammer refresh of the first target storage cell row. The present disclosure does not impose any special limitation on the order of row hammer refresh of the first target storage cell row and the second target storage cell row.

[0144] It should be noted that although the controller 610 generates two adjacent row addresses, if the storage cell row pointed to by the row hammer address is the topmost or bottommost storage cell row among multiple storage cell rows, the memory device 620 can perform row hammer refresh only on one of the adjacent row addresses. That is, the controller 610 sends the first adjacent row address (Aggressor Row Address+1) and the second adjacent row address (Aggressor Row Address-1) to the memory device 620, and the memory device 620 can perform row hammer refresh only on the first adjacent row address (Aggressor Row Address+1) or the second adjacent row address (Aggressor Row Address-1) adjacent to the row hammer address.

[0145] Based on the above-described storage system, this disclosure provides a controller coupled to a memory device, the memory device including multiple rows of storage cells, and each row of storage cells including multiple storage cells; the controller is configured to: determine one of the cached row addresses as a row hammer address based on the counting data corresponding to each row address in the cached multiple row addresses; generate adjacent row addresses based on the row hammer address; wherein the target storage cell row pointed to by the adjacent row address is adjacent to the storage cell row pointed to by the row hammer address; and send the adjacent row address and a row hammer refresh operation command to the memory device; wherein the row hammer refresh operation command is used to instruct the target storage cell row to perform a row hammer refresh operation.

[0146] In some embodiments, the controller is further configured to: send a plurality of activation commands to a memory device; wherein an activation command is used to indicate activation of a target row address; and randomly latch at least one target row address corresponding to an activation command based on a generated random number.

[0147] In some embodiments, the controller includes a random number generation circuit; the random number generation circuit is configured to generate random numbers based on power-on of the storage system.

[0148] In some embodiments, the controller further includes a row address latching circuit coupled to a random number generation circuit; the row address latching circuit is configured to latch at least one target row address corresponding to an activation command based on the generated random number; wherein the count of activation commands corresponding to the latched target row address is an integer multiple of the random number.

[0149] In some embodiments, the controller further includes a row address counting circuit coupled to a row address latching circuit; the row address counting circuit is configured to increment the count data corresponding to the latched target row address based on a hit of the latched target row address.

[0150] In some embodiments, the controller further includes a row address cache circuit, which is coupled to the row address latch circuit and the row address counting circuit respectively; the row address cache circuit is configured to: determine whether to cache the latched target row address based on a missed latched target row address; the row address counting circuit is further configured to: increment the count data corresponding to the cached target row address based on the cached latched target row address.

[0151] In some embodiments, the row address caching circuit is specifically configured to cache the latched target row address based on the fact that the latched target row address is not hit and the cache capacity of the row address caching circuit is sufficient.

[0152] In some embodiments, the row address caching circuit is specifically configured to: determine the count data corresponding to each row address already cached in the row address caching circuit based on the latched target row address not being hit and the cache capacity of the row address caching circuit not being met; and delete the row address with the smallest corresponding count data among the cached row addresses based on the fact that the count data corresponding to at least one of the cached row addresses is less than or equal to a first preset threshold, and cache the latched target row address.

[0153] In some embodiments, the row address caching circuit is specifically configured to: determine the target row address not to be cached based on the fact that the count data corresponding to each cached row address is greater than a first preset threshold.

[0154] In some embodiments, the controller further includes a row hammer refresh operation command generation circuit, which is coupled to a row address cache circuit and a row address counting circuit, respectively. The row hammer refresh operation command generation circuit is configured to generate a row hammer refresh operation command based on the count data corresponding to one of the cached row addresses being greater than or equal to a second preset threshold. The second preset threshold is greater than a first preset threshold.

[0155] In some embodiments, the controller further includes a command output circuit coupled to a row hammer refresh operation command generation circuit; the command output circuit is configured to: complete the data transmission operation based on the memory bank to which the target memory cell row belongs, and output a row hammer refresh operation command.

[0156] In some embodiments, the command output circuit is further configured to delay outputting a row hammer refresh operation command based on the fact that the memory bank to which the target memory cell row belongs is performing a data transfer operation.

[0157] In some embodiments, the controller further includes a determination circuit coupled to a command output circuit; the determination circuit is configured to determine whether the memory bank to which the target memory cell row belongs is performing a data transfer operation.

[0158] In some embodiments, the command output circuit is coupled to the random number generation circuit; the command output circuit is further configured to output a plurality of refresh commands during a refresh cycle; wherein the refresh commands are used to instruct at least one of the plurality of memory cell rows to perform a refresh operation; the random number generation circuit is further configured to update the generated random number based on the output refresh commands.

[0159] In some embodiments, the command output circuit is coupled to the row address cache circuit; the row address cache circuit is further configured to: delete the cached row address based on the output refresh command; the row address counting circuit is further configured to: reset the counting data corresponding to the cached row address.

[0160] In some embodiments, the row hammer refresh operation command includes a row hammer activation command and a precharge command; wherein, the row hammer activation command is used to instruct an activation operation to be performed on the row address corresponding to the target storage cell row, and the precharge command is used to instruct a precharge operation to be performed on the column address corresponding to the selected storage cell among a plurality of storage cells in the target storage cell row.

[0161] In this embodiment, the controller may be the same as the controller in the storage system of any of the foregoing embodiments. The controller can also achieve the technical effects that the storage systems in the foregoing embodiments can achieve, and will not be described in detail here. Regarding the controller in the above embodiments, the various circuits have been described in detail in the embodiments of the relevant storage systems, and will not be elaborated upon here.

[0162] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A storage system, comprising: A controller and a memory device coupled to the controller, the memory device including a plurality of memory cell rows, the memory cell rows including a plurality of memory cells; The controller is configured to: Based on the count data corresponding to each of the cached row addresses, one of the cached row addresses is determined as the row hammer address; Based on the row hammer address, an adjacent row address is generated that is adjacent to the row hammer address; wherein the target memory cell row pointed to by the adjacent row address is adjacent to the memory cell row pointed to by the row hammer address; Send the adjacent row address and row hammer refresh operation command to the memory device; wherein the row hammer refresh operation command is used to instruct the row hammer refresh operation to be performed on the target memory cell row.

2. The storage system according to claim 1, wherein, The controller is also configured to: Multiple activation commands are sent to the memory device; wherein one of the activation commands is used to instruct the activation of a target row address; Based on the generated random number, at least one of the target row addresses corresponding to the activation command is randomly latched.

3. The storage system according to claim 2, wherein, The controller includes: A random number generation circuit, configured to generate the random number upon power-up of the storage system; A row address latching circuit, coupled to the random number generation circuit, is configured to latch at least one target row address corresponding to an activation command based on the generated random number; wherein the count of activation commands corresponding to the latched target row address is an integer multiple of the random number; A row address counting circuit, coupled to the row address latching circuit, is configured to increment the count data corresponding to the latched target row address based on a hit of the latched target row address.

4. The storage system according to claim 3, wherein, The controller also includes: A row address caching circuit is coupled to the row address latching circuit and the row address counting circuit respectively. The row address caching circuit is configured to determine whether to cache the latched target row address based on a miss of the latched target row address. The row address counting circuit is further configured to: increase the count data corresponding to the cached target row address based on the cached target row address.

5. The storage system according to claim 4, wherein, The row address cache circuit is specifically configured as follows: The latched target row address is cached based on the fact that the latched target row address is not hit and the cache capacity of the row address cache circuit is sufficient.

6. The storage system according to claim 4, wherein, The row address cache circuit is specifically configured as follows: Based on the fact that the target row address is not hit and the cache capacity of the row address cache circuit is not met, the count data corresponding to each row address already cached in the row address cache circuit is determined; Based on the fact that the count data corresponding to at least one of the cached row addresses is less than or equal to a first preset threshold, delete the row address with the smallest corresponding count data among the cached row addresses, and cache the latched target row address.

7. The storage system according to claim 6, wherein, The row address cache circuit is specifically configured as follows: Based on the fact that the count data corresponding to each of the cached row addresses is greater than the first preset threshold, it is determined that the latched target row address will not be cached.

8. The storage system according to claim 6, wherein, The controller also includes: A row hammer refresh operation command generation circuit, which is coupled to the row address cache circuit and the row address counting circuit respectively, is configured as follows: The row hammer refresh operation command is generated based on the fact that the count data corresponding to one of the cached row addresses is greater than or equal to a second preset threshold; wherein the second preset threshold is greater than the first preset threshold.

9. The storage system according to claim 8, wherein, The controller also includes: A command output circuit, coupled to the row hammer refresh operation command generation circuit, is configured to: complete the data transmission operation based on the storage bank to which the target storage cell row belongs, and output the row hammer refresh operation command.

10. The storage system according to claim 9, wherein, The command output circuit is further configured to delay outputting the row hammer refresh operation command based on the fact that the storage bank to which the target storage cell row belongs is performing the data transmission operation.

11. The storage system according to claim 9, wherein, The controller also includes: A determination circuit, coupled to the command output circuit, is configured to determine whether the memory bank to which the target memory cell row belongs is currently performing the data transmission operation.

12. The storage system according to claim 9, wherein, The command output circuit is coupled to the random number generation circuit; The command output circuit is further configured to output a plurality of refresh commands during a refresh cycle; wherein the refresh commands are used to instruct a refresh operation to be performed on at least one of the plurality of memory cell rows; The random number generation circuit is further configured to update the generated random number based on the output of the refresh command.

13. The storage system according to claim 12, wherein, The command output circuit is coupled to the row address cache circuit; The row address caching circuit is further configured to: delete the cached row address based on the output of the refresh command; The row address counting circuit is also configured to reset the count data corresponding to the cached row address.

14. The storage system according to claim 1, wherein, The row hammer refresh operation command includes a row hammer activation command and a precharge command; wherein, the row hammer activation command is used to instruct the row address corresponding to the target storage cell row to perform an activation operation, and the precharge command is used to instruct the column address corresponding to the selected storage cell among the multiple storage cells in the target storage cell row to perform a precharge operation.

15. The storage system according to claim 1, wherein, The memory device includes dynamic random access memory.

16. A method of operating a storage system, comprising: Based on the count data corresponding to each of the cached row addresses, one of the cached row addresses is determined as the row hammer address; Based on the row hammer address, an adjacent row address is generated that is adjacent to the row hammer address; wherein the target memory cell row pointed to by the adjacent row address is adjacent to the memory cell row pointed to by the row hammer address; Send the adjacent row address and row hammer refresh operation command to the memory device in the storage system; wherein the row hammer refresh operation command is used to instruct the target memory cell row among the plurality of memory cell rows of the memory device to perform a row hammer refresh operation.

17. The operating method according to claim 16, wherein, The operation method further includes: Multiple activation commands are sent to the memory device; wherein one of the activation commands is used to instruct the activation of a target row address; Based on the generated random number, at least one of the target row addresses corresponding to the activation command is randomly latched.

18. The operating method according to claim 17, wherein, The operation method further includes: The random number is generated based on the power-on of the storage system; Based on the generated random number, latch at least one target row address corresponding to the activation command; wherein the count of the activation commands corresponding to the latched target row address is an integer multiple of the random number; Based on the hit of the latched target row address, the count data corresponding to the latched target row address is increased.

19. The operating method according to claim 18, wherein, The operation method further includes: Based on the fact that the latched target row address is not hit, determine whether to cache the latched target row address; Based on the cached target row address, increment the count data corresponding to the cached target row address.

20. The operating method according to claim 19, wherein, If the target row address based on the latch is not found, determining whether to cache the latched target row address includes: The latched target row address is cached based on the fact that the latched target row address is not hit and the cache capacity of the row address cache circuit is sufficient.

21. The operating method according to claim 19, wherein, If the target row address based on the latch is not found, determining whether to cache the latched target row address includes: Based on the fact that the target row address is not hit and the cache capacity of the row address cache circuit is not met, the count data corresponding to each cached row address is determined; Based on the fact that the count data corresponding to at least one of the cached row addresses is less than or equal to a first preset threshold, delete the row address with the smallest corresponding count data among the cached row addresses, and cache the latched target row address.

22. The operating method according to claim 21, wherein, The determination of whether to cache the latched target row address when the latched target row address is not found further includes: Based on the fact that the count data corresponding to each of the cached row addresses is greater than the first preset threshold, it is determined that the latched target row address will not be cached.

23. The operating method according to claim 21, wherein, The operation method further includes: The row hammer refresh operation command is generated based on the fact that the count data corresponding to one of the cached row addresses is greater than or equal to a second preset threshold; wherein the second preset threshold is greater than the first preset threshold.

24. The operating method according to claim 22, wherein, The operation method further includes: The data transmission operation is completed based on the storage bank to which the target storage cell row belongs, and the row hammer refresh operation command is output.

25. The operating method according to claim 24, wherein, The operation method further includes: The row hammer refresh operation command is delayed because the storage bank to which the target storage cell row belongs is currently performing the data transmission operation.

26. The operating method according to claim 24, wherein, The operation method further includes: determining whether the storage bank to which the target storage cell row belongs is currently performing the data transmission operation.

27. The operating method according to claim 24, wherein, The operation method further includes: Multiple refresh commands are output during the refresh cycle; wherein, the refresh commands are used to instruct a refresh operation to be performed on at least one of the multiple storage cell rows; The generated random number is updated based on the refresh command output.

28. The operating method according to claim 27, wherein, The operation method further includes: Based on the refresh command output, delete the cached row address; Reset the count data corresponding to the cached row address.

29. The operating method according to claim 16, wherein, The row hammer refresh operation command includes a row hammer activation command and a precharge command; wherein, the row hammer activation command is used to instruct the row address corresponding to the target storage cell row to perform an activation operation, and the precharge command is used to instruct the column address corresponding to the selected storage cell among the multiple storage cells in the target storage cell row to perform a precharge operation.

30. A controller coupled to a memory device, the memory device including a plurality of memory cell rows, the memory cell rows including a plurality of memory cells; the controller being configured to: Based on the count data corresponding to each of the cached row addresses, one of the cached row addresses is determined as the row hammer address; Based on the row hammer address, generate adjacent row addresses that are adjacent to the row hammer address; wherein, The target storage cell row pointed to by the adjacent row address is adjacent to the storage cell row pointed to by the row hammer address; Send the adjacent row address and row hammer refresh operation command to the memory device; wherein the row hammer refresh operation command is used to instruct the row hammer refresh operation to be performed on the target memory cell row.

31. The controller according to claim 30, wherein, The controller is also configured to: Multiple activation commands are sent to the memory device; wherein one of the activation commands is used to instruct the activation of a target row address; Based on the generated random number, at least one of the target row addresses corresponding to the activation command is randomly latched.

32. The controller according to claim 31, wherein, The controller includes: A random number generation circuit, configured to generate the random number upon power-up of the controller; A row address latching circuit, coupled to the random number generation circuit, is configured to latch at least one target row address corresponding to an activation command based on the generated random number; wherein the count of activation commands corresponding to the latched target row address is an integer multiple of the random number; A row address counting circuit, coupled to the row address latching circuit, is configured to increment the count data corresponding to the latched target row address based on a hit of the latched target row address.

33. The controller according to claim 32, wherein, The controller also includes: A row address caching circuit is coupled to the row address latching circuit and the row address counting circuit respectively. The row address caching circuit is configured to determine whether to cache the latched target row address based on a miss of the latched target row address. The row address counting circuit is further configured to: increase the count data corresponding to the cached target row address based on the cached target row address.

34. The controller according to claim 33, wherein, The row address cache circuit is specifically configured as follows: The latched target row address is cached based on the fact that the latched target row address is not hit and the cache capacity of the row address cache circuit is sufficient.

35. The controller according to claim 33, wherein, The row address cache circuit is specifically configured as follows: Based on the fact that the target row address is not hit and the cache capacity of the row address cache circuit is not met, the count data corresponding to each row address already cached in the row address cache circuit is determined; Based on the fact that the count data corresponding to at least one of the cached row addresses is less than or equal to a first preset threshold, delete the row address with the smallest corresponding count data among the cached row addresses, and cache the latched target row address.

36. The controller according to claim 35, wherein, The row address cache circuit is specifically configured as follows: Based on the fact that the count data corresponding to each of the cached row addresses is greater than the first preset threshold, it is determined that the latched target row address will not be cached.

37. The controller according to claim 35, wherein, The controller also includes: A row hammer refresh operation command generation circuit, which is coupled to the row address cache circuit and the row address counting circuit respectively, is configured as follows: The row hammer refresh operation command is generated based on the fact that the count data corresponding to one of the cached row addresses is greater than or equal to a second preset threshold; wherein the second preset threshold is greater than the first preset threshold.

38. The controller according to claim 37, wherein, The controller also includes: A command output circuit, coupled to the row hammer refresh operation command generation circuit, is configured to: complete the data transmission operation based on the storage bank to which the target storage cell row belongs, and output the row hammer refresh operation command.

39. The controller according to claim 38, wherein, The command output circuit is further configured to delay outputting the row hammer refresh operation command based on the fact that the storage bank to which the target storage cell row belongs is performing the data transmission operation.

40. The controller according to claim 38, wherein, The controller also includes: A determination circuit, coupled to the command output circuit, is configured to determine whether the memory bank to which the target memory cell row belongs is currently performing the data transmission operation.

41. The controller according to claim 38, wherein, The command output circuit is coupled to the random number generation circuit; The command output circuit is further configured to output a plurality of refresh commands during a refresh cycle; wherein the refresh commands are used to instruct a refresh operation to be performed on at least one of the plurality of memory cell rows; The random number generation circuit is further configured to update the generated random number based on the output of the refresh command.

42. The controller according to claim 41, wherein, The command output circuit is coupled to the row address cache circuit; The row address caching circuit is further configured to: delete the cached row address based on the output of the refresh command; The row address counting circuit is also configured to reset the count data corresponding to the cached row address.

43. The controller according to claim 30, wherein, The row hammer refresh operation command includes a row hammer activation command and a precharge command; wherein, the row hammer activation command is used to instruct the row address corresponding to the target storage cell row to perform an activation operation, and the precharge command is used to instruct the column address corresponding to the selected storage cell among the multiple storage cells in the target storage cell row to perform a precharge operation.

Images