Phase-locked structure, signal generation circuit and equipment thereof

Abstract

The utility model discloses a phase-locked structure, a signal generation circuit and equipment thereof, and relates to the technical field of communication. The phase-locked structure comprises a phase discriminator, a loop filter, a voltage-controlled oscillator, an FPGA and a D trigger. The phase discriminator is used for acquiring a reference clock signal and a first output signal to determine a phase difference between the reference clock signal and the first output signal, and converting the phase difference into a voltage difference; the loop filter is connected to the phase discriminator so as to filter the voltage difference; the voltage-controlled oscillator is connected to the loop filter and generates an output signal of the phase-locked structure according to the filtered voltage difference; the FPGA is connected to the voltage-controlled oscillator so as to perform frequency division on an output signal of the phase-locked structure; the clock end of the D trigger obtains the output signal of the phase-locked structure, and the input end of the D trigger obtains the output signal after frequency division so as to generate the signal of the first output signal. The utility model provides a phase-locked structure, a signal generation circuit and equipment thereof, which can achieve higher frequency precision and higher phase noise level.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a phase-locked structure, a signal generating circuit and a device thereof. Background Art

[0002] In modern communication technology, phase-locked loops are almost everywhere. The output of the phase-locked loop either participates in the mixing of other signals or provides a reference clock for the subsequent phase-locked loop. Its frequency accuracy, phase noise, and spurious level will greatly affect the performance of the entire RF system.

[0003] Frequency accuracy is an important parameter of a phase-locked loop. For a phase-locked loop, the frequency deviation of its reference clock will be reflected in the frequency output of the oscillator in the same proportion. For example, if the frequency accuracy of the reference clock is 1ppm (Parts Per Million), the phase-locked loop may have a maximum absolute frequency deviation of 10kHz when outputting a 10GHz frequency. In addition, if the frequency synthesizer based on the phase-locked loop can have the highest possible frequency resolution (or the smallest possible frequency adjustment step) and the widest possible frequency output range, it will also increase the versatility of the same set of RF circuits or reduce restrictions in the design stage.

[0004] The phase noise of the phase-locked loop output signal will also have a considerable impact on the entire system. Phase noise is the phase jitter of the phase-locked loop voltage-controlled oscillator output signal, which is reflected in the frequency domain as random jitter of the output signal frequency, which will cause a noise sideband centered on the average frequency of the output signal to be observed on its spectrum. If the phase noise level of the phase-locked loop, which is the local oscillator of the RF receiver, is too large, it will cause the same sideband to appear in the intermediate frequency. This will cause serious bit error problems when receiving broadband signals, especially modulated signals such as QAM or PSK that include information in the phase, which is fatal to digital communications.

[0005] In addition to phase noise, the output of a phase-locked loop may also contain various spurious signals, which are usually integer boundary spurious signals or parasitic frequencies introduced by the return period of the frequency-divided pulse. These spurious signals will cause similar effects to phase noise after being output by the phase-locked loop. If such a poor quality signal is used as the reference clock input of another phase-locked loop, it may even cause it to fail to lock.

[0006] Therefore, to improve the performance of the RF system, it is necessary to take into account the above four parameters, generate high-quality clock signals, and take into account the cost of the system. Utility Model Content

[0007] The main technical problem solved by the present application is to provide a phase-locked structure, a signal generating circuit and a device thereof that can achieve higher frequency accuracy and higher phase noise level.

[0008] According to the first aspect, an embodiment provides a phase-locked structure, including:

[0009] A phase detector, used to obtain a reference clock signal and a first output signal to determine a phase difference between the reference clock signal and the first output signal, and convert the phase difference into a voltage difference;

[0010] A loop filter connected to the phase detector to filter the voltage difference;

[0011] A voltage-controlled oscillator, connected to the loop filter, generating an output signal of the phase-locked structure according to the filtered voltage difference;

[0012] FPGA, connected to the voltage-controlled oscillator to divide the frequency of the output signal of the phase-locked structure;

[0013] A D flip-flop, wherein a clock end of the D flip-flop obtains an output signal of the phase-locked structure, and an input end of the D flip-flop obtains a frequency-divided output signal to generate the first output signal.

[0014] In one embodiment, the FPGA comprises:

[0015] A Σ-Δ modulator, used to obtain a preset fractional frequency division ratio and generate a pseudo-random number according to the preset fractional frequency division ratio;

[0016] An adder, used for obtaining a preset integer frequency division ratio and the pseudo-random number to generate a frequency division ratio;

[0017] The multi-mode frequency divider is used to obtain the output signal of the phase-locked structure and the frequency division ratio, so as to divide the output signal of the phase-locked structure according to the frequency division ratio.

[0018] In one embodiment, the pseudo-random number output by the Σ-Δ modulator is updated at the rising edge of the output signal of the phase-locked structure.

[0019] In one embodiment, the Σ-Δ modulator adopts a 3rd-order MASH structure.

[0020] In one embodiment, the preset integer division ratio and the preset fractional division ratio are determined by a host computer.

[0021] According to the second aspect, an embodiment further provides a signal generating circuit, comprising:

[0022] A clock input module, used to generate a reference clock signal;

[0023] A phase-locked structure connected to the clock input module to generate an output signal;

[0024] The phase-locked structure includes a phase detector, a loop filter, a voltage-controlled oscillator, an FPGA and a D flip-flop; the phase detector is used to obtain a reference clock signal and a first output signal to determine a phase difference between the reference clock signal and the first output signal, and convert the phase difference into a voltage difference; the loop filter is connected to the phase detector to filter the voltage difference; the voltage-controlled oscillator is connected to the loop filter to generate an output signal of the phase-locked structure according to the filtered voltage difference; the FPGA is connected to the voltage-controlled oscillator to divide the output signal of the phase-locked structure; the clock end of the D flip-flop obtains the output signal of the phase-locked structure, and the input end of the D flip-flop obtains the divided output signal to generate the first output signal;

[0025] The frequency adjustment module is connected to the phase-locked structure to adjust the output signal to meet the preset requirements.

[0026] In one embodiment, the FPGA comprises:

[0027] A Σ-Δ modulator, used to obtain a preset fractional frequency division ratio and generate a pseudo-random number according to the preset fractional frequency division ratio;

[0028] An adder, used for obtaining a preset integer frequency division ratio and the pseudo-random number to generate a frequency division ratio;

[0029] The multi-mode frequency divider is used to obtain the output signal of the phase-locked structure and the frequency division ratio, so as to divide the output signal of the phase-locked structure according to the frequency division ratio.

[0030] In one embodiment, the pseudo-random number output by the Σ-Δ modulator is updated at the rising edge of the output signal of the phase-locked structure.

[0031] In one embodiment, the Σ-Δ modulator adopts a 3rd-order MASH structure.

[0032] According to the third aspect, an embodiment further provides a device, which includes the signal generating circuit in any one of the above embodiments.

[0033] According to the phase-locked structure, signal generating circuit and device thereof of the above-mentioned embodiment, the phase-locked structure includes a phase detector, a loop filter, a voltage-controlled oscillator, an FPGA and a D flip-flop. A frequency divider with excellent phase noise level is formed by FPGA and D flip-flop to divide the output signal of the phase-locked structure more accurately, so that the output signal of the phase-locked structure can achieve a higher frequency accuracy. The output signal of the phase-locked structure output by the voltage-controlled oscillator is divided into two paths, one of which is input to the D flip-flop as the clock of the D flip-flop, and the other is input to the FPGA for different intervals to achieve different frequency divisions, and the divided frequency is output to the input end of the D flip-flop. Since the output signal output by the locked voltage-controlled oscillator is very stable, the D flip-flop uses the output signal output by the voltage-controlled oscillator as a clock signal, and the jitter of the first output signal output by the D flip-flop is related to the clock signal, so that the low jitter of the first output signal output by the D flip-flop is guaranteed, that is, low phase noise, thereby ultimately ensuring the phase noise of the output signal of the output phase-locked structure, and achieving frequency division. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of the structure of a phase-locked loop frequency synthesizer in the prior art;

[0035] Figure 2 A schematic diagram of a phase-locked structure according to an embodiment;

[0036] Figure 3 A schematic diagram of the structure of an FPGA according to an embodiment;

[0037] Figure 4 A signal block diagram of a 3rd-order MASH structure Σ-Δ modulator according to an embodiment;

[0038] Figure 5 An FPGA logic simulation configuration diagram of an embodiment;

[0039] Figure 6 A schematic diagram of FPGA logic simulation signals according to an embodiment;

[0040] Figure 7 FIG. 4 is a schematic structural diagram of a signal generating circuit according to another embodiment. DETAILED DESCRIPTION

[0041] The present application is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments adopt associated similar element numbers. In the following embodiments, many detailed descriptions are intended to enable the present application to be better understood. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, and methods. In some cases, some operations related to the present application are not shown or described in the specification, in order to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0042] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.

[0043] The serial numbers of the components in this document, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).

[0044] Please refer to Figure 1 , the phase-locked loop frequency synthesizer usually consists of four main components: phase detector, loop filter, voltage-controlled oscillator and programmable divider. The phase detector, loop filter and voltage-controlled oscillator are mainly responsible for the locking of the phase-locked loop, and its frequency-adjustable characteristics benefit from the programmable divider on the feedback loop. Suppose the reference clock signal of the phase-locked loop is Fr, the output signal of the voltage-controlled oscillator is Fo, and the division ratio of the programmable divider is N, then within the output signal range of the voltage-controlled oscillator, Fr = Fo / N. It can be seen that the accuracy and value of N directly determine the accuracy and range of the phase-locked loop output signal.

[0045] Programmable frequency dividers can be roughly divided into integer frequency dividers and fractional frequency dividers. Integer frequency dividers only support integer N. The advantage of integer frequency dividers is that they are simple in structure and can be constructed with only a few D flip-flops, but their disadvantage is that their frequency flexibility is extremely poor. If the target Fo is not an integer multiple of Fr, Fr can only be modified to make Fo fall on a specific N, or to reduce Fr or improve the accuracy of Fo. Fractional frequency dividers use frequency synthesis to output frequency-divided pulse outputs with different frequency-dividing ratios in a certain proportion, so that their period average is equal to the period of the target frequency-dividing output signal. Fractional frequency dividers have high flexibility and no theoretical upper limit on frequency accuracy, which depends on the number of register bits used for counting, but their structure is complex.

[0046] Most existing solutions use integrated PLL chips (phase-locked loop chips) to generate signals. Although integrated PLL chips are easy to use and highly integrated, their phase noise and spurious levels are usually difficult to achieve a good level. In addition, frequency resolution and spurious avoidance are also limited by manufacturers and are not flexible enough. For RF systems with higher requirements for phase noise levels, a phase-locked structure consisting of a discrete phase detector and a multi-mode divider will be used, but there are few multi-mode dividers available on the market and they are expensive.

[0047] In response to the above problems, this application utilizes the existing FPGA or CPLD in the system with a D flip-flop to complete the function of a multi-mode divider, which can not only achieve higher frequency accuracy, higher phase noise and spurious levels, but also greatly save costs, which is explained in detail below.

[0048] Please refer to Figure 2 The present application provides a phase-locked structure 100 , including a phase detector 110 , a loop filter 120 , a voltage-controlled oscillator 130 , an FPGA 140 and a D flip-flop 150 .

[0049] In one embodiment, the phase detector 110 is used to obtain a reference clock signal (ie Figure 2 Fr in) and the first output signal (i.e. Figure 2 Fd in to determine the phase difference between the reference clock signal and the first output signal, and convert the phase difference into a voltage difference.

[0050] In one embodiment, the loop filter 120 is connected to the phase detector 110 to obtain the voltage difference between the reference clock signal and the first output signal (ie Figure 2 Vp in the filter) to filter the voltage difference Vp, thereby obtaining a filtered voltage Vc.

[0051] In one embodiment, the voltage controlled oscillator 130 is connected to the loop filter 120 , and the voltage controlled oscillator obtains the filtered voltage Vc to generate an output signal of the phase locked structure 100 .

[0052] In one embodiment, the FPGA 140 is connected to the voltage-controlled oscillator 130 , and the FPGA 140 is used to obtain the output signal of the phase-locked structure 100 to divide the frequency of the output signal.

[0053] Please refer to Figure 3 In one embodiment, the FPGA 140 includes a Σ-Δ modulator 141, an adder 142, and a multi-mode divider 143. The Σ-Δ modulator 141 is used to obtain a preset fractional frequency division ratio and generate a pseudo-random number according to the preset fractional frequency division ratio. The adder 142 is used to obtain a preset integer frequency division ratio and a pseudo-random number to generate a frequency division ratio. The multi-mode divider 143 is used to obtain the output signal and the frequency division ratio of the phase-locked structure to divide the output signal of the phase-locked structure according to the frequency division ratio. Among them, the Σ-Δ modulator 141 is also connected to the output end of the multi-mode divider 143, so that the pseudo-random number output by the Σ-Δ modulator 141 is updated at the rising edge of the output signal of the phase-locked structure 100. In addition, the preset integer frequency division ratio and the preset fractional frequency division ratio are determined by the host computer.

[0054] It should be noted that the FPGA140 in the present application includes a Σ-Δ modulator 141, an adder 142 and a multi-mode divider 143, which means that the Σ-Δ modulator 141, the adder 142 and the multi-mode divider 143 are implemented in the FPGA140, and the Σ-Δ modulator 141, the adder 142 and the multi-mode divider 143 are existing hardware circuits.

[0055] In one embodiment, the Σ-Δ modulator 141 may be composed of a comparator, an integrator, and a digital quantizer. Its working principle is to continuously compare the input signal, integrate the comparison result, and then compare the integral value with the digital quantizer, and finally output a digital signal. When the Σ-Δ modulator 141 is implemented using FPGA140, the comparator can be first implemented using the logic gates and triggers of the FPGA. The comparator compares the input signal with the output of the integrator and generates a comparison result. Then, the integrator is implemented using the counter and adder of the FPGA. The integrator integrates the comparison result and outputs the integral value. Finally, the digital quantizer is implemented using the logic gates of the FPGA. The digital quantizer compares the integral value with a threshold value and outputs a digital signal, thereby implementing the Σ-Δ modulator 141.

[0056] In one embodiment, a multi-mode frequency divider can be implemented using a counter of an FPGA. The multi-mode frequency divider 143 can generate a corresponding frequency-divided pulse signal according to the frequency-dividing ratio inputted by its control terminal. The principle is to count the rising edge of the output signal of the input phase-locked structure 100. When the count reaches the input positive integer value N of the control terminal, a high-level pulse will be generated at its output terminal, and its internal counter will be reset to 1 at the rising edge of the output signal of the next phase-locked structure 100; if the count does not reach N, the output terminal will maintain a low level. That is, the multi-mode frequency divider 143 is used to count the rising edge of the output signal of the phase-locked structure 100, and when the frequency-dividing ratio obtained by the multi-mode frequency divider 143 is reached, a high level is outputted to divide the output signal of the phase-locked structure 100.

[0057] The core of the frequency synthesis technology in the phase-locked structure 100 is to control the dual-mode frequency divider or the multi-mode frequency divider to output frequency-divided pulses with different integer frequency-dividing ratios according to a certain ratio, so that the average period of these frequency-divided pulses is equal to the product of the input signal period and the fractional frequency-dividing ratio. For example, there is a 10 / 11 dual-mode frequency divider, the target frequency-dividing ratio is 10.2, and the input clock period is T. Then, the pulses with a period of 11T output by the dual-mode frequency divider account for 20% of the total number of pulses, and the pulses with a period of 10T account for 80%. Then, the average period of the output pulse is 10.2T. After a series of operations such as phase discrimination, the output signal Fo of the voltage-controlled oscillator can be locked at 10.2 times the reference clock input Fr. In the present application, the host computer does not directly control the multi-mode frequency divider to perform multiple frequency-dividing ratio switching in the fractional frequency division, but sends a preset integer frequency-dividing ratio N and a preset fractional frequency-dividing ratio x to the FPGA 140, where x is a decimal greater than or equal to 0 and less than 1. After the Σ-Δ modulator obtains the fractional frequency division ratio x, it generates a pseudo-random number y according to the fractional frequency division ratio x and sends it to the adder 142. The adder 142 obtains the preset integer frequency division ratio N and the pseudo-random number y sent by the host computer, and the range is {-3, -2, -1, 0, 1, 2, 3, 4}, thereby generating a frequency division ratio N+y, which means that the pulse period of the multi-mode frequency divider 143 (that is, the output signal of the phase-locked structure) has the possibility of N+{-3, -2, -1, 0, 1, 2, 3, 4}. In this application, the core of the pulse period finally output by the multi-mode frequency divider 143 is the Σ-Δ modulator,

[0058] In one embodiment, the third-order MASH structure Σ-Δ modulator used in this application is shown in FIG. Figure 4This is a signal block diagram of a Σ-Δ modulator with a 3rd-order MASH structure. The Σ-Δ modulator performs an accumulation on the input x (0≤x<1) at the rising edge of each multi-mode divider output signal. When the accumulated value Σ is greater than or equal to 1, it is considered an overflow. At this time, Σ is subtracted by 1 and y is set to 1. If Σ does not overflow, Σ remains unchanged and y is set to 0 (that is, the pseudo-random number output by the Σ-Δ modulator is updated at the rising edge of the multi-mode divider output signal). Taking the implementation of 5.25 division as an example, the preset integer division ratio N is 5, and the preset fractional division ratio x is 0.25. The logic simulation of the FPGA is as follows: Figure 5 and Figure 6 As shown, the pseudo-random number output by the Σ-Δ modulator according to the fractional frequency division ratio x=0.25 is {0, 1, -1, 2, -2, 3, -2, 1}, and the average of its output is Y_avg=(0+1-1+2-2+3-2+1) / 8=0.25. The pseudo-random number is input to the adder, and the frequency division ratio N+y generated by the adder is 5+{0, 1, -1, 2, -2, 3, -2, 1}={5, 6, 4, 7, 3, 8, 3, 6}. According to the frequency division ratio, within a regression cycle of the frequency division pulse sequence output ( Figure 5 There are 8 divided frequency pulse outputs in total (the waveform area between the two vertical lines), and the average pulse width is: T_avg = (5+6+4+7+3+8+3+6) / 8 = 5.25. Figure 4 and Figure 5 From the simulation results in , we can see that the 3rd-order MASH Σ-Δ modulator can generate a divided-frequency pulse output with an average period equal to N+x.

[0059] In one embodiment, the clock terminal of the D flip-flop 150 obtains the output signal of the voltage-controlled oscillator 130, and the input terminal of the D flip-flop 150 (i.e. Figure 2 The D end in the D-terminal of the FPGA 140 is connected to the output end of the FPGA 140 to obtain the output signal of the phase-locked structure 100 after the frequency division, thereby generating a first output signal to the phase detector 110. Although the pseudo-random sequence of the Σ-Δ modulator of the 3rd-order MASH structure suppresses a part of the phase noise, after obtaining the frequency division pulse output by the multi-mode frequency divider, it should also be passed through a D-flip-flop driven by the output signal Fo of the voltage-controlled oscillator, so that the first output signal Fd that performs the phase detection operation with the reference clock signal Fr is synchronized with the output signal Fo of the voltage-controlled oscillator. After passing through the D-flip-flop, the phase noise level of Fd will be determined by Fo, avoiding the phase noise deterioration caused by the frequency divider. That is, since the output signal output by the voltage-controlled oscillator 130 is very stable, the D-flip-flop 150 uses the output signal output by the voltage-controlled oscillator 130 as a clock signal, and the first output signal output by the D-flip-flop 150 is related to the clock signal of the D-flip-flop 150, thereby ensuring the low jitter of the first output signal output by the D-flip-flop 150, that is, low phase noise.

[0060] Please refer to Figure 7 Another embodiment of the present application provides a signal generating circuit 200 , and the signal generating circuit 200 includes a clock input module 210 , a phase-locked structure 100 and a frequency adjustment module 220 .

[0061] In one embodiment, the clock input module 210 is used to generate a reference clock signal.

[0062] In one embodiment, the phase-locked structure 100 is connected to a clock input module 210 to generate an output signal.

[0063] In one embodiment, the phase-locked structure 100 includes a phase detector 110, a loop filter 120, a voltage-controlled oscillator 130, an FPGA 140, and a D flip-flop 150. The phase detector 110 is used to obtain a reference clock signal and a first output signal to determine a phase difference between the reference clock signal and the first output signal, and convert the phase difference into a voltage difference. The loop filter 120 is connected to the phase detector 110, and is used to obtain a voltage difference between the reference clock signal and the first output signal to filter the voltage difference Vp, thereby obtaining a filtered voltage Vc. The voltage-controlled oscillator 130 is connected to the loop filter 120, and the voltage-controlled oscillator obtains the filtered voltage Vc to generate an output signal of the phase-locked structure 100. The FPGA 140 is connected to the voltage-controlled oscillator 130, and the FPGA 140 is used to obtain the output signal of the phase-locked structure 100 to divide the frequency of the output signal. The clock end of the D flip-flop 150 obtains the output signal of the voltage-controlled oscillator 130 , and the input end of the D flip-flop 150 is connected to the output end of the FPGA 140 to obtain the output signal of the phase-locked structure 100 after frequency division, thereby generating a first output signal to the phase detector 110 .

[0064] In one embodiment, FPGA140 includes a Σ-Δ modulator 141, an adder 142 and a multi-mode divider 143. The Σ-Δ modulator 141 is used to obtain a preset fractional frequency division ratio and generate a pseudo-random number according to the preset fractional frequency division ratio. The adder 142 is used to obtain a preset integer frequency division ratio and a pseudo-random number to generate a frequency division ratio. The multi-mode divider 143 is used to obtain the output signal and the frequency division ratio of the phase-locked structure to divide the output signal of the phase-locked structure according to the frequency division ratio. Among them, the Σ-Δ modulator 141 is also connected to the output end of the multi-mode divider 143 so that the pseudo-random number output by the Σ-Δ modulator 141 is updated at the rising edge of the output signal of the phase-locked structure 100. In addition, the preset integer frequency division ratio and the preset fractional frequency division ratio are determined by the host computer.

[0065] It should be noted that the FPGA140 in the present application includes a Σ-Δ modulator 141, an adder 142 and a multi-mode divider 143, which means that the Σ-Δ modulator 141, the adder 142 and the multi-mode divider 143 are implemented in the FPGA140, and the Σ-Δ modulator 141, the adder 142 and the multi-mode divider 143 are existing hardware circuits.

[0066] In one embodiment, the present application uses a 3rd-order MASH structure Σ-Δ modulator. The Σ-Δ modulator performs an accumulation on the input x (0≤x<1) at the rising edge of each multi-mode divider output signal. When the accumulated value Σ is greater than or equal to 1, it is judged as overflow. At this time, Σ is subtracted by 1 and y is set to 1; if Σ does not overflow, Σ remains unchanged and y is set to 0 (that is, the pseudo-random number output by the Σ-Δ modulator is updated at the rising edge of the multi-mode divider output signal).

[0067] In one embodiment, the frequency adjustment module 220 is connected to the phase-locked structure 100 to adjust the output signal to meet a preset requirement.

[0068] As another embodiment, the present application further provides a device, which includes the signal generating circuit 200 in any one of the above embodiments. Since the signal generating circuit 200 has been clearly explained in the above embodiments, it will not be repeated here.

[0069] The above specific examples are used to illustrate the present application, which is only used to help understand the present application and is not intended to limit the present application. For technicians in the technical field to which the present application belongs, they can also make some simple deductions, deformations or substitutions based on the ideas of the present application.

Claims

1. A phase-locked structure, It is characterized in that include: A phase detector, used to obtain a reference clock signal and a first output signal to determine a phase difference between the reference clock signal and the first output signal, and convert the phase difference into a voltage difference; A loop filter connected to the phase detector to filter the voltage difference; A voltage-controlled oscillator, connected to the loop filter, generating an output signal of the phase-locked structure according to the filtered voltage difference; FPGA, connected to the voltage-controlled oscillator to divide the frequency of the output signal of the phase-locked structure; A D flip-flop, wherein a clock end of the D flip-flop obtains an output signal of the phase-locked structure, and an input end of the D flip-flop obtains a frequency-divided output signal to generate the first output signal.

2. The phase-locked structure according to claim 1, It is characterized in that The FPGA comprises: A Σ-Δ modulator, used to obtain a preset fractional frequency division ratio and generate a pseudo-random number according to the preset fractional frequency division ratio; An adder, used for obtaining a preset integer frequency division ratio and the pseudo-random number to generate a frequency division ratio; The multi-mode frequency divider is used to obtain the output signal of the phase-locked structure and the frequency division ratio, so as to divide the output signal of the phase-locked structure according to the frequency division ratio.

3. The phase-locked structure as claimed in claim 2, It is characterized in that The pseudo-random number output by the Σ-Δ modulator is updated at the rising edge of the output signal of the phase-locked structure.

4. The phase-locked structure according to claim 2, It is characterized in that The Σ-Δ modulator adopts a third-order MASH structure.

5. The phase-locked structure according to claim 2, It is characterized in that The preset integer frequency division ratio and the preset fractional frequency division ratio are determined by a host computer.

6. A signal generating circuit, It is characterized in that include: A clock input module, used to generate a reference clock signal; A phase-locked structure connected to the clock input module to generate an output signal; The phase-locked structure includes a phase detector, a loop filter, a voltage-controlled oscillator, an FPGA and a D flip-flop; the phase detector is used to obtain a reference clock signal and a first output signal to determine a phase difference between the reference clock signal and the first output signal, and convert the phase difference into a voltage difference; the loop filter is connected to the phase detector to filter the voltage difference; the voltage-controlled oscillator is connected to the loop filter to generate an output signal of the phase-locked structure according to the filtered voltage difference; the FPGA is connected to the voltage-controlled oscillator to divide the output signal of the phase-locked structure; the clock end of the D flip-flop obtains the output signal of the phase-locked structure, and the input end of the D flip-flop obtains the divided output signal to generate the first output signal; The frequency adjustment module is connected to the phase-locked structure to adjust the output signal to meet the preset requirements.

7. The signal generating circuit as claimed in claim 6, It is characterized in that The FPGA comprises: A Σ-Δ modulator, used to obtain a preset fractional frequency division ratio and generate a pseudo-random number according to the preset fractional frequency division ratio; An adder, used for obtaining a preset integer frequency division ratio and the pseudo-random number to generate a frequency division ratio; The multi-mode frequency divider is used to obtain the output signal of the phase-locked structure and the frequency division ratio, so as to divide the output signal of the phase-locked structure according to the frequency division ratio.

8. The signal generating circuit as claimed in claim 7, It is characterized in that The pseudo-random number output by the Σ-Δ modulator is updated at the rising edge of the output signal of the phase-locked structure.

9. The signal generating circuit as claimed in claim 7, It is characterized in that The Σ-Δ modulator adopts a third-order MASH structure.

10. A device, It is characterized in that The device comprises a signal generating circuit as claimed in any one of claims 6 to 9.

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