Image sensor with improved signal readout

Abstract

The utility model provides an image sensor for improving signal readout, which comprises a plurality of pixel blocks arranged in an array, and each pixel block comprises a photosensitive unit and an overflow unit. The photosensitive unit generates a first charge signal and a second charge signal based on photoelectric conversion, stores the first charge signal and transfers the first charge signal to the main floating diffusion node; the overflow unit comprises an overflow path and a quantization path, and the second charge signal is stored in the overflow unit through the overflow path and transferred to the secondary floating diffusion node through the quantization path; wherein at least one of the first charge signal and the first reset signal corresponding to the first charge signal and at least one of the second charge signal and the second reset signal corresponding to the second charge signal are quantized and read based on the main floating diffusion node and the secondary floating diffusion node respectively, so as to adjust and improve the reading of the actual image signal. The image sensor solves the problem that an existing image sensor is slow in quantitative reading speed.

Description

Technical Field

[0001] The utility model relates to the technical field of image sensors, in particular to an image sensor with improved signal readout. Background Art

[0002] The image sensor is composed of a number of pixel units arranged in an array. When each pixel unit performs quantitative readout, each signal is usually quantized and read out in sequence, such as LCG_RST (low gain reset signal), HCG_RST (high gain reset signal), HCG_SIG (high gain image signal), LCG_SIG (low gain image signal), OF_SIG (overflow image signal), OF_RST (overflow reset signal) are quantized and read out in sequence, thereby completing the quantitative readout of each signal in the pixel unit. However, the above-mentioned quantitative readout method will result in a slow quantitative readout speed. Therefore, how to improve the quantitative readout speed is a technical problem that those skilled in the art are eager to solve.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the utility model and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the utility model. Utility Model Content

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an image sensor with improved signal readout, so as to solve the problem of slow quantization readout speed in the prior image sensor.

[0005] To achieve the above-mentioned object and other related objects, the utility model provides an image sensor for improving signal readout, comprising a plurality of pixel blocks arranged in an array, wherein the pixel blocks include a photosensitive unit and an overflow unit;

[0006] The photosensitive unit generates a first charge signal and a second charge signal based on photoelectric conversion, stores the first charge signal, and transfers the first charge signal to the main floating diffusion node;

[0007] The overflow unit includes an overflow path and a quantization path, the second charge signal is stored in the overflow unit through the overflow path, and is transferred to the secondary floating diffusion node through the quantization path;

[0008] Among them, the first charge signal and at least one of its corresponding first reset signals and the second charge signal and at least one of its corresponding second reset signals are quantized and read out based on the main floating diffusion node and the secondary floating diffusion node respectively to adjust and improve the readout of the actual image signal.

[0009] Optionally, the primary floating diffusion node and the secondary floating diffusion node belong to the same pixel block, and the pixel block further includes a first reset unit, a second reset unit, a first readout unit, and a second readout unit;

[0010] The first reset unit is coupled to the main floating diffusion node and is used to reset at least one of the main floating diffusion node and the photosensitive unit;

[0011] The second reset unit is coupled to the secondary floating diffusion node and is used to reset at least the secondary floating diffusion node;

[0012] The first readout unit is coupled to the main floating diffusion node and is used to perform quantized readout of at least the first charge signal transferred to the main floating diffusion node;

[0013] The second readout unit is coupled to the secondary floating diffusion node and is used to perform quantized readout of at least the second charge signal transferred to the secondary floating diffusion node;

[0014] The first reset unit and / or the second reset unit is also used to reset the overflow unit, and the first readout unit and the second readout unit perform quantized readout through different column lines.

[0015] Optionally, the primary floating diffusion node and the secondary floating diffusion node belong to the pixel block in different rows in the same column, and the pixel block further includes a third resetting unit and a third readout unit;

[0016] The third reset unit is coupled to the corresponding floating diffusion node and is used to reset at least one of the corresponding floating diffusion node, the photosensitive unit and the overflow unit;

[0017] The third readout unit is coupled to the corresponding floating diffusion node and is used to at least quantize and read out the corresponding charge signal transferred to the corresponding floating diffusion node;

[0018] The third readout unit in the pixel block corresponding to the primary floating diffusion node and the third readout unit in the pixel block corresponding to the secondary floating diffusion node perform quantized readout through different column lines.

[0019] Optionally, the pixel blocks in different rows in the same column include pixel blocks in two adjacent rows in the same column, wherein, in the pixel blocks in two adjacent rows in the same column, the floating diffusion nodes corresponding to the pixel blocks in the next row always serve as the sub-floating diffusion nodes of the pixel blocks in the previous row, or the floating diffusion nodes corresponding to the pixel blocks in the previous row always serve as the sub-floating diffusion nodes of the pixel blocks in the next row; or, the floating diffusion nodes corresponding to the pixel blocks in two rows are each other's sub-floating diffusion nodes.

[0020] Optionally, the overflow unit includes a first overflow transistor, a first quantization transistor and a first storage device; the control end of the first overflow transistor receives a first overflow control signal, the first end is coupled to the photosensitive unit, and the second end is coupled to the first end of the first storage device; the control end of the first quantization transistor receives a first quantization control signal, the first end is coupled to the secondary floating diffusion node, and the second end is coupled to the first end of the first storage device; the second end of the first storage device is coupled to a reference potential; wherein the path where the first overflow transistor is located is the overflow path, and the path where the first quantization transistor is located is the quantization path; or, when the main floating diffusion node and the secondary floating diffusion node belong to the same pixel block, the overflow unit removes the first quantization transistor, at which time, the second end of the first overflow transistor is coupled to the first end of the first storage device and is also coupled to the secondary floating diffusion node, wherein the path where the first overflow transistor is located is the overflow path, and the path from the first end of the first storage device to the secondary floating diffusion node is the quantization path.

[0021] Optionally, the pixel block also includes a gain unit, coupled between the corresponding reset unit and the corresponding floating diffusion node, for switching between different gain modes; wherein, when the main floating diffusion node and the secondary floating diffusion node belong to the pixel blocks in different rows in the same column, the first end of the first quantization transistor is directly coupled to the secondary floating diffusion node or coupled to the secondary floating diffusion node through the gain unit corresponding to the secondary floating diffusion node.

[0022] Optionally, when the primary floating diffusion node and the secondary floating diffusion node belong to the pixel blocks in different rows in the same column, the overflow unit includes a second overflow transistor, a second quantization transistor, a second storage device and a first shared transistor; the control end of the second overflow transistor receives a second overflow control signal, the first end is coupled to the photosensitive unit, and the second end is coupled to the first end of the second storage device; the control end of the second quantization transistor receives a second quantization control signal, the first end is coupled to the primary floating diffusion node, and the second end is coupled to the first end of the second storage device; the second end of the second storage device is coupled to a reference potential; the control end of the first shared transistor receives a first shared control signal, the first end is coupled to the secondary floating diffusion node, and the second end is coupled to the first end of the second storage device or the first end of the second quantization transistor; wherein the path where the second overflow transistor is located is the overflow path, and the path where the first shared transistor is located is the quantization path;

[0023] When the floating diffusion nodes corresponding to the two rows of pixel blocks are each other's secondary floating diffusion nodes, the first shared transistor of the overflow unit of the next row of pixel blocks in the two rows of pixel blocks is removed.

[0024] Optionally, when the primary floating diffusion node and the secondary floating diffusion node belong to the pixel blocks in different rows in the same column, the overflow unit includes a third overflow transistor, a third quantization transistor, a third storage device and a second shared transistor; the control end of the third overflow transistor receives a third overflow control signal, the first end is coupled to the photosensitive unit, and the second end is coupled to the first end of the third storage device; the control end of the third quantization transistor receives a third quantization control signal, the first end is coupled to the primary floating diffusion node and to the secondary floating diffusion node through the second shared transistor, and the second end is coupled to the first end of the third storage device; the second end of the third storage device is coupled to a reference potential; the control end of the second shared transistor receives a second shared control signal; wherein the path where the third overflow transistor is located is the overflow path, and the path where the third quantization transistor is located is the quantization path;

[0025] When the floating diffusion nodes corresponding to two rows of pixel blocks are each other's secondary floating diffusion nodes, the first end of the third quantization transistor of the overflow unit of the next row of pixel blocks in the two rows of pixel blocks is no longer coupled to the corresponding floating diffusion node of the next row of pixel blocks.

[0026] Optionally, the pixel block also includes a gain unit, coupled between the third reset unit and the corresponding floating diffusion node, for switching between different gain modes; wherein, when the overflow unit includes the first shared transistor, the first end of the first shared transistor is coupled to the secondary floating diffusion node through the gain unit corresponding to the secondary floating diffusion node; when the overflow unit includes the second shared transistor, the first end of the third quantization transistor is coupled to the secondary floating diffusion node through the second shared transistor and the gain unit in the overflow unit corresponding to the secondary floating diffusion node.

[0027] As described above, the image sensor with improved signal readout of the utility model realizes simultaneous quantization readout of the first charge signal and at least one of its corresponding first reset signal and the second charge signal and at least one of its corresponding second reset signal based on the main floating diffusion node and the secondary floating diffusion node by designing two floating diffusion nodes in one pixel block or sharing the floating diffusion nodes through different rows of pixel blocks, thereby improving the signal quantization readout speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shown is a first structural schematic diagram of the image sensor of the utility model.

[0029] Figure 2 Display as Figure 1 The structure diagram of the first quantization transistor in the pixel block overflow removal unit of the image sensor is shown.

[0030] Figure 3 Display as Figure 1 The schematic diagram of the structure of adding a gain unit to the pixel block of the image sensor is shown.

[0031] Figure 4 The figure shows a second structural schematic diagram of the image sensor of the present invention.

[0032] Figure 5 Shown is a third structural schematic diagram of the image sensor of the utility model.

[0033] Figure 6 and Figure 7 The fourth structural schematic diagram of the image sensor of the utility model is shown, wherein: Figure 6 For any pixel block in the same column, nodes are shared with the pixel block in the next row. Figure 7 A solution for node sharing is to combine two pixel blocks in the same column.

[0034] Figure 8 and Fig. 9 The fifth structural schematic diagram of the image sensor of the utility model is shown, wherein: Figure 8For any pixel block in the same column, nodes are shared with the pixel block in the next row. Fig. 9 A solution for node sharing is to combine two pixel blocks in the same column.

[0035] Fig.10 and Fig.11 The sixth structural schematic diagram of the image sensor of the utility model is shown, wherein: Fig.10 For any pixel block in the same column, nodes are shared with the pixel block in the next row. Fig.11 A solution for node sharing is to combine two pixel blocks in the same column.

[0036] Fig.12 Display as Figure 1 The first timing diagram corresponding to the image sensor shown.

[0037] Fig.13 Display as Figure 1 The second timing diagram corresponding to the image sensor shown.

[0038] Fig.14 Display as Figure 3 The first timing diagram corresponding to the image sensor shown.

[0039] Fig.15 Display as Figure 1 The third timing diagram corresponding to the image sensor shown.

[0040] Fig.16 Display as Figure 1 The fourth timing diagram corresponding to the image sensor shown.

[0041] Fig.17 Display as Figure 3 The second timing diagram corresponding to the image sensor shown.

[0042] Component number description

[0043] 100 Image Sensor

[0044] 110 pixel block

[0045] 111 Photosensitive unit

[0046] 112 Overflow Unit

[0047] 113a First reset unit

[0048] 113b Second reset unit

[0049] 113c Third reset unit

[0050] 114a First readout unit

[0051] 114b Second readout unit

[0052] 114c Third readout unit

[0053] 115 Gain Unit DETAILED DESCRIPTION

[0054] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] See also Figures 1 to 17 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the utility model in a schematic manner, and the illustrations only show the components related to the utility model rather than the number, shape and size of the components in actual implementation. The form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0056] like Figures 1 to 5 As shown, this embodiment provides an image sensor 100 for improving signal readout, including a plurality of pixel blocks 110 arranged in an array; wherein the pixel block 110 includes a photosensitive unit 111 and an overflow unit 112 .

[0057] The photosensitive unit 111 generates a first charge signal and a second charge signal based on photoelectric conversion, stores the first charge signal, and transfers the first charge signal to the main floating diffusion node FD0; the overflow unit 112 includes an overflow path and a quantization path, the second charge signal is stored in the overflow unit 112 through the overflow path, and is transferred to the secondary floating diffusion node FD1 through the quantization path. In one implementation, the overflow unit 112 is coupled to the photosensitive unit 111; wherein, at least one of the first charge signal and its corresponding first reset signal and at least one of the second charge signal and its corresponding second reset signal are respectively quantized and read out based on the main floating diffusion node FD0 and the secondary floating diffusion node FD1 to adjust and improve the readout of the actual image signal.

[0058] In an optional scheme, the first charge signal, at least one of the first reset signal and the second charge signal, at least one of the second reset signal are simultaneously quantized and read out based on the main floating diffusion node FD0 and the secondary floating diffusion node FD1, respectively, so as to improve the signal quantization readout speed; for example, the first charge signal and the second charge signal are simultaneously quantized and read out based on the main floating diffusion node FD0 and the secondary floating diffusion node FD1, respectively, or the first reset signal and the second reset signal are simultaneously quantized and read out based on the main floating diffusion node FD0 and the secondary floating diffusion node FD1, respectively. Of course, it is also feasible to simultaneously quantize and read out the corresponding charge signal and the corresponding reset signal.

[0059] It should be noted that the simultaneous quantization readout here is not strictly consistent. As long as there is a timing overlap between the two signals during the quantization readout, the overall quantization readout speed can be improved, which can be understood by those skilled in the art. In addition, the above-mentioned signals can also be signals in different gain modes. Through the design of the utility model, the above-mentioned signals can be read out flexibly, and the frame rate can be improved by designing the readout order between different signals.

[0060] In one embodiment, if Figure 1 As shown, the primary floating diffusion node FD0 and the secondary floating diffusion node FD1 belong to the same pixel block 110 ; in this embodiment, one pixel block 110 includes two floating diffusion nodes, namely, the primary floating diffusion node FD0 and the secondary floating diffusion node FD1 .

[0061] Furthermore, in this embodiment, the pixel block 110 further includes a first resetting unit 113a, a second resetting unit 113b, a first readout unit 114a and a second readout unit 114b.

[0062] The first reset unit 113a is coupled to the main floating diffusion node FD0, and is used to reset at least one of the main floating diffusion node FD0 and the photosensitive unit 111; the second reset unit 113b is coupled to the secondary floating diffusion node FD1, and is used to reset at least the secondary floating diffusion node FD1; the first readout unit 114a is coupled to the main floating diffusion node FD0, and is used to quantize and read out at least the first charge signal transferred to the main floating diffusion node FD0; the second readout unit 114b is coupled to the secondary floating diffusion node FD1, and is used to quantize and read out at least the second charge signal transferred to the secondary floating diffusion node FD1; wherein the first reset unit 113a and / or the second reset unit 113b are also used to reset the overflow unit 112, and the first readout unit 114a and the second readout unit 114b are quantized and read out through different column lines, so as to realize simultaneous quantization and readout of the signal. In practical applications, the second reset unit 113b is usually used to reset the overflow unit 112.

[0063] Furthermore, if Figure 3 As shown, the pixel block 110 of this embodiment further includes a gain unit 115, coupled between the first reset unit 113a and the main floating diffusion node FD0, for switching between different gain modes, such as switching between a low conversion gain (LCG) mode and a high conversion gain (HCG) mode.

[0064] Next, combine Figures 1 to 3 , the specific circuit structure of each functional unit in the pixel block 110 of this embodiment is introduced in detail.

[0065] The photosensitive unit 111 includes at least one photosensitive element PD and at least one transfer transistor M1; the control end of the transfer transistor M1 receives a transfer control signal TX, the first end is coupled to the main floating diffusion node FD0, the second end is coupled to the first end of the photosensitive element PD, and the second end of the photosensitive element PD is coupled to the ground potential or the negative potential.

[0066] As an example, the photosensitive element PD includes a photodiode, and the transfer transistor M1 includes an NMOS tube. At this time, the gate of the transfer transistor M1 receives the transmission control signal TX, the drain is connected to the main floating diffusion node FD0, the source is connected to the first end of the photosensitive element PD (such as the N-type ion doping region), and the second end of the photosensitive element PD (such as the P-type ion doping region) is connected to the ground potential or the negative potential. Of course, in other examples, it is also feasible for the photosensitive element PD to include a grating or a photoconductor and the transfer transistor M1 to include a PMOS tube, which has no effect on this embodiment.

[0067] Typically, the photosensitive element PD is designed to correspond one to one with the transfer transistor M1, and the number of the photosensitive element PD and the transfer transistor M1 can be designed according to actual needs. For example, the photosensitive element PD can be one, or a shared structure formed by two, four, eight, etc. This embodiment does not impose any restrictions on this.

[0068] For the photosensitive unit 111, combined with the actual application scenario, the first charge signal refers to the charge signal corresponding to the potential well portion, and the second charge signal refers to the charge signal corresponding to the overflow portion after the charge exceeds the potential well; when the amount of charge sensed by the photosensitive unit 111 does not reach the overflow state, the charge signal converted therefrom only includes the first charge signal, which is stored in the photosensitive element PD. At this time, the second charge signal can be considered to be zero; when the amount of charge sensed by the photosensitive unit 111 reaches the overflow state, the charge signal converted therefrom includes the first charge signal and the second charge signal. The first charge signal is stored in the photosensitive element PD, and the second charge signal overflows the photosensitive element PD and is stored in the overflow unit 112 based on the overflow path. In some applications, the first charge signal can also be defined as a potential well charge signal, and the second charge signal can be defined as an overflow charge signal.

[0069] In one implementation, Figure 1 As shown, the overflow unit 112 includes a first overflow transistor M20, a first quantization transistor M30 and a first storage device C10; the control end of the first overflow transistor M20 receives a first overflow control signal OFG0, the first end is coupled to the photosensitive unit 111, such as the first end of the photosensitive element PD, and the second end is coupled to the first end of the first storage device C10; the control end of the first quantization transistor M30 receives a first quantization control signal OF_CTL0, the first end is coupled to the secondary floating diffusion node FD1, and the second end is coupled to the first end of the first storage device C10; the second end of the first storage device C10 is coupled to a reference potential, such as a ground potential; wherein the path where the first overflow transistor M20 is located is an overflow path, and the path where the first quantization transistor M3 is located is a quantization path.

[0070] As an example, the first storage device C10 includes a capacitor device, the first overflow transistor M20 includes an NMOS tube, and the first quantization transistor M30 includes an NMOS tube. At this time, the gate of the first overflow transistor M20 receives the first overflow control signal OFG0, the drain is connected to one end of the photosensitive element PD, the source is connected to the first end of the first storage device C10, the gate of the first quantization transistor M30 receives the first quantization control signal OF_CTL0, the drain is connected to the secondary floating diffusion node FD1, and the source is connected to the first end of the first storage device C10. Of course, in other examples, it is also feasible for the first overflow transistor M20 to include a PMOS tube and the first quantization transistor M30 to include a PMOS tube, which has no effect on this embodiment.

[0071] In another implementation, Figure 2 As shown, the overflow unit 112 can also remove the first quantization transistor M30. At this time, the second end of the first overflow transistor M20 is coupled to the first end of the first storage device C10 and is also coupled to the secondary floating diffusion node FD1. In this implementation, the overflow unit 112 includes the first overflow transistor M20 and the first storage device C10. The control end of the first overflow transistor M20 receives the first overflow control signal OFG0, the first end is coupled to the photosensitive unit 111, such as the first end of the photosensitive element PD, the second end is coupled to the first end of the first storage device C10 and coupled to the secondary floating diffusion node FD1, and the second end of the first storage device C10 is coupled to a reference potential, such as a ground potential; wherein the path where the first overflow transistor M20 is located is an overflow path, and the path from the first end of the first storage device C10 to the secondary floating diffusion node FD1 is a quantization path.

[0072] In one implementation, the pixel block 110 also includes a fast reset unit, coupled to both ends of the first storage device C10 in the overflow unit 112, for resetting the overflow unit 112, and the fast reset unit can cooperate with the corresponding reset unit to reset the overflow unit. Among them, the overflow unit 112 can be quickly reset during the global reset of the circuit or the reset reading process of the signal in the first storage device, which is beneficial to the reset of the first storage device and the improvement of the timing control of the device. Of course, the fast reset unit can also be turned on according to other requirements. In one implementation, the fast reset unit may include a fast reset transistor, the control end receives a fast reset control signal, the first end is coupled to one end of the first storage device C10, and the second end is coupled to the other end of the first storage device C10. Optionally, the other end of the first storage device C10 is coupled to a variable potential, at which time, the corresponding end of the fast reset transistor is also coupled to the variable potential, and the two can be simultaneously regulated based on the optional potential. In other embodiments, the other end of the first storage device C10 can also be coupled to a ground potential instead of a variable potential. In addition, according to the threshold of the fast reset transistor, the control terminal of the fast reset transistor and the terminal coupled to the variable potential can be short-circuited while ensuring the normal switching of the transistor.

[0073] In one implementation, the fast reset transistor includes an NMOS transistor. At this time, the gate of the fast reset transistor receives a fast reset control signal, the drain is connected to the first end of the first storage device C10, and the source is connected to the second end of the first storage device C10. Of course, in other implementations, it is also feasible for the fast reset control signal to include a PMOS transistor, which has no substantial impact on this embodiment.

[0074] The first reset unit 113 a includes a first reset transistor M40 , a control terminal of which receives a first reset control signal RST0 , a first terminal of which is coupled to a first power supply potential, and a second terminal of which is coupled to a main floating diffusion node FD0 .

[0075] As an example, the first reset transistor M40 includes an NMOS tube. At this time, the gate of the first reset transistor M40 receives the first reset control signal RST0, the drain is connected to the first power supply potential, and the source is connected to the main floating diffusion node FD0; wherein the first power supply potential is usually the potential of the working voltage and is always a high potential. Of course, in other examples, it is also feasible for the first reset transistor M40 to include a PMOS tube, which has no effect on this embodiment.

[0076] The second reset unit 113 b includes a second reset transistor M41 , a control terminal of which receives a second reset control signal RST1 , a first terminal of which is coupled to a second power supply potential, and a second terminal of which is coupled to the secondary floating diffusion node FD1 .

[0077] As an example, the second reset transistor M41 includes an NMOS tube. At this time, the gate of the second reset transistor M41 receives the second reset control signal RST1, the drain is connected to the second power supply potential, and the source is connected to the secondary floating diffusion node FD1; wherein the second power supply potential is usually the potential of the working voltage and is always a high potential. Of course, in other examples, it is also feasible for the second reset transistor M41 to include a PMOS tube, which has no effect on this embodiment.

[0078] The first read-out unit 114a includes a first source follower transistor M50 and a first selection transistor M60; the control end of the first source follower transistor M50 is coupled to the main floating diffusion node FD0, the first end is coupled to the third power supply potential, and the second end is coupled to the first end of the first selection transistor M60; the control end of the first selection transistor M60 receives the first selection signal SEL0, and the second end is coupled to the first column line BIT0.

[0079] As an example, the first source follower transistor M50 includes an NMOS tube, and the first selection transistor M60 includes an NMOS tube. At this time, the gate of the first source follower transistor M50 is connected to the main floating diffusion node FD0, the drain is connected to the third power supply potential, and the source is connected to the drain of the first selection transistor M60. The gate of the first selection transistor M60 receives the first selection control signal SEL0, and the source is connected to the first column line BIT0; wherein the third power supply potential is usually the potential of the working voltage, which is always a high potential. Of course, in other examples, it is also feasible for the first source follower transistor M50 to include a PMOS tube and the first selection transistor M60 to include a PMOS tube, which has no effect on this embodiment.

[0080] The second read-out unit 114b includes a second source follower transistor M51 and a second selection transistor M61; the control end of the second source follower transistor M51 is coupled to the secondary floating diffusion node FD1, the first end is coupled to the fourth power supply potential, and the second end is coupled to the first end of the second selection transistor M61; the control end of the second selection transistor M61 receives the second selection signal SEL1, and the second end is coupled to the second column line BIT1.

[0081] As an example, the second source follower transistor M51 includes an NMOS tube, and the second selection transistor M61 includes an NMOS tube. At this time, the gate of the second source follower transistor M51 is connected to the secondary floating diffusion node FD1, the drain is connected to the fourth power supply potential, the source is connected to the drain of the second selection transistor M61, the gate of the second selection transistor M61 receives the second selection signal SEL1, and the source is connected to the second column line BIT1; wherein the fourth power supply potential is usually the potential of the working voltage, which is always a high potential. Of course, in other examples, it is also feasible for the second source follower transistor M51 to include a PMOS tube and the second selection transistor M61 to include a PMOS tube, which has no effect on this embodiment.

[0082] The gain unit 115 includes a gain transistor M7, a control terminal receiving a gain control signal DCG, a first terminal coupled to the first reset unit 113a, and a second terminal coupled to the main floating diffusion node FD0. If the gain transistor M7 is turned on, the image sensor operates in the LCG mode, and if the gain transistor M7 is turned off, the image sensor operates in the HCG mode.

[0083] As an example, the gain transistor M7 includes an NMOS tube. At this time, the gate of the gain transistor M7 receives the gain control signal DCG, the drain is connected to the source of the first reset transistor M40 in the first reset unit 113a (at this time, the source of the first reset transistor M40 is no longer connected to the main floating diffusion node FD0), and the source is connected to the main floating diffusion node FD0. Of course, in other examples, it is also feasible for the gain transistor M7 to include a PMOS tube, which has no effect on this embodiment.

[0084] In another embodiment, if Figure 4 and Figure 5 As shown, the primary floating diffusion node FD0 and the secondary floating diffusion node FD1 belong to pixel blocks 110 in different rows in the same column; in this embodiment, one pixel block 110 includes only one floating diffusion node, and through node sharing, one pixel block 110 can simultaneously perform quantization readout of signals based on two floating diffusion nodes. It should be noted that here, one floating diffusion node includes at least one floating diffusion region, such as one floating diffusion node only includes one floating diffusion region and performs signal readout based on it, or one floating diffusion node includes at least two floating diffusion regions and each floating diffusion region is commonly connected to a readout unit (such as commonly connected to the gate of a source follower transistor), so that signal readout is realized based on one floating diffusion node composed of several floating diffusion regions.

[0085] In an optional solution, the pixel blocks 110 in different rows in the same column include two adjacent rows of pixel blocks 110 in the same column; wherein, when the pixel blocks 110 in two adjacent rows in the same column share nodes, there are at least the following two situations:

[0086] The first case is that when a quantization readout operation is performed on any pixel block 110, the pixel block always uses the floating diffusion node corresponding to the pixel block 110 in the next row as the secondary floating diffusion node. At this time, the floating diffusion node corresponding to the pixel block 110 in the previous row is used as the main floating diffusion node, and the floating diffusion node corresponding to the pixel block 110 in the next row is used as the secondary floating diffusion node of the pixel block 110 in the previous row. Figure 4 Of course, the opposite is also true, that is, when a quantization readout operation is performed on any pixel block 110, the pixel block always uses the floating diffusion node corresponding to the pixel block 110 in the previous row as the secondary floating diffusion node.

[0087] The second case is to combine the pixel blocks 110 in the same column in pairs. In any combination, the floating diffusion nodes corresponding to the pixel blocks 110 in two rows are each other's secondary floating diffusion nodes. Figure 5 For example, when a quantization readout operation is performed on the pixel block 110 in the previous row, the floating diffusion node corresponding to the pixel block 110 in the previous row is used as the main floating diffusion node, and the floating diffusion node corresponding to the pixel block 110 in the next row is used as the secondary floating diffusion node of the pixel block 110 in the previous row; when a quantization readout operation is performed on the pixel block 110 in the next row, the floating diffusion node corresponding to the pixel block 110 in the next row is used as the main floating diffusion node, and the floating diffusion node corresponding to the pixel block 110 in the previous row is used as the secondary floating diffusion node of the pixel block 110 in the next row.

[0088] Furthermore, in this embodiment, the pixel block 110 also includes a third reset unit 113c and a third readout unit 114c; the third reset unit 113c is coupled to the corresponding floating diffusion node, and is used to reset at least one of the corresponding floating diffusion node, the photosensitive unit 111 and the overflow unit 112; the third readout unit 114c is coupled to the corresponding floating diffusion node, and is used to at least quantize and read out the corresponding charge signal transferred to the corresponding floating diffusion node; wherein the third readout unit 114c in the pixel block 110 corresponding to the main floating diffusion node FD0 and the third readout unit 114c in the pixel block 110 corresponding to the secondary floating diffusion node FD1 are quantized and read out through different column lines.

[0089] Furthermore, in this embodiment, the pixel block 110 also includes a gain unit 115, coupled between the third reset unit 113c and the corresponding floating diffusion node, for switching between different gain modes, such as switching between a low conversion gain (LCG) mode and a high conversion gain (HCG) mode.

[0090] With respect to the case where the pixel block 110 in the present embodiment includes a gain unit 115, there are two schemes for coupling the quantization path of the overflow unit 112 in the pixel block 110 where the main floating diffusion node FD0 is located to the secondary floating diffusion node FD1: one scheme is that the quantization path is directly coupled to the secondary floating diffusion node FD1, such as the first end of the first quantization transistor M30 in the overflow unit 112 is connected to the secondary floating diffusion node FD1; the other scheme is that the quantization path is coupled to the secondary floating diffusion node FD1 through the gain unit 115 corresponding to the secondary floating diffusion node FD1, that is, the quantization path is coupled to the low gain node of the gain unit 115, such as the first end of the first quantization transistor M30 in the overflow unit 112 is connected to the drain of the gain transistor M7 in the gain unit 115, which is beneficial to the control of low gain.

[0091] Next, combine Figure 4 and Figure 5 , the specific circuit structure of each functional unit in the pixel block 110 of this embodiment is introduced in detail.

[0092] The photosensitive unit 111 is the same as the previous embodiment, and the overflow unit 112 is the same as an implementation method in the previous embodiment. The relevant contents can be found in the above text and will not be repeated here. It should be noted that the diagrams are all based on the example of connecting the first end of the first quantization transistor M30 in the overflow unit 112 to the drain of the gain transistor M7 in the gain unit 115, but those skilled in the art should understand that it is also feasible to directly connect the first end of the first quantization transistor M30 in the overflow unit 112 to the secondary floating diffusion node FD1.

[0093] Of course, the overflow unit 112 may also have a circuit structure different from that of the previous embodiment, especially for the first case in this embodiment.

[0094] As an alternative, Figure 6 As shown, the overflow unit 112 includes a second overflow transistor M21, a second quantization transistor M31, a second storage device C11 and a first shared transistor Ms0; the control end of the second overflow transistor M21 receives a second overflow control signal OFG1, the first end is coupled to the photosensitive unit 111, such as the first end of the photosensitive element PD, and the second end is coupled to the first end of the second storage device C11; the control end of the second quantization transistor M31 receives a second quantization control signal OF_CTL1, the first end is coupled to the main floating diffusion node FD0, and the second end is coupled to the first end of the second storage device C11; the second end of the second storage device C11 is coupled to a reference potential, such as a ground potential; the control end of the first shared transistor Ms0 receives a first shared control signal OF_SH0, the first end is coupled to the secondary floating diffusion node FD1, and the second end is coupled to the first end of the second storage device C11; wherein the path where the second overflow transistor M21 is located is an overflow path, and the path where the first shared transistor Ms0 is located is a quantization path.

[0095] In the above optional scheme, when the pixel block 110 includes a gain unit 115, the first end of the second quantization transistor M31 is no longer directly coupled to the main floating diffusion node FD0, but is coupled to the main floating diffusion node FD0 through the gain unit 115 of its own pixel block 110; similarly, the first end of the first shared transistor Ms0 is no longer directly coupled to the secondary floating diffusion node FD1, but is coupled to the secondary floating diffusion node FD1 through the gain unit 115 of the pixel block 110 corresponding to the secondary floating diffusion node FD1.

[0096] As an example, the second storage device C11 includes a capacitor device, the second overflow transistor M21 includes an NMOS tube, the second quantization transistor M31 includes an NMOS tube, and the first shared transistor Ms0 includes an NMOS tube. At this time, the gate of the second overflow transistor M21 receives the second overflow control signal OFG1, the drain is connected to the first end of the photosensitive element PD, and the source is connected to the first end of the second storage device C11. The gate of the second quantization transistor M31 receives the second quantization control signal OF_CTL1, the drain is connected to the main floating diffusion node FD0, and the source is coupled to the first end of the second storage device C11. The gate of the first shared transistor Ms0 receives the first shared control signal OF_SH0, the drain is connected to the secondary floating diffusion node FD1, and the source is connected to the first end of the second storage device C11. Of course, in other examples, it is also feasible that the second overflow transistor M21 includes a PMOS tube, the second quantization transistor M31 includes a PMOS tube, and the first shared transistor Ms0 includes a PMOS tube, which has no effect on this embodiment.

[0097] In addition, when the circuit structure of the overflow unit 112 is applied to the second case in this embodiment, the connection relationship of each device remains unchanged; only in any combination, the first shared transistor Ms0 of the overflow unit 112 in the next row of pixel blocks 110 needs to be removed, that is, in any combination, the upper and lower rows of pixel blocks 110 share the same first shared transistor Ms0. Figure 7 shown.

[0098] For the above optional solution, the second end of the first sharing transistor Ms0 can be replaced by the first end coupled to the second storage device C11 and the first end coupled to the second quantization transistor M31. Figure 8 As shown. In practical applications, this optional solution is usually applied to the case where the pixel block 110 includes a gain unit 115. In addition, this replacement solution is not only applicable to the first case in this embodiment, but also to the second case in this embodiment. For the second case, the connection relationship of each device remains unchanged; only in any combination, the first shared transistor Ms0 of the overflow unit 112 in the next row of pixel blocks 110 needs to be removed, that is, in any combination, the upper and lower rows of pixel blocks 110 share the same first shared transistor Ms0, as shown in FIG. Fig. 9 shown.

[0099] As another alternative, Fig.10As shown, the overflow unit 112 includes a third overflow transistor M22, a third quantization transistor M32, a third storage device C12 and a second shared transistor Ms1; the control end of the third overflow transistor M22 receives a third overflow control signal OFG2, the first end is coupled to the photosensitive unit 111, such as the first end of the photosensitive element PD, and the second end is coupled to the first end of the third storage device C12; the control end of the third quantization transistor M32 receives a third quantization control signal OF_CTL2, the first end is coupled to the main floating diffusion node FD0 and to the secondary floating diffusion node FD1 through the second shared transistor Ms1, and the second end is coupled to the first end of the third storage device C12; the second end of the third storage device C12 is coupled to a reference potential, such as a ground potential; the control end of the second shared transistor Ms1 receives a second shared control signal OF_SH1; wherein the path where the third overflow transistor M22 is located is an overflow path, and the path where the third quantization transistor M32 is located is a quantization path. In the above optional solution, the first end of the second shared transistor Ms1 is coupled to the corresponding floating diffusion node, and the second end is coupled to the first end of the third quantization transistor M32 in its own pixel block 110. The first end of the third quantization transistor M32 is also coupled to the second end of the second shared transistor Ms1 of the overflow unit 112 in another row of pixel blocks 110. Wherein, when the pixel block 110 includes the gain unit 115, the first end of the second shared transistor Ms1 is no longer directly coupled to the corresponding floating diffusion node, but is coupled to the corresponding floating diffusion node through the gain unit 115; at this time, the first end of the third quantization transistor M32 is coupled to the secondary floating diffusion node FD1 through the second shared transistor Ms1 in the overflow unit 112 corresponding to the secondary floating diffusion node FD1 and the gain unit 115.

[0100] As an example, the third storage device C12 includes a capacitor device, the third overflow transistor M22 includes an NMOS tube, the third quantization transistor M32 includes an NMOS tube, and the second shared transistor Ms1 includes an NMOS tube. At this time, the gate of the third overflow transistor M22 receives the third overflow control signal OFG2, the drain is connected to the first end of the photosensitive element PD, the source is connected to the first end of the third storage device C12, the gate of the third quantization transistor M32 receives the third quantization control signal OF_CTL2, the drain is respectively connected to the source of the second shared transistor Ms1 in the pixel block 110 corresponding to the main floating diffusion node FD0 and the secondary floating diffusion node FD1, the source is connected to the first end of the third storage device C12, the gate of the second shared transistor Ms1 receives the second shared control signal OF_SH1, and the drain is connected to the main floating diffusion node. Of course, in other examples, it is also feasible that the third overflow transistor M22 includes a PMOS tube, the third quantization transistor M32 includes a PMOS tube, and the second shared transistor Ms1 includes a PMOS tube, which has no effect on this embodiment.

[0101] In addition, when the circuit structure of the overflow unit 112 is applied to the second case in the present embodiment, the connection relationship of each device remains unchanged; only in any combination, the connection between the third quantization transistor M32 of the overflow unit 112 in the next row of pixel blocks 110 and its next row needs to be omitted, that is, the first end of the third quantization transistor M32 of the overflow unit 112 in the next row of pixel blocks 110 is no longer coupled to the corresponding floating diffusion node of the next row of pixel blocks, such as Fig.11 shown.

[0102] The third reset unit 113c includes a third reset transistor M42, a control terminal of which receives a third reset control signal RST2, a first terminal of which is coupled to a fifth power supply potential, and a second terminal of which is coupled to a corresponding floating diffusion node.

[0103] As an example, the third reset transistor M42 includes an NMOS tube. At this time, the gate of the third reset transistor M42 receives the third reset control signal RST2, the drain is connected to the fifth power supply potential, and the source is connected to the corresponding floating diffusion node; wherein the fifth power supply potential is usually the potential of the working voltage, which is always a high potential. Of course, in other examples, it is also feasible for the third reset transistor M42 to include a PMOS tube, which has no effect on this embodiment.

[0104] The third read-out unit 114c includes a third source follower transistor M52 and a third selection transistor M62; the control end of the third source follower transistor M52 is coupled to the corresponding floating diffusion node, the first end is coupled to the sixth power supply potential, and the second end is coupled to the first end of the third selection transistor M62; the control end of the third selection transistor M62 receives the third selection signal SEL2, and the second end is coupled to the corresponding column line.

[0105] As an example, the third source follower transistor M52 includes an NMOS tube, and the third selection transistor M62 includes an NMOS tube. At this time, the gate of the third source follower transistor M52 is connected to the corresponding floating diffusion node, the drain is connected to the sixth power supply potential, the source is connected to the drain of the third selection transistor M62, the gate of the third selection transistor M62 receives the third selection control signal SEL2, and the source is connected to the corresponding column line; wherein the sixth power supply potential is usually the potential of the working voltage, which is always a high potential. Of course, in other examples, it is also feasible for the third source follower transistor M52 to include a PMOS tube and the third selection transistor M62 to include a PMOS tube, which has no effect on this embodiment.

[0106] Correspondingly, this embodiment also provides a control method for an image sensor, including a reset stage, an exposure stage and a quantization stage; wherein the image sensor is implemented using the circuit structure described above.

[0107] Reset phase:

[0108] A reset operation is performed on the primary floating diffusion node FD0 , the secondary floating diffusion node FD1 , the photosensitive unit 111 , and the overflow unit 112 .

[0109] For the first embodiment, the pixel block 110 includes two reset units, namely, a first reset unit 113a and a second reset unit 113b; in this case, the first reset unit 113a performs a reset operation on the primary floating diffusion node FD0 and the photosensitive unit 111, and the second reset unit 113b performs a reset operation on the secondary floating diffusion node FD1 and the overflow unit 112. Of course, it is also feasible to perform a reset operation on the overflow unit 112 through the first reset unit 113a or to perform a reset operation on the overflow unit 112 through the first reset unit 113a and the second reset unit 113b at the same time.

[0110] For the second embodiment, the pixel block 110 includes a reset unit, that is, a third reset unit 113c; in this case, the two pixel blocks 110 sharing a node are divided into a main pixel block (a pixel block corresponding to the main floating diffusion node FD0) and a sub-pixel block (a pixel block corresponding to the sub-floating diffusion node FD1), and the main floating diffusion node FD0 and its photosensitive unit 111 and the overflow unit 112 are reset by the third reset unit 113c of the main pixel block, and the sub-floating diffusion node FD1 is reset by the third reset unit 113c of the sub-pixel block. Of course, it is also feasible to reset the overflow unit 112 of the main pixel block by the third reset unit 113c of the sub-pixel block, or to reset the overflow unit 112 of the main pixel block by the third reset unit 113c of the sub-pixel block and the third reset unit 113c of the main pixel block at the same time.

[0111] by Figure 1Taking the circuit structure shown as an example, the first reset transistor M40 in the first reset unit 113a and the transfer transistor M1 in the photosensitive unit 111 are controlled to be turned on, and the charge of the main floating diffusion node FD0 and the photosensitive element PD in the photosensitive unit 111 is cleared to achieve signal reset; the second reset transistor M41 in the second reset unit 113b and the first quantization transistor M30 in the overflow unit 112 are controlled to be turned on, and the charge of the secondary floating diffusion node FD1 and the first storage device C10 in the overflow unit 112 is cleared to achieve signal reset; in this way, the reset operation is completed. Afterwards, the first reset transistor M40, the transfer transistor M1, the second reset transistor M41, and the first quantization transistor M30 are controlled to be turned off. In an optional solution, at least one of the first overflow transistor M20 and the first quantization transistor M30 in the overflow unit 112 can also be controlled to remain turned on during the reset phase, which is conducive to achieving a fast reset of the first storage device C10. Of course, the first reset transistor M40 and the second reset transistor M41 may not be turned off at the end of the reset phase, for example, both are turned on in the reset phase and turned off in the quantization phase. Furthermore, the first reset transistor M40 is turned off after the first selection transistor M60 in the first readout unit 114a is turned on for the first time, and the second reset transistor M41 is turned off after the second selection transistor M61 in the second readout unit 114b is turned on for the first time, so as to avoid crosstalk of other pixel blocks to the corresponding floating diffusion nodes of the current pixel block in the exposure phase. The relevant timing can be seen in detail. Figure 12 to Figure 14 .like Figure 3 As shown, when the pixel block 110 includes a gain unit 115, the control method corresponding to the reset stage is substantially the same as the above control method, except that at this time, the gain transistor M7 in the gain unit 115 needs to be controlled to be turned on to facilitate the execution of the reset operation; wherein, the gain transistor M7 is turned on in the reset stage and turned off in the quantization stage.

[0112] Exposure stage:

[0113] The overflow path is opened and the quantization path is closed, and the second charge signal is stored in the overflow unit 112 through the overflow path.

[0114] by Figure 1 Taking the circuit structure shown in the figure as an example, the first overflow transistor M20 in the overflow unit 112 is controlled to be turned on, and the overflow path is opened at this time. The second charge signal overflowed by the photosensitive element PD in the photosensitive unit 111 is transferred to the first storage device C10 of the overflow unit 112 through the overflow path for storage. After that, the first overflow transistor M20 is controlled to be turned off. The relevant timing can be seen in detail. Figure 12 to Figure 14 .

[0115] When the amount of charge sensed by the photosensitive element PD in the photosensitive unit 111 has not reached the overflow state, the converted charge signal only includes the first charge signal, which is stored on the photosensitive element PD. At this time, although the overflow path is opened, there is no second charge signal transferred to the first storage device C10 through the overflow path. It can be considered that the corresponding second charge signal in this process is zero.

[0116] When the amount of charge sensed by the photosensitive element PD in the photosensitive unit 111 reaches an overflow state, the converted charge signal includes a first charge signal and a second charge signal, wherein the first charge signal is stored on the photosensitive element PD, and the second charge signal is transferred to the first storage device C10 through an overflow path for storage.

[0117] Quantification stage:

[0118] The overflow path is closed and the quantization path is opened to perform quantization readout of at least the first charge signal and at least one of the first reset signal corresponding thereto and at least one of the second charge signal and at least one of the second reset signal corresponding thereto based on the main floating diffusion node FD0 and the secondary floating diffusion node FD1, respectively. In an optional scheme, at least the first charge signal, at least one of the first reset signal, and at least one of the second charge signal and at least one of the second reset signal are simultaneously quantized and readout based on the main floating diffusion node FD0 and the secondary floating diffusion node FD1, respectively, to improve the signal quantization readout speed. In an implementation scheme, the quantization stage performs correlated double sampling on both the first charge signal and the second charge signal.

[0119] Specifically, it includes: closing the overflow path to simultaneously perform quantization reading of the first reset signal and the second reset signal based on the main floating diffusion node FD0 and the secondary floating diffusion node FD1, respectively; opening the quantization path to simultaneously perform quantization reading of the first charge signal and the second charge signal based on the main floating diffusion node FD0 and the secondary floating diffusion node FD1, respectively.

[0120] by Figure 1Taking the circuit structure shown as an example, since the first overflow transistor M20 in the overflow unit 112 is closed during the exposure phase, the overflow path is closed; first, the first selection transistor M60 in the first readout unit 114a and the second selection transistor M61 in the second readout unit 114b are controlled to be turned on, so as to simultaneously perform quantization reading of the first reset signal (i.e., PD_RST) and the second reset signal (i.e., OF_RST) based on the main floating diffusion node FD0 and the secondary floating diffusion node FD1, respectively; then, the transfer transistor M1 in the photosensitive unit 111 is controlled to be turned on and then turned off, so as to transfer the first charge signal stored in the photosensitive element PD to the main floating diffusion node FD0, and at the same time, the first quantization transistor M30 in the overflow unit 112 is controlled to be turned on and then turned off, so as to transfer the second charge signal stored in the first storage device C10 in the overflow unit 112 to the secondary floating diffusion node FD1 through the quantization path, so as to simultaneously perform quantization reading of the first charge signal (i.e., PD_SIG) and the second charge signal (i.e., OF_SIG) based on the main floating diffusion node FD0 and the secondary floating diffusion node FD1, respectively. In which, corresponding to the process of the transmission transistor M1 being turned on and then turned off, the first selection transistor M60 is turned off and then turned on; corresponding to the process of the first quantization transistor M30 being turned on and then turned off, the second selection transistor M61 is turned off and then turned on. The relevant timing can be seen in detail. Fig.12 .

[0121] Of course, the second charge signal (i.e., OF_SIG) can also be transferred after the first charge signal (i.e., PD_SIG), for example, the transfer transistor M1 in the photosensitive unit 111 is controlled to be turned on and then turned off, so as to transfer the first charge signal stored in the photosensitive element PD to the main floating diffusion node FD0, and then the first quantization transistor M30 in the overflow unit 112 is controlled to be turned on and then turned off, so as to transfer the second charge signal stored in the first storage device C10 in the overflow unit 112 to the secondary floating diffusion node FD1 through the quantization path; in addition, in the process of controlling the first quantization transistor M30 to be turned on and then turned off, the first overflow transistor M20 can also be controlled to be turned on and then turned off, and the relevant timing can be seen in detail. Fig.13 Further, when the pixel block 110 includes a gain unit 115, the gain unit 115 is controlled to be turned on and then turned off to quantize and read out the first reset signal in different gain modes based on the main floating diffusion node FD0, and the gain unit 115 is controlled to be turned off and then turned on to quantize and read out the first charge signal in different gain modes based on the main floating diffusion node FD0. At this time,

[0122] In the case where the primary floating diffusion node FD0 and the secondary floating diffusion node FD1 belong to the same pixel block 110, the second reset signal is quantized and read out simultaneously with the first reset signal in the low gain mode or the high gain mode, and the second charge signal is quantized and read out simultaneously with the first charge signal in the low gain mode or the high gain mode;

[0123] For the case where the main floating diffusion node FD0 and the secondary floating diffusion node FD1 belong to pixel blocks 110 in different rows in the same column, the second reset signal is quantized and read out simultaneously with the first reset signal in the low gain mode, and the second charge signal is quantized and read out simultaneously with the first charge signal in the low gain mode.

[0124] by Figure 2 The circuit structure shown is taken as an example, and the second reset signal is quantized and read out simultaneously with the first reset signal in the low gain mode, and the second charge signal is quantized and read out simultaneously with the first charge signal in the low gain mode.

[0125] Since the gain transistor M7 in the gain unit 115 is turned on and remains on during the reset phase, the image sensor operates in the low gain mode; first, the first selection transistor M60 in the first readout unit 114a and the second selection transistor M61 in the second readout unit 114b are controlled to be turned on, so as to simultaneously perform quantization reading of the first reset signal (i.e., LCG_RST) and the second reset signal (i.e., OF_RST) in the low gain mode based on the main floating diffusion node FD0 and the secondary floating diffusion node FD1, respectively; then, the gain transistor M7 is controlled to be turned off, so that the image sensor switches to the high gain mode, so as to perform quantization reading of the first reset signal (i.e., HCG_RST) in the high gain mode based on the main floating diffusion node FD0; and the transmission transistor M1 in the photosensitive unit 111 is controlled to be turned on and then turned off, so as to transfer the first electric current stored in the photosensitive element PD to the photosensitive element PD. The charge signal is transferred to the main floating diffusion node FD0, so as to quantize and read out the first charge signal (i.e., HCG_SIG) in the high gain mode based on the main floating diffusion node FD0; then the gain transistor M7 is controlled to be turned on, so that the image sensor switches to the low gain mode again, and the transfer transistor M1 is controlled to be turned on and then turned off, so as to transfer the first charge signal stored in the photosensitive element PD to the main floating diffusion node FD0. At the same time, the first quantization transistor M30 in the overflow unit 112 is controlled to be turned on and then turned off, and the second charge signal stored in the first storage device C10 in the overflow unit 112 is transferred to the secondary floating diffusion node FD1 through the quantization path, so as to quantize and read out the first charge signal (i.e., LCG_SIG) and the second charge signal (i.e., OF_SIG) in the low gain mode based on the main floating diffusion node FD0 and the secondary floating diffusion node FD1 respectively. Optionally, in the process of the transmission transistor M1 being turned on and then turned off, the first selection transistor M60 is turned off and then turned on; in the process of the first quantization transistor M30 being turned on and then turned off, the second selection transistor M61 is turned off and then turned on; in order to simplify the control, the gates of the first selection transistor M60 and the second selection transistor M61 can be connected to the same control signal. The relevant timing can be seen in detail. Fig.14 .

[0126] In another implementation, the quantization stage only performs correlated double sampling on the first charge signal, and performs non-true correlated double sampling on the second charge signal.

[0127] Specifically, it includes: closing the overflow path to quantize and read out the first reset signal based on the main floating diffusion node FD0, opening the quantization path to simultaneously quantize and read out the first charge signal and the second charge signal based on the main floating diffusion node FD0 and the secondary floating diffusion node FD1, respectively, closing the quantization path, performing a secondary reset operation on the secondary floating diffusion node FD1, and quantizing and reading out the second reset signal based on the secondary floating diffusion node FD1.

[0128] by Figure 1 Taking the circuit structure shown in FIG. 1 as an example, since the first overflow transistor M20 in the overflow unit 112 is turned off during the exposure phase, the overflow path is turned off; first, the first selection transistor M60 in the first readout unit 114a and the second selection transistor M61 in the second readout unit 114b are controlled to be turned on, so as to perform quantization reading of the first reset signal (i.e., PD_RST) based on the main floating diffusion node FD0; then, the transfer transistor M1 in the photosensitive unit 111 is controlled to be turned on and then turned off, so as to transfer the first charge signal stored in the photosensitive element PD to the main floating diffusion node FD0, and at the same time, the first quantization transistor M60 in the overflow unit 112 is controlled to be turned on and then turned off. The body transistor M30 is turned on, and the second charge signal stored in the first storage device C10 in the overflow unit 112 is transferred to the secondary floating diffusion node FD1 through the quantization path, so as to simultaneously perform quantization reading of the first charge signal (i.e., PD_SIG) and the second charge signal (i.e., OF_SIG) based on the main floating diffusion node FD0 and the secondary floating diffusion node FD1; and the second reset transistor M41 in the second reset unit 113b is controlled to be turned on and then turned off, and a secondary reset operation is performed on the secondary floating diffusion node FD1, so as to perform quantization reading of the second reset signal (i.e., OF_RST) based on the secondary floating diffusion node FD1. In which, corresponding to the process of turning on and then turning off the transmission transistor M1, the first selection transistor M60 is turned off and then turned on; in the process of quantization reading of the second reset signal based on the secondary reset operation, the process of turning on and then turning off the second reset transistor M41 corresponds to the operation of turning off and then turning on the second selection transistor M61, wherein the second reset transistor M41 is turned off during the turning-off period of the second selection transistor M61, and the relevant timing can be seen in detail. Fig.15 .

[0129] Of course, the second charge signal (i.e., OF_SIG) can also be transferred after the first charge signal (i.e., PD_SIG), for example, the transfer transistor M1 in the photosensitive unit 111 is controlled to be turned on and then turned off, so as to transfer the first charge signal stored in the photosensitive element PD to the main floating diffusion node FD0, and then the first quantization transistor M30 in the overflow unit 112 is controlled to be turned on, and the second charge signal stored in the first storage device C10 in the overflow unit 112 is transferred to the secondary floating diffusion node FD1 through the quantization path; in addition, in the process of controlling the first quantization transistor M30 to be turned on, the first overflow transistor M20 can also be controlled to be turned on and then turned off, and the relevant timing can be seen in detail. Fig.16 .

[0130] Further, when the pixel block 110 includes the gain unit 115, the gain unit 115 is controlled to be turned on and then turned off to quantize and read out the first reset signal in different gain modes based on the main floating diffusion node FD0, and the gain unit 115 is controlled to be turned off and then turned on to quantize and read out the first charge signal in different gain modes based on the main floating diffusion node FD1. At this time,

[0131] In the case where the primary floating diffusion node FD0 and the secondary floating diffusion node FD1 belong to the same pixel block 110, the second charge signal is quantized and read out simultaneously with the first charge signal in the low gain mode or the high gain mode;

[0132] In the case where the primary floating diffusion node FD0 and the secondary floating diffusion node FD1 belong to the pixel blocks 110 in different rows in the same column, the second charge signal is quantized and read out simultaneously with the first charge signal in the low gain mode.

[0133] by Figure 2 The circuit structure shown is taken as an example, and the second charge signal is quantized and read out simultaneously with the first charge signal in the low gain mode.

[0134] Since the gain transistor M7 in the gain unit 115 is turned on and remains on during the reset phase, the image sensor operates in the low gain mode; first, the first selection transistor M60 in the first readout unit 114a and the second selection transistor M61 in the second readout unit 114b are controlled to be turned on, so as to quantize and read out the first reset signal (i.e., LCG_RST) in the low gain mode based on the main floating diffusion node FD0; then, the gain transistor M7 is controlled to be turned off, so that the image sensor switches to the high gain mode, so as to quantize and read out the first reset signal (i.e., HCG_RST) in the high gain mode based on the main floating diffusion node FD0; and the transfer transistor M1 in the photosensitive unit 111 is controlled to be turned on and then turned off, so as to transfer the first charge signal stored in the photosensitive element PD to the main floating diffusion node FD0, so as to quantize the first charge signal (i.e., HCG_SIG) in the high gain mode based on the main floating diffusion node FD0. Read out; then control the gain transistor M7 to turn on, so that the image sensor switches to the low gain mode again, control the transfer transistor M1 to turn on and then turn off, and transfer the first charge signal stored in the photosensitive element PD to the main floating diffusion node FD0. At the same time, control the first quantization transistor M30 in the overflow unit 112 to turn on, and transfer the second charge signal stored in the first storage device C10 in the overflow unit 112 to the secondary floating diffusion node FD1 through the quantization path, so as to simultaneously perform quantization readout of the first charge signal (i.e., LCG_SIG) and the second charge signal (i.e., OF_SIG) in the low gain mode based on the main floating diffusion node FD0 and the secondary floating diffusion node FD1; and control the second reset transistor M41 in the second reset unit 113b to turn on and then turn off, and perform a secondary reset operation on the secondary floating diffusion node FD1, so as to perform quantization readout of the second reset signal (i.e., OF_RST) based on the secondary floating diffusion node FD1. Optionally, in the process of the transmission transistor M1 being turned on and then turned off, the first selection transistor M60 is turned off and then turned on; in the process of quantizing and reading out the second reset signal based on the secondary reset operation, the process of the second reset transistor M41 being turned on and then turned off corresponds to the operation of the second selection transistor M61 being turned off and then turned on, wherein the second reset transistor M41 is turned off during the period when the second selection transistor M61 is turned off. The relevant timing can be seen in detail. Fig.17 .

[0135] It should be noted that other circuit structures are Figure 1 and Figure 3The main control method of the circuit structure shown is the same, but the control of each transistor is slightly different, but this does not affect the pixel blocks of other circuit structures to achieve related functions. In addition, the quantization readout of each signal of the utility model is more flexible. For example, if the second charge signal and the first charge signal in the low gain mode cannot be quantized and read out at the same time, the second charge signal and the first charge signal in the high gain mode can be quantized and read out at the same time, and the same is true for the related reset signal.

[0136] In summary, the image sensor of the utility model for improving signal readout realizes simultaneous quantitative readout of at least one of the first charge signal and its corresponding first reset signal and at least one of the second charge signal and its corresponding second reset signal based on the primary floating diffusion node and the secondary floating diffusion node by designing two floating diffusion nodes in one pixel block or sharing floating diffusion nodes through different rows of pixel blocks, thereby improving the signal quantization readout speed. Therefore, the utility model effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0137] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

1. An image sensor with improved signal readout, characterized in that It comprises a plurality of pixel blocks arranged in an array, wherein the pixel blocks comprise a photosensitive unit and an overflow unit; The photosensitive unit generates a first charge signal and a second charge signal based on photoelectric conversion, stores the first charge signal, and transfers the first charge signal to the main floating diffusion node; The overflow unit includes an overflow path and a quantization path, the second charge signal is stored in the overflow unit through the overflow path, and is transferred to the secondary floating diffusion node through the quantization path; Among them, the first charge signal and at least one of its corresponding first reset signals and the second charge signal and at least one of its corresponding second reset signals are quantized and read out based on the main floating diffusion node and the secondary floating diffusion node respectively to adjust and improve the readout of the actual image signal.

2. The image sensor with improved signal readout according to claim 1, characterized in that The primary floating diffusion node and the secondary floating diffusion node belong to the same pixel block, and the pixel block further includes a first reset unit, a second reset unit, a first readout unit, and a second readout unit; The first reset unit is coupled to the main floating diffusion node and is used to reset at least one of the main floating diffusion node and the photosensitive unit; The second reset unit is coupled to the secondary floating diffusion node and is used to reset at least the secondary floating diffusion node; The first readout unit is coupled to the main floating diffusion node and is used to perform quantized readout of at least the first charge signal transferred to the main floating diffusion node; The second readout unit is coupled to the secondary floating diffusion node and is used to perform quantized readout of at least the second charge signal transferred to the secondary floating diffusion node; The first reset unit and / or the second reset unit are also used to reset the overflow unit, and the first readout unit and the second readout unit perform quantized readout through different column lines.

3. The image sensor with improved signal readout according to claim 1, characterized in that: The primary floating diffusion node and the secondary floating diffusion node belong to the pixel block in different rows in the same column, and the pixel block further includes a third resetting unit and a third readout unit; The third reset unit is coupled to the corresponding floating diffusion node and is used to reset at least one of the corresponding floating diffusion node, the photosensitive unit and the overflow unit; The third readout unit is coupled to the corresponding floating diffusion node and is used to at least quantize and read out the corresponding charge signal transferred to the corresponding floating diffusion node; The third readout unit in the pixel block corresponding to the primary floating diffusion node and the third readout unit in the pixel block corresponding to the secondary floating diffusion node perform quantized readout through different column lines.

4. The image sensor with improved signal readout according to claim 1, characterized in that: The pixel blocks in different rows in the same column include the pixel blocks in two adjacent rows in the same column, wherein, in the pixel blocks in two adjacent rows in the same column, the floating diffusion nodes corresponding to the pixel blocks in the next row always serve as the sub-floating diffusion nodes of the pixel blocks in the previous row, or the floating diffusion nodes corresponding to the pixel blocks in the previous row always serve as the sub-floating diffusion nodes of the pixel blocks in the next row; or, the floating diffusion nodes corresponding to the pixel blocks in two rows are each other's sub-floating diffusion nodes.

5. The image sensor with improved signal readout according to any one of claims 1 to 4, characterized in that: The overflow unit includes a first overflow transistor, a first quantization transistor and a first storage device; the control end of the first overflow transistor receives a first overflow control signal, the first end is coupled to the photosensitive unit, and the second end is coupled to the first end of the first storage device; the control end of the first quantization transistor receives a first quantization control signal, the first end is coupled to the secondary floating diffusion node, and the second end is coupled to the first end of the first storage device; the second end of the first storage device is coupled to a reference potential; wherein the path where the first overflow transistor is located is the overflow path, and the path where the first quantization transistor is located is the quantization path; or, when the main floating diffusion node and the secondary floating diffusion node belong to the same pixel block, the overflow unit removes the first quantization transistor, at which time, the second end of the first overflow transistor is coupled to the first end of the first storage device and is also coupled to the secondary floating diffusion node, the path where the first overflow transistor is located is the overflow path, and the path from the first end of the first storage device to the secondary floating diffusion node is the quantization path.

6. The image sensor with improved signal readout according to claim 5, characterized in that The pixel block also includes a gain unit, coupled between the corresponding reset unit and the corresponding floating diffusion node, for switching between different gain modes; wherein, when the main floating diffusion node and the secondary floating diffusion node belong to the pixel blocks in different rows in the same column, the first end of the first quantization transistor is directly coupled to the secondary floating diffusion node or coupled to the secondary floating diffusion node through the gain unit corresponding to the secondary floating diffusion node.

7. The image sensor with improved signal readout according to claim 3, characterized in that: When the primary floating diffusion node and the secondary floating diffusion node belong to the pixel blocks in different rows in the same column, the overflow unit includes a second overflow transistor, a second quantization transistor, a second storage device and a first shared transistor; the control end of the second overflow transistor receives a second overflow control signal, the first end is coupled to the photosensitive unit, and the second end is coupled to the first end of the second storage device; the control end of the second quantization transistor receives a second quantization control signal, the first end is coupled to the primary floating diffusion node, and the second end is coupled to the first end of the second storage device; the second end of the second storage device is coupled to a reference potential; The control terminal of the first sharing transistor receives a first sharing control signal, the first terminal is coupled to the secondary floating diffusion node, and the second terminal is coupled to the first terminal of the second storage device or the first terminal of the second quantization transistor; wherein the path where the second overflow transistor is located is the overflow path, and the path where the first sharing transistor is located is the quantization path; When the floating diffusion nodes corresponding to the two rows of pixel blocks are each other's secondary floating diffusion nodes, the first shared transistor of the overflow unit of the next row of pixel blocks in the two rows of pixel blocks is removed.

8. The image sensor with improved signal readout according to claim 3, characterized in that: When the primary floating diffusion node and the secondary floating diffusion node belong to the pixel blocks in different rows in the same column, the overflow unit includes a third overflow transistor, a third quantization transistor, a third storage device and a second shared transistor; the control end of the third overflow transistor receives a third overflow control signal, the first end is coupled to the photosensitive unit, and the second end is coupled to the first end of the third storage device; the control end of the third quantization transistor receives a third quantization control signal, the first end is coupled to the primary floating diffusion node and to the secondary floating diffusion node through the second shared transistor, and the second end is coupled to the first end of the third storage device; the second end of the third storage device is coupled to a reference potential; The control terminal of the second sharing transistor receives a second sharing control signal; wherein the path where the third overflow transistor is located is the overflow path, and the path where the third quantization transistor is located is the quantization path; When the floating diffusion nodes corresponding to two rows of pixel blocks are each other's secondary floating diffusion nodes, the first end of the third quantization transistor of the overflow unit of the next row of pixel blocks in the two rows of pixel blocks is no longer coupled to the corresponding floating diffusion node of the next row of pixel blocks.

9. The image sensor with improved signal readout according to claim 7 or 8, characterized in that: The pixel block also includes a gain unit, coupled between the third reset unit and the corresponding floating diffusion node, for switching between different gain modes; wherein, when the overflow unit includes a first shared transistor, the first end of the first shared transistor is coupled to the secondary floating diffusion node through the gain unit corresponding to the secondary floating diffusion node; when the overflow unit includes a second shared transistor, the first end of the third quantization transistor is coupled to the secondary floating diffusion node through the second shared transistor and the gain unit in the overflow unit corresponding to the secondary floating diffusion node.

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