Display panel and display device
By optimizing the GOA layout in the rounded corner area of the display panel and increasing the width of the VSS area, the problem of excessive current caused by too narrow VSS traces in the narrow border display panel is solved, and the reliability of the display panel is improved.
Patent Information
- Application Number
- CN202323490450.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-20
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2033-12-20
AI Technical Summary
In the design of a narrow bezel display screen, the VSS trace in the rounded corner area is too narrow and causes too much current, which may cause adverse problems such as burns.
By optimizing the drive control unit (GOA) layout in the rounded corner area of the display panel, omitting the last row of the GOA part of the effective shift register unit and replacing it with the partial effective shift register unit in the last row of the effective GOA, increasing the circle VSS area width of corner part.
It effectively solves the problem of excessive current caused by too narrow VSS trace, avoids adverse phenomena such as burns, and improves the reliability of the display panel.
Smart Images
Figure CN222213623U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art
[0002] As consumers demand a larger screen-to-body ratio, narrow-border screens are becoming the mainstream of market development. However, as the border becomes narrower, the requirements for the drive control unit (GOA) and the optimization of the spatial layout of the GOA become higher and higher during the design process. Utility Model Content
[0003] In view of this, an object of the present application is to provide a display panel and a display device.
[0004] Based on the above purpose, the present application provides a display panel, comprising: a display area; and a peripheral area arranged at the periphery of the display area;
[0005] The peripheral area includes a plurality of rounded corner areas; the rounded corner areas are provided with a plurality of effective shift registers arranged in sequence, and a first virtual shift register arranged before the last effective shift register; the first virtual shift register is used to connect the effective shift registers of adjacent stages and to arrange the effective shift registers of adjacent stages in parallel and in correspondence; each effective shift register includes a first number of effective shift register units; the first virtual shift register includes a first number of virtual shift register units;
[0006] Among them, in the rounded corner area of at least one of the peripheral areas, a second number of valid shift register units are missing on the side of the last-level valid shift register away from the display area; a second number of virtual shift register units are missing on the side of the first virtual shift register away from the display area, and include a second number of valid shift register units; the second number is less than the first number; the second number of valid shift register units in the first virtual shift register are connected to the remaining valid shift register units in the last-level valid shift register.
[0007] In some embodiments, the missing of the second number of valid shift register units is the missing of one valid shift register unit; the missing of the second number of dummy shift register units is the missing of one dummy shift register unit.
[0008] In some embodiments, the missing second number of valid shift register units is the missing of multiple valid shift register units; the missing second number of dummy shift register units is the missing of multiple dummy shift register units;
[0009] The arrangement of the second number of valid shift register units included in the first virtual shift register is the same as the arrangement of the second number of valid shift register units on the side away from the display area in the valid shift registers except the last stage valid shift register.
[0010] In some of the embodiments, the last stage effective shift register only includes effective shift register units close to one side of the display area and connected to the gate lines of the display area.
[0011] In some embodiments, the structure of the second number of valid shift register units included in the first virtual shift register is the same as the structure of the second number of valid shift register units on a side away from the display area in the valid shift registers except the last stage valid shift register.
[0012] In some embodiments, the output end of the effective shift register unit in the first virtual shift register is connected to the gate line jumper of the display area.
[0013] In some embodiments, the first number is three, four or five; and the multi-stage effective shift register is used to drive multiple rows of pixels respectively.
[0014] In some embodiments, the first number is four, and the number of pixel rows driven by the remaining valid shift register units in the last stage of valid shift register is less than the number of pixel rows driven by the missing second number of valid shift register units.
[0015] In some embodiments, the rounded corner area of the peripheral area further includes at least one second virtual shift register, and the second virtual shift register is alternately arranged with a preset number of effective shift registers so that multiple stages of effective shift registers are arranged in parallel and correspondingly.
[0016] In some embodiments, the second virtual shift register and the first virtual shift register are arranged adjacent to each other and are arranged alternately with two stages of effective shift registers.
[0017] In some of the embodiments, the rounded corner area of at least one of the peripheral areas includes a plurality of rounded corner areas.
[0018] In some of the embodiments, in the plurality of rounded corner areas, the number of the missing second number of valid shift register units in the last stage of valid shift register on the side away from the display area is the same.
[0019] In some of the embodiments, in the plurality of rounded corner areas, the number of the second number of valid shift register units missing on the side of the last stage of valid shift register away from the display area is different.
[0020] Some of the embodiments further include data routing lines, and part of the data routing lines are arranged in a region between an end of the last-stage effective shift register away from the display area and a border of the peripheral region away from the display area.
[0021] An embodiment of the present application also provides a display device, comprising a display panel as shown in any of the preceding items.
[0022] As can be seen from the above, the display panel provided by the present application comprises: a display area; and a peripheral area arranged outside the display area; wherein the peripheral area comprises a plurality of rounded corner areas; the rounded corner areas are provided with a plurality of stages of effective shift registers arranged in sequence, and a first virtual shift register arranged before the last stage of effective shift register; the first virtual shift register is used to connect the effective shift registers of adjacent stages and to arrange the effective shift registers of adjacent stages in parallel and in correspondence; each stage of effective shift registers comprises a first number of effective shift register units; the first virtual shift register comprises a first number of virtual shift register units; wherein, in at least one of the In the rounded corner area of the peripheral area, a second number of valid shift register units are missing on a side of the last-level valid shift register away from the display area; a second number of virtual shift register units are missing on a side of the first virtual shift register away from the display area, and include a second number of valid shift register units; the second number is less than the first number; the second number of valid shift register units in the first virtual shift register are connected to the remaining valid shift register units in the last-level valid shift register, thereby increasing the width of the VSS area of the rounded corner part, and to a certain extent solving the problem of excessive current caused by the narrowness of some VSS lines, resulting in burns and other adverse problems. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0024] Figure 1 A schematic diagram of the regional distribution of an exemplary display panel according to an embodiment of the present application;
[0025] Figure 2 A schematic diagram of an exemplary display area of an embodiment of the present application;
[0026] Figure 3 It is another schematic diagram of area distribution of an exemplary display panel according to an embodiment of the present application;
[0027] Figure 4a A schematic diagram of an exemplary effective shift register and a virtual shift register alternately arranged in an embodiment of the present application;
[0028] Figure 4b Another schematic diagram of an exemplary effective shift register and a virtual shift register alternately arranged in an embodiment of the present application;
[0029] Figure 4c Another schematic diagram of an exemplary effective shift register and a virtual shift register alternately arranged in an embodiment of the present application;
[0030] Figure 4d It is a schematic diagram of an exemplary embodiment of the present application in which effective shift registers and virtual shift registers with no missing effective shift register units are alternately arranged;
[0031] Figure 5a A schematic diagram of an exemplary valid shift register according to an embodiment of the present application in which a second number of valid shift register units are not missing;
[0032] Figure 5b A schematic diagram of an exemplary valid shift register missing a second number of valid shift register units according to an embodiment of the present application;
[0033] Figure 5c The present invention is another schematic diagram of an exemplary valid shift register missing a second number of valid shift register units according to an embodiment of the present application. DETAILED DESCRIPTION
[0034] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.
[0035] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0036] As people's requirements for display screens become higher and higher, such as requiring a larger screen-to-body ratio, the development trend of displays such as mobile phones is to require an increasingly larger display area ratio, so the borders of mobile phones tend to be gradually narrowed. At the same time, in order to meet higher requirements for the display effect, refresh rate and contrast of the display screen, the structure of the drive control circuit (GateDriver on Array, GOA) has become more and more complex, and will take up more space in the layout. In the related art, due to the small space at the rounded corners of the frame, the remaining VSS power line routing space after the GOA layout is completed may often be too narrow, resulting in the VSS routing width being too small. After the process is completed, the VSS routing part in the rounded corner area will have too much current, resulting in burns and other adverse problems.
[0037] Based on this, an embodiment of the present application provides a display panel, which optimizes the GOA arrangement in the rounded corner area, omits some EM GOA units in the last row of valid GOA in the GOA, and replaces some EM GOA units in the dummy GOA before the last row of valid GOA in the GOA unit with some EM GOA units omitted in the last row of valid GOA. The layout and arrangement of some GOAs can be optimized, thereby increasing the width of the VSS area in the rounded corner part, and to a certain extent solving the problem of excessive current caused by the narrowness of some VSS lines, resulting in burns and other adverse problems.
[0038] Figures 1 to 3 A schematic structural diagram of an exemplary display panel according to an embodiment of the present application is shown.
[0039] like Figure 1 As shown, the embodiment of the present application can be as follows Figure 1 As shown, the display panel 100 includes: a display area 11 (active area, AA; referred to as AA area; also referred to as effective display area 11) and a peripheral area 12 arranged around the display area 11. The display panel can be an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diode (Micro LED) display panel, etc., and the utility model does not make specific limitations on this. In some embodiments, the display panel can be a flexible display panel.
[0040] The following embodiments are described by taking a display panel that is a flexible organic light emitting diode display panel as an example.
[0041] like Figure 2 As shown, the display area 11 is an area corresponding to the pixel array, and may further include a plurality of pixel areas 111 arranged in an array, and the pixel area 111 may further include a plurality of sub-pixels 112. It should be noted that: Figure 2 The relative position relationship of the sub-pixels 112 in the pixel area 111 and the arrangement of the pixel area 111 in the display area 1110 are only illustrated for exemplary purposes. It can be understood that in actual products, the arrangement of the sub-pixels 112 and the size and arrangement of the pixel area 111 can be adjusted according to actual needs.
[0042] In some embodiments, the pixel area 111 may include a plurality of sub-pixels 112, for example, three sub-pixels 112. The three sub-pixels 112 may further include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that the pixel area 111 may achieve full-color display under the drive of the pixel circuit. It is understood that in order to achieve different effects or functions, the number and color of the sub-pixels 112 in the pixel area 111 can be selected by those skilled in the art, and are not limited to the examples given herein.
[0043] In some embodiments, the display area 11 may further include a plurality of gate lines and a plurality of data lines arranged in a cross pattern, wherein the gate lines are used to provide a start signal, and the data lines are used to provide a data signal, so that the pixel circuit can use the data signal to drive the sub-pixel 112. A gate driving circuit 121 connected to the gate lines and a data driving circuit connected to the data lines may be provided in the peripheral area 12.
[0044] In some embodiments, the gate driving circuit 121 may be disposed on a side along the extending direction of the gate line, and the data driving circuit may be disposed on a side along the extending direction of the data line.
[0045] In some embodiments, in order to reduce the manufacturing cost of the display panel and narrow the border width of the display device, the gate driving circuit 121 may be a GOA circuit, that is, the gate driving circuit 121 is directly integrated into the array substrate of the display panel.
[0046] In some embodiments, Figure 3 As shown, the display panel can be provided with GOA circuits on two sides along the extension direction of the gate line in the peripheral area 12, and the gate lines are driven sequentially from both sides row by row through two gate driving circuits 121, that is, the two sides are driven simultaneously. In some other embodiments, the display panel can also be provided with a GOA circuit on only one side along the extension direction of the gate line in the peripheral area 12. Among them, the gate driving circuit 121 may include a multi-stage shift register arranged in sequence.
[0047] Figures 4a to 4dA schematic diagram of multiple cascaded shift registers in the rounded corner area 122 of the peripheral area 12 according to an exemplary embodiment of the present application is shown.
[0048] like Figures 4a to 4c As shown, in some embodiments, in the rounded corner area 122 (such as the upper rounded corner area and the lower rounded corner area, etc.) of the peripheral area 12, a plurality of shift registers cascaded in the first direction may generally be included. The cascaded plurality of shift registers may include: a plurality of stages of valid shift registers 123 arranged in sequence, and a dummy shift register (dummy GOA) arranged alternately with the valid shift registers 123 of a preset order. The dummy shift register may be used to connect the valid shift register 123 disposed adjacent to it, and to fill the gap between the valid shift registers 123 disposed adjacent to it, so that the plurality of stages of valid shift registers 123 in the rounded corner area 122 can be disposed in parallel and correspondingly one by one.
[0049] Among them, the composition and structure of the virtual shift register unit included in each level of the virtual shift register used by the effective shift register 123 can be the same as the composition and structure of the effective shift register unit included in the effective shift register 123, except that each level of the virtual shift register is not connected to the gate line of the display area 11. In addition, there will be a transistor whose signal is interrupted among the multiple transistors in the virtual shift register, so that the virtual shift register only plays the role of connecting the previous level effective shift register 123 and the next level effective shift register 123. Specifically, when patterning is performed using a mask process, the specific pattern of forming the virtual shift register unit can be the same as the specific pattern of forming the effective shift register 123 unit 1231.
[0050] Each level of effective shift register 123 is respectively connected to the gate line of the display area 11. The output signal of the effective shift register 123 of the current level can be output to the effective shift register 123 of the previous level (if any) through the virtual shift register of the previous level (if any) as a reset signal of the effective shift register 123 of the previous level; and can also be output to the effective shift register 123 of the next level (if any) through the virtual shift register of the next level (if any) as an input signal of the effective shift register 123 of the next level. Among them, the input end of the first-stage effective shift register 123 is connected to the start signal end, and the signal input end of any effective shift register 123 except the first-stage effective shift register 123 is connected to the signal output end of the effective shift register 123 at the previous stage through the virtual shift register (if any) or directly (for example, there is no virtual shift register between two adjacent effective shift registers 123); except the last-stage effective shift register 123, the reset signal end of any effective shift register 123 is connected to the signal output end of the effective shift register 123 at the next stage through the virtual shift register (if any) or directly (for example, there is no virtual shift register between two adjacent effective shift registers 123). In some possible embodiments, the reset signal end of the last-stage effective shift register 123 can be connected through a reset control circuit. The reset control circuit can be configured to generate a reset signal of the last-stage effective shift register 123.
[0051] Generally, the virtual shift register and the effective shift register 123 may be arranged alternately in various ways. For example, Figure 4a As shown, two effective shift registers 123 and two virtual shift registers are arranged alternately. For example, Figure 4b As shown, an effective shift register 123 and a virtual shift register are arranged alternately. Or, illustratively, as Figure 4c As shown, two effective shift registers 123 and a virtual shift register are arranged alternately. In a possible implementation, three or more effective shift registers 123 and a virtual shift register may be arranged alternately, etc. Specifically, it can be determined according to the size of the R angle of the rounded corner area 122 and the specific number of transistors and capacitors included in the effective shift register 123, etc., as long as the multi-stage effective shift registers 123 arranged in the rounded corner area 122 can be arranged in parallel and correspondingly.
[0052] In some embodiments, the virtual shift register includes at least a first virtual shift register 124 disposed before the last level of effective shift register 123. The composition and structure of the virtual shift register unit included in the first virtual shift register 124 may be the same as the composition and structure of the effective shift register unit included in the effective shift register 123. In other embodiments, the virtual shift register also includes at least one second virtual shift register 125, and the second virtual shift register 125 is alternately arranged with a preset number of effective shift registers 123, so that multiple levels of effective shift registers 123 are arranged in parallel and correspondingly. Among them, before the next level of effective shift register 123, two levels of virtual shift registers may be included. For example, one level of the second virtual shift register 125 is included, and the first level of the second virtual shift register 125 may be arranged adjacent to the first virtual shift register 124, and alternately arranged with the two levels of effective shift registers 123.
[0053] In some embodiments, the effective shift register 123 may include a plurality of (e.g., a first number of) effective shift register units 1231, and each effective shift register unit 1231 may be connected to different control signal lines. Each effective shift register 123 may be used to drive multiple rows (e.g., two rows) of pixels. The number of effective shift register units included in the effective shift register 123 may be determined according to the type of pixel circuit in the display area 11. Among them, the plurality of effective shift register units may provide different types of start-up signals for the pixel circuits, respectively, and be connected to the gate lines of the display area, respectively. For example, they may be connected to the gate lines of the display area through adapters. For example, for a pixel circuit in which the transistor is a low-temperature polysilicon transistor (LTPSTFT), such as a pixel circuit in which 3T1C (including 3 thin-film transistors TFT and 1 capacitor) is used, each level of effective shift register 123 may include 3 effective shift register units. For example, for a pixel circuit in which the transistor is 7T1C (including 7 thin-film transistors TFT and 1 capacitor), each level of effective shift register 123 may include 4 effective shift register units. For example, for a pixel circuit with 8T2C transistors (including 8 thin film transistors tft and 2 capacitors), each level of effective shift register 123 may include 5 effective shift register units, etc. Correspondingly, the first virtual shift register 124 may include a plurality of (e.g., a first number) virtual shift register units. For example, it may include 3 virtual shift register units, 4 virtual shift register units, or 5 virtual shift register units, etc. The specific setting may be based on different project requirements.
[0054] In some of the embodiments, in at least one of the rounded corner areas 122 of the peripheral area 12, the side of the last effective shift register 123 away from the display area 11 lacks a second number of effective shift register units 1232; the side of the first virtual shift register 124 away from the display area 11 lacks a second number of virtual shift register units 1242, and includes a second number of effective shift register units 1232; the second number is less than the first number; the second number of effective shift register units 1232 in the first virtual shift register 124 is connected to the remaining effective shift register units 1231 in the last effective shift register. In this way, the width of the area between the end of the last effective shift register 123 (i.e., the end away from the display area 11) and the border of the peripheral area 12 away from the display area 11 can be increased (for example, from Figure 4d to Figure 4a ), thereby increasing the width of the data routing (eg, vss routing) arranged in this area.
[0055] In some of the embodiments, the structure of the second number of valid shift register units 1232 included in the first virtual shift register 124 can be the same as the structure of the second number of valid shift register units 1232 on the side away from the display area 11 in the valid shift register 123 except the last stage valid shift register 123, and the same pattern can be used as the valid shift register 123 during manufacturing to simplify the manufacturing process.
[0056] Among them, the remaining valid 1231 shift register units in the last level valid shift register 123 are used to connect the gate line of the display area 11, and the specific number of the second number of valid shift register units 1232 missing in the last level valid shift register 123 can be set according to specific needs. The specific number of the second number of valid shift register units 1232 missing in the last level valid shift register 123 has a lower limit of one and an upper limit of all valid shift register units contained in the valid shift register 123 except the valid shift register unit 1231 connected to the gate line arranged on the side close to the display area 11. It can be determined specifically according to project requirements.
[0057] In some embodiments, for example Figure 5bAs shown, the missing second number of valid shift register units is the missing of one valid shift register unit 1232; the missing second number of virtual shift register units is the missing of one virtual shift register unit 1242. One valid shift register unit 1232 in the first virtual shift register 124 is connected (e.g., connected in parallel) to the remaining valid shift register units 1231 in the last stage of valid shift register 123. In this way, it is convenient to connect the first virtual shift register 124 with the last stage of valid shift register 123.
[0058] In some other embodiments, for example Figure 5c As shown, the missing second number of valid shift register 123 units is the missing of multiple valid shift register units 1232; the missing second number of virtual shift register units is the missing of multiple virtual shift register units 1242; wherein the arrangement of the second number of valid shift register units 1232 included in the first virtual shift register 124 is the same as the arrangement of the second number of valid shift register units 1232 on the side away from the display area 11 in the valid shift registers other than the last level of valid shift register 123. The multiple valid shift register units 1232 in the first virtual shift register 124 are connected (for example, connected in parallel) to the remaining valid shift register units 1231 in the last level of valid shift register 123. In this way, the width of the area between the end of the last level of valid shift register 123 (that is, the end away from the display area 11) and the frame of the peripheral area 12 away from the display area 11 can be further increased, thereby increasing the width of the data routing (for example, vss routing) set in this area.
[0059] Furthermore, the last effective shift register 123 only includes a third number (e.g., two) of effective shift register units 1231 close to one side of the display area and connected to the gate line of the display area 11. In this way, the width of the area between the end of the last effective shift register 123 (i.e., the end away from the display area 11) and the frame of the peripheral area 12 away from the display area 11 can be maximized, thereby increasing the width of the data routing (e.g., vss routing) arranged in the area.
[0060] The effective shift register 123 includes 4 effective shift register units and the first virtual shift register 124 includes 4 virtual shift register units. Figure 5aAs shown, before the second number of valid shift register units 1232 are missing, the valid shift register 123 may include 4 valid shift register units, and the two valid shift register units 1241 close to the display area 11 are respectively used to connect to the gate line of the display area 11, and can be connected to the clock signal line PCB and the clock signal line PCK respectively, and are respectively used to drive a row of pixels in a one-to-one correspondence. The two valid shift register units 1232 far away from the display area 11 can be connected to the clock signal line CB and the clock signal line CK respectively, and are respectively used to drive two rows of pixels in a one-to-one correspondence. That is, the first number is four, and the number of pixel rows driven by the remaining valid shift register units 1231 in the last stage of the valid shift register 123 is less than the number of pixel rows driven by the missing second number of valid shift register units 1232. The number of pixel rows driven by the remaining valid shift register units 1231 in the last stage of the valid shift register 123 can be one row, and the number of pixel rows driven by the missing second number of valid shift register units 1232 can be two rows.
[0061] Correspondingly, the virtual shift register (e.g., the first virtual shift register 124 or the second virtual shift register 125) may include four virtual shift register units, and the specific structure in each virtual shift register unit (e.g., the first virtual shift register unit 1241 and the second virtual shift register unit 1242) may correspond to the structure in the four effective shift registers 123, and the specific arrangement may also be the same. The specific number of the second number of virtual shift register units 1242 missing in the first virtual shift register 124 is lowered to one (e.g., Figure 5b ), with an upper limit of two (e.g. Figure 5c ), that is, all virtual shift register units 1242 except the virtual shift register unit 1241 arranged on the side close to the display area 11 are missing.
[0062] In some embodiments, the fillet area 122 of at least one of the peripheral areas 12 may include a plurality of fillet areas 122. For example, only the lower fillet area 122 (e.g., at least one of the lower left fillet area 122 and the lower right fillet area 122) may be included. Only the upper fillet area 122 (e.g., at least one of the upper left fillet area 122 and the upper right fillet area 122) may also be included. The lower fillet area 122 (e.g., at least one of the lower left fillet area 122 and the lower right fillet area 122) and the upper fillet area 122 (e.g., at least one of the upper left fillet area 122 and the upper right fillet area 122) may also be included at the same time. The specific setting can be made according to the actual needs of the project.
[0063] In some embodiments, in the plurality of rounded corner areas 122 , the number of the second number of valid shift register units 1232 missing on the side of the last stage of valid shift register 123 away from the display area 11 may be the same, which can simplify the process.
[0064] In some of the embodiments, in the multiple rounded corner areas 122, the number of the second number of valid shift register units 1232 missing on the side away from the display area 11 in the last level of valid shift register 123 may also be different. In this way, personalized setting requirements can be realized and different requirements of different rounded corner areas 122 domains can be met.
[0065] In some embodiments, the output end of the effective shift register unit 1232 in the first virtual shift register 124 is connected to the gate line jumper 126 of the display area. The jumper 126 can be understood as a connecting line, which is connected to the output end of the effective shift register unit 1232 in the first virtual shift register 124 and the input end of the remaining effective shift register unit 1231 in the last stage of the effective shift register 123. The static electricity caused by the excessive length of the connecting line can be avoided by using the jumper 126 connection method.
[0066] In some embodiments, data routing may also be included, and part of the data routing (such as vss routing) is arranged in the area between the end of the last effective shift register 123 away from the display area 11 and the frame of the peripheral area 12 away from the display area 11. In this way, the width of the area between the end of the last effective shift register 123 (that is, the end away from the display area 11) and the frame of the peripheral area 12 away from the display area 11 can be further increased, thereby increasing the width of the data routing (such as vss routing) arranged in the area, and avoiding burns and other defects caused by the width of the data routing (such as vss routing) being too narrow.
[0067] Based on the same utility model concept, corresponding to any of the above-mentioned embodiments, the present application also provides a display device. The display device may be a television, a mobile phone, a computer, a laptop, a tablet computer, a personal digital assistant (PDA), a car computer, etc. The display device may include a frame, a display panel arranged in the frame, a circuit board, a display driver IC, and other electronic accessories.
[0068] The device of the above embodiment includes the corresponding display panel in any of the above embodiments, and has the beneficial effects of the corresponding display panel embodiment, which will not be described in detail here.
[0069] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.
[0070] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.
[0071] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
[0072] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.
Claims
1. A display panel, characterized in that: include: Display area; and a peripheral area disposed at the periphery of the display area; The peripheral area includes a plurality of rounded corner areas; the rounded corner areas are provided with a plurality of effective shift registers arranged in sequence, and a first virtual shift register arranged before the last effective shift register; the first virtual shift register is used to connect the effective shift registers of adjacent stages and to arrange the effective shift registers of adjacent stages in parallel and in correspondence; each effective shift register includes a first number of effective shift register units; the first virtual shift register includes a first number of virtual shift register units; Among them, in the rounded corner area of at least one of the peripheral areas, a second number of valid shift register units are missing on the side of the last-level valid shift register away from the display area; a second number of virtual shift register units are missing on the side of the first virtual shift register away from the display area, and include a second number of valid shift register units; the second number is less than the first number; the second number of valid shift register units in the first virtual shift register are connected to the remaining valid shift register units in the last-level valid shift register.
2. The display panel according to claim 1, characterized in that: The missing of the second number of valid shift register units is the missing of one valid shift register unit; the missing of the second number of virtual shift register units is the missing of one virtual shift register unit.
3. The display panel according to claim 1, characterized in that: The missing of the second number of valid shift register units is the missing of a plurality of valid shift register units; the missing of the second number of dummy shift register units is the missing of a plurality of dummy shift register units; The arrangement of the second number of valid shift register units included in the first virtual shift register is the same as the arrangement of the second number of valid shift register units on the side away from the display area in the valid shift registers except the last stage valid shift register.
4. The display panel according to claim 2 or 3, characterized in that: The last stage effective shift register only includes effective shift register units close to one side of the display area and connected to the gate lines of the display area.
5. The display panel according to claim 1, characterized in that: The structure of the second number of effective shift register units included in the first virtual shift register is the same as the structure of the second number of effective shift register units on a side away from the display area in the effective shift registers except the last stage effective shift register.
6. The display panel according to claim 4, characterized in that: The output end of the effective shift register unit in the first virtual shift register is connected to the gate line jumper of the display area.
7. The display panel according to claim 1, characterized in that: The first number is three, four or five; the multi-stage effective shift register is used to drive multiple rows of pixels respectively.
8. The display panel according to claim 7, characterized in that: The first number is four, and the number of pixel rows driven by the remaining valid shift register units in the last stage of valid shift register is less than the number of pixel rows driven by the missing second number of valid shift register units.
9. The display panel according to claim 1, characterized in that: The rounded corner area of the peripheral area also includes at least one second virtual shift register, and the second virtual shift register is alternately arranged with a preset number of effective shift registers, so that multiple stages of effective shift registers are arranged in parallel and correspondingly.
10. The display panel according to claim 9, characterized in that: The second virtual shift register is arranged adjacent to the first virtual shift register and is arranged alternately with the two-stage effective shift register.
11. The display panel according to claim 1, characterized in that: The rounded corner area of the at least one peripheral area includes a plurality of rounded corner areas.
12. The display panel according to claim 11, characterized in that: In the plurality of rounded corner areas, the number of the missing second number of valid shift register units in the last stage of valid shift register on the side away from the display area is the same.
13. The display panel according to claim 11, characterized in that: In the plurality of rounded corner areas, the number of the missing second number of valid shift register units on the side away from the display area in the last stage of valid shift register is different.
14. The display panel according to claim 1, characterized in that: It also includes data routing lines, and part of the data routing lines are arranged in a region between an end of the last-stage effective shift register away from the display region and a frame of the peripheral region away from the display region.
15. A display device, comprising the display panel as claimed in any one of claims 1 to 14.