Chip anti-interference structure
The chip anti-interference structure addresses deformation and parasitic photosensitivity issues by adding a non-transparent covering layer to increase thickness and isolate non-photosensitive areas, enhancing strength and signal stability.
Patent Information
- Application Number
- CN202421026559.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-11
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2034-05-11
AI Technical Summary
Chips are prone to deformation, cracking, and parasitic photosensitivity due to thin thickness and CMOS process limitations, leading to reduced strength and signal interference.
A chip anti-interference structure with a covering layer made of non-transparent material covering the non-photosensitive area, isolating it from ambient light and increasing chip thickness, while incorporating a through hole and adhesive layer for connection.
Enhances chip strength and reduces parasitic photosensitivity, improving signal quality and performance stability by blocking unnecessary electron generation and noise interference.
Smart Images
Figure CN222214186U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chips, in particular to a chip anti-interference structure. Background Art
[0002] After the chip is produced by photolithography, due to the limitations of the process and wafer materials, the thickness of the chip is relatively thin, generally 80um, which makes the physical strength of the chip itself insufficient. Therefore, the chip is prone to deformation or cracking when subjected to external pressure or stress caused by thermal expansion and contraction of the material due to temperature changes, increasing the risk of chip damage during the process of chip use, transportation and storage.
[0003] Secondly, the chip is usually divided into two areas. There is a pixel photosensitive area in the center of the chip, which is used to receive light and generate electrons. Around the photosensitive area are the chip's digital analog circuits and the chip's pins. In theory, photons will only be absorbed by the pixels in the photosensitive area, but when photons hit the surrounding areas of the photosensitive area, due to the CMOS process technology used in the entire chip and the strong penetration of near-infrared light in CMOS semiconductor materials, the CMOS digital analog circuit area with the same material around the photosensitive area will also absorb photons, and then generate electrons at the bottom of the chip, which may flow to the photosensitive area. This phenomenon is called parasitic photosensitivity (PLS). The parasitic photosensitivity phenomenon will introduce interference to the device and generate erroneous electronic noise, thereby affecting the signal quality and performance stability of the device. Utility Model Content
[0004] The purpose of the utility model is to provide a chip anti-interference structure to solve the problems raised in the above background technology.
[0005] To achieve the above-mentioned purpose, the utility model provides the following technical solutions: a chip anti-interference structure, suitable for a chip body, the chip body is provided with a photosensitive area, a covering layer is provided on the chip body, the covering layer is located around the photosensitive area, and is used to cover the non-photosensitive area of the chip body.
[0006] Preferably, the covering layer is made of non-transparent material.
[0007] Preferably, the cover layer has a through hole, and the photosensitive area is located in the through hole.
[0008] Preferably, an isolation zone is provided between the inner edge of the through hole and the outer edge of the photosensitive area.
[0009] Preferably, an adhesive layer is provided on the top of the chip body.
[0010] Preferably, the chip body and the cover layer are connected via the adhesive layer.
[0011] Preferably, the adhesive layer and the covering layer have the same shape.
[0012] Preferably, the thickness of the covering layer is 300um to 310um.
[0013] Preferably, a plurality of welding balls are arranged at the bottom of the chip body.
[0014] The chip's anti-interference structure has the following beneficial effects:
[0015] 1. The chip's anti-interference structure sets a covering layer on the chip body, which greatly increases the thickness of the entire chip, thereby effectively increasing the overall strength of the chip.
[0016] 2. The chip has an anti-interference structure. The digital and analog circuits on the non-photosensitive area of the chip body are blocked by a covering layer. The covering layer isolates the non-photosensitive area of the chip body from the ambient light, reduces the parasitic light sensitivity of the chip body, and prevents the digital and analog circuits from being interfered with and generating erroneous electronic noise, thereby improving the signal quality and performance stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A top view of the chip anti-interference structure provided in an embodiment of the present application;
[0018] Figure 2 A bottom view of the chip anti-interference structure provided in an embodiment of the present application;
[0019] Figure 3 A front view of a chip anti-interference structure provided in an embodiment of the present application;
[0020] Figure 4 A cross-sectional view of the chip anti-interference structure provided in an embodiment of the present application.
[0021] In the figure: 1. chip body; 11. photosensitive area; 2. adhesive layer; 3. cover layer; 31. through hole; 4. solder ball. DETAILED DESCRIPTION
[0022] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0023] like Figure 1-Figure 2As shown, the utility model provides a chip anti-interference structure, which is applicable to a chip body 1. A plurality of welding balls 4 are arranged at the bottom of the chip body 1 for connecting to an external PCB board (not shown in the figure). A photosensitive area 11 is arranged at the chip body 1.
[0024] like Figure 1 , Figure 3 As shown, a covering layer 3 is disposed on the chip body 1, wherein an adhesive layer 2 is disposed on the top of the chip body 1, the chip body 1 and the covering layer 3 are connected via the adhesive layer 2, and the adhesive layer 2 and the covering layer 3 have the same shape.
[0025] Specifically, the covering layer 3 is located around the photosensitive area 11 and is used to cover the non-photosensitive area of the chip body 1. The covering layer 3 is made of non-transparent material, which can absorb natural light and block photons from reaching the non-photosensitive area of the chip body 1. The thickness of the covering layer 3 is 300um~310um. Preferably, the thickness of the covering layer 3 is 305um, while the thickness of the commonly used chip body 1 is 80um, which is relatively thin. Adding a thicker covering layer 3 can greatly increase the overall thickness of the chip, thereby increasing the overall strength of the chip.
[0026] In this embodiment, the digital and analog circuits on the non-photosensitive area of the chip body 1 are blocked by the covering layer 3, and the covering layer 3 isolates the non-photosensitive area of the chip body 1 from the ambient light, so that photons cannot reach the digital and analog circuits in the non-photosensitive area, avoids unnecessary electrons from being generated and flowing into the photosensitive area 11, reduces the parasitic photosensitivity of the chip body 1, and prevents the digital and analog circuits from being interfered with and generating erroneous electronic noise, thereby improving the signal quality and performance stability of the device.
[0027] Further, such as Figure 1 , Figure 4 As shown, the covering layer 3 has a through hole 31, the photosensitive area 11 is located in the through hole 31, and an isolation belt is set between the inner edge of the through hole 31 and the outer edge of the photosensitive area 11. The isolation belt also serves as the photosensitive area of the chip body 1, but the isolation belt is located at the edge of the photosensitive area 11, which will be affected by noise. Therefore, in actual operation, the operator does not use the data at the isolation belt, but uses the data at the photosensitive area 11. The data of the photosensitive area 11 used is: light generates electric charge on the photosensitive pixel part, and the photosensitive area 11 converts the light signal into an electric signal of the charge, and the electric signal is used to calculate the distance.
[0028] Working principle: The digital analog circuits on the non-photosensitive area of the chip body 1 are blocked by the covering layer 3, which isolates the non-photosensitive area in the chip body 1 from the ambient light, so that photons cannot reach the digital analog circuits in the non-photosensitive area, avoiding unnecessary electrons from being generated and flowing into the photosensitive area 11, and reducing the parasitic photosensitivity of the chip body 1.
[0029] In summary, although the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.
Claims
1. A chip anti-interference structure, applicable to a chip body (1), wherein the chip body (1) is provided with a photosensitive area (11), characterized in that: A covering layer (3) is provided on the chip body (1); the covering layer (3) is located around the photosensitive area (11) and is used to cover the non-photosensitive area of the chip body (1).
2. The chip anti-interference structure according to claim 1, characterized in that: The covering layer (3) is made of non-transparent material.
3. The chip anti-interference structure according to claim 1, characterized in that: The cover layer (3) is provided with a through hole (31), and the photosensitive area (11) is located in the through hole (31).
4. The chip anti-interference structure according to claim 3, characterized in that: An isolation zone is provided between the inner edge of the through hole (31) and the outer edge of the photosensitive area (11).
5. The chip anti-interference structure according to claim 1, characterized in that: An adhesive layer (2) is arranged on the top of the chip body (1).
6. The chip anti-interference structure according to claim 5, characterized in that: The chip body (1) and the cover layer (3) are connected via the adhesive layer (2).
7. The chip anti-interference structure according to claim 6, characterized in that: The adhesive layer (2) and the covering layer (3) have the same shape.
8. The chip anti-interference structure according to claim 1, characterized in that: The thickness of the covering layer (3) is 300um to 310um.
9. The chip anti-interference structure according to claim 1, characterized in that: A plurality of welding balls (4) are arranged at the bottom of the chip body (1).