Switch lock control circuit and switch system

Abstract

The utility model discloses a switch lock control circuit and a switch system, and relates to the technical field of state control. The main control MCU circuit is used for starting the first state control circuit or the second state control circuit according to a control instruction of an upper computer; the first state control circuit is used for controlling the response end to output a first state; the second state control circuit is used for controlling the response end to output a second state; the second state control circuit is connected with the main control MCU circuit; the scheme is applied to the object management device, when the to-be-managed object needs to be taken, the main control MCU circuit starts the first state control circuit, the first state control circuit controls the electromagnetic lock to be unlocked to release the to-be-managed object, and when the to-be-managed object needs to be taken, the main control MCU circuit starts the second state control circuit, and the second state control circuit controls the electromagnetic lock to be unlocked to release the to-be-managed object. And the second state control circuit controls the electromagnetic lock to be closed to lock the to-be-managed object.

Description

Technical Field

[0001] The utility model relates to the technical field of state control, in particular to a switch lock control circuit and a switch system. Background Art

[0002] The management of batches of small items, such as room keys, warehouse keys, etc., currently mainly relies on manual storage management. Each object needs to be matched one by one with the room or warehouse. Manual management is more troublesome, and each management process needs to be checked and matched one by one. The batch management process has low management efficiency and high cost. Utility Model Content

[0003] The technical problem to be solved by the utility model is: in an object management device, an electromagnetic lock is required to be opened or closed as needed, and it is difficult to directly apply a traditional electromagnetic lock to the object management device; the utility model aims to provide a switch lock control circuit and a switch system, which realizes the control of the response end (electromagnetic lock) to output the first state or the second state through the cooperation of the main control MCU circuit, the first state control circuit and the second state control circuit, and realizes the switching of different states of the response end (electromagnetic lock); the scheme also adds a bus transmission circuit for transmitting the control instructions of the host computer or the output state of the output end, so as to realize the intelligent management of the state control circuit.

[0004] The utility model is realized by the following technical solutions:

[0005] This solution provides a state control circuit, including:

[0006] A main control MCU circuit is used to start the first state control circuit or the second state control circuit according to the control instruction of the host computer;

[0007] A first state control circuit, used for controlling the responding end to output a first state; the first state control circuit is connected to the main control MCU circuit;

[0008] A second state control circuit, used for controlling the responding end to output a second state; the second state control circuit is connected to the main control MCU circuit;

[0009] A bus transmission circuit is used to transmit the control instructions of the host computer or the output status of the output terminal; the bus transmission circuit is connected between the main control MCU circuit and the response terminal;

[0010] The power supply circuit is used to provide power.

[0011] In this solution, the first state and the second state are a set of opposite states, such as the disconnection and connection of a switch, the output of high potential and low potential, etc. This solution is mainly applied to object management devices. When the object to be managed contacts the object management device, the electromagnetic lock needs to be in the closed state to lock the object to be managed. When the object to be managed needs to be taken, the electromagnetic lock needs to be in the open state to release the object to be managed. The state control circuit provided by this solution is mainly used to control the electromagnetic lock to be in the open state or the locked state. Therefore, the first state is the open state and the second state is the locked state.

[0012] Working principle of this solution: In an object management device, an electromagnetic lock is required to be opened or closed as needed, and it is difficult to directly apply a traditional electromagnetic lock to the object management device; the purpose of this utility model is to provide a switch lock control circuit and a switch system, which can realize the control of the response end (electromagnetic lock) to output the first state or the second state through the cooperation of the main control MCU circuit, the first state control circuit and the second state control circuit, and realize the switching of different states of the response end (electromagnetic lock); this solution also adds a bus transmission circuit for transmitting the control instructions of the host computer or the output state of the output end, so as to realize the intelligent management of the state control circuit.

[0013] The control instructions of the host computer in this solution include switch signals and sensing signals. The main control MCU circuit is connected with sensing components. When the object to be locked contacts the sensing components, the main control MCU circuit receives the sensing signal and controls the response end (electromagnetic lock) to output the first state (open).

[0014] A further optimized solution is that the first state control circuit includes: a first input terminal, a resistor R1, a transistor Q1, a resistor R2, a resistor R3, a P-MOS transistor M1 and a diode D1;

[0015] The main control MCU circuit is connected to the first input end; one end of the resistor R1 is connected to the first input end, and the other end is connected to the base of the transistor Q1; the emitter of the transistor Q1 is grounded, and the collector of the transistor Q1 is connected to the G pole of the P-MOS tube M1; one end of the resistor R2 is grounded, and the other end is connected to the G pole of the P-MOS tube M1; one end of the resistor R3 is connected to the power supply circuit, and the other end is connected to the G pole of the P-MOS tube M1; the D pole of the P-MOS tube M1 is connected to the power supply circuit; the S pole of the P-MOS tube M1 is connected to the positive pole of the diode D1, and the negative pole of the diode D1 is connected to the response end.

[0016] In this solution, the main control MCU circuit is connected to the first input terminal A_LOCK, the resistor R1 is 1KΩ; the resistor R2 is 100KΩ; the resistor R3 is 20KΩ, and the D pole of the P-MOS tube M1 is connected to a 12V power supply.

[0017] A further optimized solution is that the second state control circuit includes: a second input terminal, a resistor R4, a transistor Q3, a resistor R5, a P-MOS tube M2, a diode D2 and a resistor R6;

[0018] The main control MCU circuit is connected to the second input end; one end of the resistor R4 is connected to the second input end, and the other end is connected to the base of the transistor Q2; the emitter of the transistor Q2 is grounded, and the collector of the transistor Q2 is connected to the G pole of the P-MOS tube M2; one end of the resistor R5 is connected to the power supply circuit, and the other end is connected to the collector of the transistor Q2; the D pole of the P-MOS tube M2 is connected to the power supply circuit; the S pole of the P-MOS tube M1 is connected to the positive pole of the diode D2, and the negative pole of the diode D2 is connected to the response end after being connected in series with the resistor R6.

[0019] In this solution, the main control MCU circuit is connected to the second input terminal A_LOCK1, the resistor R4 is 1KΩ; the resistor R5 is 20KΩ; the resistor R6 is 1KΩ, and the D pole of the P-MOS tube M1 is connected to a 5V power supply.

[0020] A further optimized solution is that the bus transmission circuit includes: a chip TJA1057, a capacitor C1, a resistor R7, a resistor R8, a resistor R9, a capacitor C2, a capacitor C3, a bidirectional voltage regulator F1, a bidirectional voltage regulator F2 and a bidirectional voltage regulator F3;

[0021] The main control MCU circuit is connected to the TXD port and the RXD port of the chip TJA1057; the Vcc port of the chip TJA1057 is connected to the power supply circuit; one end of the capacitor C1 is connected to the Vcc port of the chip TJA1057, and the other end is grounded; the S port of the chip TJA1057 is grounded;

[0022] The CANH port of the chip TJA1057 is connected in series with a resistor R7 and then connected to the first interface of the response end; the CANL port of the chip TJA1057 is connected in series with a resistor R8 and then connected to the second interface of the response end;

[0023] Resistor R9 is connected between the first interface and the second interface of the response end, one end of capacitor C2 is connected to the first interface of the response end, and the other end is grounded; one end of capacitor C3 is connected to the second interface of the response end, and the other end is grounded; one end of the bidirectional voltage regulator F1 is connected to the first interface of the response end, and the other end is grounded; one end of the bidirectional voltage regulator F2 is connected to the second interface of the response end, and the other end is grounded; the bidirectional voltage regulator F3 is connected between the first interface and the second interface of the response end.

[0024] In this solution, capacitor C1 is 0.1uF / 50V, the Vcc port of chip TJA1057 is connected to a 5V power supply, capacitor C2 is 30pF, and capacitor C3 is 30pF.

[0025] A further optimization scheme is that the main control MCU circuit includes: a main control chip, model STM32F103RBT6;

[0026] The PB3 interface of the main control chip is connected to the first state control circuit, and the PB1 interface of the main control chip is connected to the second state control circuit; the VSS_A interface and the VSS_1 interface of the main control chip are grounded, and the VDD1 interface of the main control chip is connected to the power supply circuit.

[0027] Correspondingly, when there are multiple groups of status control circuits, the corresponding VSS_2 interface, VSS_3 interface and VSS_4 interface are all grounded, and the corresponding VDD2 interface, VDD3 interface and VDD4 interface are all connected to the power supply circuit.

[0028] A further optimization solution is to ground the BOOT0 port of the main control chip.

[0029] A further optimization scheme is to further include a display circuit, which includes: a resistor R13 and a light-emitting diode P1, the positive electrode of the light-emitting diode P1 is connected to the power supply circuit, and the negative electrode of the light-emitting diode P1 is connected in series with the resistor R13 and then connected to the PB6 interface of the main control chip.

[0030] A further optimized solution is that the power supply circuit includes: capacitor C4, capacitor C5, capacitor C6, capacitor C7, resistor R10, resistor R11, resistor R12, inductor L1 and conversion chip TPS563201;

[0031] The external power supply is connected to the VIN interface of the conversion chip TPS563201; one end of the capacitor C5 is connected to the VIN interface of the conversion chip TPS563201, and the other end is grounded; one end of the capacitor C6 is connected to the VIN interface of the conversion chip TPS563201, and the other end is grounded;

[0032] One end of capacitor C4 is grounded, and the other end is connected in series with inductor L1 and then connected to the SW port of conversion chip TPS563201; the GND port of conversion chip TPS563201 is grounded; one end of capacitor C7 is connected to the SW port of conversion chip TPS563201, and the other end is connected to the VBST port of conversion chip TPS563201;

[0033] The VFB port of the conversion chip TPS563201 is connected in series with resistor R11 and then connected between capacitor C4 and inductor L1; one end of resistor R10 is connected to the VFB port of the conversion chip TPS563201, and the other end is grounded; one end of capacitor C8 is connected to the EN port of the conversion chip TPS563201, and the other end is grounded; the EN port of the conversion chip TPS563201 is connected in series with resistor R12 and then output.

[0034] A further optimization scheme is that capacitor C4 and capacitor C5 are both 100uF / 25V, capacitor C6 is 10uF / 16V, capacitor C7 is 0.1uF / 50V, and capacitor C8 is 0.1uF / 50V; inductor L1 is 3.3uH / 3A; resistor R10 is 10KΩ, resistor R11 is 54.9KΩ, and resistor R12 is 10KΩ.

[0035] The present solution also provides a switch lock system, including the above-mentioned switch lock control circuit.

[0036] Compared with the prior art, the utility model has the following advantages and beneficial effects:

[0037] The utility model provides a switch lock control circuit and a switch system, which control a response end (electromagnetic lock) to output a first state or a second state through a main control MCU circuit, a first state control circuit and a second state control circuit, thereby realizing switching of different states of the response end (electromagnetic lock).

[0038] The utility model provides a switch lock control circuit and a switch system, which uses a main control chip as a main control MCU circuit, and can integrate multiple sets of state control circuits on the main control chip. Multiple groups of state control circuits (each group of state control circuits includes a first state control circuit and a second state control circuit) can be managed by one main control MCU circuit to achieve control of different states of multiple response ends. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings described herein are used to provide a further understanding of the embodiments of the present utility model, constitute a part of this application, and do not constitute a limitation of the embodiments of the present utility model. In the drawings:

[0040] Figure 1 It is a schematic diagram of the state control circuit structure;

[0041] Figure 2 is a schematic diagram of the structure of the first state control circuit;

[0042] Figure 3 is a schematic diagram of the structure of the second state control circuit;

[0043] Figure 4 It is a schematic diagram of the bus transmission circuit structure;

[0044] Figure 5 This is a schematic diagram of the main control MCU circuit structure;

[0045] Figure 6 To show the schematic diagram of the circuit structure;

[0046] Figure 7 It is a schematic diagram of the power supply circuit structure. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the utility model more clearly understood, the utility model is further described in detail below in conjunction with embodiments and drawings. The schematic implementation manner of the utility model and its description are only used to explain the utility model and are not intended to limit the utility model.

[0048] In the object management device, the electromagnetic lock is required to be opened or closed as needed. It is difficult to directly apply the traditional electromagnetic lock to the object management device. In view of this, the utility model provides the following embodiments to solve the above technical problems:

[0049] Example 1

[0050] This embodiment provides a state control circuit, such as Figure 1 As shown, including:

[0051] A main control MCU circuit is used to start the first state control circuit or the second state control circuit according to the control instruction of the host computer;

[0052] A first state control circuit, used for controlling the responding end to output a first state; the first state control circuit is connected to the main control MCU circuit;

[0053] A second state control circuit, used for controlling the responding end to output a second state; the second state control circuit is connected to the main control MCU circuit;

[0054] A bus transmission circuit is used to transmit the control instructions of the host computer or the output status of the output terminal; the bus transmission circuit is connected between the main control MCU circuit and the response terminal;

[0055] The power supply circuit is used to provide power.

[0056] like Figure 2 As shown, the first state control circuit includes: a first input terminal, a resistor R1, a transistor Q1, a resistor R2, a resistor R3, a P-MOS tube M1 and a diode D1;

[0057] The main control MCU circuit is connected to the first input end; one end of the resistor R1 is connected to the first input end, and the other end is connected to the base of the transistor Q1; the emitter of the transistor Q1 is grounded, and the collector of the transistor Q1 is connected to the G pole of the P-MOS tube M1; one end of the resistor R2 is grounded, and the other end is connected to the G pole of the P-MOS tube M1; one end of the resistor R3 is connected to the power supply circuit, and the other end is connected to the G pole of the P-MOS tube M1; the D pole of the P-MOS tube M1 is connected to the power supply circuit; the S pole of the P-MOS tube M1 is connected to the positive pole of the diode D1, and the negative pole of the diode D1 is connected to the response end.

[0058] The main control MCU circuit of this embodiment is connected to the first input terminal A_LOCK, the resistor R1 is 1KΩ; the resistor R2 is 100KΩ; the resistor R3 is 20KΩ, and the D pole of the P-MOS tube M1 is connected to a 12V power supply.

[0059] like Figure 3 As shown, the second state control circuit includes: a second input terminal, a resistor R4, a transistor Q3, a resistor R5, a P-MOS tube M2, a diode D2 and a resistor R6;

[0060] The main control MCU circuit is connected to the second input end; one end of the resistor R4 is connected to the second input end, and the other end is connected to the base of the transistor Q2; the emitter of the transistor Q2 is grounded, and the collector of the transistor Q2 is connected to the G pole of the P-MOS tube M2; one end of the resistor R5 is connected to the power supply circuit, and the other end is connected to the collector of the transistor Q2; the D pole of the P-MOS tube M2 is connected to the power supply circuit; the S pole of the P-MOS tube M1 is connected to the positive pole of the diode D2, and the negative pole of the diode D2 is connected to the response end after being connected in series with the resistor R6.

[0061] The main control MCU circuit of this embodiment is connected to the second input terminal A_LOCK1, the resistor R4 is 1KΩ; the resistor R5 is 20KΩ; the resistor R6 is 1KΩ, and the D pole of the P-MOS tube M1 is connected to a 5V power supply.

[0062] like Figure 4 As shown, the bus transmission circuit includes: chip TJA1057, capacitor C1, resistor R7, resistor R8, resistor R9, capacitor C2, capacitor C3, bidirectional voltage regulator F1, bidirectional voltage regulator F2 and bidirectional voltage regulator F3;

[0063] The main control MCU circuit is connected to the TXD port and the RXD port of the chip TJA1057; the Vcc port of the chip TJA1057 is connected to the power supply circuit; one end of the capacitor C1 is connected to the Vcc port of the chip TJA1057, and the other end is grounded; the S port of the chip TJA1057 is grounded;

[0064] The CANH port of the chip TJA1057 is connected in series with a resistor R7 and then connected to the first interface of the response end; the CANL port of the chip TJA1057 is connected in series with a resistor R8 and then connected to the second interface of the response end;

[0065] Resistor R9 is connected between the first interface and the second interface of the response end, one end of capacitor C2 is connected to the first interface of the response end, and the other end is grounded; one end of capacitor C3 is connected to the second interface of the response end, and the other end is grounded; one end of the bidirectional voltage regulator F1 is connected to the first interface of the response end, and the other end is grounded; one end of the bidirectional voltage regulator F2 is connected to the second interface of the response end, and the other end is grounded; the bidirectional voltage regulator F3 is connected between the first interface and the second interface of the response end.

[0066] In this embodiment, the capacitor C1 is 0.1uF / 50V, the Vcc port of the chip TJA1057 is connected to a 5V power supply, the capacitor C2 is 30pF, and the capacitor C3 is 30pF.

[0067] like Figure 5 As shown, the main control MCU circuit includes: a main control chip, model STM32F103RBT6;

[0068] The PB3 interface of the main control chip is connected to the first state control circuit, and the PB1 interface of the main control chip is connected to the second state control circuit; the VSS_A interface and the VSS_1 interface of the main control chip are grounded, and the VDD1 interface of the main control chip is connected to the power supply circuit.

[0069] Correspondingly, when there are multiple groups of status control circuits, the corresponding VSS_2 interface, VSS_3 interface and VSS_4 interface are all grounded, and the corresponding VDD2 interface, VDD3 interface and VDD4 interface are all connected to the power supply circuit; the BOOT0 port of the main control chip is grounded.

[0070] like Figure 6 As shown, it also includes a display circuit, which includes: a resistor R13 and a light-emitting diode P1, the positive electrode of the light-emitting diode P1 is connected to the power supply circuit, and the negative electrode of the light-emitting diode P1 is connected in series with the resistor R13 and then connected to the PB6 interface of the main control chip.

[0071] like Figure 7 As shown, the power supply circuit includes: capacitor C4, capacitor C5, capacitor C6, capacitor C7, resistor R10, resistor R11, resistor R12, inductor L1 and conversion chip TPS563201;

[0072] The external power supply is connected to the VIN interface of the conversion chip TPS563201; one end of the capacitor C5 is connected to the VIN interface of the conversion chip TPS563201, and the other end is grounded; one end of the capacitor C6 is connected to the VIN interface of the conversion chip TPS563201, and the other end is grounded;

[0073] One end of capacitor C4 is grounded, and the other end is connected in series with inductor L1 and then connected to the SW port of conversion chip TPS563201; the GND port of conversion chip TPS563201 is grounded; one end of capacitor C7 is connected to the SW port of conversion chip TPS563201, and the other end is connected to the VBST port of conversion chip TPS563201;

[0074] The VFB port of the conversion chip TPS563201 is connected in series with resistor R11 and then connected between capacitor C4 and inductor L1; one end of resistor R10 is connected to the VFB port of the conversion chip TPS563201, and the other end is grounded; one end of capacitor C8 is connected to the EN port of the conversion chip TPS563201, and the other end is grounded; the EN port of the conversion chip TPS563201 is connected in series with resistor R12 and then output.

[0075] Capacitor C4 and capacitor C5 are both 100uF / 25V, capacitor C6 is 10uF / 16V, capacitor C7 is 0.1uF / 50V, and capacitor C8 is 0.1uF / 50V; inductor L1 is 3.3uH / 3A; resistor R10 is 10KΩ, resistor R11 is 54.9KΩ, and resistor R12 is 10KΩ.

[0076] This embodiment is applied to an object management device. When it is necessary to take the object to be managed, the main control MCU circuit starts the first state control circuit, and the first state control circuit controls the electromagnetic lock to open and release the object to be managed. When it is necessary to take the object to be managed, the main control MCU circuit starts the second state control circuit, and the second state control circuit controls the electromagnetic lock to close and lock the object to be managed.

[0077] Example 2

[0078] This embodiment provides a switch lock system, including the switch lock control circuit mentioned above.

[0079] The utility model provides a switch lock control circuit and a switch system, which control a response end (electromagnetic lock) to output a first state or a second state through a main control MCU circuit, a first state control circuit and a second state control circuit, thereby realizing switching of different states of the response end (electromagnetic lock).

[0080] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the utility model in detail. It should be understood that the above description is only the specific implementation method of the utility model and is not used to limit the protection scope of the utility model. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the utility model should be included in the protection scope of the utility model.

Claims

1. A switch lock control circuit, characterized in that: include: A main control MCU circuit is used to start the first state control circuit or the second state control circuit according to the control instruction of the host computer; A first state control circuit, used for controlling the responding end to output a first state; the first state control circuit is connected to the main control MCU circuit; A second state control circuit, used for controlling the responding end to output a second state; The second state control circuit is connected to the main control MCU circuit; A bus transmission circuit is used to transmit the control instructions of the host computer or the output status of the output terminal; the bus transmission circuit is connected between the main control MCU circuit and the response terminal; The power supply circuit is used to provide power.

2. A switch lock control circuit according to claim 1, characterized in that: The first state control circuit includes: a first input terminal, a resistor R1, a transistor Q1, a resistor R2, a resistor R3, a P-MOS transistor M1 and a diode D1; The main control MCU circuit is connected to the first input end; one end of the resistor R1 is connected to the first input end, and the other end is connected to the base of the transistor Q1; the emitter of the transistor Q1 is grounded, and the collector of the transistor Q1 is connected to the G pole of the P-MOS tube M1; one end of the resistor R2 is grounded, and the other end is connected to the G pole of the P-MOS tube M1; one end of the resistor R3 is connected to the power supply circuit, and the other end is connected to the G pole of the P-MOS tube M1; the D pole of the P-MOS tube M1 is connected to the power supply circuit; the S pole of the P-MOS tube M1 is connected to the positive pole of the diode D1, and the negative pole of the diode D1 is connected to the response end.

3. A switch lock control circuit according to claim 1, characterized in that: The second state control circuit includes: a second input terminal, a resistor R4, a transistor Q3, a resistor R5, a P-MOS tube M2, a diode D2 and a resistor R6; The main control MCU circuit is connected to the second input terminal; one end of the resistor R4 is connected to the second input terminal, and the other end is connected to the base of the transistor Q2; the emitter of the transistor Q2 is grounded, and the collector of the transistor Q2 is connected to the G pole of the P-MOS tube M2; one end of the resistor R5 is connected to the power supply circuit, and the other end is connected to the collector of the transistor Q2; the D pole of the P-MOS tube M2 is connected to the power supply circuit; the S pole of the P-MOS tube M1 is connected to the positive pole of the diode D2, and the negative pole of the diode D2 is connected in series with the resistor R6 and then connected to the response terminal.

4. A switch lock control circuit according to claim 1, characterized in that: The bus transmission circuit includes: a chip TJA1057, a capacitor C1, a resistor R7, a resistor R8, a resistor R9, a capacitor C2, a capacitor C3, a bidirectional voltage regulator F1, a bidirectional voltage regulator F2 and a bidirectional voltage regulator F3; The main control MCU circuit is connected to the TXD port and the RXD port of the chip TJA1057; the Vcc port of the chip TJA1057 is connected to the power supply circuit; one end of the capacitor C1 is connected to the Vcc port of the chip TJA1057, and the other end is grounded; the S port of the chip TJA1057 is grounded; The CANH port of the chip TJA1057 is connected in series with a resistor R7 and then connected to the first interface of the response end; the CANL port of the chip TJA1057 is connected in series with a resistor R8 and then connected to the second interface of the response end; Resistor R9 is connected between the first interface and the second interface of the response end, one end of capacitor C2 is connected to the first interface of the response end, and the other end is grounded; one end of capacitor C3 is connected to the second interface of the response end, and the other end is grounded; one end of the bidirectional voltage regulator F1 is connected to the first interface of the response end, and the other end is grounded; one end of the bidirectional voltage regulator F2 is connected to the second interface of the response end, and the other end is grounded; the bidirectional voltage regulator F3 is connected between the first interface and the second interface of the response end.

5. A switch lock control circuit according to claim 1, characterized in that: The main control MCU circuit includes: a main control chip, model STM32F103RBT6; The PB3 interface of the main control chip is connected to the first state control circuit, and the PB1 interface of the main control chip is connected to the second state control circuit; the VSS_A interface and the VSS_1 interface of the main control chip are grounded, and the VDD1 interface of the main control chip is connected to the power supply circuit.

6. A switch lock control circuit according to claim 5, characterized in that: The BOOT0 port of the main control chip is grounded.

7. A switch lock control circuit according to claim 6, characterized in that: It also includes a display circuit, which includes: a resistor R13 and a light-emitting diode P1, the positive electrode of the light-emitting diode P1 is connected to the power supply circuit, and the negative electrode of the light-emitting diode P1 is connected in series with the resistor R13 and then connected to the PB6 interface of the main control chip.

8. A switch lock control circuit according to claim 1, characterized in that: The power supply circuit includes: capacitor C4, capacitor C5, capacitor C6, capacitor C7, resistor R10, resistor R11, resistor R12, inductor L1 and conversion chip TPS563201; The external power supply is connected to the VIN interface of the conversion chip TPS563201; one end of the capacitor C5 is connected to the VIN interface of the conversion chip TPS563201, and the other end is grounded; one end of the capacitor C6 is connected to the VIN interface of the conversion chip TPS563201, and the other end is grounded; One end of capacitor C4 is grounded, and the other end is connected in series with inductor L1 and then connected to the SW port of conversion chip TPS563201; the GND port of conversion chip TPS563201 is grounded; one end of capacitor C7 is connected to the SW port of conversion chip TPS563201, and the other end is connected to the VBST port of conversion chip TPS563201; The VFB port of the conversion chip TPS563201 is connected in series with resistor R11 and then connected between capacitor C4 and inductor L1; one end of resistor R10 is connected to the VFB port of the conversion chip TPS563201, and the other end is grounded; one end of capacitor C8 is connected to the EN port of the conversion chip TPS563201, and the other end is grounded; the EN port of the conversion chip TPS563201 is connected in series with resistor R12 and then output.

9. A switch lock control circuit according to claim 8, characterized in that: Capacitor C4 and capacitor C5 are both 100uF / 25V, capacitor C6 is 10uF / 16V, capacitor C7 is 0.1uF / 50V, and capacitor C8 is 0.1uF / 50V; inductor L1 is 3.3uH / 3A; resistor R10 is 10KΩ, resistor R11 is 54.9KΩ, and resistor R12 is 10KΩ.

10. A switch system, characterized in that: A switch lock control circuit comprising any one of claims 1-9.

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