Receiving end circuit of LIN bus transceiver

Abstract

The utility model provides a receiving end circuit of an LIN bus transceiver. Radio frequency interference received by a BUS pin is shielded through a sensing module, a comparison module and a hysteresis generation module. The working process of the circuit is as follows: when an initial BUS pin is at a high level, under the action of the sensing module and the comparison module, a logic level of the high level is output, and at the moment, a reference voltage is a first value; when the BUS pin is changed from a high level to a low level, the sensing module compares the input voltage with a first value, so that the comparison module outputs a logic level of the low level, and at the moment, the reference voltage is increased from the first value to a second value; when the BUS pin changes from the low level to the high level, the sensing module compares the input voltage with the second value, and when the input voltage is higher than the second value, the comparison module can output the logic level of the high level, that is, hysteresis voltage is generated, and the situation that oscillation signals are caused by electromagnetic interference near threshold voltage is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of automobile distributed electronic systems, and in particular to a LIN bus transceiver receiving end circuit. Background Art

[0002] LIN bus is a low-cost serial communication network defined for automotive distributed electronic systems. Typical LIN bus applications are joint assembly unit control of automobiles, such as doors, steering wheels, seats, air conditioners, lighting, temperature sensors, and alternators. In the implementation of its control of in-vehicle components, the LIN bus transceiver plays the role of a transfer station. It is a bridge between the controller and the physical bus, and is mainly composed of a sending structure that sends data to the bus and a receiving structure that receives bus data.

[0003] Compared with consumer chips and general industrial chips, the working environment of automotive chips is more severe: wide temperature range, high vibration, high dust, electromagnetic interference, etc. Due to personal safety issues, automotive chips have higher requirements for reliability and safety, and "automotive-grade" chips need to go through a rigorous certification process. The BUS pin of the LIN transceiver converts the logic signal of the VBAT voltage domain into the logic signal of the VDD internal voltage domain, and at the same time receives radio frequency interference from the harsh environment of the car. The radio frequency interference on the bus may cause circuit functional failures, such as destroying the duty cycle and changing the logical state of the LIN bus signal, resulting in unstable communication functions. Utility Model Content

[0004] The purpose of the embodiments of the present application is to provide a LIN bus transceiver receiving end circuit for shielding the radio frequency interference received by the BUS pin.

[0005] A LIN bus transceiver receiving end circuit provided in an embodiment of the present application includes:

[0006] A sensing module is used to receive an input voltage of a BUS pin; compare the input voltage with a reference voltage to obtain a first comparison result; generate a sensing current according to the first comparison result, and output the sensing current to the comparison module;

[0007] A comparison module, used for generating a logic level after comparing the sense current with the bias current, and outputting the logic level;

[0008] The hysteresis generation module is used to set the reference voltage to a second value when the logic level is a low level; and to set the reference voltage to a first value when the logic level is a high level; wherein the second value is greater than the first value.

[0009] In the above technical solution, the radio frequency interference received by the BUS pin is shielded by the sensing module, the comparison module and the hysteresis generation module. The working process of the circuit is: when the initial BUS pin is at a high level, the sensing module and the comparison module output a high-level logic level, and the reference voltage is the first value at this time; when the BUS pin changes from a high level to a low level, the sensing module compares the input voltage with the first value, so that the comparison module outputs a low-level logic level, and the reference voltage increases from the first value to the second value at this time; when the BUS pin changes from a low level to a high level, the sensing module compares the input voltage with the second value, and only when the input voltage is higher than the second value can the comparison module output a high-level logic level, that is, a hysteresis voltage is generated to avoid the situation where an oscillation signal occurs near the threshold voltage due to electromagnetic interference.

[0010] In some optional implementations, the sensing module includes a first current source, a first PMOS transistor, a second PMOS transistor, a second resistor, and a current mirror circuit;

[0011] The input end of the first current source is connected to the voltage VBAT, and the output end of the first current source is connected to point a; point a is connected to the source end of the first PMOS tube, the gate end of the first PMOS tube is connected to the gate end of the second PMOS tube, the source end of the second PMOS tube is connected to point b, and the drain of the second PMOS tube is connected to the first end of the current mirror circuit; the voltage VBAT is connected to point b after passing through the second resistor, and the second end of the current mirror circuit is connected to point c.

[0012] In the above technical solution, the working process of the sensing module is as follows: when the BUS pin is at a high level, point a is approximately equal to the input voltage of the BUS pin, point a to the first PMOS tube and point b to the second PMOS tube form a symmetrical structure, the input voltage at point a is higher than the reference voltage at point b, the second PMOS tube is insufficient to turn on, no current flows through both ends of the current mirror circuit, and the value of the sensing current is 0. When the BUS pin is at a low level, the input voltage at point a is lower than the reference voltage at point b, the second PMOS tube is turned on, and current flows through both ends of the current mirror circuit, and the value of the sensing current is the set current value.

[0013] The sensing module also includes a first diode, a second diode and a third diode. The input end of the first diode is connected to the output end of the first current source, and the output end of the first diode is connected to point a; the input end of the second diode is connected to point a, and the output end of the second diode is connected to the source of the first PMOS tube. The input end of the third diode is connected to point b, and the output end of the third diode is connected to the source of the second PMOS tube. The first diode and the third diode prevent the BUS pin from reversely charging when the VBAT voltage is positive, and the second diode and the third diode are matched.

[0014] The sensing module also includes a first Zener tube and a second Zener tube, wherein the input end of the first Zener tube is connected to the gate of the first PMOS tube, and the source of the first PMOS tube is connected to the output end of the first Zener tube; the input end of the second Zener tube is connected to the gate of the second PMOS tube, and the source of the second PMOS tube is connected to the output end of the second Zener tube. The first Zener tube Z and the second Zener tube protect the gate oxides of the first PMOS tube and the second PMOS tube respectively.

[0015] In some optional implementations, the sensing module further includes a first NMOS tube and a second current source:

[0016] The drain of the first PMOS tube is connected to the drain of the first NMOS tube, the source of the first NMOS tube is connected to the input end of the second current source, the output end of the second current source is grounded, and the gate of the first NMOS tube is connected to the power supply VDD.

[0017] In the above technical solution, the first NMOS tube is arranged to withstand the branch high voltage to protect the second current source.

[0018] In some optional implementations, the current mirror circuit includes a second NMOS transistor and a third NMOS transistor;

[0019] The drain of the second PMOS tube is connected to the drain of the second NMOS tube, the gate of the second NMOS tube is connected to the gate of the third NMOS tube, the source of the second NMOS tube is grounded, the source of the third NMOS tube is grounded, and the drain of the third NMOS tube is connected to point c.

[0020] In the above technical solution, the second NMOS tube and the third NMOS tube form a current mirror circuit, and the current flowing through the first end of the current mirror circuit is amplified by a 1:k current mirror, so that a current of a set current value flows through the second end of the current mirror circuit.

[0021] In some optional implementations, the hysteresis generating module includes a third resistor, a fourth resistor and a fifth NMOS tube;

[0022] The first end of the third resistor is connected to point b, the second end of the third resistor is connected to the first end of the fourth resistor, the second end of the fourth resistor is grounded, the first end of the fourth resistor is connected to the drain of the fifth NMOS tube, the second end of the fourth resistor is connected to the source of the fifth NMOS tube, and the gate of the fifth NMOS tube is connected to the output end of the comparison module.

[0023] In the above technical solution, the resistance value R3 of the third resistor is equal to the resistance value R2 of the second resistor, and R3 is greater than the resistance value R4 of the fourth resistor. When the comparator outputs a high level, the fifth NMOS tube is closed, and the reference voltage at point b is 0.5VBAT; when the comparator outputs a low level, the fifth NMOS tube is disconnected, and the reference voltage at point b increases and is higher than 0.5VBAT.

[0024] In some optional implementations, the comparison module includes a third current source;

[0025] An input terminal of the third current source is connected to the power supply VDD, and an output terminal of the third current source is connected to point c.

[0026] In the above technical solution, the third current source outputs a current of a set current value. When a current of the set current value flows through the second end of the current mirror circuit, the voltage at point c is pulled down to GND; when the current flowing through the second end of the current mirror circuit is 0, the voltage at point c is pulled up to VDD.

[0027] In some optional implementations, the comparison module further includes an output filtering module; the input end of the output filtering module is connected to point c, and the output filtering module is used to filter out burrs and spikes on the logic level before outputting.

[0028] In some optional implementations, the output filter module includes a fourth current source, a third PMOS transistor, a fourth NMOS transistor, a fifth current source, an inverter, and a second capacitor:

[0029] The input end of the fourth current source is connected to the power supply VDD, the output end of the fourth current source is connected to the source of the third PMOS tube, the drain of the third PMOS tube is connected to point d, the drain of the fourth NMOS tube is connected to point d, the source of the fourth NMOS tube is connected to the input end of the fifth current source, the output end of the fifth current source is grounded, point d is grounded after passing through the second capacitor, point d is connected to the input end of the inverter, and the output end of the inverter outputs the filtered logic level.

[0030] In the above technical solution, the working process of the output filter module is as follows: when the voltage at point c is VDD, the third PMOS tube is disconnected, the fourth NMOS tube is turned on, the voltage at point d is pulled down to GND, the voltage at point d is steadily at a low level, and then a high level logic level is output through the inverter; when the voltage at point c is GND, the third PMOS tube is turned on, the fourth NMOS tube is turned off, the voltage at point d is pulled up to VDD, the voltage at point d is steadily at a high level, and then a low level logic level is output through the inverter.

[0031] In some optional implementations, an input filter module is further included; the input filter module includes a first resistor and a first capacitor;

[0032] The BUS pin is connected to the first end of the first resistor, and the second end of the first resistor is connected to point a; the second end of the first resistor is also connected to the ground after passing through the first capacitor.

[0033] In some optional implementations, the method further includes: a switch; the switch is arranged between the power supply VBAT and the second resistor.

[0034] In the above technical solution, a switch is also provided. When the LIN bus transceiver receiving end circuit is not used, the overall power consumption is reduced by closing the switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 A functional module diagram of a LIN bus transceiver receiving end circuit provided in an embodiment of the present application;

[0037] Figure 2 A circuit structure diagram of a LIN bus transceiver receiving end provided in an embodiment of the present application.

[0038] Icon: 1- perception module, 2- comparison module, 3- hysteresis generation module. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0040] Please refer to Figure 1 , Figure 1 A functional module diagram of a LIN bus transceiver receiving end circuit provided in an embodiment of the present application specifically includes a sensing module 1, a comparison module 2 and a hysteresis generating module 3.

[0041] Among them, the sensing module 1 is used to receive the input voltage of the BUS pin; after comparing the input voltage with the reference voltage, a first comparison result is obtained; a sensing current is generated according to the first comparison result, and the sensing current is output to the comparison module 2. The comparison module 2 is used to generate a logic level after comparing the sensing current with the bias current, and output the logic level. The hysteresis generation module 3 is used to set the reference voltage to a second value when the logic level is a low level; and set the reference voltage to a first value when the logic level is a high level; wherein the second value is greater than the first value.

[0042] Specifically, the input end of the hysteresis generation module 3 is connected to the output end of the comparison module 2, the hysteresis generation module 3 detects the output end voltage of the comparison module 2, the BUS pin receives the input voltage of the external voltage domain VBAT, and when the input voltage is greater than the reference voltage 0.5VBAT, the comparison module 2 outputs a high-level logic signal of the internal voltage domain VDD, and the hysteresis generation module 3 maintains the reference voltage at 0.5VBAT according to the high-level logic signal. When the input voltage changes from greater than 0.5VBAT to less than 0.5VBAT, the comparison module 2 outputs a low-level logic signal, and the hysteresis generation module 3 sets the reference voltage to a second value slightly higher than 0.5VBAT according to the low-level logic signal. Only when the input voltage changes from less than 0.5VBAT to greater than the second value, the comparison module 2 will output a high-level logic signal of the internal voltage domain VDD, and the hysteresis generation module 3 detects the high-level logic signal and sets the reference voltage to 0.5VBAT.

[0043] In the embodiment of the present application, the radio frequency interference received by the BUS pin is shielded by the sensing module 1, the comparison module 2 and the hysteresis generation module 3. The working process of the circuit is as follows: when the initial BUS pin is at a high level, the sensing module 1 and the comparison module 2 output a high-level logic level, and the reference voltage is the first value at this time; when the BUS pin changes from a high level to a low level, the sensing module 1 compares the input voltage with the first value, so that the comparison module 2 outputs a low-level logic level, and the reference voltage increases from the first value to the second value at this time; when the BUS pin changes from a low level to a high level, the sensing module 1 compares the input voltage with the second value, and only when the input voltage is higher than the second value can the comparison module 2 output a high-level logic level, that is, a hysteresis voltage is generated to avoid the situation where an oscillation signal occurs near the threshold voltage due to electromagnetic interference.

[0044] For details, please refer to Figure 2 , Figure 2 A circuit structure diagram of a LIN bus transceiver receiving end provided in an embodiment of the present application.

[0045] In some optional implementations, the sensing module 1 includes a first current source B1, a first PMOS transistor PM1, a second PMOS transistor PM2, a second resistor R2 and a current mirror circuit;

[0046] The input end of the first current source B1 is connected to the voltage VBAT, and the output end of the first current source B1 is connected to point a; point a is connected to the source end of the first PMOS tube PM1, the gate end of the first PMOS tube PM1 is connected to the gate end of the second PMOS tube PM2, the source end of the second PMOS tube PM2 is connected to point b, and the drain of the second PMOS tube PM2 is connected to the first end of the current mirror circuit; the voltage VBAT is connected to point b after passing through the second resistor R2, and the second end of the current mirror circuit is connected to point c.

[0047] The sensing module 1 also includes a first diode D1, a second diode D2 and a third diode D3. The input end of the first diode D1 is connected to the output end of the first current source B1, and the output end of the first diode D1 is connected to point a; the input end of the second diode D2 is connected to point a, and the output end of the second diode D2 is connected to the source of the first PMOS tube PM1. The input end of the third diode D3 is connected to point b, and the output end of the third diode D3 is connected to the source of the second PMOS tube PM2. The first diode D1 and the third diode D3 prevent the BUS pin from reversely charging when the VBAT voltage is positive, and the second diode D2 and the third diode D3 are matched.

[0048] The sensing module 1 further includes a first Zener tube Z1 and a second Zener tube Z2, wherein the input end of the first Zener tube Z1 is connected to the gate of the first PMOS tube PM1, and the source of the first PMOS tube PM1 is connected to the output end of the first Zener tube Z1; the input end of the second Zener tube Z2 is connected to the gate of the second PMOS tube PM2, and the source of the second PMOS tube PM2 is connected to the output end of the second Zener tube Z2. The first Zener tube Z1 and the second Zener tube Z2 protect the gate oxides of the first PMOS tube PM1 and the second PMOS tube PM2 respectively.

[0049] In the embodiment of the present application, the working process of the sensing module 1 is as follows: when the BUS pin is at a high level, point a is approximately equal to the input voltage of the BUS pin, point a to the first PMOS tube PM1 and point b to the second PMOS tube PM2 form a symmetrical structure, the input voltage at point a is higher than the reference voltage at point b, the second PMOS tube PM2 is insufficient to turn on, no current flows through both ends of the current mirror circuit, and the value of the sensed current is 0. When the BUS pin is at a low level, the input voltage at point a is lower than the reference voltage at point b, the second PMOS tube PM2 is turned on, and current flows through both ends of the current mirror circuit, and the value of the sensed current is the set current value.

[0050] In some optional embodiments, the sensing module 1 further includes a first NMOS tube NM1 and a second current source B2. The drain of the first PMOS tube PM1 is connected to the drain of the first NMOS tube NM1, the source of the first NMOS tube NM1 is connected to the input end of the second current source B2, the output end of the second current source B2 is grounded, and the gate of the first NMOS tube NM1 is connected to the power supply VDD. In the embodiment of the present application, the first NMOS tube NM1 is set to withstand the branch high voltage to protect the second current source B2.

[0051] In some optional embodiments, the current mirror circuit includes a second NMOS tube NM2 and a third NMOS tube NM3. The drain of the second PMOS tube PM2 is connected to the drain of the second NMOS tube NM2, the gate of the second NMOS tube NM2 is connected to the gate of the third NMOS tube NM3, the gate of the second NMOS tube NM2 is also connected to the drain of the second NMOS tube NM2, the source of the second NMOS tube NM2 is grounded, the source of the third NMOS tube NM3 is grounded, and the drain of the third NMOS tube NM3 is connected to point c.

[0052] In the embodiment of the present application, the second NMOS tube NM2 and the third NMOS tube NM3 form a current mirror circuit, and the current flowing through the first end of the current mirror circuit is amplified by a 1:k current mirror, so that a current of a set current value flows through the second end of the current mirror circuit.

[0053] In some optional embodiments, the hysteresis generating module 3 includes a third resistor R3, a fourth resistor R4 and a fifth NMOS tube NM5; wherein, the first end of the third resistor R3 is connected to point b, the second end of the third resistor R3 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is grounded, the first end of the fourth resistor R4 is connected to the drain of the fifth NMOS tube NM5, the second end of the fourth resistor R4 is connected to the source of the fifth NMOS tube NM5, and the gate of the fifth NMOS tube NM5 is connected to the output end of the comparison module 2.

[0054] In the embodiment of the present application, the resistance value R3 of the third resistor R3 is equal to the resistance value R2 of the second resistor R2, and R3 is greater than the resistance value R4 of the fourth resistor R4. When the comparator outputs a high level, the fifth NMOS tube NM5 is closed, and the reference voltage at point b is 0.5VBAT; when the comparator outputs a low level, the fifth NMOS tube NM5 is disconnected, and the reference voltage at point b increases and is higher than 0.5VBAT.

[0055] In some optional implementations, the comparison module 2 includes a third current source B3; an input end of the third current source B3 is connected to the power supply VDD, and an output end of the third current source B3 is connected to point c.

[0056] In the embodiment of the present application, the third current source B3 outputs a current of a set current value. When a current of the set current value flows through the second end of the current mirror circuit, the voltage at point c is pulled down to GND; when the current flowing through the second end of the current mirror circuit is 0, the voltage at point c is pulled up to VDD.

[0057] In some optional implementations, the comparison module 2 further includes an output filtering module; the input end of the output filtering module is connected to point c, and the output filtering module is used to filter out burrs and spikes on the logic level before outputting.

[0058] In some optional implementations, the output filter module includes a fourth current source B4, a third PMOS transistor PM3, a fourth NMOS transistor NM4, a fifth current source, an inverter I1 and a second capacitor.

[0059] Among them, the input end of the fourth current source B4 is connected to the power supply VDD, the output end of the fourth current source B4 is connected to the source of the third PMOS tube PM3, the drain of the third PMOS tube PM3 is connected to point d, the drain of the fourth NMOS tube NM4 is connected to point d, the source of the fourth NMOS tube NM4 is connected to the input end of the fifth current source, the output end of the fifth current source is grounded, point d is grounded after passing through the second capacitor, point d is connected to the input end of the inverter I1, and the output end of the inverter I1 outputs the filtered logic level.

[0060] In the embodiment of the present application, the working process of the output filter module is as follows: when the voltage at point c is VDD, the third PMOS tube PM3 is disconnected, the fourth NMOS tube NM4 is turned on, the voltage at point d is pulled down to GND, the voltage at point d is steadily at a low level, and then a high level logic level is output through the inverter I1; when the voltage at point c is GND, the third PMOS tube PM3 is turned on, the fourth NMOS tube NM4 is turned off, the voltage at point d is pulled up to VDD, the voltage at point d is steadily at a high level, and then a low level logic level is output through the inverter I1.

[0061] In some optional embodiments, an input filter module is also included; the input filter module includes a first resistor R1 and a first capacitor; wherein the BUS pin is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to point a; the second end of the first resistor R1 is also grounded after passing through the first capacitor.

[0062] In some optional implementations, it further includes: a switch; the switch is arranged between the power supply VBAT and the second resistor R2. In the embodiment of the present application, a switch is also arranged, and when the LIN bus transceiver receiving end circuit is not used, the overall power consumption is reduced by closing the switch.

[0063] like Figure 2In the embodiment, Ⅰ, Ⅱ, Ⅲ are input stage, comparison stage, output filter stage respectively, and I1 is buffer stage. R1 and C1 form a filter structure; B1 provides pull-up current to BUS to prevent high impedance state when BUS is floating, and at the same time limits the power consumption of the branch; power diodes D1 and D3 prevent BUS from reversely charging when VBAT voltage is positive; D2 matches D3; Zener tubes Z1 and Z2 protect the gate oxide of high-voltage tubes PM1 and PM2 respectively; R2, R3, R4 (R2 and R3 are equal in value, with larger resistance, which limits the power consumption of the branch; R4 is relatively small) form a voltage divider structure for VBAT, providing a reference voltage, which is controlled by switch S1. The switch is disconnected when not in use to reduce power consumption; NM2 , NM3 form a 1:k current mirror; B3 has a small current value, which limits the power consumption of the branch on the one hand, and provides a higher detection sensitivity on the other hand; B4, B5, PM3, and NM4 form a filter circuit, which can filter out abnormal flip glitches caused by complex electromagnetic interference received by the bus, and further improve the overall electromagnetic compatibility (EMC) of the receiving end; the filtered signal passes through the reverse buffer stage I1 to reach the final output OUT, and the logic value of OUT controls the gate of NM5, that is, controls the serial connection and disconnection of R4, and generates a hysteresis voltage for the entire receiving structure, further improving the anti-interference ability of the structure. VBAT is the bus voltage domain, VDD is the internal low-voltage power domain, and GND is the chip common ground.

[0064] The specific working process is as follows: Initially, the BUS voltage is high, the B1 value is low, point a is close to the BUS, and the reference voltage at point b is about 0.5VBAT (precisely 0.5VBAT when NM5 is closed). Because point a to PM1 and point b to PM2 form a symmetrical structure, PM2 is not enough to turn on, and NM2 and NM3 have no current. Point c is pulled up to the internal power supply voltage VDD by B3, and the steady-state value of point d is GND, and OUT is high. When BUS gradually decreases to a certain voltage (0.5VBAT) (defined as the threshold of the receiver), PM2 will turn on, and current will flow into NM2. After being amplified by the 1:k current mirror and equal to the B3 value, point c is pulled down to GND, and the steady state of point d is high, and OUT is low, realizing the flip of the logic value. Because the B3 value is small, 1:k is an amplifying current mirror, and the flip threshold is close to the reference voltage at point b. Additionally, after OUT is low, NM5 is closed, R4 is connected in series to the branch where R2 and R3 are located, and when BUS changes from low to high, the threshold voltage (R3+R4) / (R2+R3+R4)×VBAT of the receiving structure increases, that is, a hysteresis voltage is generated to avoid an oscillation signal due to electromagnetic interference near the threshold voltage.

[0065] In summary, the LIN bus transceiver receiving end circuit of this embodiment is a safe and reliable receiving end circuit structure. It is based on the current comparison structure and places high-voltage protection and transient interference filtering elements at the input and output ends, so that the receiving structure has better performance and better adaptability, and can avoid the generation of oscillation signals due to electromagnetic interference near the threshold voltage. It has the advantages of high safety, high reliability, and wide applicability.

[0066] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0067] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0068] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0069] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0070] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A LIN bus transceiver receiving end circuit, characterized in that: include: A sensing module, used to receive the input voltage of the BUS pin; After comparing the input voltage with the reference voltage, a first comparison result is obtained; generating a sensing current according to the first comparison result, and outputting the sensing current to a comparison module; The comparison module is used to generate a logic level after comparing the sensing current with the bias current, and output the logic level; a hysteresis generating module, configured to set the reference voltage to a second value when the logic level is at a low level; When the logic level is a high level, the reference voltage is set to a first value; wherein the second value is greater than the first value.

2. The circuit according to claim 1, characterized in that The sensing module includes a first current source, a first PMOS tube, a second PMOS tube, a second resistor and a current mirror circuit; The input end of the first current source is connected to the voltage VBAT, and the output end of the first current source is connected to point a; point a is connected to the source end of the first PMOS tube, the gate end of the first PMOS tube is connected to the gate end of the second PMOS tube, the source end of the second PMOS tube is connected to point b, and the drain of the second PMOS tube is connected to the first end of the current mirror circuit; the voltage VBAT is connected to point b after passing through the second resistor, and the second end of the current mirror circuit is connected to point c.

3. The circuit according to claim 2, characterized in that The sensing module further includes a first NMOS tube and a second current source: The drain of the first PMOS tube is connected to the drain of the first NMOS tube, the source of the first NMOS tube is connected to the input end of the second current source, the output end of the second current source is grounded, and the gate of the first NMOS tube is connected to the power supply VDD.

4. The circuit according to claim 2, characterized in that The current mirror circuit comprises a second NMOS tube and a third NMOS tube; The drain of the second PMOS tube is connected to the drain of the second NMOS tube, the gate of the second NMOS tube is connected to the gate of the third NMOS tube, the source of the second NMOS tube is grounded, the source of the third NMOS tube is grounded, and the drain of the third NMOS tube is connected to point c.

5. The circuit according to claim 2, characterized in that The hysteresis generating module comprises a third resistor, a fourth resistor and a fifth NMOS tube; The first end of the third resistor is connected to point b, the second end of the third resistor is connected to the first end of the fourth resistor, the second end of the fourth resistor is grounded, the first end of the fourth resistor is connected to the drain of the fifth NMOS tube, the second end of the fourth resistor is connected to the source of the fifth NMOS tube, and the gate of the fifth NMOS tube is connected to the output end of the comparison module.

6. The circuit according to claim 2, characterized in that The comparison module comprises a third current source; An input end of the third current source is connected to a power source VDD, and an output end of the third current source is connected to point c.

7. The circuit according to claim 6, characterized in that The comparison module further includes an output filter module; the input end of the output filter module is connected to point c, and the output filter module is used to filter out burrs and spikes on the logic level before outputting.

8. The circuit according to claim 7, characterized in that The output filter module includes a fourth current source, a third PMOS tube, a fourth NMOS tube, a fifth current source, an inverter and a second capacitor: The input end of the fourth current source is connected to the power supply VDD, the output end of the fourth current source is connected to the source of the third PMOS tube, the drain of the third PMOS tube is connected to point d, the drain of the fourth NMOS tube is connected to point d, the source of the fourth NMOS tube is connected to the input end of the fifth current source, the output end of the fifth current source is grounded, point d is grounded after passing through the second capacitor, point d is connected to the input end of the inverter, and the output end of the inverter outputs the filtered logic level.

9. The circuit according to any one of claims 2 to 8, characterized in that: It also includes an input filter module; the input filter module includes a first resistor and a first capacitor; The BUS pin is connected to the first end of the first resistor, and the second end of the first resistor is connected to point a; the second end of the first resistor is also connected to the ground after passing through the first capacitor.

10. The circuit according to any one of claims 2 to 8, characterized in that: Also includes: switch; the switch is arranged between the power supply VBAT and the second resistor.

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