Radio frequency switch

Abstract

The utility model relates to a radio frequency switch. The radio frequency switch provided by the embodiment of the utility model comprises a switch stack of k-order common resistors, which is configured to transmit a grid bias voltage to a grid bias resistor of each switch unit after passing through a k-order grid total branch resistor network, and transmit a body region bias voltage to a body region bias resistor of each switch unit after passing through a k-order body region total branch resistor network, the control unit is used for controlling each switch unit to be switched on or switched off, so that the switch stack is controlled to switch on or switch off transmission of radio-frequency signals; wherein k is a natural number greater than or equal to 2. According to the embodiment of the invention, the insertion loss can be reduced, the power capacity can be improved, extra and excessive layout area is not occupied, and the layout area is effectively saved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a radio frequency switch. Background Art

[0002] RF switches are often used in the transmission of RF signals. RF switches are devices that can control the conversion of RF signal transmission channels. On the one hand, when RF signals are transmitted using RF switches, it is expected that the loss will be reduced to ensure signal quality; on the other hand, the transmission of high-power RF signals also requires the RF switch to have a higher power capacity to ensure the security and stability of transmission.

[0003] Therefore, how to reduce insertion loss and increase power capacity is crucial for RF switches. Utility Model Content

[0004] In view of this, an embodiment of the present application provides a radio frequency switch to solve at least one problem existing in the background technology.

[0005] An embodiment of the present application provides a radio frequency switch, the radio frequency switch comprising:

[0006] A switch stack with a k-order common resistor is configured to transmit a gate bias voltage to the gate bias resistor of each switch unit through a k-order gate total divided resistor network, and to transmit a body bias voltage to the body bias resistor of each switch unit through a k-order body total divided resistor network, so as to control each switch unit to be turned on or off, thereby controlling the switch stack to turn on or off the transmission of the radio frequency signal; wherein k is a natural number greater than or equal to 2.

[0007] In an optional implementation, the switch stack of k-order common resistors is a switch stack of 2-order common resistors.

[0008] In an optional implementation, the switch stack of the 2nd-order common resistor includes a 2nd-order gate total divided resistor network, a 2nd-order body region total divided resistor network and an n-order switch stack; wherein n is a natural number greater than or equal to 2;

[0009] The 2-stage gate total divided resistance network is configured to transmit a gate bias voltage to a gate bias resistor of each switch unit in the n-stage switch stack;

[0010] The 2nd-stage body region total divided resistance network is configured to transmit a body region bias voltage to a body region bias resistor of each switch unit in the n-stage switch stack.

[0011] In an optional implementation, the 2nd-order gate total divided resistance network includes a gate total resistance and p gate 1-level divided resistances; wherein p is a natural number greater than or equal to 2;

[0012] The first end of the total gate resistor is configured to input a gate bias voltage, and the second end of the total gate resistor is respectively connected to the first ends of p gate 1-stage resistors; the second end of each gate 1-stage resistor is configured to output an internal gate bias voltage.

[0013] In an optional implementation, the 2nd-order body region total divided resistance network includes a body region total resistance and a p body region 1-level divided resistance;

[0014] The first end of the total body resistance is configured to input the body bias voltage, and the second end of the total body resistance is respectively connected to the first end of the p body 1 division resistor; the second end of each body 1 division resistor is configured to output the internal body bias voltage.

[0015] In an optional implementation, the n-stage switch stack includes p groups of switch units;

[0016] Each switch cell in any group of switch cells is configured to receive the internal gate bias voltage output from the second end of a gate 1 stage resistor through a gate bias resistor, and to receive the internal body bias voltage output from the second end of a body 1 stage resistor through a body bias resistor.

[0017] In an optional implementation, the gate 1 divided resistor includes a first gate 1 divided resistor, a second gate 1 divided resistor and a third gate 1 divided resistor;

[0018] The body region 1 divided resistors include a first body region 1 divided resistor, a second body region 1 divided resistor and a third body region 1 divided resistor;

[0019] The n-stage switch stack includes a first switch unit group, a second switch unit group and a third switch unit group;

[0020] The first end of the first gate 1 divided resistor, the first end of the second gate 1 divided resistor, and the first end of the third gate 1 divided resistor are respectively connected to the second end of the gate total resistor, the second end of the first gate 1 divided resistor is respectively connected to the second end of the gate bias resistor of each switch unit in the first group of switch units, the second end of the second gate 1 divided resistor is respectively connected to the second end of the gate bias resistor of each switch unit in the second group of switch units, and the second end of the third gate 1 divided resistor is respectively connected to the second end of the gate bias resistor of each switch unit in the third group of switch units;

[0021] The first end of the first body region 1 divided resistor, the first end of the second body region 1 divided resistor and the first end of the third body region 1 divided resistor are respectively connected to the second end of the body region total resistor, the second end of the first body region 1 divided resistor is respectively connected to the second end of the body region bias resistor of each switch unit in the first group of switch units, the second end of the second body region 1 divided resistor is respectively connected to the second end of the body region bias resistor of each switch unit in the second group of switch units, and the second end of the third body region 1 divided resistor is respectively connected to the second end of the body region bias resistor of each switch unit in the third group of switch units.

[0022] In an optional implementation manner, the first switch unit group includes a first switch unit, a second switch unit, a third switch unit and a fourth switch unit;

[0023] The second switch unit group includes a fifth switch unit, a sixth switch unit, a seventh switch unit and an eighth switch unit;

[0024] The third switch unit group includes a ninth switch unit, a tenth switch unit, an eleventh switch unit and a twelfth switch unit;

[0025] The second end of the first gate bias resistor of the first switch unit, the second end of the second gate bias resistor of the second switch unit, the second end of the third gate bias resistor of the third switch unit, and the second end of the fourth gate bias resistor of the fourth switch unit are respectively connected to the second end of the first gate 1-divided resistor; the second end of the first body bias resistor of the first switch unit, the second end of the second body bias resistor of the second switch unit, the second end of the third body bias resistor of the third switch unit, and the second end of the fourth body bias resistor of the fourth switch unit are respectively connected to the second end of the first body 1-divided resistor;

[0026] The second end of the fifth gate bias resistor of the fifth switch unit, the second end of the sixth gate bias resistor of the sixth switch unit, the second end of the seventh gate bias resistor of the seventh switch unit, and the second end of the eighth gate bias resistor of the eighth switch unit are respectively connected to the second end of the second gate 1-divided resistor; the second end of the fifth body region bias resistor of the fifth switch unit, the second end of the sixth body region bias resistor of the sixth switch unit, the second end of the seventh body region bias resistor of the seventh switch unit, and the second end of the eighth body region bias resistor of the eighth switch unit are respectively connected to the second end of the second body region 1-divided resistor;

[0027] The second end of the ninth gate bias resistor of the ninth switch unit, the second end of the tenth gate bias resistor of the tenth switch unit, the second end of the eleventh gate bias resistor of the eleventh switch unit, and the second end of the twelfth gate bias resistor of the twelfth switch unit are respectively connected to the second end of the third gate 1-divided resistor; the second end of the ninth body region bias resistor of the ninth switch unit, the second end of the tenth body region bias resistor of the tenth switch unit, the second end of the eleventh body region bias resistor of the eleventh switch unit, and the second end of the twelfth body region bias resistor of the twelfth switch unit are respectively connected to the second end of the third body region 1-divided resistor.

[0028] In an optional embodiment, the first switch unit includes a first NMOS transistor, a first gate bias resistor, a first body bias resistor and a first drain-source linearization resistor; the gate of the first NMOS transistor is connected to the first end of the first gate bias resistor, the substrate of the first NMOS transistor is connected to the first end of the first body bias resistor, and the source and drain of the first NMOS transistor are connected to each other through the first drain-source linearization resistor;

[0029] The second switch unit includes a second NMOS transistor, a second gate bias resistor, a second body bias resistor and a second drain-source linearization resistor; the gate of the second NMOS transistor is connected to the first end of the second gate bias resistor, the substrate of the second NMOS transistor is connected to the first end of the second body bias resistor, and the source and drain of the second NMOS transistor are connected to each other through the second drain-source linearization resistor;

[0030] The third switch unit includes a third NMOS transistor, a third gate bias resistor, a third body bias resistor and a third drain-source linearization resistor; the gate of the third NMOS transistor is connected to the first end of the third gate bias resistor, the substrate of the third NMOS transistor is connected to the first end of the third body bias resistor, and the source and drain of the third NMOS transistor are connected to each other through the third drain-source linearization resistor;

[0031] The fourth switch unit includes a fourth NMOS transistor, a fourth gate bias resistor, a fourth body bias resistor and a fourth drain-source linearization resistor; the gate of the fourth NMOS transistor is connected to the first end of the fourth gate bias resistor, the substrate of the fourth NMOS transistor is connected to the first end of the fourth body bias resistor, and the source and drain of the fourth NMOS transistor are connected to each other through the fourth drain-source linearization resistor;

[0032] The fifth switch unit includes a fifth NMOS transistor, a fifth gate bias resistor, a fifth body bias resistor and a fifth drain-source linearization resistor; the gate of the fifth NMOS transistor is connected to the first end of the fifth gate bias resistor, the substrate of the fifth NMOS transistor is connected to the first end of the fifth body bias resistor, and the source and drain of the fifth NMOS transistor are connected to each other through the fifth drain-source linearization resistor;

[0033] The sixth switch unit includes a sixth NMOS transistor, a sixth gate bias resistor, a sixth body bias resistor and a sixth drain-source linearization resistor; the gate of the sixth NMOS transistor is connected to the first end of the sixth gate bias resistor, the substrate of the sixth NMOS transistor is connected to the first end of the sixth body bias resistor, and the source and drain of the sixth NMOS transistor are connected to each other through the sixth drain-source linearization resistor;

[0034] The seventh switch unit includes a seventh NMOS transistor, a seventh gate bias resistor, a seventh body bias resistor and a seventh drain-source linearization resistor; the gate of the seventh NMOS transistor is connected to the first end of the seventh gate bias resistor, the substrate of the seventh NMOS transistor is connected to the first end of the seventh body bias resistor, and the source and drain of the seventh NMOS transistor are connected to each other through the seventh drain-source linearization resistor;

[0035] The eighth switch unit includes an eighth NMOS transistor, an eighth gate bias resistor, an eighth body bias resistor and an eighth drain-source linearization resistor; the gate of the eighth NMOS transistor is connected to the first end of the eighth gate bias resistor, the substrate of the eighth NMOS transistor is connected to the first end of the eighth body bias resistor, and the source and drain of the eighth NMOS transistor are connected to each other through the eighth drain-source linearization resistor;

[0036] The ninth switch unit includes a ninth NMOS transistor, a ninth gate bias resistor, a ninth body bias resistor and a ninth drain-source linearization resistor; the gate of the ninth NMOS transistor is connected to the first end of the ninth gate bias resistor, the substrate of the ninth NMOS transistor is connected to the first end of the ninth body bias resistor, and the source and drain of the ninth NMOS transistor are connected to each other through the ninth drain-source linearization resistor;

[0037] The tenth switch unit includes a tenth NMOS transistor, a tenth gate bias resistor, a tenth body bias resistor and a tenth drain-source linearization resistor; the gate of the tenth NMOS transistor is connected to the first end of the tenth gate bias resistor, the substrate of the tenth NMOS transistor is connected to the first end of the tenth body bias resistor, and the source and drain of the tenth NMOS transistor are connected to each other through the tenth drain-source linearization resistor;

[0038] The eleventh switch unit includes an eleventh NMOS transistor, an eleventh gate bias resistor, an eleventh integral region bias resistor and an eleventh drain-source linearization resistor; the gate of the eleventh NMOS transistor is connected to the first end of the eleventh gate bias resistor, the substrate of the eleventh NMOS transistor is connected to the first end of the eleventh integral region bias resistor, and the source and drain of the eleventh NMOS transistor are connected to each other through the eleventh drain-source linearization resistor;

[0039] The twelfth switch unit includes a twelfth NMOS transistor, a twelfth gate bias resistor, a twelfth body bias resistor and a twelfth drain-source linearization resistor; the gate of the twelfth NMOS transistor is connected to the first end of the twelfth gate bias resistor, the substrate of the twelfth NMOS transistor is connected to the first end of the twelfth body bias resistor, and the source and drain of the twelfth NMOS transistor are interconnected through the twelfth drain-source linearization resistor.

[0040] The beneficial effects brought about by the technical solution provided in the embodiment of the present application include: through the switch stack of the k-order common resistor, the gate bias voltage and the body bias voltage can be transmitted to the gate bias resistor and the body bias resistor of the switch unit through the k-order gate total divided resistor network and the k-order body total divided resistor network respectively, which can increase the resistance value of the bias resistor and reduce the leakage current, thereby reducing the insertion loss and improving the power capacity, and will not occupy too much additional layout area, effectively saving the layout area.

[0041] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below and in part will become apparent from the description below or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application for those skilled in the art by referring to specific embodiments. In the drawings:

[0043] Figure 1 A circuit diagram of a specific example of a switch stack in an embodiment of the present application;

[0044] Figure 2 A schematic diagram of a specific example of a radio frequency switch in an embodiment of the present application;

[0045] Figure 3 A circuit diagram of a specific example of a three-order total divided resistance network in an embodiment of the present application;

[0046] Figure 4 A circuit diagram of a specific example of a switch stack of a 2nd-order common resistor in an embodiment of the present application;

[0047] Figure 5 A circuit diagram of a specific example of a 12-stage switch stack with a 2-stage common resistor in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the technical solutions and beneficial effects of the embodiments of the present application more obvious and easy to understand, the following is a detailed description by listing specific embodiments. Among them, the drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meaning as those in the technical field to which the embodiments of the present application belong.

[0049] It should be noted that the terms "first", "second", etc. may be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. When describing "first", it does not mean that there must be a "second"; and when discussing "second", it does not mean that there must be a "first" in this application. The singular forms of "one", "an" and "said / the" may also be intended to include plural forms, unless the context clearly indicates otherwise. The term "includes" is to determine the existence of the included features, but does not exclude the existence or addition of one or more other features. The term "and / or" includes any and all combinations of the relevant listed items. The term "plurality" means two or more.

[0050] In the present application embodiment, Figure 1 As shown, the switch stack 01 can be mainly composed of multiple switch units 011 connected in series, that is, a transistor stacking method. Multiple switch units 011 connected in series can be called a stacking chain. By connecting multiple switch units 011 in series to form a switch stack 01, the large voltage swing to be carried can be distributed to each stacked switch unit 011, thereby significantly improving power capacity and linearity.

[0051] As a specific example, the switch unit 011 may include an NMOS transistor (N-type metal oxide semiconductor field effect transistor), a gate bias resistor Rg, a body bias resistor Rb, and a drain-source linearization resistor Rds. The gate G of the NMOS transistor may be connected to the first end of the gate bias resistor Rg, the substrate B of the NMOS transistor may be connected to the first end of the body bias resistor Rb, and the source S and drain D of the NMOS transistor may be connected to each other through the drain-source linearization resistor Rds; the second end of the gate bias resistor Rg may be configured to input a gate bias voltage, and the second end of the body bias resistor Rb may be configured to input a body bias voltage. The source S of the NMOS transistor may be connected to the drain of the NMOS transistor of the previous switch unit or configured to input a radio frequency signal, and the drain D of the NMOS transistor may be connected to the source of the NMOS transistor of the next switch unit or configured to output a radio frequency signal. The number of switch units 011 connected in series in the switch stack 01 may be used as the order of the switch stack 01 . For example, if 12 NMOS transistors are connected in series in the switch stack 01 , it may be called a 12-order switch stack.

[0052] In the embodiment of the present application, an NMOS transistor is used as the switch tube in the switch unit 011. Those skilled in the art should understand that the switch tube in the switch unit 011 may also adopt other controllable semiconductor switching devices, for example, it may include at least one of MOSFET (metal oxide semiconductor field effect transistor, MOS tube for short) and IGBT (insulated gate bipolar transistor) and other devices.

[0053] The embodiment of the present application can isolate the RF signal from the DC signal through the gate bias resistor Rg and the body bias resistor Rb, prevent the RF signal from leaking to the gate equivalent AC ground terminal, and reduce the RF loss; and can improve the voltage carrying capacity of the switch unit 011, such as the voltage carrying capacity can be increased by at least one time when the switch unit 011 is turned off, prevent the drain-gate junction of the NMOS transistor from being broken down too early, thereby improving the power capacity of the switch stack 01. And through the drain-source linearization resistor Rds, the DC potential of the drain and source ends can be stabilized, and the drain and source potential of the FET can be stabilized at the ground potential in the series-parallel switch structure, preventing the switch from generating a significant DC voltage drop in the drain and source during the switching process. The gate bias voltage and the body bias voltage are used to control the NMOS transistor to be turned on or off, thereby controlling the switch stack 01 to be turned on or off.

[0054] In an optional embodiment, the switch stack 01 may further include a gate common resistor Rgc and a body common resistor Rbc. The first end of the gate common resistor Rgc is configured to input a gate bias voltage, and the second end of the gate common resistor Rgc is respectively connected to the second end of the gate bias resistor Rg of each switch unit 011. The first end of the body common resistor Rbc is configured to input a body bias voltage, and the second end of the body common resistor Rbc is respectively connected to the second end of the body bias resistor Rb of each switch unit 011. The embodiment of the present application can further increase the bias resistance of the gate end and the substrate end through the gate common resistor Rgc and the body common resistor Rbc, thereby reducing the leakage current of the gate end and the substrate end, and can further improve the power capacity of the switch stack 01.

[0055] like Figure 1 The switch stack 01 shown in FIG. 1 includes n NMOS transistors connected in series, which can be called an n-stage switch stack with a 1-stage common resistor. For example, the gate equivalent bias resistor of the NMOS transistor is: R gc ×n+R g , where R gc Represents the resistance value of the gate common resistor Rgc, R g The calculation of the equivalent bias resistance of the body region of each NMOS transistor can be similar to the calculation of the equivalent bias resistance of the gate of the NMOS transistor, which will not be repeated here.

[0056] However, in order to reduce the leakage current at the gate and substrate ends and improve the insertion loss, the switch stack 01 of this structure can only increase the resistance values ​​of the gate common resistor Rgc and the body common resistor Rbc. The increase in resistance value will lead to an increase in the layout area, which is not desired.

[0057] To this end, the present application embodiment provides a radio frequency switch, such as Figure 2 As shown, the radio frequency switch 100 includes:

[0058] The switch stack 10 with a k-stage common resistor is configured to transmit the gate bias voltage to the gate bias resistor Rg of each switch unit 011 through a k-stage gate total divided resistor network, and transmit the body bias voltage to the body bias resistor Rb of each switch unit 011 through a k-stage body total divided resistor network, so as to control each switch unit 011 to be turned on or off, thereby controlling the switch stack 10 to turn on or off the transmission of the radio frequency signal; wherein k is a natural number greater than or equal to 2.

[0059] In the embodiment of the present application, the k-order common resistor structure in the switch stack 10 of the k-order common resistor can be relative to Figure 1The 1st-order common resistance structure in the n-order switch stack of the 1st-order common resistance shown in is defined. The 1st-order common resistance structure may have only one total resistance (i.e., the gate common resistance Rgc or the body common resistance Rbc) without its subordinate sub-resistors. The k-order common resistance structure may include a total resistance and its subordinate k-1 sub-resistors to form a k-order total sub-resistance network, which can improve the overall resistance value without increasing the resistance value of a single resistor, and can save layout area. Both the k-order gate total sub-resistance network and the k-order body total sub-resistance network can be the k-order total sub-resistance network, in which the specific connection form of each resistor can be set according to actual needs. For example, Figure 3 As shown, the 3rd-order total divided resistor network may include a total resistor R1, a 1-level divided resistors R2 and b 2-level divided resistors R3. For example, the gate bias resistor Rg of the switch unit 011 may be correspondingly connected to the 2-level divided resistor R3 of the 3rd-order gate total divided resistor network; wherein a and b are both natural numbers.

[0060] Figure 2 The left side of the switch stack 10 can be the RF input terminal RFin, and the right side of the switch stack 10 can be the RF output terminal RFout. The switch stack 10 is controlled to be turned on or off by the gate bias voltage and the body bias voltage, so that the RF signal input from the RF input terminal RFin is output from the RF output terminal RFout in a controlled manner.

[0061] The embodiment of the present application uses a switch stack of a k-order common resistor to transmit the gate bias voltage and the body bias voltage to the gate bias resistor and the body bias resistor of the switch unit through a k-order gate total divided resistor network and a k-order body total divided resistor network, respectively, thereby increasing the resistance value of the bias resistor and reducing the leakage current, thereby reducing the insertion loss and increasing the power capacity, and does not occupy too much additional layout area, thereby effectively saving the layout area.

[0062] In an optional implementation, the switch stack 10 of k-order common resistors is a switch stack of 2-order common resistors.

[0063] In the embodiment of the present application, by k=2, a 2nd-order gate total divided resistance network and a 2nd-order body region total divided resistance network can be obtained. The 2nd-order common resistance structure can be a total resistor and a plurality of 1-level divided resistances below it. The number of 1-level divided resistances can be set according to actual needs to achieve corresponding connection after grouping the switch units 011 in the switch stack 10. Since the resistance value of the total resistance in the equivalent 2nd-order common resistance structure is magnified n times (n is the order of the switch stack, i.e., an n-order switch stack), it is not necessary to use resistors with excessive resistance values, that is, the 2nd-order gate total divided resistance network and the 2nd-order body region total divided resistance network are the same, thereby greatly reducing the layout area occupied.

[0064] In an optional implementation, the switch stack of the 2nd-order common resistor includes a 2nd-order gate total divided resistor network, a 2nd-order body region total divided resistor network and an n-order switch stack; wherein n is a natural number greater than or equal to 2;

[0065] The 2-stage gate total distribution resistor network is configured to transmit the gate bias voltage to the gate bias resistor Rg of each switch unit 011 in the n-stage switch stack;

[0066] The 2nd-stage body region total divided resistor network is configured to transmit the body region bias voltage to the body region bias resistor Rb of each switch unit 011 in the n-stage switch stack.

[0067] In an alternative embodiment, if Figure 4 As shown, the 2-stage gate total divided resistance network includes a gate total resistance Rgcc and p gate 1-stage divided resistances (Rgc1, ..., Rgcp); wherein p is a natural number greater than or equal to 2;

[0068] The first end of the total gate resistor Rgcc is configured to input the gate bias voltage, and the second end of the total gate resistor Rgcc is respectively connected to the first ends of p gate 1-stage resistors; the second end of each gate 1-stage resistor is configured to output the internal gate bias voltage.

[0069] In an optional embodiment, the 2nd-order body region total divided resistance network includes a body region total resistance Rbcc and p body region 1 level divided resistances (Rbc1, ..., Rbcp);

[0070] The first end of the total body resistance Rbcc is configured to input the body bias voltage, and the second end of the total body resistance Rbcc is respectively connected to the first end of the p body 1 division resistor; the second end of each body 1 division resistor is configured to output the internal body bias voltage.

[0071] In an optional implementation, the n-stage switch stack includes p switch unit groups (switch unit group 1, ..., switch unit group p);

[0072] Each switch unit 011 in any group of switch unit groups i is configured to receive an internal gate bias voltage output from the second end of a gate 1 sub-resistor Rgci through a gate bias resistor Rg, and to receive an internal body region bias voltage output from the second end of a body region 1 sub-resistor Rbci through a body region bias resistor Rb; wherein i=1,2,…,p.

[0073] In the embodiment of the present application, the n switch units 011 in the n-stage switch stack 10 can be evenly or unevenly divided into p switch unit groups, that is, the number of switch units in each switch unit group can be equal or unequal. Correspondingly, the number of gate 1 level resistors Rgc and body 1 level resistors Rbc can also be set to p, so that each switch unit 011 in each switch unit group can be connected to a gate 1 level resistor Rgc and a body 1 level resistor Rbc, respectively, to achieve one-to-one corresponding connection.

[0074] If n switch units 011 are divided into p groups, each group consists of m switch units 011, then the gate equivalent bias resistance of the NMOS transistor in the first switch unit is: R gcc ×n+R gc1 ×m+R g1 , where R gcc Represents the total gate resistance Rgcc, R gc1 represents the resistance value of the first gate 1 sub-resistance Rgc1, R g1 represents the resistance value of the first gate bias resistor Rg1 connected to the gate of the NMOS transistor in the first switch unit. Figure 1 The gate equivalent bias resistance of the NMOS transistor is: R gc ×n+R g It can be seen that the embodiment of the present application further improves the bias resistance based on the original design, and can do so without occupying too much additional layout area.

[0075] As a specific example, Figure 5 As shown, the gate 1 divided resistors include a first gate 1 divided resistor Rgc1, a second gate 1 divided resistor Rgc2 and a third gate 1 divided resistor Rgc3;

[0076] The body region 1 divided resistors include a first body region 1 divided resistor Rbc1, a second body region 1 divided resistor Rbc2 and a third body region 1 divided resistor Rbc3;

[0077] The n-stage switch stack includes a first switch unit group 101, a second switch unit group 102 and a third switch unit group 103;

[0078] The first end of the first gate 1 divided resistor Rgc1, the first end of the second gate 1 divided resistor Rgc2, and the first end of the third gate 1 divided resistor Rgc3 are respectively connected to the second end of the gate total resistor Rgcc, the second end of the first gate 1 divided resistor Rgc1 is respectively connected to the second end of the gate bias resistor of each switch unit in the first switch unit group 101, the second end of the second gate 1 divided resistor Rgc2 is respectively connected to the second end of the gate bias resistor of each switch unit in the second switch unit group 102, and the second end of the third gate 1 divided resistor Rgc3 is respectively connected to the second end of the gate bias resistor of each switch unit in the third switch unit group 103;

[0079] The first end of the first body region 1 divided resistor Rbc1, the first end of the second body region 1 divided resistor Rbc2 and the first end of the third body region 1 divided resistor Rbc3 are respectively connected to the second end of the body region total resistor Rbcc, the second end of the first body region 1 divided resistor Rbc1 is respectively connected to the second end of the body region bias resistor of each switch unit in the first group of switch unit groups 101, the second end of the second body region 1 divided resistor Rbc2 is respectively connected to the second end of the body region bias resistor of each switch unit in the second group of switch unit groups 102, and the second end of the third body region 1 divided resistor Rbc3 is respectively connected to the second end of the body region bias resistor of each switch unit in the third group of switch unit groups 103.

[0080] As a specific example, the first switch unit group 101 includes a first switch unit, a second switch unit, a third switch unit and a fourth switch unit;

[0081] The second switch unit group 102 includes a fifth switch unit, a sixth switch unit, a seventh switch unit and an eighth switch unit;

[0082] The third switch unit group 103 includes a ninth switch unit, a tenth switch unit, an eleventh switch unit and a twelfth switch unit;

[0083] The second end of the first gate bias resistor Rg1 of the first switch unit, the second end of the second gate bias resistor Rg2 of the second switch unit, the second end of the third gate bias resistor Rg3 of the third switch unit, and the second end of the fourth gate bias resistor Rg4 of the fourth switch unit are respectively connected to the second end of the first gate 1 grading resistor Rgc1; the second end of the first body bias resistor Rb1 of the first switch unit, the second end of the second body bias resistor Rb2 of the second switch unit, the second end of the third body bias resistor Rb3 of the third switch unit, and the second end of the fourth body bias resistor Rb4 of the fourth switch unit are respectively connected to the second end of the first body 1 grading resistor Rbc1;

[0084] The second end of the fifth gate bias resistor Rg5 of the fifth switch unit, the second end of the sixth gate bias resistor Rg6 of the sixth switch unit, the second end of the seventh gate bias resistor Rg7 of the seventh switch unit, and the second end of the eighth gate bias resistor Rg8 of the eighth switch unit are respectively connected to the second end of the second gate 1 stage resistor Rgc2; the second end of the fifth body region bias resistor Rb5 of the fifth switch unit, the second end of the sixth body region bias resistor Rb6 of the sixth switch unit, the second end of the seventh body region bias resistor Rb7 of the seventh switch unit, and the second end of the eighth body region bias resistor Rb8 of the eighth switch unit are respectively connected to the second end of the second body region 1 stage resistor Rbc2;

[0085] The second end of the ninth gate bias resistor Rg9 of the ninth switch unit, the second end of the tenth gate bias resistor Rg10 of the tenth switch unit, the second end of the eleventh gate bias resistor Rg11 of the eleventh switch unit and the second end of the twelfth gate bias resistor Rg12 of the twelfth switch unit are respectively connected to the second end of the third gate 1 phase-divided resistor Rgc3; the second end of the ninth body region bias resistor Rb9 of the ninth switch unit, the second end of the tenth body region bias resistor Rb10 of the tenth switch unit, the second end of the eleventh body region bias resistor Rb11 of the eleventh switch unit and the second end of the twelfth body region bias resistor Rb12 of the twelfth switch unit are respectively connected to the second end of the third body region 1 phase-divided resistor Rbc3.

[0086] As a specific example, the first switch unit includes a first NMOS transistor M1, a first gate bias resistor Rg1, a first body bias resistor Rb1 and a first drain-source linearization resistor Rds1; the gate of the first NMOS transistor M1 is connected to the first end of the first gate bias resistor Rg1, the substrate of the first NMOS transistor M1 is connected to the first end of the first body bias resistor Rb1, and the source and drain of the first NMOS transistor M1 are connected to each other through the first drain-source linearization resistor Rds1;

[0087] The second switch unit includes a second NMOS transistor M2, a second gate bias resistor Rg2, a second body bias resistor Rb2, and a second drain-source linearization resistor Rds2; the gate of the second NMOS transistor M2 is connected to the first end of the second gate bias resistor Rg2, the substrate of the second NMOS transistor M2 is connected to the first end of the second body bias resistor Rb2, and the source and drain of the second NMOS transistor M2 are connected to each other through the second drain-source linearization resistor Rds2;

[0088] The third switch unit includes a third NMOS transistor M3, a third gate bias resistor Rg3, a third body bias resistor Rb3 and a third drain-source linearization resistor Rds3; the gate of the third NMOS transistor M3 is connected to the first end of the third gate bias resistor Rg3, the substrate of the third NMOS transistor M3 is connected to the first end of the third body bias resistor Rb3, and the source and drain of the third NMOS transistor M3 are connected to each other through the third drain-source linearization resistor Rds3;

[0089] The fourth switch unit includes a fourth NMOS transistor M4, a fourth gate bias resistor Rg4, a fourth body bias resistor Rb4 and a fourth drain-source linearization resistor Rds4; the gate of the fourth NMOS transistor M4 is connected to the first end of the fourth gate bias resistor Rg4, the substrate of the fourth NMOS transistor M4 is connected to the first end of the fourth body bias resistor Rb4, and the source and drain of the fourth NMOS transistor M4 are connected to each other through the fourth drain-source linearization resistor Rds4;

[0090] The fifth switch unit includes a fifth NMOS transistor M5, a fifth gate bias resistor Rg5, a fifth body bias resistor Rb5 and a fifth drain-source linearization resistor Rds5; the gate of the fifth NMOS transistor M5 is connected to the first end of the fifth gate bias resistor Rg5, the substrate of the fifth NMOS transistor M5 is connected to the first end of the fifth body bias resistor Rb5, and the source and drain of the fifth NMOS transistor M5 are connected to each other through the fifth drain-source linearization resistor Rds5;

[0091] The sixth switch unit includes a sixth NMOS transistor M6, a sixth gate bias resistor Rg6, a sixth body bias resistor Rb6 and a sixth drain-source linearization resistor Rds6; the gate of the sixth NMOS transistor M6 is connected to the first end of the sixth gate bias resistor Rg6, the substrate of the sixth NMOS transistor M6 is connected to the first end of the sixth body bias resistor Rb6, and the source and drain of the sixth NMOS transistor M6 are connected to each other through the sixth drain-source linearization resistor Rds6;

[0092] The seventh switch unit includes a seventh NMOS transistor M7, a seventh gate bias resistor Rg7, a seventh body bias resistor Rb7 and a seventh drain-source linearization resistor Rds7; the gate of the seventh NMOS transistor M7 is connected to the first end of the seventh gate bias resistor Rg7, the substrate of the seventh NMOS transistor M7 is connected to the first end of the seventh body bias resistor Rb7, and the source and drain of the seventh NMOS transistor M7 are connected to each other through the seventh drain-source linearization resistor Rds7;

[0093] The eighth switch unit includes an eighth NMOS transistor M8, an eighth gate bias resistor Rg8, an eighth body bias resistor Rb8 and an eighth drain-source linearization resistor Rds8; the gate of the eighth NMOS transistor M8 is connected to the first end of the eighth gate bias resistor Rg8, the substrate of the eighth NMOS transistor M8 is connected to the first end of the eighth body bias resistor Rb8, and the source and drain of the eighth NMOS transistor M8 are connected to each other through the eighth drain-source linearization resistor Rds8;

[0094] The ninth switch unit includes a ninth NMOS transistor M9, a ninth gate bias resistor Rg9, a ninth body bias resistor Rb9 and a ninth drain-source linearization resistor Rds9; the gate of the ninth NMOS transistor M9 is connected to the first end of the ninth gate bias resistor Rg9, the substrate of the ninth NMOS transistor M9 is connected to the first end of the ninth body bias resistor Rb9, and the source and drain of the ninth NMOS transistor M9 are connected to each other through the ninth drain-source linearization resistor Rds9;

[0095] The tenth switch unit includes a tenth NMOS transistor M10, a tenth gate bias resistor Rg10, a tenth body bias resistor Rb10 and a tenth drain-source linearization resistor Rds10; the gate of the tenth NMOS transistor M10 is connected to the first end of the tenth gate bias resistor Rg10, the substrate of the tenth NMOS transistor M10 is connected to the first end of the tenth body bias resistor Rb10, and the source and drain of the tenth NMOS transistor M10 are connected to each other through the tenth drain-source linearization resistor Rds10;

[0096] The eleventh switch unit includes an eleventh NMOS transistor M11, an eleventh gate bias resistor Rg11, an eleventh integrated region bias resistor Rb11 and an eleventh drain-source linearization resistor Rds11; the gate of the eleventh NMOS transistor M11 is connected to the first end of the eleventh gate bias resistor Rg11, the substrate of the eleventh NMOS transistor M11 is connected to the first end of the eleventh integrated region bias resistor Rb11, and the source and drain of the eleventh NMOS transistor M11 are connected to each other through the eleventh drain-source linearization resistor Rds11;

[0097] The twelfth switch unit includes a twelfth NMOS transistor M12, a twelfth gate bias resistor Rg12, a twelfth body bias resistor Rb12 and a twelfth drain-source linearization resistor Rds12; the gate of the twelfth NMOS transistor M12 is connected to the first end of the twelfth gate bias resistor Rg12, the substrate of the twelfth NMOS transistor M12 is connected to the first end of the twelfth body bias resistor Rb12, and the source and drain of the twelfth NMOS transistor M12 are interconnected through the twelfth drain-source linearization resistor Rds12.

[0098] The embodiment of the present application can significantly reduce the layout area when the target equivalent value of the bias resistor is determined. For example, in a 12-stage switch stack, when the Gate requires a 600kΩ bias resistor, the traditional method can directly add a 600kΩ gate bias resistor Rg connected to the gate of the NMOS transistor. Or you can use Figure 1 In the structure shown in FIG. 1 , the gate bias resistor Rg is 300 kΩ, and a 25 kΩ gate common resistor Rgc is added, then the equivalent bias resistor of the gate is 300 kΩ+25 kΩ×12=600 kΩ. Figure 5 In the structure shown, the first gate bias resistor Rg1 to the twelfth gate bias resistor Rg12 can all be 100kΩ, the first gate 1 sub-resistance Rgc1 to the third gate 1 sub-resistance Rgc3 can all be 50kΩ, and the total gate resistance Rgcc can be 25kΩ, then the equivalent bias resistance of the Gate is 100kΩ+50kΩ×4+25kΩ×12=600kΩ. But obviously, Figure 5 In the structure shown, the resistance of each resistor is smaller, the gate bias resistor Rg directly connected to the gate of the NMOS transistor is greatly reduced, and the layout area is greatly reduced. In addition, the reduction of the layout area can also reduce the parasitic introduced by the resistor.

[0099] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes may be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A radio frequency switch, characterized in that: The radio frequency switch comprises: A switch stack with a k-order common resistor is configured to transmit a gate bias voltage to the gate bias resistor of each switch unit through a k-order gate total divided resistor network, and to transmit a body bias voltage to the body bias resistor of each switch unit through a k-order body total divided resistor network, so as to control each switch unit to be turned on or off, thereby controlling the switch stack to turn on or off the transmission of the radio frequency signal; wherein k is a natural number greater than or equal to 2.

2. The radio frequency switch according to claim 1, characterized in that: The switch stack of the k-order common resistor is a switch stack of the 2-order common resistor.

3. The radio frequency switch according to claim 2, characterized in that: The switch stack of the second-order common resistor includes a second-order gate total divided resistor network, a second-order body region total divided resistor network and an n-order switch stack; wherein n is a natural number greater than or equal to 2; The 2-stage gate total divided resistance network is configured to transmit a gate bias voltage to a gate bias resistor of each switch unit in the n-stage switch stack; The 2nd-stage body region total divided resistance network is configured to transmit a body region bias voltage to a body region bias resistor of each switch unit in the n-stage switch stack.

4. The radio frequency switch according to claim 3, characterized in that: The 2-stage gate total divided resistance network includes a gate total resistance and p gate 1-stage divided resistances; wherein p is a natural number greater than or equal to 2; The first end of the total gate resistor is configured to input a gate bias voltage, and the second end of the total gate resistor is respectively connected to the first ends of p gate 1-stage resistors; the second end of each gate 1-stage resistor is configured to output an internal gate bias voltage.

5. The radio frequency switch according to claim 4, characterized in that: The 2nd-order body region total divided resistance network includes the body region total resistance and the p-body region 1-order divided resistance; The first end of the total body resistance is configured to input the body bias voltage, and the second end of the total body resistance is respectively connected to the first end of the p body 1 division resistor; the second end of each body 1 division resistor is configured to output the internal body bias voltage.

6. The radio frequency switch according to claim 5, characterized in that: The n-stage switch stack includes p groups of switch units; Each switch cell in any group of switch cells is configured to receive the internal gate bias voltage output from the second end of a gate 1 stage resistor through a gate bias resistor, and to receive the internal body bias voltage output from the second end of a body 1 stage resistor through a body bias resistor.

7. The radio frequency switch according to claim 5 or 6, characterized in that: The gate 1 divided resistors include a first gate 1 divided resistor, a second gate 1 divided resistor and a third gate 1 divided resistor; The body region 1 divided resistors include a first body region 1 divided resistor, a second body region 1 divided resistor and a third body region 1 divided resistor; The n-stage switch stack includes a first switch unit group, a second switch unit group and a third switch unit group; The first end of the first gate 1 divided resistor, the first end of the second gate 1 divided resistor, and the first end of the third gate 1 divided resistor are respectively connected to the second end of the gate total resistor, the second end of the first gate 1 divided resistor is respectively connected to the second end of the gate bias resistor of each switch unit in the first group of switch units, the second end of the second gate 1 divided resistor is respectively connected to the second end of the gate bias resistor of each switch unit in the second group of switch units, and the second end of the third gate 1 divided resistor is respectively connected to the second end of the gate bias resistor of each switch unit in the third group of switch units; The first end of the first body region 1 divided resistor, the first end of the second body region 1 divided resistor and the first end of the third body region 1 divided resistor are respectively connected to the second end of the body region total resistor, the second end of the first body region 1 divided resistor is respectively connected to the second end of the body region bias resistor of each switch unit in the first group of switch units, the second end of the second body region 1 divided resistor is respectively connected to the second end of the body region bias resistor of each switch unit in the second group of switch units, and the second end of the third body region 1 divided resistor is respectively connected to the second end of the body region bias resistor of each switch unit in the third group of switch units.

8. The radio frequency switch according to claim 7, characterized in that: The first switch unit group includes a first switch unit, a second switch unit, a third switch unit and a fourth switch unit; The second switch unit group includes a fifth switch unit, a sixth switch unit, a seventh switch unit and an eighth switch unit; The third switch unit group includes a ninth switch unit, a tenth switch unit, an eleventh switch unit and a twelfth switch unit; The second end of the first gate bias resistor of the first switch unit, the second end of the second gate bias resistor of the second switch unit, the second end of the third gate bias resistor of the third switch unit, and the second end of the fourth gate bias resistor of the fourth switch unit are respectively connected to the second end of the first gate 1-divided resistor; the second end of the first body bias resistor of the first switch unit, the second end of the second body bias resistor of the second switch unit, the second end of the third body bias resistor of the third switch unit, and the second end of the fourth body bias resistor of the fourth switch unit are respectively connected to the second end of the first body 1-divided resistor; The second end of the fifth gate bias resistor of the fifth switch unit, the second end of the sixth gate bias resistor of the sixth switch unit, the second end of the seventh gate bias resistor of the seventh switch unit, and the second end of the eighth gate bias resistor of the eighth switch unit are respectively connected to the second end of the second gate 1-divided resistor; the second end of the fifth body region bias resistor of the fifth switch unit, the second end of the sixth body region bias resistor of the sixth switch unit, the second end of the seventh body region bias resistor of the seventh switch unit, and the second end of the eighth body region bias resistor of the eighth switch unit are respectively connected to the second end of the second body region 1-divided resistor; The second end of the ninth gate bias resistor of the ninth switch unit, the second end of the tenth gate bias resistor of the tenth switch unit, the second end of the eleventh gate bias resistor of the eleventh switch unit, and the second end of the twelfth gate bias resistor of the twelfth switch unit are respectively connected to the second end of the third gate 1-divided resistor; the second end of the ninth body region bias resistor of the ninth switch unit, the second end of the tenth body region bias resistor of the tenth switch unit, the second end of the eleventh body region bias resistor of the eleventh switch unit, and the second end of the twelfth body region bias resistor of the twelfth switch unit are respectively connected to the second end of the third body region 1-divided resistor.

9. The radio frequency switch according to claim 8, characterized in that: The first switch unit includes a first NMOS transistor, a first gate bias resistor, a first body bias resistor and a first drain-source linearization resistor; the gate of the first NMOS transistor is connected to the first end of the first gate bias resistor, the substrate of the first NMOS transistor is connected to the first end of the first body bias resistor, and the source and drain of the first NMOS transistor are connected to each other through the first drain-source linearization resistor; The second switch unit includes a second NMOS transistor, a second gate bias resistor, a second body bias resistor and a second drain-source linearization resistor; the gate of the second NMOS transistor is connected to the first end of the second gate bias resistor, the substrate of the second NMOS transistor is connected to the first end of the second body bias resistor, and the source and drain of the second NMOS transistor are connected to each other through the second drain-source linearization resistor; The third switch unit includes a third NMOS transistor, a third gate bias resistor, a third body bias resistor and a third drain-source linearization resistor; the gate of the third NMOS transistor is connected to the first end of the third gate bias resistor, the substrate of the third NMOS transistor is connected to the first end of the third body bias resistor, and the source and drain of the third NMOS transistor are connected to each other through the third drain-source linearization resistor; The fourth switch unit includes a fourth NMOS transistor, a fourth gate bias resistor, a fourth body bias resistor and a fourth drain-source linearization resistor; the gate of the fourth NMOS transistor is connected to the first end of the fourth gate bias resistor, the substrate of the fourth NMOS transistor is connected to the first end of the fourth body bias resistor, and the source and drain of the fourth NMOS transistor are connected to each other through the fourth drain-source linearization resistor; The fifth switch unit includes a fifth NMOS transistor, a fifth gate bias resistor, a fifth body bias resistor and a fifth drain-source linearization resistor; the gate of the fifth NMOS transistor is connected to the first end of the fifth gate bias resistor, the substrate of the fifth NMOS transistor is connected to the first end of the fifth body bias resistor, and the source and drain of the fifth NMOS transistor are connected to each other through the fifth drain-source linearization resistor; The sixth switch unit includes a sixth NMOS transistor, a sixth gate bias resistor, a sixth body bias resistor and a sixth drain-source linearization resistor; the gate of the sixth NMOS transistor is connected to the first end of the sixth gate bias resistor, the substrate of the sixth NMOS transistor is connected to the first end of the sixth body bias resistor, and the source and drain of the sixth NMOS transistor are connected to each other through the sixth drain-source linearization resistor; The seventh switch unit includes a seventh NMOS transistor, a seventh gate bias resistor, a seventh body bias resistor and a seventh drain-source linearization resistor; the gate of the seventh NMOS transistor is connected to the first end of the seventh gate bias resistor, the substrate of the seventh NMOS transistor is connected to the first end of the seventh body bias resistor, and the source and drain of the seventh NMOS transistor are connected to each other through the seventh drain-source linearization resistor; The eighth switch unit includes an eighth NMOS transistor, an eighth gate bias resistor, an eighth body bias resistor and an eighth drain-source linearization resistor; the gate of the eighth NMOS transistor is connected to the first end of the eighth gate bias resistor, the substrate of the eighth NMOS transistor is connected to the first end of the eighth body bias resistor, and the source and drain of the eighth NMOS transistor are connected to each other through the eighth drain-source linearization resistor; The ninth switch unit includes a ninth NMOS transistor, a ninth gate bias resistor, a ninth body bias resistor and a ninth drain-source linearization resistor; The gate of the ninth NMOS transistor is connected to the first end of the ninth gate bias resistor, the substrate of the ninth NMOS transistor is connected to the first end of the ninth body bias resistor, and the source and drain of the ninth NMOS transistor are connected to each other through a ninth drain-source linearization resistor; The tenth switch unit includes a tenth NMOS transistor, a tenth gate bias resistor, a tenth body bias resistor and a tenth drain-source linearization resistor; the gate of the tenth NMOS transistor is connected to the first end of the tenth gate bias resistor, the substrate of the tenth NMOS transistor is connected to the first end of the tenth body bias resistor, and the source and drain of the tenth NMOS transistor are connected to each other through the tenth drain-source linearization resistor; The eleventh switch unit includes an eleventh NMOS transistor, an eleventh gate bias resistor, an eleventh integral region bias resistor and an eleventh drain-source linearization resistor; the gate of the eleventh NMOS transistor is connected to the first end of the eleventh gate bias resistor, the substrate of the eleventh NMOS transistor is connected to the first end of the eleventh integral region bias resistor, and the source and drain of the eleventh NMOS transistor are connected to each other through the eleventh drain-source linearization resistor; The twelfth switch unit includes a twelfth NMOS transistor, a twelfth gate bias resistor, a twelfth body bias resistor and a twelfth drain-source linearization resistor; the gate of the twelfth NMOS transistor is connected to the first end of the twelfth gate bias resistor, the substrate of the twelfth NMOS transistor is connected to the first end of the twelfth body bias resistor, and the source and drain of the twelfth NMOS transistor are interconnected through the twelfth drain-source linearization resistor.

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