Signal conversion circuit

Abstract

The utility model relates to a signal conversion circuit. The signal conversion circuit comprises a first transmission circuit, a conversion chip and a second transmission circuit, the input end of the first transmission circuit is suitable for accessing a to-be-converted signal; the output end of the first transmission circuit is connected with the input end of the second transmission circuit through the conversion chip; the output end of the second transmission circuit is suitable for outputting a conversion signal; the first transmission circuit is provided with an anti-interference module; the output end of the anti-interference module is electrically connected with the conversion chip; the second transmission circuit comprises a voltage amplifying circuit and a first filtering module; the input end of the voltage amplification circuit is electrically connected with the conversion chip; the output end of the voltage amplifying circuit is connected with the input end of the first filtering module. The anti-interference module, the voltage amplification circuit and the first filtering module are arranged to carry out voltage stabilization filtering on the first transmission circuit and the second transmission circuit at the two ends of the conversion chip, and high-precision and stable transmission of analog signals and digital signals is guaranteed.

Description

Technical Field

[0001] The present application relates to the technical field of signal conversion, and in particular to a signal conversion circuit. Background Art

[0002] ADC refers to analog / digital conversion or digital / analog conversion. Analog / digital conversion is to convert continuous analog signals into discrete digital signals, thereby achieving the conversion between electrical analog quantities and digital quantities. The conversion accuracy of the A / D converter is related to the structure of the integrated chip of the A / D converter and the interface circuit configuration. To obtain high-precision A / D conversion results, it is necessary to first ensure that the signal transmission of the external circuit configuration is stable. If the external circuit configuration is unstable and the interference signal is large, it will cause a large A / D conversion error. When the error exceeds a certain level, the A / D conversion is prone to errors.

[0003] Therefore, how to improve the signal transmission stability of the external circuit configuration and reduce the error between analog-to-digital conversion has become an urgent problem to be solved. Summary of the invention

[0004] In view of this, the present application proposes a signal conversion circuit suitable for improving the signal transmission stability of an external circuit configuration.

[0005] According to one aspect of the present application, there is provided a signal conversion circuit, comprising: a first transmission circuit, a conversion chip and a second transmission circuit;

[0006] The input end of the first transmission circuit is suitable for receiving the signal to be converted; the output end of the first transmission circuit is connected to the input end of the second transmission circuit through the conversion chip; the output end of the second transmission circuit is suitable for outputting the conversion signal;

[0007] The first transmission circuit is provided with an anti-interference module; the output end of the anti-interference module is electrically connected to the conversion chip;

[0008] The second transmission circuit includes: a voltage amplifying circuit and a first filtering module; the input end of the voltage amplifying circuit is electrically connected to the conversion chip; and the output end of the voltage amplifying circuit is connected to the input end of the first filtering module.

[0009] In a possible implementation, the anti-interference module includes: two or more isolation chips;

[0010] The output ends of the two or more isolation chips are electrically connected to the conversion chip.

[0011] In a possible implementation, two isolation chips are provided.

[0012] In a possible implementation, the voltage amplification circuit includes: a first operational amplifier and a second operational amplifier;

[0013] The non-inverting input terminal of the first operational amplifier is electrically connected to the conversion chip, the output terminal of the first operational amplifier is electrically connected to the non-inverting input terminal of the second operational amplifier; the output terminal of the second operational amplifier is electrically connected to the input terminal of the first filtering module.

[0014] In a possible implementation, the second transmission circuit further includes: a third operational amplifier;

[0015] The output end of the first filter module is electrically connected to the inverting input end of the third operational amplifier.

[0016] In a possible implementation, the second transmission circuit further includes: a second filtering module;

[0017] The output end of the third operational amplifier is electrically connected to the input end of the second filtering module; and the output end of the second filtering module is suitable for outputting a signal.

[0018] In a possible implementation, the first filtering module is provided with a first capacitor and a first resistor;

[0019] The first capacitor is electrically connected to the first resistor.

[0020] In a possible implementation, the second filtering module is provided with a second capacitor and a second resistor;

[0021] The second capacitor is electrically connected to the second resistor.

[0022] In a possible implementation, the isolation chip model is ADuM1200.

[0023] Beneficial effects: The overall structure of the present application is complete and the functions are perfect. By setting an anti-interference module, a voltage amplification circuit and a first filtering module, the first transmission circuit and the second transmission circuit at both ends of the conversion chip are stabilized and filtered, thereby ensuring high-precision and stable transmission of analog signals and digital signals.

[0024] Other features and aspects of the present application will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present application and, together with the description, serve to explain the principles of the present application.

[0026] Figure 1 A circuit diagram showing a first transmission circuit according to an embodiment of the present application;

[0027] Figure 2 A circuit diagram of a second transmission circuit according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0028] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0029] Among them, it needs to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the utility model or simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the utility model.

[0030] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0031] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0032] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0033] Figure 1 A circuit diagram showing a first transmission circuit according to an embodiment of the present application; Figure 2 FIG. 2 shows a circuit diagram of a second transmission circuit according to an embodiment of the present application. Figure 1As shown, the signal conversion circuit includes: a first transmission circuit, a conversion chip U3 and a second transmission circuit; the input end of the first transmission circuit is suitable for receiving the signal to be converted; the output end of the first transmission circuit is connected to the input end of the second transmission circuit through the conversion chip U3; the output end of the second transmission circuit is suitable for outputting the conversion signal; the first transmission circuit is provided with an anti-interference module 100; the output end of the anti-interference module 100 is electrically connected to the conversion chip U3; the second transmission circuit includes: a voltage amplification circuit 200 and a first filtering module 300; the input end of the voltage amplification circuit 200 is electrically connected to the conversion chip U3; the output end of the voltage amplification circuit 200 is connected to the input end of the first filtering module 300.

[0034] Here, it should be noted that the first transmission circuit is suitable for accessing the signal to be converted and transmitting the signal to the conversion chip U3; the conversion chip U3 is suitable for converting the analog signal into a digital signal; the second transmission circuit is suitable for receiving the converted signal and transmitting it to the host computer; the anti-interference module 100 on the first transmission circuit is suitable for reducing interference between systems, ensuring the stable transmission of analog signals to the conversion chip U3, and the voltage amplification circuit 200 is suitable for reducing the impact of voltage fluctuations on signal transmission and improving the stability of signal transmission. The first filtering module 300 is suitable for reducing signal interference between systems and ensuring the stable transmission of digital signals. The overall structure of this application is complete and the functions are perfect. By setting the anti-interference module 100, the voltage amplification circuit 200 and the first filtering module 300, the first transmission circuit and the second transmission circuit at both ends of the conversion chip U3 are stabilized and filtered, ensuring the high-precision and stable transmission of analog signals and digital signals.

[0035] In a possible implementation, the anti-interference module 100 includes: more than two isolation chips; the output ends of the more than two isolation chips are electrically connected to the conversion chip U3. Here, it should be noted that when the digital signal and the analog signal are transmitted, the isolation chip can have a very high resistance isolation characteristic, a high isolation voltage, and a strong anti-interference ability, thereby improving the stability of the first transmission circuit when transmitting the analog signal.

[0036] Furthermore, there are two isolation chips. The two isolation chips are respectively a first isolation chip U1 and a second isolation chip U2; the input ends of the first isolation chip U1 and the second isolation chip U2 are both connected to the CPU, and the output ends of the first isolation chip U1 and the second isolation chip U2 are both electrically connected to the conversion chip U3. Figure 1As shown, the first pin (VDD1 end) of the first isolation chip U1 is connected to a +3.3V voltage; the second pin (VIA end) of the first isolation chip U1 is electrically connected to the main device output end of the CPU and is suitable for connecting to the DA-MOSI signal; the third pin (VIB end) of the first isolation chip U1 is electrically connected to the clock module of the CPU and is suitable for connecting to the DA-SPI_CLK signal; the fourth pin (ground end) of the first isolation chip U1 is grounded; the fifth pin (ground end) of the first isolation chip U1 is grounded; the sixth pin (VOB end) of the first isolation chip U1 is electrically connected to the conversion chip U3 and is suitable for outputting the SPI_CLK signal; the seventh pin (VOA end) of the first isolation chip U1 is electrically connected to the conversion chip U3 and is suitable for outputting the MOSI signal; the eighth pin (VDD2 end) of the first isolation chip U1 is connected to a +5V voltage.

[0037] In a possible implementation, it also includes: a capacitor C1, which is electrically connected to the first isolation chip U1; further, one electrode of the capacitor C1 is electrically connected to a circuit connected to the first pin (VDD1 terminal) of the first isolation chip U1 with a +3.3V voltage, and the other electrode of the capacitor C1 is grounded.

[0038] In a possible implementation, it also includes: a capacitor C2, which is electrically connected to the first isolation chip U1; further, one electrode of the capacitor C2 is electrically connected to the circuit of the 8th pin (VDD2 terminal) of the first isolation chip U1 connected to the +5V voltage, and the other electrode of the capacitor C2 is grounded.

[0039] like Figure 1 As shown, the first pin (VDD1 end) of the second isolation chip U2 is connected to a +3.3V voltage; the second pin (VIA end) of the second isolation chip U2 is electrically connected to the high-function I / O unit of the CPU and is suitable for connecting to the DA-CSI signal; the third pin (VIB end) of the second isolation chip U2 is electrically connected to the CPU and is suitable for connecting to the DA-CNV signal; the fourth pin (ground end) of the second isolation chip U2 is grounded; the fifth pin (ground end) of the second isolation chip U2 is grounded; the sixth pin (VOB end) of the second isolation chip U2 is electrically connected to the conversion chip U3 and is suitable for outputting the CVN signal; the seventh pin (VOA end) of the second isolation chip U2 is electrically connected to the conversion chip U3 and is suitable for outputting the CSI signal; the eighth pin (VDD2 end) of the second isolation chip U2 is connected to a +5V voltage.

[0040] In a possible implementation, it further includes: a capacitor C3, the capacitor C3 is electrically connected to the second isolation chip U2; further, one electrode of the capacitor C3 is electrically connected to the circuit of the first pin (VDDA terminal) of the second isolation chip U2 connected to the +3.3V voltage, and the other electrode of the capacitor C3 is grounded. It should be noted that the capacitor C3 is suitable for filtering the connected voltage signal.

[0041] In a possible implementation, it further includes: a capacitor C4, which is electrically connected to the second isolation chip U2; further, one electrode of the capacitor C4 is electrically connected to the circuit of the 8th pin (VDDA terminal) of the second isolation chip U2 connected to the +5V voltage, and the other electrode of the capacitor C4 is grounded. It should be noted that the capacitor C4 is suitable for filtering the connected voltage signal.

[0042] In a possible implementation, the first pin (DIN terminal) of the conversion chip U3 is electrically connected to the seventh pin (VOA terminal) of the first isolation chip U1, which is suitable for accessing the MOSI signal; the second pin (SCLK terminal) of the conversion chip U3 is electrically connected to the sixth pin (VOB terminal) of the first isolation chip U1, which is suitable for accessing the SPI_CLK signal; the third pin (CS terminal) of the conversion chip U3 is electrically connected to the seventh pin (VOA terminal) of the second isolation chip U2, which is suitable for accessing the CS1 signal; the fourth pin (FS terminal) of the conversion chip U3 is electrically connected to the sixth pin (VOB terminal) of the second isolation chip U2, which is suitable for accessing the CNV signal; the fifth pin (ground terminal) of the conversion chip U3 is grounded; the sixth pin of the conversion chip U3 is connected to a +2.5V voltage; the seventh pin (OUT terminal) of the conversion chip U3 outputs the converted DA signal; the eighth pin of the conversion chip U3 is connected to a +5V voltage.

[0043] Furthermore, the model of the isolation chip is TLV5616IDR.

[0044] In a possible implementation, it also includes: a resistor R1; the resistor R1 is set in a circuit that electrically connects the first pin (DIN end) of the conversion chip U3 and the seventh pin (VOA end) of the first isolation chip U1.

[0045] In a possible implementation, it also includes: a resistor R2; the resistor R2 is set in a circuit that electrically connects the second pin (SCLK terminal) of the conversion chip U3 and the sixth pin (VOB terminal) of the first isolation chip U1.

[0046] In a possible implementation, the voltage amplifier circuit 200 includes: a first operational amplifier U4A and a second operational amplifier U4B; the non-inverting input terminal of the first operational amplifier U4A is electrically connected to the conversion chip U3, and the output terminal of the first operational amplifier U4A is electrically connected to the non-inverting input terminal of the second operational amplifier U4B; the output terminal of the second operational amplifier U4B is electrically connected to the input terminal of the first filter module 300. It should be noted that the addition of two operational amplifier circuits can make the second transmission circuit have the advantages of high impedance input and low impedance output. The second operational amplifier U4B with large input impedance is equivalent to an open circuit with the front pole, and the low impedance output is equivalent to a short circuit with the rear pole circuit. The input voltage value of the rear pole circuit is equal to the output voltage value of the first operational amplifier U4A, which effectively prevents the influence of voltage fluctuations and improves efficiency.

[0047] The third pin (positive phase input terminal) of the first operational amplifier U4A is electrically connected to the seventh pin (OUT terminal) of the conversion chip U3 through the resistor R5 to receive the DA signal; the second pin (inverting phase input terminal) of the first operational amplifier U4A is connected to the +5V voltage; the fourth pin of the first operational amplifier U4A is connected to the -15V voltage; the eighth pin of the first operational amplifier U4A is connected to the +15V voltage; the first pin (output terminal) of the first operational amplifier U4A outputs the DA signal. One end of the resistor R4 is electrically connected to the second pin (inverting phase output terminal) of the first operational amplifier U4A; the other end of the resistor R4 is electrically connected to the first pin (output terminal) of the first operational amplifier U4A.

[0048] In a possible implementation, it also includes: a resistor R3; one end of the resistor R3 is connected to the second pin (inverting input terminal) of the first operational amplifier U4A, and the other end of the resistor R3 and the first pin (output terminal) of the first operational amplifier U4A are connected to a +5V voltage.

[0049] The 5th pin (positive input terminal) of the second operational amplifier U4B is electrically connected to the 1st pin (output terminal) of the first operational amplifier U4A through a resistor R6 to receive the DA signal; the 6th pin (negative input terminal) of the second operational amplifier U4B is grounded through a resistor R7; and the 7th pin (output terminal) of the second operational amplifier U4B outputs the DA signal.

[0050] In a possible implementation, it also includes: a resistor R7; one end of the resistor R7 is connected to the 6th pin (inverting input terminal) of the second operational amplifier U4B and is electrically connected to the 7th pin (output terminal) of the second operational amplifier U4B; the other end of the resistor R7 is grounded.

[0051] In a possible implementation, it also includes: a resistor R8; one end of the resistor R8 is electrically connected to the 6th pin (inverting output end) of the second operational amplifier U4B; and the other end of the resistor R8 is electrically connected to the 7th pin (output end) of the second operational amplifier U4B.

[0052] In a possible implementation, the first filter module 300 is provided with a first capacitor C5 and a first resistor R9; the first capacitor C5 is electrically connected to the first resistor R9. Figure 2 As shown, one end of the first resistor R9 is electrically connected to the 7th pin (output end) of the second operational amplifier U4B, and the other end of the first resistor R9 is electrically connected to the 2nd pin (inverting input end) of the third operational amplifier U5A. One electrode of the first capacitor C5 is connected to the circuit connecting the first resistor R9 and the second operational amplifier U4B, and the other electrode of the first resistor C5 is grounded.

[0053] In a possible implementation, the second transmission circuit further includes: a third operational amplifier U5A; the output end of the first filter module 300 is electrically connected to the input end of the third operational amplifier U5A. It should be noted that the third operational amplifier U5A plays the role of isolation protection, voltage following, buffering, and improving load capacity.

[0054] Furthermore, the second pin (inverting input terminal) of the third operational amplifier U5A is electrically connected to the seventh pin (output terminal) of the second operational amplifier U4B to receive the DA signal; the third pin (non-inverting input terminal) of the third operational amplifier U5A is electrically connected to the first pin (output terminal) of the third operational amplifier U5A; the first pin (output terminal) of the third operational amplifier U5A is connected to the host computer and is suitable for outputting the DA signal.

[0055] In a possible implementation, the second transmission circuit further includes: a second filter module 400; the output end of the third operational amplifier U5A is electrically connected to the input end of the second filter module 400; and the output end of the second filter module 400 is suitable for outputting a signal. It should be noted that the second filter module 400 is suitable for reducing interference between systems and ensuring stable transmission of digital signals.

[0056] In a possible implementation, the second filter module 400 is provided with a second capacitor C6 and a second resistor R10; the second capacitor C6 is electrically connected to the second resistor R10. The capacitance of the capacitor and the resistance of the resistor can be modified as required to achieve the required digital signal amplitude. Figure 2 As shown, one end of the second resistor R10 is electrically connected to the output end of the third operational amplifier U5A, the other end of the second resistor R10 is grounded, one electrode of the second capacitor C6 is connected to the output circuit of the second resistor R10, and the other electrode of the second capacitor C6 is grounded.

[0057] In a possible implementation, the model of the isolation chip is ADuM1200. The models of the second operational amplifier U4B, the first operational amplifier U4A, and the third operational amplifier U5A are OPA2197QOKRQ1.

[0058] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A signal conversion circuit, characterized in that: include: A first transmission circuit, a conversion chip and a second transmission circuit; The input end of the first transmission circuit is suitable for receiving the signal to be converted; the output end of the first transmission circuit is connected to the input end of the second transmission circuit through the conversion chip; the output end of the second transmission circuit is suitable for outputting the conversion signal; The first transmission circuit is provided with an anti-interference module; the output end of the anti-interference module is electrically connected to the conversion chip; The second transmission circuit includes: a voltage amplifying circuit and a first filtering module; the input end of the voltage amplifying circuit is electrically connected to the conversion chip; and the output end of the voltage amplifying circuit is connected to the input end of the first filtering module.

2. The signal conversion circuit according to claim 1, characterized in that: The anti-interference module includes: more than two isolation chips; The output ends of two or more isolation chips are electrically connected to the conversion chip.

3. The signal conversion circuit according to claim 2, characterized in that: There are two isolation chips.

4. The signal conversion circuit according to claim 1, characterized in that: The voltage amplification circuit comprises: a first operational amplifier and a second operational amplifier; The non-inverting input terminal of the first operational amplifier is electrically connected to the conversion chip, the output terminal of the first operational amplifier is electrically connected to the non-inverting input terminal of the second operational amplifier; the output terminal of the second operational amplifier is electrically connected to the input terminal of the first filtering module.

5. The signal conversion circuit according to claim 4, characterized in that: The second transmission circuit further includes: a third operational amplifier; The output end of the first filtering module is electrically connected to the inverting input end of the third operational amplifier.

6. The signal conversion circuit according to claim 5, characterized in that: The second transmission circuit further includes: a second filtering module; The output end of the third operational amplifier is electrically connected to the input end of the second filtering module; the output end of the second filtering module is suitable for outputting a signal.

7. The signal conversion circuit according to claim 6, characterized in that: The first filtering module is provided with a first capacitor and a first resistor; The first capacitor is electrically connected to the first resistor.

8. The signal conversion circuit according to claim 7, characterized in that: The second filtering module is provided with a second capacitor and a second resistor; The second capacitor is electrically connected to the second resistor.

9. The signal conversion circuit according to claim 2, characterized in that: The model of the isolation chip is ADuM1200.

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