Fine circuit structure

Abstract

The utility model provides a fine line structure. The fine line structure comprises a dielectric layer; the circuit layer comprises an adhesion layer, a seed layer, a circuit layer and a protection layer, the adhesion layer is arranged on the dielectric layer, the seed layer is arranged on the adhesion layer, the circuit layer is arranged on the seed layer, and the protection layer is arranged on the circuit layer; wherein the side wall of the circuit layer is gradually shrunk from the top of the circuit layer along a second direction, and the side wall of the seed layer is gradually shrunk from the bottom of the seed layer along a first direction. Therefore, in the process of removing part of the seed layer, the protection layer is arranged, and wet etching can etch the circuit layer along the side wall, so that the part, close to the top surface, of the side wall of the circuit layer is gradually widened, the middle part is slightly narrowed, the circuit layer is further protected from being etched too seriously, the width and the shape of a circuit are protected, and the probability of line breakage is reduced; and the electrical property and the anti-pressure capability are maintained.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor packaging, in particular to a thin circuit structure. Background Art

[0002] In the process of circuit manufacturing, as the size requirements continue to shrink (less than 2 microns), many problems that have never been encountered in the production of rough lines have emerged.

[0003] One of them is that when removing the seed layer outside the circuit, part of the circuit is easily etched away. In the production of thick circuits, the impact of this etching on electrical properties and reliability is acceptable, but in the production of fine circuits, since the amount of etching that can be tolerated is greatly reduced, once the circuit is too small or the shape changes, the probability of disconnection is greatly increased, and its electrical properties and pressure resistance will also be affected.

[0004] Therefore, how to reduce the risks of thin circuit structures due to the removal of the seed layer causing the circuits to be too thin or the shape to change, resulting in broken wires, reduced electrical properties or reduced compressive strength, etc., is a technical problem that technical personnel in this field urgently need to solve. Utility Model Content

[0005] The present application proposes a thin line structure.

[0006] In a first aspect, the present application provides a thin line structure, comprising:

[0007] Dielectric layer;

[0008] A circuit layer, comprising an adhesive layer, a seed layer, a circuit layer and a protective layer, wherein the adhesive layer is disposed on the dielectric layer, the seed layer is disposed on the adhesive layer, the circuit layer is disposed on the seed layer, and the protective layer is disposed on the circuit layer;

[0009] Wherein, a first direction is defined as passing through the seed layer and the circuit layer in sequence from the adhesive layer and pointing vertically to the protective layer, and a second direction is opposite to the first direction, and the side wall of the circuit layer gradually shrinks from the top of the circuit layer along the second direction, and the side wall of the seed layer gradually shrinks from the bottom of the seed layer along the first direction.

[0010] As a possible implementation manner, the sidewall of the adhesive layer tapers from the top and the bottom of the adhesive layer toward the center of the sidewall of the adhesive layer.

[0011] As a possible implementation manner, the tapered slope of the sidewall of the circuit layer is different from the tapered slope of the sidewall of the adhesive layer.

[0012] As a possible implementation manner, a projection of the protection layer along the second direction covers the circuit layer.

[0013] As a possible implementation manner, the horizontal width of the protection layer is greater than the horizontal width of the seed layer.

[0014] As a possible implementation manner, the horizontal width of the protection layer is greater than the horizontal width of the adhesive layer.

[0015] As a possible implementation manner, the tapered slope of the sidewall of the circuit layer is different from the tapered slope of the sidewall of the seed layer.

[0016] As a possible implementation manner, a bottom of the seed layer and a top of the adhesive layer form a protruding portion.

[0017] As a possible implementation manner, the protruding portion is an acute-angle structure.

[0018] As a possible implementation manner, the thin line structure further includes:

[0019] The inner circuit layer is arranged inside the dielectric layer, and the inner circuit layer is electrically connected to the circuit layer.

[0020] As a possible implementation manner, the inner circuit layer and the circuit layer are electrically connected via a through hole.

[0021] As a possible implementation manner, the thin line structure further includes:

[0022] An upper dielectric layer covers the circuit layer.

[0023] As a possible implementation manner, the thin line structure further includes:

[0024] The outer circuit layer is disposed above the upper dielectric layer.

[0025] As a possible implementation manner, the thin line structure further includes:

[0026] A lower dielectric layer is disposed below the dielectric layer.

[0027] As a possible implementation, the dielectric layer is ABF (Ajinomoto Build-up Film), polyimide, epoxy resin, polypropylene or acrylic acid.

[0028] As a possible implementation, the circuit layer is copper, gold, silver, aluminum, palladium, platinum or nickel alloy.

[0029] In order to reduce the risks of broken wires, decreased electrical properties or compressive strength due to the removal of a seed layer causing the wires to be too thin or the shape to change, etc. in a fine wire structure, the present application proposes a fine wire structure. In the process of removing part of the seed layer, due to the provision of a protective layer, wet etching will etch the circuit layer along the side wall, causing the part of the side wall of the circuit layer close to the top surface to gradually widen and the middle part to be slightly narrower, thereby protecting the circuit layer from being etched too severely, protecting the width and shape of the wire, reducing the chance of broken wires, and maintaining its electrical properties and compressive strength. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Other features, objects and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0031] Figure 1 It is a structural schematic diagram of a thin line structure in the prior art;

[0032] Figure 2 is a schematic structural diagram of a thin circuit structure 100 according to an embodiment of the utility model;

[0033] Figure 3 is a schematic structural diagram of a thin circuit structure 200 according to an embodiment of the utility model;

[0034] Figure 4 is a schematic structural diagram of a thin circuit structure 300 according to an embodiment of the utility model;

[0035] Figure 5 is a structural schematic diagram of a thin circuit structure 400 according to an embodiment of the utility model;

[0036] Figure 6 is a dimension marking diagram of a thin circuit structure 100 according to an embodiment of the present utility model;

[0037] Figure 7A-7D A schematic diagram of the structure of a thin circuit structure 100 at various manufacturing stages according to an embodiment of the present invention.

[0038] Description of reference numerals / symbols:

[0039] 01-dielectric layer; 02-adhesion layer; 03-seed layer; 04-circuit layer; 101-dielectric layer; 102-circuit layer; 1021-adhesion layer; 1022-seed layer; 1023-circuit layer; 1024-protective layer; 103-through hole; 104-outer circuit layer; 105-lower dielectric layer; 106-adhesion layer; 107-seed layer; 108-photoresist; 109-inner circuit layer; 110-protrusion; 111-upper dielectric layer. DETAILED DESCRIPTION

[0040] The specific implementation methods of the present application are described below in conjunction with the accompanying drawings and embodiments. Through the contents recorded in this specification, those skilled in the art can easily understand the technical problems solved by the present application and the technical effects produced. It is understood that the specific embodiments described herein are only used to explain the relevant inventions, rather than to limit the inventions. In addition, for ease of description, only the parts related to the relevant inventions are shown in the accompanying drawings.

[0041] It should be readily understood that the meanings of “on,” “over,” and “over” in this application should be interpreted in the broadest manner, so that “on” not only means “directly on something,” but also means “on something” including the presence of intermediate components or layers therebetween.

[0042] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component illustrated in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0043] The term "layer" as used herein refers to a material portion including an area with a certain thickness. The layer can extend over the entire lower or upper structure, or can have a degree less than the range of the lower or upper structure. In addition, the layer can be a region of a homogeneous or inhomogeneous continuous structure, and its thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes therebetween. The layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, one or more layers can be included therein, and / or one or more layers can be present thereon, above and / or below. A layer can include multiple layers. For example, a semiconductor layer can include one or more doped or undoped semiconductor layers, and can have the same or different materials.

[0044] The term "substrate" as used herein refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer, etc. Further alternatively, the substrate may have a semiconductor device or circuit formed therein.

[0045] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present application, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed in the present application. At the same time, the terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of narration, and are not used to limit the scope of the implementation of the present application. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present application without substantially changing the technical content.

[0046] It should also be noted that the longitudinal section corresponding to the embodiment of the present application may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the top view direction.

[0047] In addition, the embodiments and features in the embodiments of the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0048] like Figure 1 As shown, Figure 1 Schematic diagram of the structure of the thin line structure in the prior art. Figure 1 The thin line structure shown includes:

[0049] The dielectric layer 01 has an adhesive layer 02, a seed layer 03 and a circuit layer 04 arranged on top of it. In the manufacturing process, in order to remove the excess seed layer and adhesive layer, Figure 1 The fine line structure on the left side of the middle is wet etched to obtain Figure 1 The fine circuit structure shown on the right side of the figure. During the etching process, due to the etching liquid corroding the top of the circuit layer 04 from top to bottom, obvious etching will occur on both sides of the top, resulting in the formation of fine circuit structure surface. Figure 1 The change from the left to the right. After etching, the cross section of the circuit layer 04 can only retain 30% to 80% of the original area. At the same time, it will cause the fine circuit structure to produce Figure 1 The cracks or damage shown by the thin line on the right weaken the pressure resistance of the thin line structure, making it more prone to wire breakage, and its electrical properties will also be affected. The above problems are particularly obvious in the thin line structure.

[0050] In order to solve the above problems, the present application proposes a thin line structure. Figure 2 , Figure 21 is a schematic diagram of a thin circuit structure 100 according to an embodiment of the present invention. The thin circuit structure 100 includes a dielectric layer 101 and a circuit layer 102 .

[0051] The circuit layer 102 includes an adhesive layer 1021, a seed layer 1022, a circuit layer 1023 and a protective layer 1024. The adhesive layer 1021 is disposed on the dielectric layer 101, the seed layer 1022 is disposed on the adhesive layer 1021, the circuit layer 1023 is disposed on the seed layer 1022, and the protective layer 1024 is disposed on the circuit layer 1023. The circuit layer 1023 may be a multi-circuit structure.

[0052] During the manufacturing process, the protective layer 1024 generated first can protect the top of the circuit layer 1023 from being etched by subsequent processes, but the etching solution will still etch the circuit layer 1023 along the side wall, causing the part of the side wall of the circuit layer 1023 close to the top surface to gradually widen, and the middle part is slightly narrower. In other words, the side wall of the circuit layer 1023 gradually shrinks from the top of the circuit layer 1023 along the second direction (the second direction is from the protective layer 1024 through the circuit layer 1023 and the seed layer 1022 in sequence, and vertically points to the adhesive layer 1021).

[0053] Because the seed layer 1022 is etched from top to bottom, the side wall of the seed layer 1022 is gradually wider near the bottom surface, and the middle part is slightly narrower. That is to say, the side wall of the bottom of the seed layer 1022 is gradually reduced along the first direction (the first direction is from the adhesive layer 1021 through the seed layer 1022, the circuit layer 1023, and vertically points to the protective layer 1024).

[0054] Therefore, due to the provision of the protection layer 1024, the width and shape of the circuit layer 102 are protected, the probability of disconnection is reduced, and the electrical properties and pressure resistance are improved. At the same time, this design is not only low-cost, but also can balance the thermal expansion during the heat treatment process, reduce or offset the bending stress generated in the protection layer 1024 due to different thermal expansion coefficients, maintain the stability and performance of the fine circuit structure, and reduce warping.

[0055] As a possible implementation, the line width of the line layer 102 may be no greater than 2 μm, or further no greater than 1.5 μm.

[0056] As a possible implementation, the protection layer 1024 has strong etching resistance, so that its projection along the second direction can cover the entire circuit layer 102 , and its horizontal width is greater than that of the seed layer 1022 and also greater than that of the adhesive layer 1021 .

[0057] As a possible implementation, since the seed layer 1022 and the adhesive layer 1021 are etched twice, during the second etching, the seed layer 1022 can protect the top adhesive layer 1021, causing the side wall of the adhesive layer 1021 to be gradually widened near the top surface and slightly narrowed in the middle; at the same time, since the etching of the adhesive layer 1021 is from top to bottom, the side wall of the adhesive layer 1021 to be gradually widened near the bottom surface and slightly narrowed in the middle, that is, the middle part of the adhesive layer 1021 is etched to a greater extent, and the side wall of the adhesive layer 1021 will gradually shrink from the top and bottom of the adhesive layer 1021 to the center of the side wall of the adhesive layer. In this way, the bottom of the seed layer 1022 and the top of the adhesive layer 1021 will form a protruding portion 110, and the protruding portion 110 is an acute angle structure.

[0058] As a possible implementation, since the seed layer 1022 may be produced by sputtering, compared with the circuit layer 1023 formed by electroplating, it has a higher density and a denser lattice (grains). Therefore, the etching degree of the seed layer 1022 will be less than that of the circuit layer 1023, and the tapered slope of the side wall of the circuit layer 1023 may be different from the tapered slope of the side wall of the seed layer 1022.

[0059] Likewise, the adhesive layer 1021 may also be made by sputtering, and the density thereof may be different from that of the circuit layer 1023 . Therefore, the slope of the tapered sidewall of the circuit layer 1023 may be different from that of the adhesive layer 1021 .

[0060] As a possible implementation, an inner circuit layer 109 may be provided inside the dielectric layer 101, and the inner circuit layer 109 is electrically connected to the circuit layer 102. This design enables the dielectric layer 101 to not only play the role of insulation and support, but also enhance the connectivity and functionality of the circuit through the inner circuit layer 109. The provision of the inner circuit layer 109 can achieve flexible connection of the internal circuit without increasing the complexity of the external circuit, thereby improving the integration and reliability of the circuit board. Specifically, the layout and design of the inner circuit layer 109 can be adjusted according to specific application requirements, and are not limited here.

[0061] As a possible implementation, a lower dielectric layer 105 is provided below the dielectric layer 101 to support the structure above it. Optionally, a corresponding circuit structure may also be provided inside the lower dielectric layer 105 to further enhance the integration and functionality of the circuit board.

[0062] As a possible implementation, the material of the dielectric layer 101 and the lower dielectric layer 105 can be photosensitive or non-photosensitive, and can be in liquid or dry film form. The specific material can be selected from the following materials: ABF (Ajinomoto Build-up Film), polyimide (PI, Polyimide), epoxy resin (epoxy), polypropylene (PP, Polypropylene), acrylic (acrylic).

[0063] The material of the protection layer 1024 can be tungsten (W), palladium (Pd), platinum (Pt), titanium (Ti), silver (Ag), gold (Au), nickel (Ni), iron (Fe), titanium (Ti), aluminum (Al) or other materials.

[0064] The materials of the adhesion layer 1021, the seed layer 1022, and the circuit layer 1023 can be selected from the following materials and their alloys: copper, gold (Au), silver (Ag), aluminum (Al), palladium (Pd), platinum (Pt), nickel (Ni), and manufactured using metal processes such as physical vapor deposition (PVD), electroplating, electroless, printing, and potting.

[0065] The above materials and manufacturing methods can be selected according to specific application requirements and process conditions and are not limited here.

[0066] See also Figure 3 , Figure 3 FIG. 2 is a schematic diagram of a thin line structure 200 according to an embodiment of the present application. The thin line structure 200 is similar to the thin line structure 100, except that:

[0067] Compared with the fine line structure 100, the line layer 102 of the fine line structure 200 is covered by the upper dielectric layer 111, and the outer line layer 104 is arranged above the upper dielectric layer 111. In other words, the line layer 102 can be exposed to the outside or wrapped by the upper dielectric layer 111. In addition, the fine line structure 200 does not include the lower dielectric layer 105, and the inner line layer 109 is not arranged inside the dielectric layer 101.

[0068] The layout and design of the outer circuit layer 104 can be adjusted according to specific application requirements to meet different circuit connection requirements and enhance the flexibility and scalability of the thin circuit structure 200 .

[0069] See also Figure 4 , Figure 4 FIG. 3 is a schematic diagram of a thin line structure 300 according to an embodiment of the present application. The thin line structure 300 is similar to the thin line structure 100, except that:

[0070] Compared with the fine line structure 100, the circuit layer 102 and the inner circuit layer 109 of the fine line structure 300 do not adopt an isolated electrical connection method, but realize electrical connection through the through hole 103, so that the electrical connection between the circuit layer 102 and the inner circuit layer 109 is more direct and efficient, thereby improving the electrical performance of the fine line structure 300, optimizing the layout and structure of the fine line structure 300, and improving the integration and reliability.

[0071] See also Figure 5 , Figure 5 FIG. 4 is a schematic diagram of a thin line structure 400 according to an embodiment of the present application. The thin line structure 400 is similar to the thin line structure 100, except that:

[0072] Compared with the fine circuit structure 100 , the distance L7 between the projections of the circuit layer 102 and the sidewalls of the protection layer 1024 on the same side of the fine circuit structure 400 along the second direction is larger, and the curvature radius of the protruding portion 110 is larger.

[0073] Because the shallower depth and simpler shape are easier to process, the fine line structure 100 has a lower cost and a faster manufacturing speed. The fine line structure 400 uses a larger depth and a larger radius of curvature, which requires a more complex manufacturing process, so the cost of the fine line structure 400 may be higher and the manufacturing time may be longer. However, the protruding portion 110 of the fine line structure 100 is similar to the shape of a needle tip and may have higher strength and hardness, which will accumulate electric charges and generate corona, thereby causing device performance degradation or damage. The fine line structure 400 can reduce the risk of corona discharge and avoid damage to device performance by reducing sharp points and edges.

[0074] See also Figure 6 , Figure 6 1 is a dimension marking diagram of a thin circuit structure 100 according to an embodiment of the present invention.

[0075] The width L1 of the circuit layer 102 ranges from tens to hundreds of nanometers (nm);

[0076] The distance L2 between adjacent circuit layers 102 ranges from tens to hundreds of nanometers (nm);

[0077] The height L3 of the circuit layer 102 ranges from a few nanometers (nm) to hundreds of nanometers (nm);

[0078] The thickness L4 of the adhesive layer 1021 ranges from a few nanometers (nm) to hundreds of nanometers (nm);

[0079] The thickness L5 of the seed layer 1022 ranges from a few nanometers (nm) to hundreds of nanometers (nm);

[0080] The thickness L6 of the protective layer 1024 ranges from a few nanometers (nm) to hundreds of nanometers (nm);

[0081] The distance L7 between the projections of the same side walls of the circuit layer 102 and the protective layer 1024 along the second direction ranges from several nanometers (nm) to hundreds of nanometers (nm) (wherein the ratio of L7 to L5 is 0.5 to 2);

[0082] The length L8 of the protruding portion 110 ranges from several nanometers (nm) to hundreds of nanometers (nm) (wherein the ratio of L8 to L4 is 0.5 to 2).

[0083] Refer to the following Figure 7A-7D The following are the steps for manufacturing a thin circuit structure 100 according to an embodiment of the present invention:

[0084] Step 1: See Fig. 7A In step (a), an adhesive layer 106 is formed on the lower dielectric layer 105. For example, the adhesive layer 106 may be formed using a PVD technique;

[0085] Step 2: See Fig. 7A In step (b), a seed layer 107 is formed on the adhesive layer 106. For example, the seed layer 107 can be formed using PVD technology;

[0086] Step 3: See Fig. 7A In step (c), a photoresist 108 is disposed on the seed layer 107, and the step of disposing the photoresist 108 may include coating, photolithography and development to define a pattern;

[0087] Step 4: See Fig. 7A In step (d), based on the pattern defined by the photoresist 108, an inner circuit layer 109 is formed by electroplating between the photoresists 108;

[0088] Step 5: See Figure 7B Step (e) in which a portion of the photoresist 108 is etched away;

[0089] Step 6: See Figure 7B In step (f), the etched inner circuit layer 109 is completely covered with the dielectric layer 101, and an adhesive layer 1021 is formed on the top of the dielectric layer 101. For example, the adhesive layer 1021 can be formed using PVD technology;

[0090] Step 7: See Figure 7B In step (g), a seed layer 1022 is formed on the adhesive layer 1021. For example, the seed layer 1022 may be formed using a PVD technique;

[0091] Step 8: See Figure 7BIn step (h), a photoresist 108 is disposed on the seed layer 1022. The step of disposing the photoresist 108 may include coating, photolithography and development to define a pattern;

[0092] Step 9: See Figure 7C In step (i), based on the pattern defined by the photoresist 108, a circuit layer 1023 is formed by electroplating between the photoresists 108;

[0093] Step 10: See Figure 7C In step (j), forming a protective layer 1024 on the circuit layer 1023;

[0094] Step 11: See Figure 7C In step (k), a wet etching method is used to remove the seed layer 1022 that is not covered by the circuit layer 1023;

[0095] Step 12: See Fig.7D In step (l), a wet etching method is used to remove the adhesive layer 1021 not covered by the seed layer 1022;

[0096] Step 13: See Fig.7D In step (m), a complete fine line structure 100 is formed.

[0097] As used herein, the terms "substantially," "substantial," "approximately," and "about" are used to indicate and explain minor variations. For example, when used in conjunction with a numerical value, the above terms may refer to a variation range of less than or equal to ±10% of the corresponding numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, the thickness of a film or layer is "substantially uniform" and may refer to a standard deviation of less than or equal to ±10% of the average thickness of the film or layer, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces that are within 50 μm along the same plane, such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm along the same plane. Two components may be considered to be "substantially aligned" if, for example, the two components overlap or overlap within 200 μm, 150 μm, 100 μm, 50 μm, 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm. Two surfaces or components may be considered to be "substantially perpendicular" if the angle between the two surfaces or components is, for example, 90°±10°, such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°. When used in conjunction with an event or situation, the terms "substantially", "substantial", "approximately", and "about" may refer to situations where the event or situation occurs exactly as well as situations where the event or situation occurs very approximately.

Claims

1. A thin line structure, characterized in that: include: Dielectric layer; A circuit layer, comprising an adhesive layer, a seed layer, a circuit layer and a protective layer, wherein the adhesive layer is disposed on the dielectric layer, the seed layer is disposed on the adhesive layer, the circuit layer is disposed on the seed layer, and the protective layer is disposed on the circuit layer; Wherein, a first direction is defined as passing through the seed layer and the circuit layer in sequence from the adhesive layer and pointing vertically to the protective layer, and a second direction is opposite to the first direction, and the side wall of the circuit layer gradually shrinks from the top of the circuit layer along the second direction, and the side wall of the seed layer gradually shrinks from the bottom of the seed layer along the first direction.

2. The thin line structure according to claim 1, characterized in that: The sidewall of the adhesive layer tapers from the top and the bottom of the adhesive layer toward the center of the sidewall of the adhesive layer.

3. The thin line structure according to claim 2, characterized in that: The tapered slope of the sidewall of the circuit layer is different from the tapered slope of the sidewall of the adhesive layer.

4. The thin line structure according to claim 1, characterized in that: The projection of the protection layer along the second direction covers the circuit layer.

5. The thin line structure according to claim 1, characterized in that: The horizontal width of the protection layer is greater than the horizontal width of the seed layer.

6. The thin line structure according to claim 1, characterized in that: The horizontal width of the protection layer is greater than the horizontal width of the adhesive layer.

7. The thin line structure according to claim 1, characterized in that: The slope of the tapered sidewall of the circuit layer is different from the slope of the tapered sidewall of the seed layer.

8. The thin line structure according to claim 1, characterized in that: A bottom of the seed layer and a top of the adhesive layer form a protrusion.

9. The thin line structure according to claim 8, characterized in that: The protruding portion is an acute-angle structure.

10. The thin line structure according to claim 1, characterized in that: The thin line structure further includes: The inner circuit layer is arranged inside the dielectric layer, and the inner circuit layer is electrically connected to the circuit layer.

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