Pixel

Abstract

A pixel is provided that operates at a first scan rate in a first mode and at a second scan rate in a second mode, in which the pixel includes: a display element having an anode and a cathode; a first transistor controlling a magnitude of a driving current flowing to the display element according to a gate-source voltage; and a second transistor in an off state in the first mode and transferring the bias voltage to the first transistor in response to the first scan signal in the second mode.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0039031 filed on March 24, 2023 and Korean Patent Application No. 10-2023-0041534 filed on March 29, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] One or more embodiments relate to a pixel and a display device. Background Art

[0003] An organic light emitting display device includes a display element whose brightness is changed by current, such as an organic light emitting diode. One pixel of the organic light emitting display device includes a display element, a driving transistor that controls the amount of current supplied to the display element according to a voltage between a gate and a source, and a switching transistor that transmits a data voltage for controlling the brightness of the display element to the driving transistor.

[0004] The voltage between the gate and source of the driving transistor needs to be kept constant in order to maintain a constant brightness of the display element during one frame. To this end, the pixel further includes a storage capacitor connected to the gate of the driving transistor.

[0005] In order to display more vivid images, the resolution of organic light-emitting display devices is gradually increasing, and the size of pixels is gradually decreasing. In order to reduce the size of pixels, the capacity of storage capacitors is also decreasing. Accordingly, even a small leakage current changes the gate voltage of the drive transistor, and therefore, changes the brightness of the display element.

[0006] In addition, in order to reduce power consumption of an organic light emitting display device or an electronic device connected thereto, a technology of driving pixels of the display device at a low frame rate according to circumstances is being applied. Utility Model Content

[0007] One or more embodiments include a pixel in which a luminance difference can be reduced during low-frequency driving and a display device including the pixel.

[0008] According to one or more embodiments, a pixel that operates at a first scanning rate in a first mode and at a second scanning rate in a second mode includes: a display element having an anode and a cathode; a first transistor that controls the magnitude of a driving current flowing to the display element according to a gate-source voltage; and a second transistor that is in a cut-off state in the first mode and transmits a bias voltage to the first transistor in response to a first scanning signal in the second mode.

[0009] According to an embodiment, the second scanning rate may be lower than the first scanning rate.

[0010] According to an embodiment, one frame period in the second mode may include a display scan period and a self scan period, and the first scan signal may have a voltage at an off level during the display scan period and may have a pulse at an on level during the self scan period.

[0011] According to an embodiment, the width of the pulse at the on level may be greater than one horizontal scanning period (1H).

[0012] According to an embodiment, the pixel may further include: a first capacitor connected to the gate of the first transistor; a third transistor transmitting a data voltage to the source of the first transistor in response to a second scan signal; and a fourth transistor transmitting a first initialization voltage to the anode of the display element in response to the third scan signal, wherein, in the second mode, the second transistor may transmit a bias voltage to the source of the first transistor in response to the first scan signal.

[0013] According to an embodiment, a frame period in the second mode may include a display scanning period and a self-scanning period, the first scanning signal may have a voltage at a cut-off level during the display scanning period and may have a first pulse at an on-level during the self-scanning period, the second scanning signal may have a second pulse at an on-level in each of the display scanning period and the self-scanning period, and the third scanning signal may have a third pulse at an on-level in each of the display scanning period and the self-scanning period.

[0014] According to an embodiment, a width of the first pulse may be greater than a width of the second pulse and a width of the third pulse.

[0015] According to an embodiment, an interval between a falling edge of the second pulse and a falling edge of the third pulse may be one horizontal scanning period (1H).

[0016] According to an embodiment, the data voltage transmitted to the source of the first transistor in the self-scan period may be substantially the same as the bias voltage.

[0017] According to an embodiment, a level of the bias voltage may be greater than a level of the first initialization voltage.

[0018] According to an embodiment, the pixel may further include: a fifth transistor connecting the gate and the drain of the first transistor to each other in response to a fourth scanning signal, wherein a frame period in the second mode may include a display scanning period and a self-scanning period, and the fourth scanning signal may have a fourth pulse at an on-level in the display scanning period and may have a voltage at an off-level during the self-scanning period.

[0019] According to an embodiment, the pixel may further include a sixth transistor that transmits a second initialization voltage to the gate of the first transistor in response to a fifth scan signal, wherein the fifth scan signal may have a fifth pulse at an on-level during a display scan period and may have a voltage at an off-level during a self-scan period.

[0020] According to an embodiment, the second scan signal may have a second pulse at an on level in each of a display scan period and a self scan period, and a width of the fourth pulse may be substantially equal to a width of the second pulse and a width of the fifth pulse.

[0021] According to an embodiment, the pixel may further include a second capacitor connected to the source of the first transistor.

[0022] According to one or more embodiments, a pixel is provided, which operates at a first scan rate in a first mode and at a second scan rate in a second mode, and is connected to first to fifth scan lines that transmit first to fifth scan signals, respectively, an emission control line that transmits an emission control signal, a data line that transmits a data voltage, a power line that transmits a driving voltage, and first to third voltage lines that transmit a first initialization voltage, a second initialization voltage, and a bias voltage, respectively. The pixel includes: a display element having an anode and a cathode; a first capacitor having a second electrode and a first electrode connected to a power line; a first transistor having a gate connected to the second electrode of the first capacitor, a source connected to the power line, and a drain connected to the anode of the display element; a second transistor having a gate connected to the first scan line, a source connected to the data line, and a drain connected to the source of the first transistor. The pixel further includes: a third transistor having a gate connected to the second scan line, a source connected to the drain of the first transistor, and a drain connected to the gate of the first transistor; a fourth transistor having a gate connected to the third scan line, a source connected to the gate of the first transistor, and a drain connected to the first voltage line; a fifth transistor having a gate connected to the emission control line, a source connected to the power line, and a drain connected to the source of the first transistor; a sixth transistor having a gate connected to the emission control line, a source connected to the drain of the first transistor, and a drain connected to the anode of the display element; a seventh transistor having a gate connected to the fourth scan line, a source connected to the anode of the display element, and a drain connected to the second voltage line; and an eighth transistor having a gate connected to the fifth scan line, a source connected to the third voltage line, and a drain connected to the source of the first transistor, and being in an off state in the first mode.

[0023] According to an embodiment, the second scanning rate may be lower than the first scanning rate.

[0024] According to an embodiment, the pixel may further include a second capacitor having a third electrode connected to the power line and a fourth electrode connected to the source of the first transistor.

[0025] According to an embodiment, a frame period in the second mode may include a display scanning period and a self-scanning period, a first pulse at an on-level may be applied to the first scanning line in each of the display scanning period and the self-scanning period, a second pulse at an on-level may be applied to the second scanning line in the display scanning period, and a voltage at an off-level may be applied to the second scanning line during the self-scanning period, a third pulse at an on-level may be applied to the third scanning line in the display scanning period, and a voltage at an off-level may be applied to the third scanning line during the self-scanning period, a fourth pulse at an on-level may be applied to the fourth scanning line in each of the display scanning period and the self-scanning period, and a voltage at an off-level may be applied to the fifth scanning line during the display scanning period, and a fifth pulse at an on-level may be applied to the fifth scanning line in the self-scanning period.

[0026] According to an embodiment, a width of the fifth pulse may be greater than a width of the first pulse and a width of the fourth pulse.

[0027] According to one or more embodiments, a display device includes a substrate extending in a first direction and a second direction and a plurality of pixels disposed on the substrate in the first direction and the second direction and including the pixel.

[0028]

[0011] Other aspects, features, and advantages in addition to those described above will become apparent from the accompanying drawings, claims, and detailed description that characterize the following disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a schematic block diagram of an organic light emitting display device according to an embodiment;

[0031] Figure 2 is a circuit diagram of a pixel according to an embodiment;

[0032] Figure 3 is a method for operating in a first mode according to an embodiment Figure 2 A timing diagram of a control signal of a pixel shown in FIG.

[0033] Figure 4 is a method for operating in the second mode according to an embodiment Figure 2 A timing diagram of a control signal of a pixel shown in FIG.

[0034] Figure 5 is a comparison table of light waveforms in the second mode according to the embodiment;

[0035] Figure 6 is a brightness curve diagram in the second mode according to an embodiment; and

[0036] Figure 7 is a method for operating in a first mode according to an embodiment Figure 2 2 is a timing diagram of the pixel control signals shown in FIG. DETAILED DESCRIPTION

[0037] The utility model can be modified in various ways and take various alternative forms, and its specific embodiments are shown in the drawings and described in detail below as examples. The effects and features of the embodiments and the methods for achieving the effects and features will become clearer with reference to the following detailed description in conjunction with the drawings. However, the present disclosure can be implemented in various forms, and is not limited to the embodiments presented below.

[0038] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings, and in the description with reference to the accompanying drawings, the same and / or corresponding components are denoted by the same reference numerals and redundant descriptions thereof are omitted.

[0039] In the embodiments, it will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component.

[0040] In the embodiments, unless clearly stated otherwise in the context, an expression in the singular number in the present specification includes an expression in the plural number.

[0041] In an embodiment, it will be further understood that the terms “include” and / or “comprises” used herein specify the presence of stated features and / or components, but do not preclude the presence and / or addition of one or more other features and / or components.

[0042] In embodiments, it will be understood that when a layer, region, and / or component is referred to as being "formed on" another layer, region, and / or component, it may be directly or indirectly formed on the other layer, region, and / or component. That is, for example, there may be intervening layers, regions, and / or components.

[0043] For the convenience of explanation, the size of the components in the drawings may be exaggerated or reduced. In other words, since the size (eg, thickness) of the components in the drawings is arbitrarily illustrated for the convenience of explanation, the following embodiments are not limited thereto.

[0044] When the embodiments can be implemented differently, the specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously and / or in the reverse order of the described order.

[0045] In the present specification, the expression "A and / or B" means A, B, or A and B. For example, the expression "at least one of A and B" means A, B, or A and B.

[0046] In an embodiment, it will be understood that when a layer, region, and / or component is connected to another layer, region, and / or component, these layers, regions, and / or components may be directly connected, or may be indirectly connected via another layer, region, and / or component therebetween. For example, in the specification, when a layer, region, and / or component is electrically connected to another layer, region, and / or component, these layers, regions, and / or components may be directly electrically connected, or may be indirectly electrically connected via another layer, region, and / or component therebetween.

[0047] The x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0048] Figure 1 is a schematic block diagram of an organic light emitting display device according to an embodiment.

[0049] refer to Figure 1 In an embodiment, the organic light emitting display device 100 includes a display unit 110 , a gate driver 120 , a data driver 130 , a timing controller 140 , and a voltage generator 150 .

[0050] In an embodiment, the display unit 110 includes pixels such as the pixel PXij located at the i-th row and the j-th column. Although for ease of understanding, Figure 1 Only one pixel PXij is illustrated, but m×n pixels may be arranged in a matrix form, for example. In this regard, m and n are natural numbers greater than 0, i is a natural number at least 1 and not greater than m, and j is a natural number at least 1 and not greater than n.

[0051] In an embodiment, the pixels are connected to the first scan lines SL1_1 to SL1_m, the second scan lines SL2_1 to SL2_m, the third scan lines SL3_1 to SL3_m, the fourth scan lines SL4_1 to SL4_m, the fifth scan lines SL5_1 to SL5_m, the emission control lines EML_1 to EML_m, and the data lines DL_1 to DL_n. The pixels are connected to the power line, the first voltage line, the second voltage line, and the third voltage line. For example, Figure 1As shown in the figure, the pixel PXij can be connected to the first scan line SL1_i, the second scan line SL2_i, the third scan line SL3_i, the fourth scan line SL4_i, the fifth scan line SL5_i, the emission control line EML_i, the data line DL_j, the power line PL_j, the first voltage line VL1_i, the second voltage line VL2_i and the third voltage line VL3_i.

[0052] In an embodiment, the first scan lines SL1_1 to SL1_m, the second scan lines SL2_1 to SL2_m, the third scan lines SL3_1 to SL3_m, the fourth scan lines SL4_1 to SL4_m, the fifth scan lines SL5_1 to SL5_m, the emission control lines EML_1 to EML_m, the first voltage lines, the second voltage lines, and the third voltage lines may extend in a first direction (e.g., a row direction) and may be connected to pixels located in the same row. The data lines DL_1 to DL_n and the power lines may extend in a second direction (e.g., a column direction) and be connected to pixels located in the same column.

[0053] In an embodiment, the first scan lines SL1_1 to SL1_m transmit the first scan signals GW_1 to GW_m output from the gate driver 120 to pixels in the same row, respectively, the second scan lines SL2_1 to SL2_m transmit the second scan signals GC_1 to GC_m output from the gate driver 120 to pixels in the same row, respectively, and the third scan lines SL3_1 to SL3_m transmit the third scan signals GI_1 to GI_m output from the gate driver 120 to pixels in the same row, respectively. The fourth scan lines SL4_1 to SL4_m transmit the fourth scan signals GB_1 to GB_m output from the gate driver 120 to pixels in the same row, respectively, and the fifth scan lines SL5_1 to SL5_m transmit the fifth scan signals EB_1 to EB_m output from the gate driver 120 to pixels in the same row, respectively.

[0054] In an embodiment, the first scan line SL1_i+1 and the fourth scan line SL4_i may be the same scan line. Both the first scan signal GW_i+1 and the fourth scan signal GB_i are transmitted through the first scan line SL1_i+1 and may be the same signal in practice.

[0055] In another embodiment, the first scan line SL1_i-1 and the fourth scan line SL4_i may be the same scan line. Both the first scan signal GW_i-1 and the fourth scan signal GB_i are transmitted through the first scan line SL1_i-1 and may be the same signal in practice.

[0056] In an embodiment, the emission control lines EML_1 to EML_m transmit emission control signals EM_1 to EM_m output from the gate driver 120 to pixels in the same row, respectively. The data lines DL_1 to DL_n transmit data voltages D1 to Dn output from the data driver 130 to pixels in the same column, respectively. The pixels PXij receive first to fifth scan signals GW_i, GC_i, GI_i, GB_i, and EB_i, data voltages Dj, and emission control signals EM_i, respectively.

[0057] In an embodiment, each of the power lines transmits the first driving voltage ELVDD output from the voltage generator 150 to pixels in the same column. Each of the first voltage lines transmits the first initialization voltage VINT1 output from the voltage generator 150 to pixels in the same row, each of the second voltage lines transmits the second initialization voltage VINT2 output from the voltage generator 150 to pixels in the same row, and each of the third voltage lines transmits the bias voltage Vb output from the voltage generator 150 to pixels in the same row.

[0058] In an embodiment, the pixel PXij includes a display element and a driving transistor that controls the size of a driving current flowing to the display element based on a data voltage Dj. The data voltage Dj is output from the data driver 130 and received by the pixel PXij through the data line DL_j. The display element may be, for example, an organic light emitting diode. Since the display element emits light having a brightness corresponding to the size of the driving current received from the driving transistor, the pixel PXij may exhibit a grayscale corresponding to the data voltage Dj.

[0059] In an embodiment, the pixel PXij may correspond to a portion (eg, a sub-pixel) of a unit pixel capable of displaying full color. The pixel PXij may further include at least one switching transistor and at least one capacitor. Figure 2 The pixel PXij is described in more detail.

[0060] In an embodiment, the voltage generator 150 may generate a voltage required to drive the pixel PXij. For example, the voltage generator 150 may generate a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, a second initialization voltage VINT2, and a bias voltage Vb. The level of the first driving voltage ELVDD may be greater than the level of the second driving voltage ELVSS. The level of the bias voltage Vb may be greater than the level of the second initialization voltage VINT2. The level of the second initialization voltage VINT2 may be greater than the level of the first initialization voltage VINT1. The level of the second initialization voltage VINT2 may be greater than the level of the second driving voltage ELVSS. The difference between the level of the second initialization voltage VINT2 and the level of the second driving voltage ELVSS may be less than the threshold voltage required for the display element of the pixel PXij to emit light.

[0061] In an embodiment, the voltage generator 150 may provide a first gate voltage VGH and a second gate voltage VGL for controlling a switching transistor of a pixel PXij to the gate driver 120. When the first gate voltage VGH is applied to the gate of the switching transistor, the switching transistor is turned off, and when the second gate voltage VGL is applied to the gate of the switching transistor, the switching transistor may be turned on. The first gate voltage VGH may be referred to as a gate-off voltage, and the second gate voltage VGL may be referred to as a gate-on voltage. The switching transistor of the pixel PXij may be a p-type MOSFET, and the level of the first gate voltage VGH may be greater than the level of the second gate voltage VGL. Although not in Figure 1 , but the voltage generator 150 may generate a gamma reference voltage and / or provide the gamma reference voltage to the data driver 130 .

[0062] In an embodiment, the timing controller 140 may control the display unit 110 by controlling the operation timing of the gate driver 120 and / or the data driver 130. The pixels of the display unit 110 may receive new data voltages D1 to Dn for each new frame period, and may display an image corresponding to the image source data RGB of one frame by emitting light having brightness corresponding to the data voltages D1 to Dn.

[0063] According to an embodiment, one frame period may include a gate initialization period, a data writing and anode initialization period, and an emission period. In the gate initialization period, a first initialization voltage VINT1 may be applied to the pixel in synchronization with the third scan signals GI_1 to GI_m. In the data writing and anode initialization period, data voltages D1 to Dn may be provided to the pixel in synchronization with the first scan signals GW_1 to GW_m, and a second initialization voltage VINT2 may be applied to the pixel in synchronization with the fourth scan signals GB_1 to GB_m. In the emission period, the pixels of the display unit 110 may emit light.

[0064] In an embodiment, the timing controller 140 receives image source data RGB and a control signal CONT from the outside. The timing controller 140 may convert the image source data RGB into image data DATA based on characteristics of the display unit 110 and pixels, etc. The timing controller 140 may provide the image data DATA to the data driver 130 .

[0065] In an embodiment, the control signal CONT may include at least one of a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. The timing controller 140 may control operation timings of the gate driver 120 and the data driver 130 by using the control signal CONT.

[0066] In an embodiment, the timing controller 140 can determine the frame period by counting the data enable signal of one horizontal scanning period (1H). In this case, the vertical synchronization signal and the horizontal synchronization signal supplied from the outside can be omitted. The image source data RGB includes the brightness information of the pixel. The brightness can have a predetermined number of gray levels, for example, 1024 (=2 10 ) grayscale, 256 (=2 8 ) grayscale or 64 (=2 6 ) grayscale.

[0067] In an embodiment, the timing controller 140 may generate control signals including a gate timing control signal GDC for controlling an operation timing of the gate driver 120 and a data timing control signal DDC for controlling an operation timing of the data driver 130 .

[0068] In an embodiment, the gate timing control signal GDC may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE) signal. The GSP is supplied to the gate driver 120 that generates the first scan signal at the start time point of the scan period. The GSC is a clock signal commonly input to the gate driver 120, and is a clock signal for shifting the GSP. The GOE signal controls the output of the gate driver 120.

[0069] In an embodiment, the data timing control signal DDC may include a source start pulse (SSP), a source sampling clock (SSC), and a source output enable (SOE) signal. The SSP controls the data sampling start time point of the data driver 130, and is provided to the data driver 130 at the start time point of the scanning period. The SSC is a clock signal that controls the data sampling operation within the data driver 130 based on a rising edge or a falling edge. The SOE signal controls the output of the data driver 130. Meanwhile, the SSP supplied to the data driver 130 may be omitted according to the data transmission method.

[0070] In an embodiment, the gate driver 120 sequentially generates first scan signals GW_1 to GW_m, second scan signals GC_1 to GC_m, third scan signals GI_1 to GI_m, fourth scan signals GB_1 to GB_m, and fifth scan signals EB_1 to EB_m in response to a gate timing control signal GDC supplied from the timing controller 140 by using a first gate voltage VGH and a second gate voltage VGL provided from the voltage generator 150.

[0071] In an embodiment, the data driver 130 samples and latches the image data DATA supplied from the timing controller 140 in response to the data timing control signal DDC supplied from the timing controller 140, and converts the image data DATA into data of a parallel data system. When converting the image data DATA into data of a parallel data system, the data driver 130 converts the image data DATA into an analog data voltage using a gamma reference voltage. The data driver 130 provides the data voltages D1 to Dn to the pixels through the data lines DL_1 to DL_n. The pixels receive the data voltages D1 to Dn in response to the first scan signals GW_1 to GW_m.

[0072] Figure 2 is a circuit diagram of a pixel according to an embodiment.

[0073] In the examples and with reference to Figure 2, the pixel PXij is connected to the first to fifth scan lines SL1_i, SL2_i, SL3_i, SL4_i and SL5_i that transmit the first to fifth scan signals GW_i, GC_i, GI_i, GB_i and EB_i respectively, the data line DL_j that transmits the data voltage Dj, and the emission control line EML_i that transmits the emission control signal EM_i. The pixel PXij is connected to the power line PL_j that transmits the first drive voltage ELVDD, the first voltage line VL1_i that transmits the first initialization voltage VINT1, the second voltage line VL2_i that transmits the second initialization voltage VINT2, and the third voltage line VL3_i that transmits the bias voltage Vb. The pixel PXij is connected to a common electrode to which the second drive voltage ELVSS is applied. The pixel PXij can be connected to Figure 1 Corresponding to the pixel PXij.

[0074] In an embodiment, the pixel PXij includes a display element OLED, a first transistor T1 to an eighth transistor T8, a first capacitor (or storage capacitor) C1 and a second capacitor C2. The display element OLED may be an organic light emitting diode having an anode and a cathode. The cathode may be a common electrode to which a second driving voltage ELVSS is applied. The first capacitor C1 may have a first electrode and a second electrode. The second capacitor C2 may have a third electrode and a fourth electrode.

[0075] In an embodiment, the first transistor T1 may be a driving transistor in which the magnitude of the source-drain current is determined according to the gate-source voltage, and the second transistor T2 to the eighth transistor T8 may each be a switching transistor that is turned on or off according to the gate-source voltage (basically the gate voltage). Each of the second transistor T2 to the eighth transistor T8 may include a switching transistor, or may include a plurality of switching transistors that are simultaneously controlled by the same gate signal and connected in series with each other. The first transistor T1 to the eighth transistor T8 may each be formed as a thin film transistor.

[0076] In an embodiment, the first transistor T1 can control the size of the driving current Id flowing from the power line PL_j to the display element OLED according to the gate-source voltage. The first transistor T1 can have a gate connected to the second electrode of the first capacitor C1, a source S connected to the power line PL_j through the fifth transistor T5, and a drain D connected to the display element OLED through the sixth transistor T6.

[0077] In an embodiment, the first transistor T1 may output a driving current Id to the display element OLED. The magnitude of the driving current Id may be determined based on the gate-source voltage of the first transistor T1. The gate-source voltage of the first transistor T1 corresponds to the difference between the gate voltage and the source voltage. For example, the magnitude of the driving current Id may be determined based on the difference between the gate-source voltage of the first transistor T1 and the threshold voltage of the first transistor T1. The display element OLED may receive the driving current Id from the first transistor T1, and may emit light having a brightness according to the magnitude of the driving current Id.

[0078] In an embodiment, the second transistor T2 receives the data voltage Dj in response to the first scan signal GW_i. The second transistor T2 transmits the data voltage Dj to the source S of the first transistor T1 in response to the first scan signal GW_i. The second transistor T2 may have a gate connected to the first scan line SL1_i, a source S connected to the data line DL_j, and a drain D connected to the source S of the first transistor T1.

[0079] In an embodiment, the first capacitor C1 is connected to the gate of the first transistor T1. The first capacitor C1 may be connected between the power line PL_j and the gate of the first transistor T1. The first capacitor C1 may have a first electrode connected to the power line PL_j and a second electrode connected to the gate of the first transistor T1. The first capacitor C1 may store a difference between the first driving voltage ELVDD applied to the power line PL_j and the gate voltage of the first transistor T1, and may maintain the gate voltage of the first transistor T1.

[0080] In an embodiment, the second capacitor C2 is connected to the source S of the first transistor T1. The second capacitor C2 may be connected between the power line PL_j and the source S of the first transistor T1. The second capacitor C2 may have a third electrode connected to the power line PL_j and a fourth electrode connected to the source S of the first transistor T1.

[0081] In an embodiment, the third transistor T3 may be connected between the gate and the drain D of the first transistor T1, and may connect the gate and the drain D of the first transistor T1 to each other in response to the second scan signal GC_i. The third transistor T3 may have a gate connected to the second scan line SL2_i, a source S connected to the drain D of the first transistor T1, and a drain D connected to the gate of the first transistor T1.

[0082] In an embodiment, when the third transistor T3 is turned on in response to the second scan signal GC_i, the drain D and the gate of the first transistor T1 are connected to each other, so that the first transistor T1 can be diode-connected. The source S of the first transistor T1 receives the data voltage Dj in response to the first scan signal GW_i, and the data voltage Dj is transmitted to the gate of the first transistor T1 through the diode-connected first transistor T1. When the gate voltage of the first transistor T1 becomes equal to a voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage Dj, the first transistor T1 is turned off, and a voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage Dj is stored in the first capacitor C1.

[0083] In an embodiment, Figure 2 As shown in , the third transistor T3 may include a pair of third transistors T3a and T3b that are simultaneously controlled by the second scan signal GC_i and are connected in series to each other between the gate and the drain D of the first transistor T1.

[0084] In an embodiment, the fourth transistor T4 applies the first initialization voltage VINT1 to the gate of the first transistor T1 in response to the third scan signal GI_i. The fourth transistor T4 may have a gate connected to the third scan line SL3_i, a source S connected to the gate of the first transistor T1, and a drain D connected to the first voltage line VL1_i.

[0085] In an embodiment, Figure 2 As shown in , the fourth transistor T4 may include a pair of fourth transistors T4a and T4b that are simultaneously controlled by the third scan signal GI_i and are connected in series to each other between the gate of the first transistor T1 and the first voltage line VL1_i.

[0086] In an embodiment, the fifth transistor T5 and the sixth transistor T6 may generate a path of the driving current Id between the power line PL_j and the display element OLED in response to the emission control signal EM_i.

[0087] In an embodiment, the fifth transistor T5 may connect the power line PL_j and the source S of the first transistor T1 to each other in response to the emission control signal EM_i. The fifth transistor T5 may have a gate connected to the emission control line EML_i, a source S connected to the power line PL_j, and a drain D connected to the source S of the first transistor T1.

[0088] In an embodiment, the sixth transistor T6 may connect the drain D of the first transistor T1 and the anode of the display element OLED to each other in response to the emission control signal EM_i. The sixth transistor T6 may have a gate connected to the emission control line EML_i, a source S connected to the drain D of the first transistor T1, and a drain D connected to the anode of the display element OLED.

[0089] In an embodiment, the seventh transistor T7 applies the second initialization voltage VINT2 to the anode of the display element OLED in response to the fourth scan signal GB_i. The seventh transistor T7 may have a gate connected to the fourth scan line SL4_i, a source S connected to the anode of the display element OLED, and a drain D connected to the second voltage line VL2_i.

[0090] In an embodiment, the eighth transistor T8 applies the bias voltage Vb to the source S of the first transistor T1 in response to the fifth scan signal EB_i. The eighth transistor T8 may have a gate connected to the fifth scan line SL5_i, a source S connected to the third voltage line VL3_i, and a drain D connected to the source S of the first transistor T1.

[0091] In an embodiment, the pixel PXij may operate at a first scan rate in a first mode and at a second scan rate in a second mode. The first scan rate and the second scan rate may be different from each other. For example, the second scan rate may be less than the first scan rate.

[0092] In an embodiment, the eighth transistor T8 is in an off state in the first mode and may transmit the bias voltage Vb to the first transistor T1 in response to the fifth scan signal EB_i in the second mode. In the first mode, the fifth scan signal EB_i may have a voltage at an off level. Figure 3 and Figure 4 This is described in more detail.

[0093] Figure 3 is a method for operating in a first mode according to an embodiment Figure 2 . Specifically, Figure 3 The figure shows a timing diagram of control signals applied to pixels operating at a first scan rate in a first mode. For example, the first scan rate may be 120 Hz.

[0094] In the embodiments and together with Figure 2 refer to Figure 3In the period in which the emission control signal EM_i has a pulse at a cut-off level (eg, a high level), the fifth transistor T5 and the sixth transistor T6 are cut off. The period in which the emission control signal EM_i has a pulse at a cut-off level may be referred to as a non-emission period.

[0095] In an embodiment, in the non-emission period, the first transistor T1 stops outputting the driving current Id, and the display element OLED stops emitting light.

[0096] In an embodiment, the third scan signal GI_i initially has a first pulse p11 at a turn-on level (eg, a low level). A period in which the third scan signal GI_i has the first pulse p11 may be referred to as a gate initialization period.

[0097] In an embodiment, during the gate initialization period, the fourth transistor T4 is turned on and the first initialization voltage VINT1 is applied to the gate of the first transistor T1, that is, the second electrode of the first capacitor C1. The difference (ELVDD-VINT1) between the first driving voltage ELVDD and the first initialization voltage VINT1 is stored in the first capacitor C1.

[0098] In an embodiment, after the third scan signal GI_i transitions to the off level, the first scan signal GW_i has the second pulse p21 at the on level, and the second scan signal GC_i has the third pulse p31 at the on level. A period in which the first scan signal GW_i has the second pulse p21 and the second scan signal GC_i has the third pulse p31 may be referred to as a data write period.

[0099] In an embodiment, during the data writing period, the second transistor T2 and the third transistor T3 are turned on, and the data voltage Dj is received by the source S of the first transistor T1. The first transistor T1 is diode-connected by the third transistor T3 and is forward biased. The voltage of the second electrode of the first capacitor C1 increases from the first initialization voltage VINT1. When the gate voltage of the first transistor T1 becomes equal to the voltage (Dj-|Vth|) obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the data voltage Dj, the first transistor T1 is turned off, and at the same time, the gate voltage of the first transistor T1 stops increasing. Accordingly, the gate voltage of the first transistor T1 becomes Dj-|Vth|, and the difference (ELVDD-Dj+|Vth|) between the first drive voltage ELVDD and the gate voltage (Dj-|Vth|) is stored in the first capacitor C1.

[0100] In addition, in an embodiment, after the third scan signal GI_i transitions to the off level, the fourth scan signal GB_i has a fourth pulse p41 at the on level. The period in which the fourth scan signal GB_i has the fourth pulse p41 may be referred to as an anode initialization period.

[0101] In an embodiment, during the anode initialization period, the seventh transistor T7 is turned on and the second initialization voltage VINT2 is applied to the anode of the display element OLED. By applying the second initialization voltage VINT2 to the anode of the display element OLED to completely prevent the display element OLED from emitting light, the phenomenon in which the display element OLED slightly emits light corresponding to the black grayscale in the next frame can be eliminated.

[0102] In an embodiment, thereafter, the first scan signal GW_i, the second scan signal GC_i and the fourth scan signal GB_i transition to the off level, and the emission control signal EM_i has the on level. The period in which the emission control signal EM_i has the on level may be referred to as an emission period.

[0103] In an embodiment, during the emission period, the fifth transistor T5 and the sixth transistor T6 are turned on. The first transistor T1 can output the voltage stored in the first capacitor C1, that is, the drive current Id having a magnitude corresponding to the voltage (ELVDD-Dj) obtained by subtracting the threshold voltage (|Vth|) of the first transistor T1 from the source-gate voltage (ELVDD-Dj+|Vth|) of the first transistor T1, and can emit light having a brightness corresponding to the magnitude of the drive current Id.

[0104] In an embodiment, while the pixel operates at the first scan rate in the first mode, the fifth scan signal EB_i may have a voltage at a turn-off level. While the pixel operates at the first scan rate in the first mode, the eighth transistor T8 may be in a turn-off state.

[0105] In an embodiment, the fourth scan signal GB_i may be substantially synchronized with the first scan signal GW_i-1 of the previous row. Figure 3 As shown in , the interval between the falling edge of the second pulse p21 and the falling edge of the fourth pulse p41 may be one horizontal scanning period (1H).

[0106] In another embodiment, the fourth scan signal GB_i may be substantially synchronized with the first scan signal GW_i+1 of the next row.

[0107] Figure 4 is a method for operating in the second mode according to an embodiment Figure 2 . Specifically, Figure 4The figure shows a timing diagram of control signals applied to pixels operating at a second scan rate in a second mode. For example, the second scan rate may be 30 Hz.

[0108] In the examples and with reference to Figure 4 In the second mode, a frame period 1Frame may include a display scanning period AD and a self-scanning period SS. Figure 4 As shown in , one frame period 1Frame may include one display scanning period AD and three self scanning periods SS.

[0109] In an embodiment, the length of the display scanning period AD and the length of the self scanning period SS may be substantially the same.

[0110] In an embodiment, the third scan signal GI_i may have a first pulse p12 at an on level in the display scan period AD, and may have a voltage at an off level in the self scan period SS. The period in which the third scan signal GI_i has the first pulse p12 may be referred to as a gate initialization period. The display scan period AD may include a gate initialization period.

[0111] In an embodiment, during the gate initialization period of the display scanning period AD, the fourth transistor T4 is turned on, and the first initialization voltage VINT1 is applied to the gate of the first transistor T1, that is, the second electrode of the first capacitor C1. The difference (ELVDD-VINT1) between the first driving voltage ELVDD and the first initialization voltage VINT1 is stored in the first capacitor C1.

[0112] In an embodiment, the first scan signal GW_i may have a second pulse p22 at an on level in the display scan period AD and the self scan period SS, respectively. The second scan signal GC_i may have a third pulse p32 at an on level in the display scan period AD, and may have a voltage at an off level in the self scan period SS. The period in which the first scan signal GW_i has the second pulse p22 and the second scan signal GC_i has the third pulse p32 may be referred to as a data write period. The display scan period AD may include a data write period.

[0113] In an embodiment, during the data writing period of the display scanning period AD, the second transistor T2 and the third transistor T3 are turned on, and the data voltage Dj is received by the source S of the first transistor T1. The first transistor T1 is diode-connected by the third transistor T3 and is forward biased. The voltage of the second electrode of the first capacitor C1 increases from the first initialization voltage VINT1. When the gate voltage of the first transistor T1 becomes equal to the voltage (Dj-|Vth|) obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the data voltage Dj, the first transistor T1 is turned off, and at the same time, the gate voltage of the first transistor T1 stops increasing. Accordingly, the gate voltage of the first transistor T1 becomes Dj-|Vth|, and the difference (ELVDD-Dj+|Vth|) between the first drive voltage ELVDD and the gate voltage (Dj-|Vth|) is stored in the first capacitor C1.

[0114] In an embodiment, while the first scan signal GW_i has the second pulse p22 in the self-scan period SS, the second transistor T2 is turned on and the data voltage Dj is received by the source S of the first transistor T1. In this case, the data voltage Dj received by the source S of the first transistor T1 in the self-scan period SS may be substantially the same as the bias voltage Vb.

[0115] In an embodiment, the fourth scan signal GB_i may have a fourth pulse p42 at a turn-on level in the display scan period AD and the self-scan period SS, respectively. The period in the display scan period AD in which the fourth scan signal GB_i has the fourth pulse p42 may be referred to as an anode initialization period. The display scan period AD may include an anode initialization period.

[0116] In an embodiment, during the anode initialization period of the display scanning period AD, the seventh transistor T7 is turned on, and the second initialization voltage VINT2 is applied to the anode of the display element OLED. By applying the second initialization voltage VINT2 to the anode of the display element OLED to completely prevent the display element OLED from emitting light, the phenomenon in which the display element OLED slightly emits light corresponding to the black grayscale in the next frame can be eliminated.

[0117] In an embodiment, while the fourth scan signal GB_i has the fourth pulse p42 in the self-scan period SS, the seventh transistor T7 is turned on, and the second initialization voltage VINT2 is applied to the anode of the display element OLED.

[0118] In an embodiment, the fifth scan signal EB_i may have a voltage at an off level during the display scan period AD, and may have the fifth pulse p52 at an on level in the self scan period SS. During the display scan period AD, the eighth transistor T8 may be in an off state.

[0119] In an embodiment, while the fifth scan signal EB_i has the fifth pulse p52 in the self-scan period SS, the eighth transistor T8 is turned on, and the bias voltage Vb is applied to the source S of the first transistor T1.

[0120] In an embodiment, the width of the fifth pulse p52 may be greater than the width of the second pulse p22 and the width of the fourth pulse p42.

[0121] In an embodiment, the width of the fifth pulse p52 may be greater than one horizontal scanning period (1H). For example, the width of the fifth pulse p52 may be four horizontal scanning periods (4H), eight horizontal scanning periods (8H), or 16 horizontal scanning periods (16H).

[0122] In an embodiment, the widths of the first to fourth pulses p12, p22, p32, and p42 may be substantially the same. For example, the width of the first to fourth pulses p12, p22, p32, and p42 may be one horizontal scanning period (1H).

[0123] In an embodiment, the fourth scan signal GB_i may be substantially synchronized with the first scan signal GW_i-1 of the previous row. Figure 4 As shown in , the interval between the falling edge of the second pulse p22 and the falling edge of the fourth pulse p42 may be one horizontal scanning period (1H).

[0124] In another embodiment, the fourth scan signal GB_i may be substantially synchronized with the first scan signal GW_i+1 of the next row.

[0125] Figure 5 is a comparison table of light waveforms in the second mode according to the embodiment, and Figure 6 is a brightness curve diagram in the second mode according to an embodiment.

[0126] First, refer to Figure 5In the embodiment, the first waveform l1 represents the brightness in the display scanning period AD when the seventh transistor T7 and the eighth transistor T8 are controlled by the same scanning signal, and the second waveform l2 represents the brightness in the self scanning period SS when the seventh transistor T7 and the eighth transistor T8 are controlled by the same scanning signal. The third waveform l3 represents the brightness in the display scanning period AD when the seventh transistor T7 and the eighth transistor T8 are respectively controlled by different scanning signals, and the fourth waveform l4 represents the brightness in the self scanning period SS when the seventh transistor T7 and the eighth transistor T8 are respectively controlled by different scanning signals.

[0127] In the embodiment, the first waveform l1 and the second waveform l2 are different from each other, and the third waveform l3 and the fourth waveform l4 are substantially the same. In other words, when the seventh transistor T7 and the eighth transistor T8 are controlled by the same scan signal, the brightness difference between the display scan period AD and the self scan period SS occurs, and when the seventh transistor T7 and the eighth transistor T8 are respectively controlled by different scan signals, the brightness difference between the display scan period AD and the self scan period SS decreases.

[0128] As referenced above Figure 3 and Figure 4 As described, according to an embodiment, the seventh transistor T7 may be controlled by the fourth scan signal GB_i, and the eighth transistor T8 may be controlled by the fifth scan signal EB_i. In this case, the fourth scan signal GB_i may have a fourth pulse p41 at a conduction level during one frame period 1Frame in the first mode, and may have a fourth pulse p42 at a conduction level in the display scan period AD and the self-scan period SS, respectively, in the second mode. The fifth scan signal EB_i may have a voltage at a cut-off level in the first mode, and may have a voltage at a cut-off level during the display scan period AD and may have a fifth pulse p52 at a conduction level in the self-scan period SS in the second mode. The width of the fifth pulse p52 may be greater than the width of the fourth pulse p42.

[0129] Likewise, in an embodiment, when the seventh transistor T7 and the eighth transistor T8 are respectively controlled by different scan signals, the eighth transistor T8 can be kept in an off state during the display scan period AD, and the length of the period in which the eighth transistor T8 is turned on can be adjusted separately during the self-scan period SS. Figure 6 As shown in , since the luminances of the display scanning period AD and the self scanning period SS become substantially the same, the luminance difference between the display scanning period AD and the self scanning period SS is reduced.

[0130] Figure 7 FIG. 2 is a diagram illustrating a method for operating in a first mode according to an embodiment Figure 2 0 is a timing diagram of the pixel control signals shown in FIG.

[0131] refer to Figure 7 , in the embodiment, different from Figure 3 As shown in the timing diagram, a frame period 1Frame may include multiple non-transmission periods. Figure 7 As shown in , one frame period 1Frame may include two non-transmission periods.

[0132] In an embodiment, the scan signal may have a pulse at a conduction level during each non-emission period. For example, the third scan signal GI_i may have a first pulse p13 at a conduction level during each non-emission period, the first scan signal GW_i may have a second pulse p23 at a conduction level during each non-emission period, the second scan signal GC_i may have a third pulse p33 at a conduction level during each non-emission period, and the fourth scan signal GB_i may have a fourth pulse p43 at a conduction level during each non-emission period.

[0133] In other words, in an embodiment, the third scan signal GI_i may have two first pulses p13 during one frame period 1Frame, the first scan signal GW_i may have two second pulses p23 during one frame period 1Frame, the second scan signal GC_i may have two third pulses p33 during one frame period 1Frame, and the fourth scan signal GB_i may have two fourth pulses p43 during one frame period 1Frame.

[0134] In the above, the pixel and the display device have been mainly described, but the present disclosure is not limited thereto. For example, a method for manufacturing such a pixel and a method for manufacturing such a display device also belong to the scope of the present disclosure.

[0135] Although the utility model has been specifically shown and described with reference to the embodiments of the utility model, it will be understood that various changes in form and details can be made herein without departing from the spirit and scope of the claims. It should be understood that the embodiments described herein should be considered only in a descriptive sense, not for the purpose of limitation. The description of the features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details can be made herein without departing from the spirit and scope defined by the claims. The embodiments of the present disclosure disclosed in the present disclosure and illustrated in the accompanying drawings are provided as specific examples to more easily illustrate the technical content according to the present disclosure and help understand the embodiments of the present disclosure, but are not intended to limit the scope of the embodiments of the present disclosure. Accordingly, the scope of the various embodiments of the present disclosure should be interpreted as including all changes or modifications of the technical ideas derived from the various embodiments of the present disclosure in addition to the embodiments disclosed herein. In addition, the embodiments or parts of the embodiments may be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A pixel that operates at a first scan rate in a first mode and operates at a second scan rate in a second mode, the pixel comprising: A display element having an anode and a cathode; a first transistor, controlling the magnitude of a driving current flowing to the display element according to a gate-source voltage; as well as The second transistor is in a cut-off state in the first mode and transmits a bias voltage to the first transistor in response to a first scan signal in the second mode.

2. The pixel according to claim 1, wherein: One frame period in the second mode includes a display scanning period and a self-scanning period, and The first scanning signal has a voltage at an off level during the display scanning period and has a pulse at an on level during the self scanning period, wherein a width of the pulse at the on level is greater than one horizontal scanning period (1H).

3. The pixel according to claim 1, further comprising: a first capacitor connected to the gate of the first transistor; a third transistor transmitting a data voltage to a source of the first transistor in response to a second scan signal; as well as a fourth transistor transmitting a first initialization voltage to the anode of the display element in response to a third scan signal, Wherein, in the second mode, the second transistor transmits the bias voltage to the source of the first transistor in response to the first scan signal.

4. The pixel according to claim 3, wherein: In the second mode, one frame period includes a display scanning period and a self-scanning period. The first scanning signal has a voltage at an off level during the display scanning period and has a first pulse at an on level during the self scanning period, The second scanning signal has a second pulse at the on-level in each of the display scanning period and the self scanning period, and The third scan signal has a third pulse at the on-level in each of the display scan period and the self scan period.

5. The pixel according to claim 4, wherein: The width of the first pulse is greater than the width of the second pulse and the width of the third pulse.

6. The pixel according to claim 4, wherein: An interval between the falling edge of the second pulse and the falling edge of the third pulse is one horizontal scanning period (1H).

7. The pixel according to claim 4, wherein: The data voltage transmitted to the source of the first transistor in the self-scan period is the same as the bias voltage.

8. The pixel according to claim 3, further comprising: a fifth transistor that connects the gate electrode of the first transistor and the drain electrode of the first transistor to each other in response to a fourth scan signal, Wherein, one frame period in the second mode includes a display scanning period and a self-scanning period, and The fourth scan signal has a fourth pulse at an on-level in the display scan period and has a voltage at an off-level during the self scan period.

9. The pixel according to claim 8, further comprising: a sixth transistor transmitting a second initialization voltage to the gate of the first transistor in response to a fifth scan signal, wherein the fifth scanning signal has a fifth pulse at the on-level in the display scanning period and has a voltage at the off-level during the self-scanning period, wherein the second scanning signal has a second pulse at the on-level in each of the display scanning period and the self-scanning period, and The width of the fourth pulse is equal to the width of the second pulse and the width of the fifth pulse.

10. The pixel according to any one of claims 3 to 9, further comprising: A second capacitor is connected to the source of the first transistor.

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