Apparatus for manufacturing display device

Abstract

An apparatus for manufacturing a display device is disclosed. The apparatus includes: a chamber in which a display substrate is disposed; a mask assembly disposed in the chamber and facing the display substrate; and a deposition source providing a deposition material to the mask assembly, where the mask assembly includes: a first mask layer including a first mask opening; a stop layer disposed on the first mask layer and including a stop layer opening overlapping the first mask opening; and an inorganic layer disposed on the stop layer and including an inorganic opening overlapping the stop layer opening.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2023-0038985 filed on March 24, 2023, and Korean Patent Application No. 10-2023-0052822 filed on April 21, 2023, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to an apparatus for manufacturing a display device and a method of manufacturing a display device. Background Art

[0004] A display device is a device that displays an image in a visual manner. A display device may use a light emitting diode to provide an image. Display devices have been used in various ways. Accordingly, various designs have been tried to improve the quality of display devices. Utility Model Content

[0005] The present disclosure provides an apparatus and method for manufacturing a display device including a mask assembly that can be manufactured with a simple process and has improved durability and stable quality.

[0006] However, this technical goal is only an example, and the technical goal to be achieved by the present disclosure is not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the embodiments of the disclosure.

[0008] According to one embodiment, an apparatus for manufacturing a display device may include: a chamber, in which a display substrate is arranged; a mask assembly, arranged in the chamber and facing the display substrate; and a deposition source, providing a deposition material to the mask assembly, wherein the mask assembly includes: a first mask layer, including a first mask opening; a stop layer, disposed on the first mask layer and including a stop layer opening overlapping with the first mask opening; and an inorganic layer, disposed on the stop layer and including an inorganic opening overlapping with the stop layer opening.

[0009] According to an embodiment, a method for manufacturing a display device may include arranging a display substrate in a chamber, arranging a mask assembly in the chamber, and providing a deposition material to the mask assembly through a deposition source. The arrangement of the mask assembly may include disposing a stop layer including a stop layer opening on a first mask layer, disposing an inorganic layer on the stop layer, forming a first mask opening in the first mask layer, and forming an inorganic opening of the inorganic layer by etching the inorganic layer corresponding to the stop layer opening.

[0010] In one embodiment, in a plan view, the shape of the stop layer opening formed in the stop layer and the shape of the inorganic opening formed in the inorganic layer may be the same.

[0011] In one embodiment, setting of the inorganic layer may include: setting a first inorganic layer on the stop layer, and setting a second inorganic layer on the first inorganic layer, the second inorganic layer having an etching selectivity higher than that of the first inorganic layer, and etching of the inorganic layer may include etching the first inorganic layer corresponding to the opening of the stop layer and etching the second inorganic layer corresponding to the opening of the stop layer.

[0012] In one embodiment, the number of the first inorganic openings formed in the first inorganic layer may correspond to the number of the second inorganic openings formed in the second inorganic layer.

[0013] In one embodiment, in a plan view, a shape of the first inorganic opening formed in the first inorganic layer and a shape of the second inorganic opening formed in the second inorganic layer may be the same.

[0014] In one embodiment, the disposing of the stop layer may include disposing a first photoresist layer including a first photo opening on the first mask layer, disposing the stop layer on the first photoresist layer, and removing the first photoresist layer.

[0015] In one embodiment, the forming of the first mask opening may include disposing a second photoresist layer including a second optical opening under the first mask layer, etching the first mask layer corresponding to the second optical opening, and removing the second photoresist layer.

[0016] In one embodiment, etching of the inorganic layer may be performed between etching of the first mask layer and removal of the second photoresist layer.

[0017] According to an embodiment, an apparatus for manufacturing a display device may include: a chamber; a mask assembly arranged in the chamber and facing a display substrate; and a deposition source arranged in the chamber, facing the mask assembly, and supplying a deposition material, which passes through the mask assembly and is deposited on the display substrate. The mask assembly may include: a first mask layer including a first mask opening; a stop layer disposed on the first mask layer and including a plurality of stop layer openings corresponding to the first mask opening; and an inorganic layer disposed on the stop layer and including a plurality of inorganic openings corresponding to the plurality of stop layer openings, the inorganic layer may include a first inorganic layer, a second inorganic layer, the second inorganic layer being disposed on the first inorganic layer and having an etching selectivity higher than that of the first inorganic layer, and the plurality of inorganic openings may include a plurality of first inorganic openings disposed in the first inorganic layer and a plurality of second inorganic openings disposed in the second inorganic layer and corresponding to the plurality of first inorganic openings.

[0018] In one embodiment, the number of the first inorganic openings may be equal to the number of the second inorganic openings.

[0019] In one embodiment, in a plan view, the shapes of the plurality of stop layer openings and the shapes of the plurality of inorganic openings may be the same.

[0020] In one embodiment, in a plan view, the shapes of the plurality of first inorganic openings and the shapes of the plurality of second inorganic openings may be the same.

[0021] Other aspects, features and advantages besides those described above will be apparent from the accompanying drawings, claims and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other aspects, features and advantages of the embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0023] Figure 1 is a schematic cross-sectional view illustrating an apparatus for manufacturing a display device according to an embodiment;

[0024] Figure 2 is a schematic cross-sectional view illustrating a mask assembly according to an embodiment;

[0025] Figure 3 is a schematic plan view illustrating a portion of a second mask layer according to an embodiment;

[0026] Figures 4 to 14 is a schematic cross-sectional view of a mask assembly for illustrating a method of manufacturing a display device according to an embodiment;

[0027] Fig.15 is a schematic perspective view illustrating a display device according to an embodiment;

[0028] Fig.16 is a schematic cross-sectional view illustrating a display device according to an embodiment;

[0029] Fig.17 is a schematic plan view illustrating a display panel according to an embodiment;

[0030] Fig.18 is a schematic diagram of an equivalent circuit of a pixel included in a display device according to an embodiment;

[0031] Fig.19 As an example, a display device according to an embodiment of the present invention is shown as follows: Fig.17 A schematic cross-sectional view taken along line D-D' in FIG.

[0032] Fig. 20 is a schematic cross-sectional view illustrating a mask assembly according to another embodiment; and

[0033] Figure 21 to Figure 29 is a schematic cross-sectional view of a mask assembly for illustrating a method of manufacturing a display device according to another embodiment. DETAILED DESCRIPTION

[0034] In the following description, for the purpose of explanation, many specific details are stated in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the device or method disclosed in this article. However, it is obvious that various embodiments can be practiced without these specific details or using one or more equivalent arrangements. Here, various embodiments do not have to be exclusive, nor are they intended to limit the present disclosure. For example, the specific shape, configuration, and features of an embodiment may be used or implemented in another embodiment.

[0035] Now will be referred to in detail embodiment, its example is illustrated in the accompanying drawings, wherein the same reference numerals represent the same elements from beginning to end. In this respect, each embodiment may have different forms and should not be construed as being limited to the description stated in this article. Accordingly, each embodiment is described below only by reference to the accompanying drawings to explain the various aspects of the description. As used in this article, the term "and / or" includes any and all combinations of one or more related listed items. For example, "A and / or B" may be understood to mean "A, B or A and B". The terms "and" and "or" may be used for the meaning of connection or separation, and may be understood to be equivalent to "and / or". Throughout this disclosure, the statement "at least one of a and b" may be interpreted as only a, only b or any combination of a and b. Moreover, "at least one of a, b and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or its variant.

[0036] As used herein, the terms "first", "second", etc. may be used herein to describe various types of elements. These terms are only used to distinguish one element from another element and do not have a limiting meaning. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0037] When a component is described herein as being “connected” to or being “connected to” another component, the components may be connected to each other as separate elements, or the components may be integral with each other.

[0038] Throughout the specification, when an element is referred to as being "connected" to another element, the element may be "directly connected" to the other element, or "electrically connected" to the other element with one or more intervening elements interposed therebetween. Also, when an element is referred to as being "in contact with" or "in contact with" another element, etc., the element may be "electrically in contact with" or "in physical contact with" the other element; or "indirectly in contact with" or "directly in contact with" the other element.

[0039] Spatially relative terms, such as "below," "lower," "above," "higher," "side" (e.g., as in "sidewall"), and the like, may be used herein for descriptive purposes to describe the relationship of one element to another element as illustrated in the accompanying drawings. In addition to the orientation depicted in the accompanying drawings, spatially relative terms are also intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, then elements or features described as "below" or "beneath" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both above and below orientations. In addition, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and as such, the spatially relative descriptors used herein are interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular form is intended to encompass the plural form as well, unless the context clearly indicates otherwise.

[0041] It will be further understood that the terms "comprises," "including," "having," and the like, when used herein, indicate the presence of recited features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially," "about," and other similar terms are used as terms of approximation rather than terms of degree, and as such, are used to take into account the inherent deviations in measured, calculated, and / or provided values ​​that would be recognized by those of ordinary skill in the art.

[0042] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, it may be directly on, connected to or coupled to another element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to physical, electrical and / or fluid connections, with or without intervening elements. Further, the x-axis, y-axis and z-axis are not limited to three axes of a rectangular coordinate system, such as an x-axis, y-axis and z-axis, and may be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0043] In the following embodiments, when a part such as a film, region, layer, substrate, or component is "on" or "over" another part, the part may be directly on the other part, or other films, regions, layers, substrates, or components may be located between them. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0044] Unless otherwise indicated, the illustrated embodiments should be understood to provide exemplary features of the present disclosure. Therefore, unless otherwise indicated, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments, etc. (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged and / or rearranged in other ways without departing from the present disclosure.

[0045] The use of cross-hatching and / or shading in the drawings is generally to clarify the boundaries between adjacent elements. As such, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the illustrated elements, and / or any other feature, attribute, characteristic, etc. of an element, unless otherwise indicated. In the drawings, the size of an element may be enlarged or reduced for ease of description or clarity and / or descriptive purposes. For example, because the size and thickness of each element are arbitrarily shown in the drawings for ease of description, the present disclosure is not necessarily limited to those illustrated.

[0046] Various embodiments are described herein with reference to cross-sectional views and / or exploded views, which are schematic diagrams of embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances should be expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as limited to the shapes of the specific illustrated regions, but rather include shape deviations due to, for example, manufacturing. In this manner, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and as such, are not necessarily intended to be limiting.

[0047] The x-axis, y-axis, and z-axis are not limited to the three axes on the rectangular coordinate system, and can be interpreted as a broad meaning including them. For example, the x-axis, y-axis, and z-axis can be orthogonal to each other, but can also refer to different directions that are not orthogonal to each other.

[0048] The surface may be parallel to the surface defined by the x-axis direction and the y-axis direction. The normal direction of the surface may refer to the z-axis direction. In this specification, the expression "when viewed from the top or in a plan view" may refer to the situation when viewed in the z-axis direction. In the following, the top surface (or front surface) and the bottom surface (or rear surface) of each layer or unit may be distinguished by the z-axis direction. However, the directions indicated by the x-axis, y-axis, and z-axis directions may be relative concepts and may be converted relative to each other, such as converted to the opposite direction.

[0049] When some embodiments may be implemented differently, a specific process order may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in a reverse order to the described order.

[0050] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an ideal or overly formal sense unless clearly defined in the specification.

[0051] Figure 1 is a schematic cross-sectional view illustrating an apparatus 1 for manufacturing a display device according to an embodiment.

[0052] The apparatus 1 for manufacturing a display device may include a chamber CH, a first support member SP1, a second support member SP2, a mask assembly MA, a deposition source SC, a magnetic part MG, a vision part VS, and a pressure regulator PSC.

[0053] The chamber CH may include a space formed therein and may accommodate the display substrate DS and the mask assembly MA. A portion of the chamber CH may be open, and the gate valve GB may be disposed in the open portion of the chamber CH. The open portion of the chamber CH may be opened or closed according to the operation of the gate valve GB.

[0054] The display substrate DS may be a display substrate DS during the manufacture of a display device (for example, see Fig.15 2), showing that the substrate DS is deposited on the following substrate 100 (reference Fig.17 and Fig.19) on the substrate 100. The display substrate DS may be the substrate 100 on which the organic layer, the inorganic layer, and the metal layer have not been deposited.

[0055] The first support member SP1 may support the display substrate DS. The first support member SP1 may have the form of a plate fixed in the chamber CH. In another embodiment, the first support member SP1 may have the form of a shuttle on which the display substrate DS is mounted and which may be linearly movable in the chamber CH. In another embodiment, the first support member SP1 may include an electrostatic chuck, an adhesive chuck, etc., which is arranged in the chamber CH and fixed in the chamber CH or movable in the chamber CH.

[0056] The second support member SP2 may support the mask assembly MA. The second support member SP2 may be arranged in the chamber CH. The second support member SP2 may adjust (e.g., fine-tune) the position of the mask assembly MA. The second support member SP2 may include a separate driver, an alignment component, etc., or a combination thereof, so that the mask assembly MA can move in a separate direction.

[0057] In another embodiment, the second support SP2 may have a shuttle form, and the second support SP2 may be loaded with the mask assembly MA and may transfer the mask assembly MA. For example, the second support SP2 may be moved to the outside of the chamber CH, and the mask assembly MA may enter the chamber CH from the outside of the chamber CH after being loaded on the second support SP2.

[0058] In an embodiment, the first support member SP1 and the second support member SP2 may be integrally formed, and the first support member SP1 and the second support member SP2 may each include a movable shuttle, etc. The first support member SP1 and the second support member SP2 may include a structure in which the mask assembly MA and the display substrate DS are fixed in a state in which the display substrate DS is loaded above (or on) the mask assembly MA, and the display substrate DS and the mask assembly MA may be linearly moved at the same time.

[0059] For convenience of explanation, an embodiment in which the first support member SP1 and the second support member SP2 are separated from each other and arranged at different positions in the chamber CH will be mainly described in detail below.

[0060] The mask assembly MA may be disposed in the chamber CH and face the display substrate DS. The deposition material M may pass through the mask assembly MA and be deposited on the display substrate DS.

[0061] The deposition source SC may face the mask assembly MA and may provide the mask assembly MA with a deposition material M, and the deposition material M may pass through the mask assembly MA and be deposited on the display substrate DS. The deposition source SC may evaporate or sublime the deposition material M by heating the deposition material M. The deposition source SC may be fixed in the chamber CH, or may be arranged in the chamber CH and may be linearly movable in a direction (e.g., an x-axis direction, a y-axis direction, or a z-axis direction).

[0062] The magnetic member MG may be disposed in the chamber CH and face the display substrate DS and / or the mask assembly MA. The magnetic member MG may apply a magnetic force to the mask assembly MA and push the mask assembly MA toward the display substrate DS.

[0063] The visual component VS may be arranged in the chamber CH, and may detect (or identify) the position of the display substrate DS and the mask assembly MA. The visual component VS may include a camera for photographing the display substrate DS and the mask assembly MA. Based on the image photographed by the visual component VS, the position of the display substrate DS and the mask assembly MA may be identified, and the deformation of the mask assembly MA may be confirmed. Based on the image, the position of the display substrate DS in the first support member SP1 or the position of the mask assembly MA on the second support member SP2 may be adjusted (e.g., fine-tuned). Hereinafter, an embodiment of aligning the position of the display substrate DS and the mask assembly MA by fine-tuning the position of the mask assembly MA on the second support member SP2 will be described in detail below.

[0064] The pressure regulator PSC may be connected to the chamber CH and adjust the pressure in the chamber CH. For example, the pressure regulator PSC may adjust the pressure in the chamber CH to be substantially the same as or similar to the atmospheric pressure. The pressure regulator PSC may adjust the pressure in the chamber CH to be substantially the same as or similar to a vacuum state.

[0065] The pressure regulator PSC may include a connection pipe 81 connected to the chamber CH and a pump 82 disposed on the connection pipe 81. According to the operation of the pump 82, external air may be introduced into the chamber CH through the connection pipe 81, or the air in the chamber CH may be discharged to the outside through the connection pipe 81.

[0066] According to a method of manufacturing a display device (not shown) using the apparatus 1 for manufacturing a display device as described above, a display substrate DS may be provided.

[0067] The pressure regulator PSC may maintain the pressure inside the chamber CH substantially equal to or similar to the atmospheric pressure, and the gate valve GB may open an opening portion of the chamber CH.

[0068] The display substrate DS can be moved from the outside of the chamber CH to the chamber CH. Various methods can be used to move the display substrate DS to the chamber CH. For example, the display substrate DS can be moved from the outside of the chamber CH to the chamber CH by a robot arm or the like arranged outside the chamber CH. In another embodiment, in the case where the first support member SP1 is formed in the form of a shuttle, the first support member SP1 can be moved from the inside of the chamber CH to the outside of the chamber CH, the display substrate DS can be mounted on the first support member SP1 by a robot arm or the like arranged outside the chamber CH, and the first support member SP1 can be moved from the outside of the chamber CH to the chamber CH.

[0069] The mask assembly MA may be moved into the chamber CH. In one embodiment, the mask assembly MA may be moved from the outside of the chamber CH to the inside of the chamber CH using a method substantially the same as or similar to that described with reference to the display substrate DS.

[0070] In the case where the display substrate DS is moved into the chamber CH, the display substrate DS may be mounted on the first support member SP1. The visual component VS may detect the position of the display substrate DS and the mask assembly MA. The positions of the display substrate DS and the mask assembly MA may be recognized based on an image captured by the visual component VS. In an embodiment, a separate controller (not shown) may be provided in the apparatus 1 for manufacturing a display device to recognize the positions of the display substrate DS and the mask assembly MA.

[0071] In a case where the positions of the display substrate DS and the mask assembly MA are recognized (eg, completely recognized), the second support member SP2 may adjust (eg, fine-tune) the position of the mask assembly MA.

[0072] The deposition source SC may provide the deposition material M to the mask assembly MA, and the deposition material M having passed through the mask assembly MA may be deposited on the display substrate DS. The deposition source SC may move in parallel relative to the display substrate DS and the mask assembly MA, or the display substrate DS and the mask assembly MA may move in parallel relative to the deposition source SC. The deposition source SC may move relative to the display substrate DS and the mask assembly MA. The pump 82 may suck air in the chamber CH, discharge the air to the outside, and maintain the pressure in the chamber CH substantially the same as or similar to a vacuum state.

[0073] The deposition material M provided from the deposition source SC can pass through the mask assembly MA and be deposited on the display substrate DS. By depositing the deposition material M on the display substrate DS, at least one of multiple layers such as an organic layer, an inorganic layer, a metal layer, etc. or a combination thereof to be stacked on the display device can be formed.

[0074] Figure 2 is a schematic cross-sectional view illustrating a mask assembly MA according to an embodiment; Figure 3is a schematic plan view illustrating a portion of a second mask layer 42 according to an embodiment. Figure 3 for Figure 2 Schematic diagram of portion A in plan view.

[0075] refer to Figure 2 and Figure 3 , the mask assembly MA may include a first mask layer 41 and a second mask layer 42 .

[0076] The first mask layer 41 may support the second mask layer 42. The first mask layer 41 may include a first mask opening OP41. The first mask opening OP41 may be arranged (or formed) in the first mask layer 41 to allow the deposition material to pass therethrough (eg, see Figure 1 The inner peripheral surface may be formed in the first mask layer 41 through the first mask opening OP41. The first mask opening OP41 may be arranged in a portion (e.g., a central portion) of the first mask layer 41. A portion (e.g., a central portion) of the second mask layer 42 may be exposed through the first mask opening OP41 of the first mask layer 41. Figure 2 It is illustrated in the cross-sectional view that the inner circumferential surface of the first mask layer 41 is inclined with respect to the second mask layer 42 , but the present disclosure is not limited thereto, and the inner circumferential surface of the first mask layer 41 may be perpendicular to the second mask layer 42 .

[0077] The first mask layer 41 may include a silicon material. For example, the first mask layer 41 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiO x N y ) at least one of.

[0078] The second mask layer 42 may be disposed on the first mask layer 41. The second mask layer 42 may include a second mask opening OP42. The second mask opening OP42 may be arranged (or formed) in the second mask layer 42 to allow the deposition material to pass therethrough (eg, see Figure 1 In a plan view, the second mask opening OP42 may overlap with the first mask opening OP41. The second mask 42 may include a plurality of second mask openings OP42. For example, Figure 3 As shown in FIG. 4 , a plurality of second mask openings OP42 may be arranged in a first direction (eg, an x-axis direction) and a second direction (eg, a y-axis direction). The second mask layer 42 may include a stop layer 421 and an inorganic layer 422 .

[0079] The stop layer 421 may be disposed on the first mask layer 41. The stop layer 421 may include an oxide-based material. For example, the stop layer 421 may include a zinc oxide-based material, such as zinc oxide, indium zinc oxide, gallium indium zinc oxide, etc., or a combination thereof. In one embodiment, the stop layer 421 may include In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO), InGa-Sn-Zn-O (IGTZO), etc., or a combination thereof, which includes metals such as indium (In), gallium (Ga), and tin (Sn) (except ZnO).

[0080] The inorganic layer 422 may be disposed on the stop layer 421. For example, the inorganic layer 422 may include SiO x 、SiN x and SiO x N y At least one of .

[0081] The second mask opening OP42 may include a stop layer opening OP421 and an inorganic opening OP422. The stop layer opening OP421 may be arranged (or formed) in the stop layer 421, and the inorganic opening OP422 may be arranged (or formed) in the inorganic layer 422. The stop layer opening OP421 and the inorganic opening OP422 may correspond to each other in a plan view, for example, overlap. Therefore, the deposited material (for example, see Figure 1 The stop layer opening OP421 and the inorganic opening OP422 may pass through the stop layer opening OP421 and the inorganic opening OP422 in sequence. For example, in a plan view, the shapes of the stop layer opening OP421 and the inorganic opening OP422 may be substantially the same as each other. In a cross-sectional view, the width of the stop layer opening OP421 and the width of the inorganic opening OP422 may be substantially the same as each other. The stop layer opening OP421 may correspond to the first mask opening OP41.

[0082] Figures 4 to 14 is a schematic cross-sectional view of a mask assembly MA for illustrating a method of manufacturing a display device according to an embodiment.

[0083] exist Figures 4 to 14 In, with Figures 1 to 3 The same reference numerals as those in the accompanying drawings denote the same components, and a description thereof will not be given repeatedly.

[0084] refer to Figures 4 to 14 , a method for manufacturing a display device may include arranging a mask assembly MA in a chamber (see, for example, Figure 1 of CH).

[0085] Arranging the mask assembly MA may include disposing a stop layer 421 having a stop layer opening OP421 disposed therein on the first mask layer 41, disposing an inorganic layer 422 on the stop layer 421, forming a first mask opening OP41 in the first mask layer 41, and etching the inorganic layer 422 to form the stop layer opening OP421.

[0086] Figures 4 to 7 It is illustrated that a stop layer 421 having a stop layer opening OP421 arranged therein is provided on the first mask layer 41 .

[0087] refer to Figure 4 and Figure 5 Disposing the stop layer 421 in which the stop layer opening OP421 is arranged on the first mask layer 41 may include disposing the first photoresist layer PRL1 in which the first photo opening OPPRL1 is arranged on the first mask layer 41 .

[0088] refer to Figure 4 , a first photoresist material PRM1 may be disposed on the first mask layer 41. The first photoresist material PRM1 may include a photosensitive material. A first photomask PMA1 that has been patterned may be disposed on the first photoresist material PRM1. The first photomask PMA1 may include a plurality of first photomask openings OPPMA1. Each first photomask opening OPPMA1 may be arranged (or formed) in the first photomask PMA1. Light LT may be irradiated from the top of the first mask layer 41 toward the first photoresist material PRM1. For example, the light LT may be ultraviolet rays, etc.

[0089] A portion of the light LT may penetrate (or pass through) the first photomask opening OPPMA1 and reach the first photoresist material PRM1, and another portion of the light LT may be blocked by the first photomask PMA1 and not reach the first photoresist material PRM1. A portion of the first photoresist material PRM1 overlapping the first photomask opening OPPMA1 in plan view may be cured.

[0090] refer to Figure 5 , which does not overlap with the first photomask opening in plan view (see, for example, Figure 4 OPPMA1) overlaps and uncured first photoresist material (e.g., see Figure 4 A portion of the PRM1) may be removed. In removing the first photoresist material (eg, see Figure 4 After a portion of the PRM1 is formed, a first photoresist layer PRL1 that has been patterned may be formed. The first photoresist layer PRL1 may include a first photo opening OPPRL1. The first photo opening OPPRL1 may be formed in the first photoresist layer PRL1.

[0091] refer to Figure 6and Figure 7 , disposing the stop layer 421 in which the stop layer opening OP421 is arranged on the first mask layer 41 may include disposing the stop layer 421 on the first photoresist layer PRL1. A portion of the stop layer 421 may be disposed on the first mask layer 41, and another portion of the stop layer 421 may be disposed on the first photoresist layer PRL1. A portion of the stop layer 421 may overlap with the first photo opening OPPRL1 in a plan view, and another portion of the stop layer 421 may not overlap with the first photo opening OPPRL1 in a plan view.

[0092] A portion of the stop layer 421 may be accommodated in the first optical opening OPPRL1 (or between the first photoresist layers PRL1). A portion of the stop layer 421 overlapping with the first optical opening OPPRL1 in a plan view may contact the top surface of the first mask layer 41, and another portion of the stop layer 421 not overlapping with the first optical opening OPPRL1 in a plan view may contact the top surface of the first photoresist layer PRL1.

[0093] refer to Figure 7 , disposing the stop layer 421 in which the stop layer opening OP421 is arranged on the first mask layer 41 may include removing the first photoresist layer (eg, see Figure 6 PRL1). After removing the first photoresist layer (see, for example, Figure 6 In the process of PRL1), contacting the first photoresist layer (for example, see Figure 6 The portion of the stop layer 421 on the top surface of the PRL1) may also be removed. Figure 6 The portion of the stop layer 421 overlapping the OPPRL1 may remain without being removed. As a result, the stop layer opening OP421 may be arranged in the stop layer 421.

[0094] Figure 8 It is illustrated that the inorganic layer 422 is disposed on the stop layer 421. In the process of disposing the inorganic layer 422 on the stop layer 421, the inorganic layer 422 may be disposed on the stop layer 421, and the stop layer 421 is disposed on the first mask layer 41. Figure 8 The inorganic layer 422 is illustrated as not formed in the stop layer opening OP421, but the present disclosure is not limited thereto, and the inorganic layer 422 may be formed in the stop layer opening OP421 depending on the physical properties of the inorganic layer 422. A portion of the inorganic layer 422 may be disposed on the stop layer 421, and another portion of the inorganic layer 422 may be disposed on the first mask layer 41.

[0095] Figures 9 to 12 It is illustrated that a first mask opening OP41 is formed in the first mask layer 41 .

[0096] refer to Figures 9 to 11 , forming the first mask opening OP41 in the first mask layer 41 may include disposing a second photoresist layer PRL2 in which the second photoresist opening OPPRL2 is arranged (or formed) under the first mask layer 41. The second photoresist layer PRL2 may include the second photo opening OPPRL2.

[0097] refer to Fig. 9 , the second photoresist material PRM2 may be disposed under the first mask layer 41. For example, the first mask layer 41 may be disposed on the second photoresist material PRM2, the stop layer 421 may be disposed on the first mask layer 41, and the inorganic layer 422 may be disposed on the stop layer 421. The second photoresist material PRM2 may include a photosensitive material.

[0098] refer to Fig.10 , the patterned second photomask PMA2 may be disposed below the second photoresist material PRM2. The second photomask PMA2 may include a plurality of second photomask openings OPPMA2. Each second photomask opening OPPMA2 may be arranged (or formed) in the second photomask PMA2. The light LT may be irradiated from the bottom of the first mask layer 41 toward the second photoresist material PRM2. For example, the light LT may be ultraviolet rays or the like.

[0099] A portion of the light LT may pass through (or penetrate) the second photomask opening OPPMA2 and reach the second photoresist material PRM2, and another portion of the light LT may be blocked by the second photomask PMA2 and cannot reach the second photoresist material PRM2. A portion of the second photoresist material PRM2 overlapping the second photomask opening OPPMA2 in a plan view may be cured.

[0100] refer to Fig.11 , which does not overlap with the second photomask opening in plan view (see, for example, Fig.10 OPPMA2) overlapped and uncured second photoresist material (e.g., see Fig.10 A portion of the PRM2) may be removed. In removing the second photoresist material (eg, see Fig.10 After forming a portion of the PRM2, a second photoresist layer PRL2 in which a second optical opening OPPRL2 is arranged may be formed. The first mask layer 41 may be exposed from the second photoresist layer PRL2 through the second optical opening OPPRL2.

[0101] refer to Fig.12, forming the first mask opening OP41 in the first mask layer 41 may include etching the first mask layer 41 overlapping the second photo opening OPPRL2 arranged in the second photoresist layer PRL2 in a plan view. A portion of the first mask layer 41 may be removed by an etching process. For example, the first mask layer 41 may be etched by a dry etching process.

[0102] As the first mask layer 41 is etched, the first mask opening OP41 may be arranged (or formed) in the first mask layer 41. Through the first mask opening OP41, the stop layer 421 may be exposed from the first mask layer 41. Through the first mask opening OP41 and the stop layer opening OP421, the inorganic layer 422 may be exposed from the first mask layer 41 and the stop layer 421.

[0103] Fig.13 The etching of a portion of the inorganic layer 422 overlapping with the stop layer opening OP421 in the plan view is illustrated. A portion of the inorganic layer 422 may be removed by an etching process. For example, the inorganic layer 422 may be etched by a dry etching process. The etching of the inorganic layer 422 may be performed in a direction (for example, +z-axis direction) in which the stop layer 421 faces the inorganic layer 422.

[0104] In the etching process of the inorganic layer 422, the stop layer 421 may not be etched. In the etching process of the inorganic layer 422, the stop layer 421 may be used as a mask. For example, the etching gas may pass through the stop layer opening OP421 and contact the inorganic layer 422. In the etching process of the inorganic layer 422, the inorganic opening OP422 may be formed in the inorganic layer 422.

[0105] refer to Fig.14 , forming the first mask opening OP41 in the first mask layer 41 may include removing the second photoresist layer (eg, see Fig.13 With the second photoresist layer PRL2 removed, the mask assembly MA may be manufactured.

[0106] Reference again Figure 12 to Figure 14 , Fig.13 The etching of the inorganic layer 422 described in Fig.12 The etching of the first mask layer 41 and Fig.14 The removal of the second photoresist layer PRL2 described in the above is performed between. Fig.13 In the etching of the inorganic layer 422 shown in FIG. 4 , the second photoresist layer PRL2 may still remain without being removed, and the first mask layer 41 may not be etched.

[0107] although Figure 4 , Figure 5 , Figures 9 to 11A negative photoresist material whose solubility decreases when exposed to light LT is exemplified, but the present disclosure is not limited thereto, and a positive photoresist material whose solubility increases when exposed to light may be used.

[0108] Fig.15 FIG. 2 is a schematic perspective view illustrating a display device 2 according to an embodiment.

[0109] refer to Fig.15 , the display device 2 may include a display area DA and a peripheral area PA disposed adjacent to the display area DA. For example, the peripheral area PA may surround the display area DA. The display device 2 may provide an image (e.g., a specific image) using light emitted from a plurality of pixels (not shown) arranged in the display area DA.

[0110] The peripheral area PA may substantially (or completely) surround the display area DA. The peripheral area PA may be a non-display area in which pixels are not arranged, and a driver or wiring that supplies electrical signals or power to the pixels may be arranged therein.

[0111] refer to Fig.15 The display device 2 may have a rectangular shape in a plan view, in which the horizontal length is greater than the vertical length, but the present disclosure is not limited thereto. The display device 2 may have various shapes, such as a polygon, a circle, an ellipse, etc., or a combination thereof.

[0112] Hereinafter, according to an embodiment, the display device 2 may be an organic light emitting display device, but the present disclosure is not limited thereto. In another embodiment, the display device 2 may be other types of display devices, such as a quantum dot light emitting display device.

[0113] Fig.16 2 is a schematic cross-sectional view illustrating a display device 2 according to an embodiment. Fig.16 It can correspond to along Fig.15 A cross section taken along line AA' is shown in FIG.

[0114] refer to Fig.16 The display device 2 may include a display panel 10, an input sensing layer 40 disposed on the display panel 10, an optical function layer 50 disposed on the input sensing layer 40, and a window 60 covering the display panel 10, the input sensing layer 40, and the optical function layer 50. The display device 2 may be various types of electronic devices, such as a mobile phone, a notebook computer, a smart watch, etc.

[0115] The display panel 10 may display an image. The display panel 10 may include pixels arranged in a display area DA. The pixels may include a display element and a pixel circuit connected to the display element. The display element may be an organic light emitting diode, a quantum dot organic light emitting diode, etc. or a combination thereof.

[0116] The input sensing layer 40 may obtain coordinate information according to external inputs such as touch events. The input sensing layer 40 may include sensing electrodes (or touch electrodes) and traces connected to the sensing electrodes. The input sensing layer 40 may be disposed on the display panel 10. The input sensing layer 40 may detect external inputs by a mutual capacitance method, a self-capacitance method, etc., or a combination thereof.

[0117] The input sensing layer 40 may be formed on the display panel 10. For example, the input sensing layer 40 may be directly formed on the display panel 10, or may be formed separately and bonded to the display panel 10 through an adhesive layer such as an optically transparent adhesive. For example, the input sensing layer 40 may be sequentially formed after a process of forming the display panel 10, the input sensing layer 40 may be a part of the display panel 10, and an adhesive layer may not be formed between the input sensing layer 40 and the display panel 10. Although Fig.16 The input sensing layer 40 is illustrated as being disposed between the display panel 10 and the optical function layer 50 , but the disclosure is not limited thereto. In another embodiment, the input sensing layer 40 may be disposed on the optical function layer 50 , and the input sensing layer 40 may be disposed between the optical function layer 50 and the window 60 .

[0118] The optical function layer 50 may include an anti-reflection layer (not shown). The anti-reflection layer may reduce the reflectivity of light (external light) incident from the outside to the display panel 10 through the window 60. In one embodiment, the anti-reflection layer may include a black matrix, a color filter (not shown), etc. or a combination thereof. The color filter may be arranged according to the color of light emitted from each of the pixels of the display panel 10.

[0119] In another embodiment, the anti-reflection layer may include a retarder (not shown) and a polarizer (not shown). The retarder may be of a film type, a liquid crystal coating type, etc., and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may be of a film type, a liquid crystal coating type, etc. The film type polarizer may include a stretched synthetic resin film, etc., and the liquid crystal coating type polarizer may include a liquid crystal of an arrangement (e.g., a specific or selectable arrangement), etc. The retarder and the polarizer may each further include a protective film (not shown), etc. The retarder and the polarizer or the protective film may be a base layer of the anti-reflection layer.

[0120] In another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light respectively reflected from the first reflective layer and the second reflective layer may undergo constructive interference, and the refractive index of the external light may be reduced.

[0121] In one embodiment, the optical function layer 50 may be sequentially formed after forming the display panel 10 and / or the input sensing layer 40. An adhesive layer may not be disposed between the display panel 10 and / or the input sensing layer 40 and the optical function layer 50.

[0122] although Fig.16 Not shown in the figure, a layer (eg, an adhesive layer) including an optically transparent adhesive or an optically transparent resin may be disposed between the window 60 and the optical functional layer 50 .

[0123] Fig.17 1 is a schematic plan view illustrating a display panel 10 according to an embodiment. Fig.16 According to the display device of one embodiment (for example, see Fig.15 2) may include a display panel 10. Fig.17 An image of the substrate 100 of the display panel 10 is illustrated.

[0124] refer to Fig.17 , the display panel 10 may include a display area DA and a peripheral area PA disposed adjacent to the display area DA. For example, the peripheral area PA may surround the display area DA. The display area DA may be an area for displaying an image, and a plurality of pixels P may be arranged in the display area DA. The display area DA may have various shapes in a plan view, such as a circle, an ellipse, a polygon, a specific pattern, etc. Fig.17 The shape of the exemplary display area DA is approximately a rectangle with rounded corners, but the present disclosure is not limited thereto.

[0125] Each of the pixels P may be a sub-pixel, and may include a display element such as an organic light emitting diode OLED, etc. The pixel P may emit, for example, red light, green light, blue light, or white light.

[0126] The peripheral area PA may be arranged adjacent to the display area DA (or may surround the display area DA). A circuit driving the pixel P (e.g., a peripheral circuit) may be arranged in the peripheral area PA. The first scan drive circuit 11, the second scan drive circuit 12, the emission control drive circuit 13, the terminal 14, the drive power wiring 15, and the common power wiring 16 may be arranged in the peripheral area PA.

[0127] The first scan driving circuit 11 may provide a scan signal to the pixel P through the scan line SL. The second scan driving circuit 12 may be arranged in parallel with the first scan driving circuit 11, and the display area DA is disposed between the first scan driving circuit 11 and the second scan driving circuit 12. Some pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit 11, and other pixels P may be connected to the second scan driving circuit 12. In another embodiment, the second scan driving circuit 12 may be omitted, and all pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit 11.

[0128] The emission control driving circuit 13 may be disposed beside (or adjacent to) the first scanning driving circuit 11, and may provide an emission control signal to the pixel P through the emission control line EL. Fig.17 The emission control driving circuit 13 is illustrated as being disposed at one side of the display area DA, but the present disclosure is not limited thereto, and the emission control driving circuit 13 may be disposed at both sides of the display area DA, similar to the first scan driving circuit 11 and the second scan driving circuit 12 .

[0129] In one embodiment, the peripheral area PA may include a bending area (not shown) extending from one side of the display area DA (in the -y axis direction). The bending area may be bent toward the back surface (or rear surface) of the display area DA, thereby reducing the area of ​​the non-display area that can be identified when viewed from the front surface (or top surface) of the display device.

[0130] The driving chip 20 may be disposed in the peripheral area PA. The driving chip 20 may include an integrated circuit (not shown) driving the display panel 10. The integrated circuit may include a data driving integrated circuit generating a data signal, but the present disclosure is not limited thereto.

[0131] The terminal 14 may be disposed in the peripheral area PA. The terminal 14 may be exposed without being covered by the insulating layer and may be electrically connected to the printed circuit board 30. The terminal 34 of the printed circuit board 30 may be electrically connected to the terminal 14 of the display panel 10.

[0132] The printed circuit board 30 may transmit signals, power, etc. of a controller (not shown) to the display panel 10. A control signal generated in the controller may be transmitted to each driving circuit through the printed circuit board 30. The controller may transmit a driving voltage (e.g., Fig.18 ELVDD) is transmitted to the driving power wiring 15, and the common voltage (for example, see Fig.18 The driving power wiring 15 may be provided to the common power wiring 16. The driving voltage ELVDD may be transmitted to each of the pixels P through the driving voltage line PL connected to the driving power wiring 15, and the common voltage ELVSS may be transmitted to the opposite electrode of the pixel P through the common power wiring 16. In a plan view, the driving power wiring 15 may have a shape extending in one direction (x-axis direction) below the display area DA. The common power wiring 16 may have a ring shape, one side of which is open and partially surrounds the display area DA in a plan view.

[0133] The controller may generate a data signal. The generated data signal may be transferred to the input line IL through the driving chip 20, and transferred to the pixel PX through the data line DL connected to the input line IL. In the specification, "line" may include "wiring".

[0134] Fig.18 According to an embodiment, a display device (eg, see Fig.15 2) is a schematic diagram of the equivalent circuit of the pixel P.

[0135] refer to Fig.18 , the pixel P may include a pixel circuit PC and an organic light emitting diode OLED as a display element electrically connected to the pixel circuit PC. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each of the pixels P may emit red light, green light, or blue light through the organic light emitting diode OLED, or emit red light, green light, blue light, or white light.

[0136] The second thin film transistor T2 as a switching thin film transistor may be electrically connected to the scan line SL and the data line DL, and may transmit a data voltage input from the data line DL to the first thin film transistor T1 based on a switching voltage input from the scan line SL. The storage capacitor Cst may be electrically connected to the second thin film transistor T2 and the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage delivered from the second thin film transistor T2 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0137] The first thin film transistor T1 as a driving thin film transistor may be electrically connected to the driving voltage line PL and the storage capacitor Cst, and may control the driving current flowing from the driving voltage line PL to the organic light emitting diode OLED in response to the voltage stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light of a certain brightness (e.g., a specific or selectable brightness) in response to the driving current. An opposing electrode (e.g., a cathode) of the organic light emitting diode OLED may receive a common voltage ELVSS.

[0138] although Fig.18 The illustrated pixel circuit PC includes two thin film transistors and one storage capacitor, but the present disclosure is not limited thereto. The number of thin film transistors and the number of storage capacitors may be modified differently according to the design of the pixel circuit PC. For example, the pixel circuit PC may further include three, four, five or more thin film transistors.

[0139] Fig.19 The display device 2 according to an embodiment is shown as an example. Fig.17 Schematic cross-sectional view taken along line DD' in FIG.

[0140] refer to Fig.19 The display device 2 (eg, the display panel 10 of the display device 2 ) may include a substrate 100 .

[0141] The substrate 100 may include glass, polymer resin, etc. or a combination thereof. In one embodiment, the substrate 100 may have a multi-layer structure in which a base layer including a polymer resin and a barrier layer for preventing foreign matter from penetrating are alternately stacked.

[0142] The base layer may include a polymer resin, which includes polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), cellulose acetate propionate (CAP), etc. or a combination thereof.

[0143] The barrier layer may include an inorganic material such as silicon nitride (SiN x ), silicon oxide (SiO x ) etc. or a combination thereof.

[0144] A first pixel P1 emitting a first color light, a second pixel P2 emitting a second color light, and a third pixel P3 emitting a third color light may be arranged in the display area DA of the substrate 100. The first color, the second color, and the third color may each be one of red, blue, green, and white.

[0145] The first pixel P1 may include a first pixel circuit PC1 and a first organic light emitting diode OLED1 electrically connected to the first pixel circuit PC1 as a display element. The second pixel P2 may include a second pixel circuit PC2 and a second organic light emitting diode OLED2 electrically connected to the second pixel circuit PC2. The third pixel P3 may include a third pixel circuit PC3 and a third organic light emitting diode OLED3 electrically connected to the third pixel circuit PC3.

[0146] The buffer layer 201 may be disposed on the substrate 100 and prevent impurities from penetrating into the semiconductor layer Act of the thin film transistor TFT of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3. The buffer layer 201 may include an inorganic insulating material such as SiN x 、Silicon Oxynitride (SiO x N y )、SiO x etc. or a combination thereof, and may have a single layer or multiple layers.

[0147] The first pixel circuit PC1, the second pixel circuit PC2 and the third pixel circuit PC3 may be disposed on the buffer layer 201. The first pixel circuit PC1 may include a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE and a drain electrode DE. Fig.19 The thin film transistor TFT shown in FIG. Fig.18 The data line DL may be electrically connected to the first thin film transistor T1. Fig.19 The second thin film transistor T2 is not shown but included in the first pixel circuit PC1. Fig.192 shows a top gate type, in which the gate electrode GE is disposed on the semiconductor layer Act, and the gate insulating layer 203 is interposed between the semiconductor layer Act and the gate electrode GE, but the present disclosure is not limited thereto, and according to another embodiment, the thin film transistor TFT may be a bottom gate type. The second pixel circuit PC2 and the third pixel circuit PC3 may have a structure substantially the same as or similar to that of the first pixel circuit PC1. Hereinafter, components of the first pixel circuit PC1 will be described.

[0148] The semiconductor layer Act may include polysilicon, etc. In another embodiment, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, an organic semiconductor, etc., or a combination thereof. The gate electrode GE may include a low-resistance metal. The gate electrode GE may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., or a combination thereof, and may have a single layer or a multilayer.

[0149] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as SiO x 、SiN x 、SiO x N y 、Alumina (Al 2 O 3 ), titanium oxide (TiO x ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or the like or a combination thereof. The gate insulating layer 203 may have a single layer or multiple layers.

[0150] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 overlapping each other in a plan view with the first interlayer insulating layer 205 interposed therebetween. In a plan view, the storage capacitor Cst may overlap the thin film transistor TFT. Fig.19 The gate electrode GE of the exemplary thin film transistor TFT is the lower electrode CE1 of the storage capacitor Cst. In another embodiment, the storage capacitor Cst may not overlap with the thin film transistor TFT in a plan view. The storage capacitor Cst may be covered by the second interlayer insulating layer 207. The upper electrode CE2 of the storage capacitor Cst may include a conductive material such as Mo, Al, Cu, Ti, etc. or a combination thereof, and may have a single layer or multiple layers.

[0151] The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may include an inorganic insulating material such as SiO x 、SiN x 、SiO x N y 、Al 2 O 3 、TiOx 、 2 O 5 , HfO 2 The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may each have a single layer or a plurality of layers.

[0152] The source electrode SE and the drain electrode DE and the data line DL may be disposed on the same layer and may include the same material. For example, the source electrode SE, the drain electrode DE and the data line DL may be disposed on the second interlayer insulating layer 207. The source electrode SE, the drain electrode DE and the data line DL may include a highly conductive material. The source electrode SE and the drain electrode DE may each include a conductive material such as Mo, Al, Cu, Ti, etc. or a combination thereof, and may have a single layer or multiple layers. In one embodiment, the source electrode SE, the drain electrode DE and the data line DL may each include a multilayer of Ti / Al / Ti.

[0153] The first, second, and third pixel circuits PC1, PC2, and PC3, each including a thin film transistor TFT and a storage capacitor Cst, may be covered by a first organic insulating layer 209. The first organic insulating layer 209 may include a substantially flat top surface.

[0154] A first organic light emitting diode OLED1 electrically connected to the first pixel circuit PC1 , a second organic light emitting diode OLED2 electrically connected to the second pixel circuit PC2 , and a third organic light emitting diode OLED3 electrically connected to the third pixel circuit PC3 may be disposed on the first organic insulating layer 209 .

[0155] The first pixel circuit PC1 may be electrically connected to the first pixel electrode 221r ​​of the first organic light emitting diode OLED1. Fig.19 , the contact metal layer CM may be disposed between the thin film transistor TFT and the first pixel electrode 221r. The contact metal layer CM may contact the thin film transistor TFT through a contact hole penetrating the first organic insulating layer 209, and the first pixel electrode 221r ​​may contact the contact metal layer CM through a contact hole penetrating the second organic insulating layer 211. The contact metal layer CM may include a conductive material such as Mo, Al, Cu, Ti, etc. or a combination thereof, and may have a single layer or multiple layers. In one embodiment, the contact metal layer CM may have multiple layers of Ti / Al / Ti.

[0156] The first organic insulating layer 209 and the second organic insulating layer 211 may each include an organic insulating material, such as a general polymer (such as polymethyl methacrylate (PMMA), polystyrene (PS)), etc. or a combination thereof, a polymer derivative having a phenol group, an acryl polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, etc. or a blend thereof. In one embodiment, the first organic insulating layer 209 and the second organic insulating layer 211 may each include polyimide, etc.

[0157] According to another embodiment, one of the first organic insulating layer 209 and the second organic insulating layer 211 may be omitted, and the contact metal layer CM may be omitted.

[0158] The first organic light emitting diode OLED1 may include a first pixel electrode 221r, a first emission layer 222r, and a first counter electrode 223r. The second organic light emitting diode OLED2 may include a second pixel electrode 221g, a second emission layer 222g, and a second counter electrode 223g. The third organic light emitting diode OLED3 may include a third pixel electrode 221b, a third emission layer 222b, and a third counter electrode 223b. The second organic light emitting diode OLED2 and the third organic light emitting diode OLED3 may have a structure substantially the same as or similar to that of the first organic light emitting diode OLED1.

[0159] The first pixel electrode 221r ​​may be disposed on the second organic insulating layer 211. The first pixel electrode 221r ​​may include a conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO), aluminum zinc oxide (AZO), etc. or a combination thereof. According to another embodiment, the first pixel electrode 221r ​​may include a reflective film such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), etc. or an alloy thereof. In another embodiment, the first pixel electrode 221r ​​may further include a reflective film such as ITO, IZO, ZnO, In 2 O 3 etc. or a combination thereof.

[0160] The pixel defining layer 213 and the bank layer 215 may be disposed on the first pixel electrode 221r. In a plan view, the pixel defining layer 213 may overlap with an edge of the first pixel electrode 221r. The pixel defining layer 213 may include an inorganic insulating material such as SiN x 、SiO x N y 、SiOx etc. or a combination thereof.

[0161] The first remaining sacrificial layer 212R may be disposed between the first pixel electrode 221r ​​and the pixel defining layer 213. The first remaining sacrificial layer 212R may include a portion remaining after removing a sacrificial layer (not shown) protecting the top surface of the first pixel electrode 221r. The first remaining sacrificial layer 212R may be disposed in a region where the pixel defining layer 213 and the first pixel electrode 221r ​​overlap each other in a plan view. For example, the first remaining sacrificial layer 212R may be arranged along an edge of the first pixel electrode 221r ​​and expose a portion (e.g., a central portion) of the first pixel electrode 221r.

[0162] The first remaining sacrificial layer 212R may be formed continuously after forming the first pixel electrode 221r, and may include a material that can be selectively etched without damaging the first pixel electrode 221r. For example, the first remaining sacrificial layer 212R may include IGZO, IZO, or the like.

[0163] The first remaining sacrificial layer 212R and the pixel defining layer 213 may overlap the edge of the first pixel electrode 221r ​​in a plan view and increase the distance between the first pixel electrode 221r ​​and the dam layer 215 and the first counter electrode 223r, thereby preventing arcing, etc. from occurring in the first pixel electrode 221r, the dam layer 215, and the first counter electrode 223r. In various embodiments, the sacrificial layer may be completely removed, and the first remaining sacrificial layer 212R may not be formed. The groove obtained by removing the sacrificial layer between the first pixel electrode 221r ​​and the pixel defining layer 213 may be empty, or the first emission layer 222r described below may be formed in the groove.

[0164] The bank layer 215 may be disposed on the pixel defining layer 213. The bank layer 215 may include a conductive material. For example, the bank layer 215 may include a conductive material such as Mo, Al, Cu, Ti, etc. or a combination thereof, and may have a single layer or multiple layers. For example, the bank layer 215 may have a double-layer structure including Al / Ti or a triple-layer structure including Ti / Al / Ti, etc.

[0165] The pixel defining layer 213 and the bank layer 215 may extend from the display area DA of the substrate 100 to the peripheral area (eg, see Fig.17 The dam layer 215 may contact (eg, directly contact) the peripheral region (eg, see Fig.17 Common power supply wiring in PAs (see, for example, Fig.17 16). Accordingly, the bank layer 215 may be used as a connection electrode or an auxiliary wiring for supplying the common voltage ELVSS to the first counter electrode 223r, the second counter electrode 223g, and the third counter electrode 223b described below.

[0166] The first conductive layer 217 may be disposed on the bank layer 215. The first conductive layer 217 may have a tip 217T protruding in a direction from the center of the first pixel electrode 221r. In a plan view, the tip 217T of the first conductive layer 217 may have a ring shape surrounding (eg, completely surrounding) the first pixel electrode 221r.

[0167] The first opening OP1 may penetrate the pixel defining layer 213, the dam layer 215, and the first conductive layer 217, and expose the center of the top surface of the first pixel electrode 221r, and the first emission layer 222r described below may overlap and contact the first pixel electrode 221r ​​through the first opening OP1 in a plan view. Accordingly, the first opening OP1 may define a first emission area EA1. The outside of the first emission area EA1 may be a non-emission area NEA. Similarly, the second opening OP2 may define a second emission area EA2, and the third opening OP3 may define a third emission area EA3.

[0168] A portion of the first conductive layer 217 may be spaced apart from the dam layer 215 in a direction perpendicular to the substrate 100 (z-axis direction), and a tip 217T protruding in a direction from the center of the first pixel electrode 221r ​​is formed. The tip 217T of the first conductive layer 217 may be formed as a portion of the sacrificial layer between the first conductive layer 217 and the dam layer 215 is removed, and the first conductive layer 217 may have an undercut structure. Accordingly, the tip 217T of the first conductive layer 217 may have an eaves structure in which the bottom surface of the tip 217T is exposed. The protruding length of the tip 217T of the first conductive layer 217 may be equal to or greater than about 0.5um. In various embodiments, the protruding length of the tip 217T of the first conductive layer 217 may be in the range of about 0.3um to about 1um. For example, the protruding length of the tip 217T of the first conductive layer 217 may be in the range of about 0.3um to about 0.7um.

[0169] The first conductive layer 217 may include a conductive material. For example, the first conductive layer 217 may include a conductive material such as Mo, Al, Cu, Ti, etc. or a combination thereof, and may have a single layer or multiple layers. For example, the first conductive layer 217 may have a double-layer structure of Al / Ti or a triple-layer structure of Ti / Al / Ti, etc.

[0170] In one embodiment, a low reflectivity layer (not shown) may be provided on the first conductive layer 217. The low reflectivity layer may include a layer having a surface reflectivity lower than that of the first conductive layer 217. The low reflectivity layer may prevent light (external light) incident to the display device 2 from being reflected on the surface of the first conductive layer 217 and being recognized by a user of the display device 2.

[0171] In one embodiment, the low reflectivity layer may include a low reflectivity material. The low reflectivity material may include a metal oxide with high absorptivity (e.g., high extinction coefficient (k)). For example, the low reflectivity layer may include copper oxide (CuO), calcium oxide (CaO), molybdenum oxide (MoO x ) and zinc oxide (ZnO). In one embodiment, the low reflectivity layer may include CuO, CaO, etc. or a combination thereof.

[0172] The second remaining sacrificial layer 214R may be disposed between the bank layer 215 and the first conductive layer 217. The second remaining sacrificial layer 214R may be a remaining portion of the sacrificial layer that is removed to form the tip 217T of the first conductive layer 217. In a plan view, the second remaining sacrificial layer 214R may be spaced apart from the first pixel electrode 221r ​​by a certain distance (e.g., a specific or optional distance), and may have a ring shape surrounding (e.g., completely surrounding) the first pixel electrode 221r. Because of the second remaining sacrificial layer 214R, the first conductive layer 217 may have an undercut structure.

[0173] The second remaining sacrificial layer 214R may determine the protruding length of the tip 217T of the first conductive layer 217. For example, the second remaining sacrificial layer 214R may be disposed inside the end of the tip 217T of the first conductive layer 217, and the protruding length of the tip 217T may be the length from the sidewall of the second remaining sacrificial layer 214R to the end of the tip 217T.

[0174] The second remaining sacrificial layer 214R may include a material that can be selectively etched without damaging the first pixel electrode 221r, the bank layer 215, and the first conductive layer 217. For example, the second remaining sacrificial layer 214R and the first remaining sacrificial layer 212R may include the same material. The second remaining sacrificial layer 214R may include IGZO, IZO, etc., or a combination thereof.

[0175] The first emission layer 222r may be disposed on the first pixel electrode 221r ​​and the first conductive layer 217. For example, the first emission layer 222r may contact the first pixel electrode 221r ​​through the first opening OP1. The first emission layer 222r may include a high-molecular or low-molecular organic material that emits light of a first color (e.g., red). According to another embodiment, the first emission layer 222r may include an inorganic material, a quantum dot, etc., or a combination thereof.

[0176] The first emission layer 222r may include a first functional layer (not shown) and a second functional layer (not shown) on and / or below the first emission layer 222r. The first functional layer may be a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer may be an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0177] although Fig.19 A single stack structure including a single emission layer is exemplified, but in various embodiments, the display device 2 may have a tandem structure such as a multi-stack structure including a plurality of emission layers. In the case where the display device 2 has a tandem structure, a charge generation layer (CGL) may be provided between the emission layers.

[0178] The first emission layer 222r may be isolated from the dummy portion 222rp by the tip 217T of the first conductive layer 217. The first emission layer 222r may include sublayers (eg, a first functional layer, a second functional layer, etc. or a combination thereof). Each sublayer and the dummy portion 222rp may have the same material and / or the same number.

[0179] The first emission layer 222r may have at least one first hole 222rh exposing a portion of the top surface of the first conductive layer 217. The second emission layer 222g may have at least one second hole 222gh exposing a portion of the top surface of the first conductive layer 217. The third emission layer 222b may have at least one third hole 222bh exposing a portion of the top surface of the first conductive layer 217.

[0180] The second emission layer 222g may include a high-molecular or low-molecular organic material that emits light of a second color (eg, green), and the third emission layer 222b may include a high-molecular or low-molecular organic material that emits light of a third color (eg, blue).

[0181] The first opposing electrode 223r may be isolated from the dummy portion 223rp by the tip 217T of the first conductive layer 217. The first opposing electrode 223r and the dummy portion 223rp may include the same material. The second opposing electrode 223g may be isolated from the dummy portion 223gp by the tip 217T of the first conductive layer 217. The third opposing electrode 223b and the dummy portion 223bp may include the same material.

[0182] The first counter electrode 223r may be a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, etc. or alloys thereof. The first counter electrode 223r may further include ITO, IZO, ZnO, In 2 O 3 etc. or a combination thereof.

[0183] The first inorganic encapsulation layer 311 may be disposed on the first counter electrode 223r. Since the first inorganic encapsulation layer 311 has step coverage, the first inorganic encapsulation layer 311 may cover at least a portion of the exposed bottom surface of the tip 217T of the first conductive layer 217. For example, the first inorganic encapsulation layer 311 may be continuously formed and cover the top and side surfaces of the first counter electrode 223r, the side surface of the first emission layer 222r, the side and bottom surfaces of the tip 217T of the first conductive layer 217, the side surface of the second remaining sacrificial layer 214R, and the top surface of the dam layer 215.

[0184] The first inorganic encapsulation layer 311 may include an inorganic insulating material such as SiN x 、SiO x N y 、SiO x The first inorganic encapsulation layer 311 may contact (e.g., directly contact) the metal surface on the side surface and the bottom surface of the tip 217T of the first conductive layer 217 and form an inorganic contact region ICR. Accordingly, the inorganic contact region ICR may form a closed loop surrounding (e.g., completely surrounding) the first organic light emitting diode OLED1, thereby reducing or preventing a path for impurities such as moisture and / or air to penetrate.

[0185] refer to Fig.19 The second inorganic encapsulation layer 312 may encapsulate the second organic light emitting diode OLED2, and the third inorganic encapsulation layer 313 may encapsulate the third organic light emitting diode OLED3. Since the first inorganic encapsulation layer 311, the second inorganic encapsulation layer 312, and the third inorganic encapsulation layer 313 form an inorganic contact region ICR in the display area DA, the peripheral area (for example, see Fig.17 Since the first to third organic light emitting diodes OLED1 to OLED3 are packaged in a pixel unit, although a path through which impurities such as moisture and / or air penetrate is formed, the defects caused by the path can be prevented from propagating to adjacent pixels.

[0186] The organic planarization layer 410 may cover the first inorganic encapsulation layer 311, the second inorganic encapsulation layer 312, and the third inorganic encapsulation layer 313. The organic planarization layer 410 may cover the bumps caused by the pixel defining layer 213, the dam layer 215, and the first conductive layer 217, thereby providing a flat base surface for the components disposed on the organic planarization layer 410. The organic planarization layer 410 may include a polymer material. For example, the organic planarization layer 410 may include an acrylic resin, an epoxy resin, a polyimide, a polyethylene, or the like, or a combination thereof.

[0187] In one embodiment, the refractive index of the organic planarization layer 410 may be greater than the refractive index of the first inorganic encapsulation layer 311, the second inorganic encapsulation layer 312, and the third inorganic encapsulation layer 313. For example, the refractive index of the organic planarization layer 410 may be equal to or greater than about 1.6. The refractive index of the organic planarization layer 410 may be in the range of about 1.6 to about 1.9. The organic planarization layer 410 may further include scattering particles for a higher refractive index. For example, metal oxide particles, such as zinc oxide (ZnO x ), titanium oxide (TiO 2 ), zirconium oxide (ZrO 2 ), barium titanate (BaTiO 3 ) or the like or a combination thereof may be dispersed in the organic planarization layer 410 .

[0188] The protective layer 420 may be disposed on the organic planarization layer 410. The protective layer 420 may include an inorganic insulating material such as SiN x 、SiO x N y 、SiO x In one embodiment, the refractive index of the protection layer 420 may be smaller than the refractive index of the organic planarization layer 410 .

[0189] The antireflection layer 500 including the first color filter 510, the second color filter 520, the third color filter 530, the light shielding layer 540 and the overcoat layer 550 may be disposed on the protective layer 420. The antireflection layer 500 may reduce reflectivity of light (external light) incident from the outside to the display device 2.

[0190] The light shielding layer 540 may overlap the dam layer 215 and the first conductive layer 217 in a plan view, and may at least partially absorb light reflected by the dam layer 215 and the first conductive layer 217 in the non-emission area NEA. The non-emission area NEA may be an area that does not overlap the first emission area EA1, the second emission area EA2, and the third emission area EA3 in a plan view. The light shielding layer 540 may include a black pigment or the like. The light shielding layer 540 may include a black matrix. The first emission area EA1 may include a first filter opening 540OP1 corresponding to the first emission area EA1, a second filter opening 540OP2 corresponding to the second emission area EA2, and a third filter opening 540OP3 corresponding to the third emission area EA3.

[0191] The first color filter 510 may be disposed in the first filter opening 540OP1 corresponding to the first emission layer 222r below the first color filter 510. The first emission layer 222r may selectively transmit light emitted from the first emission layer 222r. For example, the first color filter 510 may be a red color filter that transmits red light.

[0192] Similarly, the second color filter 520 may correspond to the second emission layer 222g and be in the second filter opening 540OP2. The second color filter 520 may selectively transmit the light emitted from the second emission layer 222g. The third color filter 530 may correspond to the third emission layer 222b and be in the third filter opening 540OP3. The third color filter 530 may selectively transmit the light emitted from the third emission layer 222b. For example, the second color filter 520 may be a green color filter that transmits green light, and the third color filter 530 may be a blue color filter that transmits blue light.

[0193] The overcoat layer 550 may be disposed on the first color filter 510, the second color filter 520, and the third color filter 530. The overcoat layer 550, which is a light-transmitting layer, may cover bumps caused by the first color filter 510, the second color filter 520, the third color filter 530, and the light-shielding layer 540 and provide a flat top surface. The overcoat layer 550 may include a colorless light-transmitting organic material such as an acrylic resin, etc.

[0194] Fig. 20 is a schematic cross-sectional view illustrating a mask assembly MA according to another embodiment.

[0195] exist Fig. 20 In, with Figure 2 The same reference numerals as in the accompanying drawings denote the same components, and some descriptions thereof will not be given repeatedly.

[0196] refer to Fig. 20 , the mask assembly MA may include a first mask layer 41 and a second mask layer 42 .

[0197] The first mask layer 41 may support the second mask layer 42. The first mask layer 41 may include a first mask opening OP41. The first mask opening OP41 may be arranged (or formed) in the first mask layer 41 to allow the deposition material (eg, see Figure 1 M) passes through.

[0198] The second mask layer 42 may be disposed on the first mask layer 41. The second mask layer 42 may include a second mask opening OP42. The second mask opening OP42 may be arranged (or formed) in the second mask layer 42 to allow the deposition material (eg, see Figure 1 The second mask opening OP42 may be provided in plural and may overlap with the first mask opening OP41 in a plan view.

[0199] The inorganic layer 422 may be disposed on the stop layer 421, and the stop layer 421 may be disposed on the first mask layer 41. The inorganic layer 422 may include a first inorganic layer 4221 and a second inorganic layer 4222. The first inorganic layer 4221 may be disposed on the stop layer 421, and the second inorganic layer 4222 may be disposed on the first inorganic layer 4221. The etching selectivity of the second inorganic layer 4222 may be greater than the etching selectivity of the first inorganic layer 4221. The etching selectivity of the first inorganic layer 4221 may be less than the etching selectivity of the second inorganic layer 4222.

[0200] The second mask opening OP42 may include a stop layer opening OP421 and an inorganic opening OP422. The stop layer opening OP421 may be arranged (or formed) in the stop layer 421, and the inorganic opening OP422 may be arranged (or formed) in the inorganic layer 422. The stop layer opening OP421 and the inorganic opening OP422 may overlap each other in a plan view.

[0201] The inorganic opening OP422 may include a first inorganic opening OP4221 and a second inorganic opening OP4222. The first inorganic opening OP4221 may be disposed in the first inorganic layer 4221, and the second inorganic opening OP4222 may be disposed in the second inorganic layer 4222. The first inorganic opening OP4221 and the second inorganic opening OP4222 may correspond to each other in a plan view, for example, overlap. The number of the first inorganic openings OP4221 may correspond to (for example, be equal to) the number of the second inorganic openings OP4222. For example, in a cross-sectional view, the widths of the first inorganic opening OP4221 and the second inorganic opening OP4222 may be substantially the same as each other. In a plan view, the shapes of the first inorganic opening OP4221 and the second inorganic opening OP4222 may be substantially the same as each other.

[0202] Figure 21 to Figure 29 is a schematic cross-sectional view of a mask assembly MA for illustrating a method of manufacturing a display device 2 according to another embodiment.

[0203] exist Figure 21 to Figure 29 In, with Fig. 20 The same reference numerals as in the accompanying drawings denote the same components, and some descriptions thereof will not be given repeatedly.

[0204] refer to Figure 21 to Figure 29 , the method of manufacturing the display device 2 may include arranging the mask assembly MA in a chamber (eg, see Figure 1 of CH).

[0205] The arrangement of the mask assembly MA may include disposing a stop layer 421 having a stop layer opening OP421 disposed therein on the first mask layer 41, disposing an inorganic layer 422 on the stop layer 421, forming a first mask opening OP41 in the first mask layer 41, and etching the inorganic layer 422 overlapping with the stop layer opening OP421 in a plan view.

[0206] Fig.21 The stop layer 421 in which the stop layer opening OP421 is arranged is provided on the first mask layer 41. Figures 4 to 7 This process is described and its description will not be repeated.

[0207] Fig. 22 The inorganic layer 422 is exemplified as being disposed on the stop layer 421. The disposition of the inorganic layer 422 may include disposing a first inorganic layer 4221 on the stop layer 421 and disposing a second inorganic layer 4222 on the first inorganic layer 4221. In this process, the stop layer 421 may be disposed on the first mask layer 41, the first inorganic layer 4221 may be disposed on the stop layer 421, and the second inorganic layer 4222 may be disposed on the first inorganic layer 4221. The etching selectivity of the second inorganic layer 4222 may be greater than the etching selectivity of the first inorganic layer 4221. The etching selectivity of the first inorganic layer 4221 may be less than the etching selectivity of the second inorganic layer 4222.

[0208] Figure 23 to Figure 26 It is illustrated that a first mask opening OP41 is formed in the first mask layer 41 .

[0209] refer to Figure 23 to Figure 25 , forming the first mask opening OP41 in the first mask layer 41 may include disposing a second photoresist layer PRL2 in which the second photo opening OPPRL2 is disposed (or formed) under the first mask layer 41. The second photoresist layer PRL2 may include the second photo opening OPPRL2.

[0210] refer to Fig.23 , the second photoresist material PRM2 may be disposed under the first mask layer 41 . The first mask layer 41 may be disposed on the second photoresist material PRM2 , the inorganic layer 422 may be disposed on the stop layer 421 , and the stop layer 421 may be disposed on the first mask layer 41 .

[0211] refer to Fig.24 , the patterned second photomask PMA2 may be disposed under the second photoresist material PRM2. The second photomask PMA2 may include a plurality of second photomask openings OPPMA2. Each second photomask opening OPPMA2 may be arranged (or formed) in the second photomask PMA2. The light LT may be irradiated from the bottom of the first mask layer 41 toward the second photoresist material PRM2.

[0212] A portion of the light LT may pass through (or penetrate) the second photomask opening OPPMA2 and reach the second photoresist material PRM2, and another portion of the light LT may be blocked by the second photomask PMA2 and cannot reach the second photoresist material PRM2. A portion of the second photoresist material PRM2 overlapping the second photomask opening OPPMA2 in a plan view may be cured.

[0213] refer to Fig.25 , which does not overlap with the second photomask opening in plan view (see, for example, Fig.24 OPPMA2) overlapped and uncured second photoresist material (e.g., see Fig.24 A portion of the PRM2) may be removed. In removing the second photoresist material (eg, see Fig.24 In the process of forming a portion of the PRM2 of the embodiment of the present invention, a second photoresist layer PRL2 in which a second optical opening OPPRL2 is arranged may be formed. The first mask layer 41 may be exposed from the second photoresist layer PRL2 through the second optical opening OPPRL2.

[0214] refer to Fig.26 , forming the first mask opening OP41 in the first mask layer 41 may include etching the first mask layer 41 overlapping the second photo opening OPPRL2 arranged in the second photoresist layer PRL2 in a plan view. A portion of the first mask layer 41 may be removed by an etching process. For example, the first mask layer 41 may be etched by a dry etching process.

[0215] As the first mask layer 41 is etched, the first mask opening OP41 may be disposed in the first mask layer 41. The stop layer 421 may be exposed from the first mask layer 41 through the first mask opening OP41. The inorganic layer 422 may be exposed from the first mask layer 41 and the stop layer 421 through the first mask opening OP41 and the stop layer opening OP421.

[0216] In the etching process of the first mask layer 41, the second inorganic layer 4222 may not be etched due to the first inorganic layer 4221. Since the etching selectivity of the first inorganic layer 4221 is relatively low, the first inorganic layer 4221 may be etched to a lower degree in the etching process of the first mask layer 41. Accordingly, in the etching process of the first mask layer 41, uneven etching of the second inorganic layer 4222 having a relatively high etching selectivity may be prevented. For example, the quality of the mask assembly MA may be improved.

[0217] Fig. 27 and Fig.28 The etching of the inorganic layer 422 is illustrated.

[0218] refer to Fig. 27, the etching of the inorganic layer 422 may include etching the first inorganic layer 4221 to form a first inorganic opening OP4221. A portion of the first inorganic layer 4221 may be removed by an etching process. As described above, for example, the first inorganic layer 4221 may be etched by a dry etching process. The etching of the first inorganic layer 4221 may be performed in a direction (e.g., +z-axis direction) in which the stop layer 421 faces the first inorganic layer 4221.

[0219] In the etching process of the first inorganic layer 4221, the stop layer 421 may not be etched. In the etching process of the first inorganic layer 4221, the stop layer 421 may be used as a mask. For example, an etching gas may pass through the stop layer opening OP421 and contact the first inorganic layer 4221. In the etching process of the first inorganic layer 4221, the first inorganic opening OP4221 may be arranged (or formed) in the first inorganic layer 4221.

[0220] refer to Fig.28 , the etching of the inorganic layer 422 may include etching the second inorganic layer 4222 to form a second inorganic opening OP4222. A portion of the second inorganic layer 4222 may be removed by an etching process. For example, the second inorganic layer 4222 may be etched by the above-mentioned dry etching process. The etching of the second inorganic layer 4222 may be performed in a direction (e.g., +z-axis direction) in which the stop layer 421 faces the second inorganic layer 4222.

[0221] In the etching process of the second inorganic layer 4222, the stop layer 421 may not be etched. In the etching process of the second inorganic layer 4222, the stop layer 421 may be used as a mask. For example, the etching gas may pass through the stop layer opening OP421 and the first inorganic opening OP4221 and contact the second inorganic layer 4222. In the etching process of the second inorganic layer 4222, the second inorganic opening OP4222 may be formed in the second inorganic layer 4222.

[0222] refer to Fig.29 , forming the first mask opening OP41 in the first mask layer 41 may include removing the second photoresist layer PRL2 (eg, see Fig.28 ). As the second photoresist layer PRL2 is removed, the mask assembly MA may be manufactured.

[0223] According to various embodiments, the quality of an apparatus for manufacturing a display device may be improved.

[0224] The above description is an example of the technical features of the present disclosure, and those skilled in the art will be able to make various modifications and changes. Therefore, the embodiments of the present disclosure as described above can be implemented separately or in combination with each other.

[0225] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the claims, and should be interpreted as all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. An apparatus for manufacturing a display device, characterized in that: The device comprises: a chamber, in which the display substrate is arranged; a mask assembly arranged in the chamber and facing the display substrate; and a deposition source, providing a deposition material to the mask assembly, The mask assembly comprises: a first mask layer including a first mask opening; a stop layer disposed on the first mask layer and comprising a stop layer opening overlapping the first mask opening; and The inorganic layer is disposed on the stop layer and includes an inorganic opening overlapping the stop layer opening.

2. The device according to claim 1, characterized in that In a plan view, a shape of the stop layer opening formed in the stop layer and a shape of the inorganic opening formed in the inorganic layer are the same.

3. The device according to claim 1, characterized in that The inorganic layer comprises: A first inorganic layer disposed on the stop layer; and The second inorganic layer is disposed on the first inorganic layer and has an etching selectivity higher than that of the first inorganic layer.

4. The device according to claim 3, characterized in that The number of first inorganic openings formed in the first inorganic layer is equal to the number of second inorganic openings formed in the second inorganic layer.

5. The device according to claim 3, characterized in that In a plan view, a shape of a first inorganic opening formed in the first inorganic layer and a shape of a second inorganic opening formed in the second inorganic layer are the same.

6. An apparatus for manufacturing a display device, characterized in that: The device comprises: Chamber; a mask assembly disposed in the chamber and facing the display substrate; and a deposition source arranged in the chamber, facing the mask assembly, and supplying a deposition material, the deposition material passing through the mask assembly and deposited on the display substrate, wherein The mask assembly comprises: a first mask layer including a first mask opening; a stop layer disposed on the first mask layer and comprising a plurality of stop layer openings corresponding to the first mask openings; and an inorganic layer disposed on the stop layer and comprising a plurality of inorganic openings corresponding to the plurality of stop layer openings, The inorganic layer comprises: a first inorganic layer; and a second inorganic layer disposed on the first inorganic layer and having an etching selectivity higher than that of the first inorganic layer, and The plurality of inorganic openings include: a plurality of first inorganic openings disposed in the first inorganic layer; and A plurality of second inorganic openings are arranged in the second inorganic layer and correspond to the plurality of first inorganic openings.

7. The device according to claim 6, characterized in that The number of the plurality of first inorganic openings is equal to the number of the plurality of second inorganic openings.

8. The device according to claim 6, characterized in that In a plan view, a shape of the plurality of stop layer openings and a shape of the plurality of inorganic openings are the same.

9. The device according to claim 6, characterized in that In a plan view, a shape of the plurality of first inorganic openings and a shape of the plurality of second inorganic openings are the same.

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