Decoder device and word line decoder circuit

Abstract

The present disclosure provides a decoder device and a word line decoder circuit. In one aspect, the decoder device includes a first logic gate and a second logic gate. The first logic gate is configured to receive a deactivation signal and a first input signal and generate a first decoder output signal at a first output node. The second logic gate is used for receiving a deactivation signal and a second input signal and generating a second decoder output signal at a second output node, and the first logic gate and the second logic gate share a transistor; the transistor has a first terminal coupled to a first output node, a second terminal coupled to a second output node, and a gate terminal receiving a deactivation signal.

Description

Technical Field

[0001] The present disclosure relates to a decoder device and a word line decoder circuit, and more particularly to a decoder device and a word line decoder circuit using a shared transistor. Background Art

[0002] The semiconductor industry has experienced rapid growth due to a series of improvements in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. The improvement in integration density comes primarily from the continuous reduction in the size of the smallest feature, which allows more components to be integrated into a given area. Utility Model Content

[0003] The present disclosure provides a decoder device, comprising a first logic gate and a second logic gate. The first logic gate is used to receive a disable signal and a first input signal, and generate a first decoder output signal at a first output node. The second logic gate is used to receive the disable signal and a second input signal, and generate a second decoder output signal at a second output node, wherein the first logic gate and the second logic gate share a transistor, the transistor having a first terminal coupled to the first output node, a second terminal coupled to the second output node, and a gate terminal receiving the disable signal.

[0004] The present disclosure document provides a word line decoder circuit, comprising a first P-channel metal oxide semiconductor (PMOS) transistor, a second PMOS transistor, a first N-channel metal oxide semiconductor (NMOS) transistor, a second NMOS transistor and a third PMOS transistor. The gate of the first PMOS transistor receives a first word line clock signal, the gate of the second PMOS transistor receives a second word line clock signal, and the source of the first PMOS transistor and the source of the second PMOS transistor receive a power supply voltage. The gate of the first NMOS transistor receives the first word line clock signal, and the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor at a first node. The gate of the second NMOS transistor receives the second word line clock signal, and the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor at a second node. The source of the third PMOS transistor is connected to the first node, the drain of the third PMOS transistor is connected to the second node, and the gate of the third PMOS transistor receives an enable signal.

[0005] The present disclosure further provides a word line decoder circuit, comprising a first P-channel metal oxide semiconductor (PMOS) transistor, a second PMOS transistor, a first N-channel metal oxide semiconductor (NMOS) transistor, a second NMOS transistor and a common transistor. The gate of the first PMOS transistor receives a first word line clock signal, the gate of the second PMOS transistor receives a second word line clock signal, and the source of the first PMOS transistor and the source of the second PMOS transistor receive a power supply voltage. The gate of the first NMOS transistor receives the first word line clock signal, and the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor at a first node. The gate of the second NMOS transistor receives the second word line clock signal, and the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor at a second node. The common transistor has a first terminal coupled to the first node, a second terminal coupled to the second node, and a gate for receiving a block selection signal. When the common transistor is turned off based on the block selection signal, the word line decoder circuit is used to generate a first word line selection signal and a second word line selection signal based on a first voltage at the first node and a second voltage at the second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the embodiments of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram of an example circuit with shared transistors for implementing a NAND-based decoder according to some embodiments;

[0008] Figure 2 is a schematic diagram of an example circuit with shared transistors for implementing a NOR-based decoder according to some embodiments;

[0009] Figure 3 is a schematic diagram of an example circuit with a shared transistor for implementing a word line decoder according to some embodiments;

[0010] Figure 4 is a schematic diagram of an example circuit with shared transistors for implementing a NAND-based three-input decoder according to some embodiments;

[0011] Figure 5 is a schematic diagram of an example circuit with shared transistors for implementing a NAND-based two-input four-output decoder according to some embodiments; and

[0012] Figure 6 FIG. 1 is a flow chart of an example method for operating a decoder circuit with shared transistors according to some embodiments of the present disclosure.

[0013]

Explanation of symbols

[0014] 100: Circuit

[0015] 102: First NAND gate

[0016] 104: Second NAND gate

[0017] 106: first output node

[0018] 108: Second output node

[0019] 200:Circuit

[0020] 206: first output node

[0021] 208: second output node

[0022] 300: Circuit

[0023] 302: word line clock signal

[0024] 304,306,308,310: Inverter

[0025] 312:NOR Gate

[0026] 314: Inverter

[0027] 316,318: Node

[0028] 320,322,324,326: output nodes

[0029] 400: Circuit

[0030] 402: First NAND gate

[0031] 404: Second NAND gate

[0032] 406: first output node

[0033] 408: Second output node

[0034] 500:Circuit

[0035] 502: First NAND gate

[0036] 504: Second NAND gate

[0037] 506: The third NAND gate

[0038] 508: Fourth NAND gate

[0039] 510: output node / first output node

[0040] 512: output node / second output node

[0041] 514: output node / third output node

[0042] 516: output node / fourth output node

[0043] 600: Method

[0044] 602,604,606: Operation

[0045] D1: first decoder output signal / output signal

[0046] D2: Second decoder output signal / output signal

[0047] D3: The third decoder output signal / output signal

[0048] D4: Fourth decoder output signal / output signal

[0049] M1~M4,M7~M11: transistor

[0050] M13~M20,M23~M26: Transistor

[0051] M29~M34,M36~M39: Transistor

[0052] M5, M12, M21, M22: shared transistor

[0053] M27,M28,M41,M42: shared transistor

[0054] M6,M35,M40: Tail transistor

[0055] VDD: power supply voltage

[0056] VSS: Second voltage

[0057] WL[0]~WL[3]: Word line selection output signal / output word line

[0058] X0[0]~X0[3]: Input clock signal

[0059] X1B: Input signal / block selection signal

[0060] X2B: Input signal / block selection signal

[0061] XB: logic input signal / inverting input signal

[0062] X: logic input signal

[0063] YB: Inverting input signal / inverting disable signal

[0064] Y: Logic input signal / logic disable signal

[0065] Z: Logic input signal / logic disable signal DETAILED DESCRIPTION

[0066] The following disclosure provides many different embodiments or examples to implement the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be directly contacted. In addition, the embodiments of the present disclosure may repeat element symbols and / or letters in each example. This repetition is for simplification and clarity purposes, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0067] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly accordingly.

[0068] A decoder circuit is an electronic circuit that receives logical binary inputs and produces outputs corresponding to specific combinations of the inputs. One function of a decoder circuit is to convert binary data from one format to another, typically from encrypted inputs to decoded outputs. Decoder circuits are used in a variety of applications, including computer memory systems, digital communication systems, and multimedia systems. In computer memory systems, decoder circuits may be used as wordline decoders that can be used to select specific columns of memory cells in a memory array for read or write operations.

[0069] Such decoders can use groups of transistors to form logic gates. The groups of these transistors are clearly defined in the circuit design using the decoder. In memory circuits and single-chip system (System-on-Chip, SoC) devices, decoders are frequently used and therefore occupy a considerable portion of the circuit area. Therefore, decoders with smaller areas are preferred. The systems and methods of the embodiments of the present disclosure provide decoder circuits that use shared transistors and therefore have low power consumption, high speed and smaller area. Various embodiments are described in the present disclosure, including decoder circuits implemented by using NAND logic configurations and NOR logic configurations. An example word line decoder for a memory circuit is also described in the present disclosure.

[0070] It should be understood that the various decoder circuits described in this disclosure may be used as components of an encoder having any number of inputs and corresponding outputs by adding appropriate logic circuits or transistors. Figures 1 to 5 Various encoders with one or two inputs are described, but applying the transistor sharing techniques described in this disclosure can produce encoders with two inputs, three inputs, four inputs, eight inputs, or any suitable number of inputs and corresponding outputs. The encoders described in this disclosure can be used in conjunction with any type of circuit that can utilize an encoder, including memory circuits, clock control circuits, or other types of circuits.

[0071] Figure 1 FIG. 1 is a schematic diagram of an example circuit 100 with shared transistors for implementing a NAND-based decoder according to some embodiments. Figure 1 As shown, the NAND-based decoder is defined by a first NAND gate 102 and a second NAND gate 104. The inputs transmitted to the circuit include a logic input signal X and a logic input signal XB. In this example, the logic input signal XB is a logic inversion signal of the logic input signal X (hereinafter also referred to as "inversion input signal XB"). The logic input signal Y is used as a logic disable signal.

[0072] like Figure 1As shown, the first NAND gate 102 receives a logic input signal X and a logic disable signal Y. The second NAND gate 104 receives an inverted input signal XB and a logic disable signal Y. The first NAND gate 102 generates a first decoder output signal D1, and the second NAND gate 104 generates a second decoder output signal D2. When the logic disable signal Y is logic low (e.g., has a voltage equal to "logic 0"), the output signals D1 and D2 of the first NAND gate 102 and the second NAND gate 104 will be set to a disable value (e.g., logic 1). Conversely, if the logic disable signal Y is set to logic high (e.g., has a voltage equal to logic "1"), the output signals D1 and D2 of the first NAND gate 102 and the second NAND gate 104 will be logic inverted signals of the logic input signal X and the logic input signal XB, respectively.

[0073] The circuit 100 uses a common transistor M5 to implement a logic decoder. The circuit 100 generates the same output signals D1 and D2 based on the same logic input signals X and XB and the logic disable signal Y. Figure 1 As shown, the circuit 100 is powered by a power supply voltage VDD, which may be a "logic high" or "logic 1" voltage of the circuit relative to a second voltage VSS, and the second voltage VSS may be a "logic low" or "logic 0" voltage of the circuit (e.g., a ground voltage). Figure 1 As shown, the circuit 100 includes transistors M1, M2, M3, M4, M5, and M6. In some implementations, the inverted input signal XB can be generated as an output of an inverter circuit that receives the logic input signal X and generates the inverted input signal XB.

[0074] The various circuits described in this disclosure (including circuit 100) include various transistors. The transistors described in this disclosure are illustrated as being of a particular type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a Complementary Metal Oxide Semiconductor (CMOS) transistor, a P-channel Metal-Oxide Semiconductor (PMOS), an N-channel Metal-Oxide Semiconductor (NMOS), a Bipolar Junction Transistor (BJT), a high voltage transistor, a high frequency transistor, a P-channel and / or N-channel Field Effect Transistor (PFET / NFET), a Fin Field Effect Transistor (FinFET), a planar MOS transistor with a raised source / drain, a nanosheet FET, a nanowire FET, or the like. In addition, although Figure 1 Transistors M1 to M6, Figure 2 M7 to M12, Figure 3 M8 to M22, Figure 4 M23 to M30 and Figure 5 M31 to M42 of the present disclosure are illustrated as transistors, but the embodiments are not limited thereto. For example, each of these transistors may include multiple transistors ("sub-transistors") connected in parallel to each other. For example, in one embodiment, the sub-transistors of any transistor described in the present disclosure may each include separate gate, drain, and source terminals.

[0075] Circuit 100 includes transistors M1, M2, M3, M4, M5, and M6. In some implementations, transistors M1, M3, and M5 each include a pMOSFET, and transistors M2, M4, and M6 each include an nMOSFET. It should be understood that transistors M1 to M6 may each include any other type of transistor (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while remaining within the scope of the embodiments of the present disclosure. Sources of transistors M1 and M3 are electrically coupled to a power supply voltage VDD. Drains of transistors M1 and M3 are electrically coupled to drains of transistors M2 and M4, respectively.

[0076] like Figure 1 As shown, the source of each of transistors M2 and M4 is electrically coupled to the drain of transistor M6. Transistor M6 may be an NMOS footer transistor. The source of transistor M6 is electrically coupled to a second voltage VSS, which may be a ground voltage. The gates of transistors M1 and M2 are electrically coupled to each other and connected to a logic input signal X. The gates of transistors M3 and M4 are electrically coupled to each other and connected to a logic inversion signal of the logic input signal X, i.e., an inversion input signal XB as described in the present disclosure.

[0077] The drains of transistors M1 and M2 are electrically coupled to a first output node 106, which is a node through which the output signal D1 is generated. The drains of transistors M3 and M4 are electrically coupled to a second output node 108, which is a node through which the output signal D2 is generated. Figure 1 As shown, the common transistor M5 has a source connected to the first output node 106 and a drain connected to the second output node 108. The gates of the tail transistor M6 and the common transistor M5 are connected to the logic disable signal Y.

[0078] When the logic disable signal Y is set to a logic high (e.g., logic 1, thereby enabling the decoder), the tail transistor M6 is enabled and turned on, while the common transistor M5 is turned off and does not conduct. When the logic disable signal Y is a logic high (e.g., enabling the decoder) and the logic input signal X is a logic low (e.g., "logic 0"), the transistor M1 is enabled and turned on, while the transistor M2 is turned off and does not conduct. The voltage at the first output node 106 is thus set to be approximately equal to the power supply voltage VDD (e.g., logic high state, logic 1).

[0079] When the logic input signal X is logic low, the inverting input signal XB is logic high. When the logic disable signal Y is logic high (e.g., enabling the decoder), and the inverting input signal XB is logic high (e.g., "logic 1"), the transistor M3 is turned off and does not conduct, and the transistor M4 is enabled and turned on. Because the transistor M6 is also enabled and turned on, the voltage at the second output node 108 is set to the second voltage VSS (e.g., logic low state, logic 0, ground voltage, etc.). Current does not flow between the first output node 106 and the second output node 108 because the common transistor M5 is turned off and does not conduct when the disable signal Y is in a logic high state.

[0080] When the logic disable signal Y is logic high (e.g., enabling the decoder), and the logic input signal X is logic high (e.g., "logic 1"), transistor M1 is turned off and does not conduct, while transistor M2 is turned on and conducts. Because the tail transistor M6 is turned on and conducts, the voltage at the first output node 106 is set to be approximately equal to the second voltage VSS (e.g., logic low state, logic 0). When the logic input signal X is logic high, the inverting input signal XB is logic low. When the logic disable signal Y is logic high (e.g., enabling the decoder), and the inverting input signal XB is logic low (e.g., "logic 0"), transistor M3 is turned on and conducts, while transistor M4 is turned off and does not conduct. The voltage at the second output node 108 is set to the power supply voltage VDD (e.g., logic high state, logic 1). Current does not flow between the first output node 106 and the second output node 108 because when the disable signal Y is in a logic high state, the common transistor M5 is turned off and does not conduct.

[0081] When the logic disable signal Y is set to a logic low (e.g., logic 0, thereby disabling the decoder), the tail transistor M6 is turned off and does not conduct, while the common transistor M5 is enabled and conducts. When the logic disable signal Y is a logic low (e.g., disabling the decoder), and the logic input signal X is a logic low (e.g., "logic 0"), the transistor M1 is enabled and conducts, while the transistor M2 is turned off and does not conduct. The voltage at the first output node 106 is therefore set to be approximately equal to the power supply voltage VDD (e.g., logic high state, logic 1).

[0082] When the logic input signal X is logic low, the inverting input signal XB is logic high. When the logic disable signal Y is logic low (e.g., disabling the decoder) and the inverting input signal XB is logic high (e.g., "logic 1"), transistor M3 is off and non-conducting, while transistor M4 is enabled and conducting. However, transistor M6 is also off because the disable signal Y is logic low. Current flows between the first output node 106 and the second output node 108 because the common transistor M5 is enabled and conducting, so the voltage at the second output node 108 is set to logic high (e.g., power supply voltage VDD).

[0083] When the logic disable signal Y is logic low (e.g., disable the decoder), and the logic input signal X is logic high (e.g., "logic 1"), transistor M1 is turned off and non-conducting, while transistor M2 is turned on and turned on. However, the tail transistor M6 is turned off and non-conducting, so the current does not flow through transistor M2. When the logic input signal X is logic high, the inverting input signal XB is logic low. When the logic disable signal Y is logic low (e.g., disable the decoder), and the inverting input signal XB is logic low (e.g., "logic 0"), transistor M3 is turned on and turned on, while transistor M4 is turned off and non-conducting. The voltage at the second output node 108 is set to the power supply voltage VDD (e.g., logic high state, logic 1). Current flows between the first output node 106 and the second output node 108 because when the disable signal Y is in a logic low state, the common transistor M5 is turned on and turned on. When the disable signal Y is set to logic low (eg, disabling the decoder), the voltages at the first and second output nodes 106 and 108 (output signals D1 and D2 ) are therefore set to logic high regardless of the logic state of the input signal X.

[0084] Figure 2 FIG. 2 is a schematic diagram of an example circuit 200 with a shared transistor M12 for implementing a NOR-based decoder according to some embodiments. The decoder shown in the circuit 200 may be similar to the one shown in FIG. Figure 1 Circuit 100 in FIG. 1 is implemented using NOR gates. Figure 2 As shown, circuit 200 includes transistors M7, M8, M9, M10, M11, and M12. In some implementations, transistors M7, M8, and M10 each include a pMOSFET, and transistors M9, M11, and M12 each include an nMOSFET. It should be understood that transistors M7-M12 may each include any other type of transistor (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while remaining within the scope of the embodiments of the present disclosure.

[0085] The sources of transistors M9 and M11 are electrically coupled to a second voltage VSS (eg, a logic low voltage, a ground voltage, etc.). The drains of transistors M8 and M10 are electrically coupled to the drains of transistors M9 and M11, respectively. Figure 2 As shown, the sources of transistors M8 and M19 are each electrically coupled to the drain of transistor M7. The source of transistor M7 is electrically coupled to a power supply voltage VDD (e.g., a logic high voltage). The gates of transistors M8 and M9 are electrically coupled to each other and to a logic input signal X. The gates of transistors M10 and M11 are electrically coupled to each other and to a logic inversion signal of input signal X, i.e., an inversion input signal XB as described in the present disclosure.

[0086] The drains of transistors M8 and M9 are electrically coupled to a first output node 206, where the output signal D1 is generated. The drains of transistors M10 and M11 are electrically coupled to a second output node 208, where the output signal D2 is generated. Figure 2 As shown, the common transistor M12 has a source connected to the second output node 208 and a drain connected to the first output node 206. The gates of the transistor M7 and the common transistor M12 are connected to the inverted signal of the logic disable signal Y, i.e. Figure 2 The inverted disable signal YB is shown in FIG.

[0087] When the inverted disable signal YB is set to a logic low (e.g., logic 0, thereby enabling the decoder), transistor M7 is enabled and turned on, while the shared transistor M12 is turned off and does not conduct. When the inverted disable signal YB is a logic low (e.g., enabling the decoder), and the logic input signal X is a logic low (e.g., "logic 0"), transistor M8 is enabled and turned on, while transistor M9 is turned off and does not conduct. The voltage at the first output node 206 is thus set to be approximately equal to the power supply voltage VDD (e.g., logic high state, logic 1), thereby preventing current from flowing through transistors M7 and M8.

[0088] When the logic input signal X is logic low, the inverting input signal XB is logic high. When the inverting disable signal YB is logic low (e.g., enabling the decoder), and the inverting input signal XB is logic high (e.g., "logic 1"), the transistor M10 is turned off and does not conduct, and the transistor M11 is turned on and conducts. The voltage at the second output node 108 is therefore set to the second voltage VSS (e.g., logic low state, logic 0, ground voltage, etc.). Current does not flow between the first output node 206 and the second output node 208 because the common transistor M12 is turned off and does not conduct when the inverting disable signal YB is in a logic low state.

[0089] When the inverted disable signal YB is logic low (e.g., enabling the decoder) and the logic input signal X is logic high (e.g., "logic 1"), transistor M8 is turned off and does not conduct, while transistor M9 is turned on and conducts. The voltage at the first output node 206 is therefore set to be approximately equal to the second voltage VSS (e.g., logic low state, logic 0). When the logic input signal X is logic high, the inverted input signal XB is logic low. When the inverted disable signal YB is logic low (e.g., enabling the decoder) and the inverted input signal XB is logic low (e.g., "logic 0"), transistor M10 is turned on and conducts, while transistor M11 is turned off and does not conduct. Because transistor M7 is turned on and conducts, the voltage at the second output node 208 is set to the power supply voltage VDD (e.g., logic high state, logic 1). Current does not flow between the first output node 206 and the second output node 208 because the common transistor M12 is turned off and does not conduct when the inverted disable signal YB is in a logic low state.

[0090] When the inverted disable signal YB is set to a logic high (e.g., logic 1, thereby disabling the decoder), transistor M7 is turned off and does not conduct, while the shared transistor M12 is enabled and conducts. When the inverted disable signal YB is a logic high (e.g., disabling the decoder), and the logic input signal X is a logic low (e.g., "logic 0"), transistor M8 is enabled and conducts, while transistor M9 is turned off and does not conduct. However, transistor M6 is also turned off because the inverted disable signal YB is a logic high.

[0091] When the logic input signal X is logic low, the inverting input signal XB is logic high. When the inverting disable signal YB is logic high (e.g., the decoder is disabled) and the inverting input signal XB is logic high (e.g., "logic 1"), the transistor M10 is turned off and does not conduct, while the transistor M11 is enabled and turned on. In this case, the voltage at the second output node 208 is set to the second voltage VSS (e.g., logic low state, logic 0). Current flows between the first output node 206 and the second output node 208 because the common transistor M12 is enabled and turned on, so the voltage at the first output node 606 is set to logic low (e.g., the second voltage VSS).

[0092] When the inverted disable signal YB is logic high (e.g., disables the decoder) and the logic input signal X is logic high (e.g., "logic 1"), transistor M8 is turned off and does not conduct, while transistor M9 is turned on and conducts. In this case, the voltage at the first output node 206 is set to be approximately equal to the second voltage VSS (e.g., logic low state, logic 0). When the logic input signal X is logic high, the inverted input signal XB is logic low. When the inverted disable signal YB is logic high (e.g., disables the decoder) and the inverted input signal XB is logic low (e.g., "logic 0"), transistor M10 is turned on and conducts, while transistor M11 is turned off and does not conduct. However, since transistor M7 is turned off and does not conduct, current does not flow through transistor M7 or transistor M10. Current flows between the first output node 206 and the second output node 208 because the common transistor M12 is turned on and conducts when the inverted disable signal YB is in a logic high state. The voltage at the second output node 208 is thus set to the second voltage VSS (e.g., logic low state, logic 0). When the inverted disable signal YB is set to logic high (e.g., disables the decoder), the voltages at the first output node 206 and the second output node 208 (output signals D1 and D2) are thus set to logic low, regardless of the logic state of the input signal X.

[0093] Figure 3 FIG. 3 is a schematic diagram of an example circuit 300 with shared transistors for implementing a word line decoder according to some embodiments. Figure 3 As shown, the circuit 300 includes a NOR gate 312 that receives input signals X1B and X2B. The input signals X1B and X2B may be block selection signals of a word line decoder. When the input signal X1B is logic low (e.g., the second voltage VSS, the ground voltage, logic 0, etc.), and the input signal X2B is logic low, the NOR gate 312 generates a logic high (e.g., approximately equal to the power supply voltage VDD, logic 1, etc.) signal at a node 316. When the input signal X1B is logic high, and the input signal X2B is logic low, the NOR gate 312 generates a logic low signal at the node 316.

[0094] When the input signal X1B is a logic low and the input signal X2B is a logic high, the NOR gate 312 generates a logic low signal at the node 316. When the input signal X1B is a logic high and the input signal X2B is a logic high, the NOR gate 312 generates a logic low signal at the node 316. The circuit 300 includes an inverter 314, which receives the output of the NOR gate 312 at the node 316. When the node 316 is a logic low, the inverter 314 generates a logic high signal at the node 318. When the node 316 is a logic high, the inverter 314 generates a logic low signal at the node 318.

[0095] Circuit 300 uses shared transistors M21 and M22 to implement a word line decoder. Figure 3 As shown, the circuit 300 is powered by a power supply voltage VDD, which may be a "logic high" or "logic 1" voltage of the circuit. The logic high voltage may be relative to a second logic low voltage (e.g., a ground voltage, such as the second voltage VSS described in this disclosure, etc.). Figure 3 As shown, circuit 300 includes transistors M13, M14, M15, M16, M17, M18, M19, M20, M21, and M22. The word line decoder receives a word line clock signal 302. The word line clock signal 302 may be a one-hot clock signal having input clock signals X0[0], X0[1], X0[2], and X0[3], which correspond to word line select output signals WL[0], WL[1], WL[2], and WL[3], respectively. In this example, when block select signal X1B is logic low and block select signal X2B is logic low (e.g., block select signal "00"), output word lines WL[0], WL[1], WL[2], and WL[3] are selected.

[0096] Circuit 300 includes inverters 304, 306, 308, and 310. Inverters 304, 306, 308, and 310 receive voltages generated at output nodes 320, 322, 324, and 326, respectively, and generate corresponding word line select output signals WL[0], WL[1], WL[2], and WL[3] as outputs of circuit 300. Figure 3 As shown, circuit 300 includes transistors M13, M14, M15, M16, M17, M18, M19, M20, M21, and M22. In some implementations, transistors M13, M15, M17, M19, M21, and M22 each include a pMOSFET, and transistors M14, M16, M18, and M20 each include an nMOSFET. It should be understood that transistors M13-M22 may each include any other type of transistor (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while remaining within the scope of the embodiments of the present disclosure.

[0097] The sources of transistors M13, M15, M17, and M19 are electrically coupled to a supply voltage VDD. The sources of transistors M14, M16, M18, and M20 are electrically coupled to the output of inverter 314 at node 318. When either or both of input signals X1B and X2B are logic high, NOR gate 312 generates a logic low signal at node 316, and inverter 314 generates a logic high signal at node 318 (deselecting output word lines WL[0], WL[1], WL[2], and WL[3], and effectively disabling this portion of the word line decoder). In addition, setting node 316 to a logic low signal activates both common transistors M21 and M22, causing current to flow between output nodes 320 and 322 and between output nodes 324 and 326, respectively. When both input signals X1B and X2B are logic low, the voltage at node 318 is logic low, which enables the outputs of output word lines WL[0], WL[1], WL[2], and WL[3], effectively enabling the decoder. This causes the voltage at node 316 to be logic high, turning off both common transistors M21 and M22 and preventing current from flowing between output nodes 320 and 322 and between output nodes 324 and 326.

[0098] like Figure 3 As shown, the drains of transistors M13, M15, M17, and M19 are electrically coupled to the drains of transistors M14, M16, M18, and M20, respectively. When node 318 is in a logic high state (decoder disabled), current does not flow through transistors M14, M16, M18, and M20, regardless of the logic state of input clock signals X0[0], X0[1], X0[2], and X0[3]. Because the input clock signals are one-hot clock signals, at most one of the input clock signals X0[0], X0[1], X0[2], and X0[3] can be in a logic high state while the other three are in a logic low state. In some implementations, the input clock signals X0[0], X0[1], X0[2], and X0[3] can all be in a logic low state.

[0099] In the disabled state (e.g., either or both of the block select signals X1B or X2B are in a logic high state, so that the node 316 is in a logic low state and the node 318 is in a logic high state), if any of the transistors M13, M15, M17 or M19 is activated by any of the clock input signals X0[0], X0[1], X0[2] and X0[3] in a logic low state, respectively, then the voltage at the output node 320, 322, 324 or 326 will be in a logic high state.

[0100] Because the shared transistors M21 and M22 are both enabled, and because the transistors M14, M16, M18, and M20 are not turned on, the voltage at the output node 322 is set to be approximately equal to the voltage at the output node 320, and the voltage at the output node 324 is set to be approximately equal to the voltage at the output node 326. Since the input clock signals X0[0], X0[1], X0[2], and X0[3] are one-hot signals, at least one of the output nodes 320 and 322 and at least one of the output nodes 324 and 326 are set to a logic high state. The shared transistors M21 and M22 are enabled and turned on, so that the other of the output nodes 320 and 322 and the other of the output nodes 324 and 326 are set to a logic high state. Therefore, in the disabled state (e.g., either or both of the block select signals X1B or X2B are in a logic high state, such that node 316 is in a logic low state and node 318 is in a logic high state), all output nodes 320, 322, 324, and 326 will be set to a logic high state. This causes the inverters to generate a logic low signal for each of the output word lines WL[0], WL[1], WL[2], and WL[3].

[0101] In an enabled state (e.g., either or both of the block select signals X1B or X2B are in a logic high state, such that node 316 is in a logic high state and node 318 is in a logic low state), input clock signals X0[0], X0[1], X0[2], and X0[3] may be used to generate corresponding word line select output signals for output word lines WL[0], WL[1], WL[2], and WL[3]. In the enabled state, if input clock signal X0[0] is logic high and input clock signals X0[1], X0[2], and X0[3] are logic low, transistor M19 is turned off and non-conducting, while transistor M20 is turned on and conducting, thereby generating a logic low voltage at output node 326 and causing inverter 310 to generate a logic high output voltage for output word line WL[0]. Furthermore, transistors M13, M15, and M17 are enabled and conducting, while transistors M14, M16, and M18 are turned off and non-conducting, thereby generating logic high voltages at output nodes 320, 322, and 324, respectively. This causes inverters 304, 306, and 308 to generate outputs of logic low signals for each of output word lines WL[3], WL[2], and WL[1], respectively.

[0102] In the enabled state, if the input clock signal X0[1] is logic high and the input clock signals X0[0], X0[2] and X0[3] are logic low, transistor M17 is turned off and does not conduct, while transistor M18 is turned on and conducts, thereby generating a logic low voltage at the output node 324 and causing the inverter 308 to generate a logic high output voltage to the output word line WL[1]. In addition, transistors M13, M15 and M19 are turned on and conduct, while transistors M14, M16 and M20 are turned off and do not conduct, thereby generating a logic high voltage at the output nodes 320, 322 and 326, respectively. This situation causes the inverters 304, 306 and 310 to generate an output of a logic low signal for each of the output word lines WL[3], WL[2] and WL[0], respectively.

[0103] In the enabled state, if the input clock signal X0[2] is logic high and the input clock signals X0[0], X0[1] and X0[3] are logic low, transistor M15 is turned off and does not conduct, while transistor M16 is turned on and conducts, thereby generating a logic low voltage at output node 322 and causing inverter 306 to generate a logic high output voltage to output word line WL[2]. In addition, transistors M13, M17 and M19 are turned on and conduct, while transistors M14, M18 and M20 are turned off and do not conduct, thereby generating a logic high voltage at output nodes 320, 324 and 326, respectively. This situation causes inverters 304, 308 and 310 to generate an output of a logic low signal for each of the output word lines WL[3], WL[1] and WL[0], respectively.

[0104] In the enabled state, if the input clock signal X0[3] is logic high and the input clock signals X0[0], X0[1] and X0[2] are logic low, transistor M13 is turned off and non-conducting, and transistor M14 is turned on and conducting, thereby generating a logic low voltage at the output node 320 and causing the inverter 304 to generate a logic high output voltage to the output word line WL[3]. In addition, transistors M15, M17 and M19 are turned on and conducting, while transistors M16, M18 and M20 are turned off and non-conducting, thereby generating a logic high voltage at the output nodes 322, 324 and 326, respectively. This situation causes the inverters 306, 308 and 310 to generate an output of a logic low signal for each of the output word lines WL[2], WL[1] and WL[0], respectively.

[0105] In the enabled state, if the input clock signals X0[0], X0[1], X0[2] and X0[3] are all logic low, transistors M13, M15, M17 and M19 are enabled and turned on, and M14, M16, M18 and 20 are turned off and non-conductive, so that a logic high voltage is generated at each of the output nodes 320, 322, 324 and 326. This causes inverters 304, 306, 308 and 310 to generate an output of a logic low signal for each of the output word lines WL[3], WL[2], WL[1] and WL[0], respectively.

[0106] Figure 4 FIG. 4 is a schematic diagram of an example circuit 400 with shared transistors M27 and M28 for implementing a NAND-based three-input decoder according to some embodiments. The circuit 400 can be implemented such that the decoder operates when the logic input signal Y and the logic input signal Z are logic high. Figure 4 As shown, a NAND-based three-input decoder is defined by a first NAND gate 402 and a second NAND gate 404. Inputs transmitted to the circuit include a logic input signal X, a logic input signal XB, and logic input signals Y and Z. In this example, the logic input signal XB is a logic inversion signal of the logic input signal X. The logic input signals Y and Z are used in combination as a logic disable signal (hereinafter also referred to as "logic disable signals Y, Z").

[0107] like Figure 4 As shown, the first NAND gate 402 receives a logic input signal X and logic disable signals Y and Z. The second NAND gate 404 receives an inverted input signal XB and logic disable signals Y and Z. The first NAND gate 402 generates a first decoder output signal D1, and the second NAND gate 404 generates a second decoder output signal D2. When either or both of the logic disable signals Y and Z are logic low (e.g., have a voltage equal to "logic 0"), the output signals D1 and D2 of the first NAND gate 402 and the second NAND gate 404 will be set to a disable value (e.g., logic 1). Conversely, if both of the logic disable signals Y and Z are set to logic high (e.g., have a voltage equal to logic "0"), the output signals D1 and D2 of the logic NAND gates 402 and 404 will be the logic inversion signals of the logic input signal X and the logic input signal XB, respectively.

[0108] Circuit 400 uses shared transistors M27 and M28 to implement a logic decoder. Circuit 400 generates the same output signals D1 and D2 based on the same logic input signals X and XB and logic disable signals Y and Z. Figure 4As shown, the circuit 400 is powered by a power supply voltage VDD, which may be a "logic high" or "logic 1" voltage of the circuit relative to a second voltage VSS, which may be a "logic low" or "logic 0" voltage (e.g., a ground voltage) of the circuit. Figure 4 As shown, circuit 400 includes transistors M23, M24, M25, M26, M27, M28, M29, and M30. In some implementations, the inverted output signal XB can be generated as an output of an inverter circuit that can receive a logic input signal X and generate an inverted output signal XB.

[0109] Circuit 400 includes transistors M23, M24, M25, M26, M27, M28, M29, and M30. In some implementations, transistors M23, M25, M27, and M28 each include a pMOSFET, and transistors M24, M26, M29, and M30 each include an nMOSFET. It should be understood that transistors M23 to M30 may each include any other type of transistor (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while remaining within the scope of the embodiments of the present disclosure. The sources of transistors M23 and M25 are electrically coupled to a power supply voltage VDD. The drains of transistors M23 and M25 are electrically coupled to the drains of transistors M24 and M26, respectively.

[0110] like Figure 4 As shown, the sources of transistors M24 and M26 are each electrically coupled to the drain of transistor M29. Transistor M29 is connected in series with transistor M30. The source of transistor M30 is electrically coupled to a second voltage VSS, which may be a ground voltage. The gates of transistors M23 and M24 are electrically coupled to each other and to a logic input signal X. The gates of transistors M25 and M26 are electrically coupled to each other and to a logic inversion signal of the logic input signal X, i.e., an inversion input signal XB as described in the present disclosure.

[0111] The drains of transistors M23 and M24 are electrically coupled to a first output node 406, which is a node through which the output signal D1 is generated. The drains of transistors M25 and M26 are electrically coupled to a second output node 408, which is a node through which the output signal D2 is generated. Figure 4 As shown, common transistors M27 and M28 are connected in parallel and each have a source connected to the first output node 406 and a drain connected to the second output node 408. The gates of transistors M27 and M29 are connected to a logic disable signal Y, and the gates of transistors M28 and M30 are connected to a logic disable signal Z.

[0112] When both logic disable signals Y and Z are set to logic high (e.g., logic 1, thereby enabling the decoder), transistors M29 and M30 are enabled and turned on, while shared transistors M27 and M28 are turned off and do not conduct. When both logic disable signals Y and Z are logic high (e.g., enabling the decoder), and logic input signal X is logic low (e.g., "logic 0"), transistor M23 is enabled and turned on, while transistor M24 is turned off and does not conduct. The voltage at the first output node 406 is therefore set to be approximately equal to the power supply voltage VDD (e.g., logic high state, logic 1).

[0113] When the logic input signal X is logic low, the inverting input signal XB is logic high. When the logic disable signals Y and Z are logic high (e.g., enabling the decoder), and the inverting input signal XB is logic high (e.g., "logic 1"), the transistor M25 is turned off and does not conduct, and the transistor M26 is started and turned on. Because the transistors M29 and M30 are started and turned on based on the logic disable signals Y and Z being logic high, the voltage at the second output node 408 is set to the second voltage VSS (e.g., logic low state, logic 0, ground voltage, etc.). Current does not flow between the first output node 406 and the second output node 408 because when the disable signals Y and Z are in a logic high state, the shared transistors M27 and M28 are turned off and do not conduct.

[0114] When the logic disable signals Y and Z are logic high (e.g., enabling the decoder), and the logic input signal X is logic high (e.g., "logic 1"), transistor M23 is turned off and does not conduct, while transistor M24 is turned on and conducts. Because transistors M29 and M30 are turned on and conduct, the voltage at the first output node 406 is set to be approximately equal to the second voltage VSS (e.g., logic low state, logic 0). When the logic input signal X is logic high, the inverting input signal XB is logic low. When the logic disable signals Y and Z are both logic high (e.g., enabling the decoder), and the inverting input signal XB is logic low (e.g., "logic 0"), transistor M25 is turned on and conducts, and transistor M26 is turned off and does not conduct. The voltage at the second output node 408 is set to the power supply voltage VDD (e.g., logic high state, logic 1). Current does not flow between the first output node 406 and the second output node 408 because the common transistors M27 and M28 are turned off and do not conduct when the disable signals Y and Z are in logic high states, respectively.

[0115] When either or both of the logic disable signals Y or Z are set to a logic low (e.g., a logic 0, thereby disabling the decoder), either or both of the transistors M29 (if Y is a logic low) or M30 (if Z is a logic low) are turned off and do not conduct. In addition, either or both of the common transistors M27 (if Y is a logic low) or M28 (if Z is a logic low) are enabled and turned on. When either or both of the logic disable signals Y or Z are set to a logic low (e.g., disabling the decoder), and the logic input signal X is a logic low (e.g., a “logic 0”), transistor M23 is enabled and turned on, while transistor M24 is turned off and does not conduct. The voltage at the first output node 406 is thus set to be approximately equal to the power supply voltage VDD (e.g., a logic high state, a logic 1).

[0116] When the logic input signal X is logic low, the inverting input signal XB is logic high. When one or both of the logic disable signals Y or Z are set to logic low (e.g., to disable the decoder), and the inverting input signal XB is logic high (e.g., "logic 1"), transistor M25 is turned off and does not conduct, while transistor M26 is enabled and conducts. However, either or both of transistors M29 or M30 are also turned off because either or both of the disable signals Y or Z are logic low, respectively. Current flows between the first output node 406 and the second output node 408 because either or both of the shared transistors M27 or M28 are enabled and conduct, so the voltage at the second output node 408 is set to logic high (e.g., power supply voltage VDD).

[0117] When either or both of the logic disable signals Y or Z are set to logic low (e.g., to disable the decoder), and the logic input signal X is logic high (e.g., "logic 1"), transistor M23 is turned off and does not conduct, while transistor M24 is turned on and conducts. However, either or both of transistors M29 (if the logic disable signal Y is logic low) or M30 (if the logic disable signal Z is logic low) are turned off and do not conduct, so current does not flow through transistor M24. When the logic input signal X is logic high, the inverting input signal XB is logic low. When either or both of the logic disable signals Y or Z are set to logic low (e.g., to disable the decoder), and the inverting input signal XB is logic low (e.g., "logic 0"), transistor M25 is turned on and conducts, while transistor M26 is turned off and does not conduct. The voltage at the second output node 408 is set to the power supply voltage VDD (e.g., logic high state, logic 1). Current flows between the first output node 406 and the second output node 408 because either or both of the common transistors M27 (if the logic disable signal Y is logic low) or M28 (if the logic disable signal Z is logic low) are enabled and turned on. When either or both of the disable signals Y or Z are set to logic low (e.g., disabling the decoder), the voltages at the first output node 406 and the second output node 408 (output signals D1 and D2) are thus set to logic high, regardless of the logic state of the logic input signal X.

[0118] Figure 5 FIG. 5 is a schematic diagram of an example circuit 500 with shared transistors M41 and M42 for implementing a NAND-based two-input four-output decoder according to some embodiments. Figure 5 As shown, the NAND-based two-input decoder is defined by a first NAND gate 502, a second NAND gate 504, a third NAND gate 506, and a fourth NAND gate 508. The inputs transmitted to the circuit include a logic input signal X, an inverted input signal XB, a logic input signal Y, and an inverted input signal YB. In the two-input decoder of this example, the inputs may be a logic input signal X and a logic input signal Y, the inverted input signal XB is a logic inverted signal of the logic input signal X, and the inverted input signal YB is a logic inverted signal of the logic input signal Y.

[0119] like Figure 5As shown, the first NAND gate 502 receives a logic input signal X and a logic input signal Y. The second NAND gate 504 receives an inverted input signal XB and a logic input signal Y. The third NAND gate 506 receives a logic input signal X and an inverted input signal YB. The fourth NAND gate 508 receives an inverted input signal XB and an inverted input signal YB. The first NAND gate 502 generates a first decoder output signal D1, the second NAND gate 504 generates a second decoder output signal D2, the third NAND gate 506 generates a third decoder output signal D3, and the fourth NAND gate 508 generates a fourth decoder output signal D4.

[0120] When the logic input signal Y is logic low (e.g., having a voltage equal to "logic 0"), and the logic input signal X is logic low, the output signal D1 is logic high, the output signal D2 is logic high, the output signal D3 is logic high, and the output signal D4 is logic low. When the logic input signal Y is logic low (e.g., having a voltage equal to "logic 0"), and the logic input signal X is logic high, the output signal D1 is logic high, the output signal D2 is logic high, the output signal D3 is logic low, and the output signal D4 is logic high. When the logic input signal Y is logic high (e.g., having a voltage equal to "logic 0"), and the logic input signal X is logic low, the output signal D1 is logic high, the output signal D2 is logic low, the output signal D3 is logic high, and the output signal D4 is logic low. When logic input signal Y is logic high (eg, has a voltage equal to “logic 0”) and logic input signal X is logic high, output signal D1 is logic low, output signal D2 is logic high, output signal D3 is logic high, and output signal D4 is logic high.

[0121] The circuit 500 uses the common transistors M41 and M42 to implement a logic decoder. The circuit 500 generates the same output signals D1, D2, D3 and D4 based on the same logic input signals X and XB, logic input signal Y and inverted input signal YB. Figure 5 As shown, the circuit 500 is powered by a power supply voltage VDD, which can be a "logic high" or "logic 1" voltage of the circuit relative to a second voltage VSS, which can be a "logic low" or "logic 0" voltage (e.g., a ground voltage) of the circuit. Figure 5As shown, circuit 500 includes transistors M31, M32, M33, M34, M35, M36, M37, M38, M39, M40, M41, and M42. In some implementations, an inverted input signal XB can be generated as an output of an inverter circuit, which can receive a logic input signal X and generate an inverted input signal XB. In some implementations, an inverted logic signal YB can be generated as an output of an inverter circuit, which can receive a logic input signal Y and generate an inverted input signal YB.

[0122] Circuit 500 includes transistors M31, M32, M33, M34, M35, M36, M37, M38, M39, M40, M41, and M42. In some implementations, transistors M31, M33, M41, M36, M38, and M42 each include a pMOSFET, and transistors M32, M34, M35, M37, M39, and M40 each include an nMOSFET. It should be understood that transistors M31-M42 may each include any other type of transistor (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while remaining within the scope of the embodiments of the present disclosure. Sources of transistors M31, M33, M36, and M38 are electrically coupled to a power supply voltage VDD. The drains of the transistors M31 and M33 are electrically coupled to the drains of the transistors M32 and M34 , respectively, and the drains of the transistors M36 and M38 are electrically coupled to the drains of the transistors M37 and M39 , respectively.

[0123] The operation of the portion of circuit 500 including transistors M31, M32, M33, M34, M35, and M41 is similar to the operation of the portion of circuit 500 including transistors M36, M37, M38, M39, M40, and M42. The portion of circuit 500 that generates output signals D1 and D2 at output nodes 510 and 512, respectively, receives logic input signals X and Y and an inverted input signal XB. The portion of circuit 500 that generates output signals D3 and D4 at output nodes 514 and 516, respectively, receives logic input signal X and inverted input signals XB and YB.

[0124] like Figure 5 As shown, the source of each of transistors M32 and M34 is electrically coupled to the drain of transistor M35. Transistor M35 can be an NMOS tail transistor. The source of transistor M35 is electrically coupled to a second voltage VSS, which can be a ground voltage. The gates of transistors M31 and M32 are electrically coupled to each other and connected to a logic input signal X. The gates of transistors M33 and M34 are electrically coupled to each other and connected to a logic inversion signal of input signal X, i.e., an inversion input signal XB as described in the present disclosure.

[0125] The drains of transistors M41 and M42 are electrically coupled to a first output node 510, which is a node through which the output signal D1 is generated. The drains of transistors M33 and M34 are electrically coupled to a second output node 512, which is a node through which the output signal D2 is generated. Figure 5 As shown, the common transistor M41 has a source connected to the first output node 510 and a drain connected to the second output node 512. The gates of the tail transistor M35 and the common transistor M41 are connected to the logic input signal Y.

[0126] like Figure 5 As shown, the source of each of transistors M37 and M39 is electrically coupled to the drain of transistor M40. Transistor M40 may be an NMOS tail transistor. The source of transistor M40 is electrically coupled to a second voltage VSS which may be a ground voltage. The gates of transistors M36 and M37 are electrically coupled to each other and connected to a logic input signal X. The gates of transistors M38 and M39 are electrically coupled to each other and connected to a logic inversion signal of input signal X, i.e., an inversion input signal XB as described in the present disclosure.

[0127] The drains of transistors M41 and M42 are electrically coupled to a third output node 514, which is a node through which the output signal D3 is generated. The drains of transistors M38 and M39 are electrically coupled to a fourth output node 516, which is a node through which the output signal D4 is generated. Figure 5 As shown, the common transistor M41 has a source connected to the third output node 514 and a drain connected to the fourth output node 516. The gates of the tail transistor M40 and the common transistor M42 are connected to the inverted input signal YB.

[0128] When the logic input signal Y is set to logic high, the inverting input signal YB is set to logic low. Therefore, the tail transistor M35 is started and turned on, the tail transistor M40 is turned off and not conducting, the common transistor M41 is turned off and not conducting, and the common transistor M42 is started and turned on. When the logic input signal Y is logic high, the inverting input signal YB is logic low, and the logic input signal X is logic low (for example, "logic 0"), the transistor M31 is started and turned on, and the transistor M32 is turned off and not conducting. In addition, the transistor M36 is turned off and not conducting, and the transistor M37 is started and turned on. The voltage at the first output node 510 (and the output signal D1 of the decoder) is therefore set to be approximately equal to the power supply voltage VDD (for example, logic high state, logic 1). Current does not flow through the transistor M37 because the transistor M40 is turned off and not conducting.

[0129] When the logic input signal X is logic low, the inverting input signal XB is logic high. When the logic input signal Y is logic high (e.g., enabling the decoder), the inverting input signal YB is set to logic low, and the inverting input signal XB is logic high (e.g., "logic 1"), the transistor M33 is turned off and does not conduct, the transistor M34 is activated and conducts, the transistor M38 is activated and conducts, and the transistor M39 is turned off and does not conduct. Because the transistor M35 is also activated and conducts, the voltage at the second output node 512 (the output signal D2 of the decoder) is set to the second voltage VSS (e.g., logic low state, logic 0, ground voltage, etc.). Current does not flow between the first output node 512 and the second output node 514 because the common transistor M41 is turned off and does not conduct when the input signal Y is in a logic high state. Because the transistor M38 is activated and the transistor M39 is turned off, the voltage at the fourth output node 516 (the output signal D4 of the decoder) is set to logic high (e.g., approximately equal to the power supply voltage VDD). Current will flow between the fourth output node 516 and the third output node 514 because the transistor M42 is enabled and turned on, and thus the third output node 514 (the output signal D3 of the decoder) is also set to logic high.

[0130] When the logic input signal Y is logic high, the inverting input signal YB is set to logic low, and the logic input signal X is logic high (e.g., "logic 1"), the transistor M31 is turned off and non-conducting, while the transistor M32 is turned on and turned on. In addition, the transistor M36 is turned off and non-conducting, while the transistor M37 is turned on and turned on. Because the tail transistor M35 is turned on and turned on, the voltage at the first output node 510 is set to be approximately equal to the second voltage VSS (e.g., logic low state, logic 0). Current does not flow through the transistor M37 because the tail transistor M40 is turned off and non-conducting.

[0131] When the logic input signal X is logic high, the inverting input signal XB is logic low. When the logic input signal Y is logic high, the inverting input signal YB is set to logic low, and the inverting input signal XB is logic low (e.g., "logic 0"), transistor M33 is started and turned on, transistor M34 is turned off and non-conducting, transistor M38 is started and turned on, and transistor M39 is turned off and non-conducting. The voltage at the second output node 512 and the fourth output node 516 is set to the power supply voltage VDD (e.g., logic high state, logic 1). Current will not flow between the first output node 510 and the second output node 512 because when the logic input signal Y is in a logic high state, the common transistor M41 is turned off and non-conducting. Current will flow between the third output node 514 and the fourth output node 516 because when the inverting input signal YB is in a logic low state, transistor M42 is started and turned on, thereby setting the third output node 514 to a logic high state.

[0132] When the logic input signal Y is set to logic low, the inverting input signal YB is set to logic high. In this case, the tail transistor M35 is turned off and does not conduct, the common transistor M41 is activated and turned on, the tail transistor M40 is activated and turned on, and the common transistor M42 is turned off and does not conduct. When the logic input signal Y is logic low, the inverting input signal YB is set to logic high, and the logic input signal X is logic low, the transistor M31 is activated and turned on, the transistor M32 is turned off and does not conduct, the transistor M36 is activated and turned on, and the transistor M37 is turned off and does not conduct. The voltage at the first output node 510 and the third output node 514 is therefore set to be approximately equal to the power supply voltage VDD (e.g., logic high state, logic 1).

[0133] When the logic input signal X is logic low, the inverting input signal XB is logic high. When the logic input signal Y is logic low, the inverting input signal YB is set to logic high, and the inverting input signal XB is logic high, the transistor M33 is turned off and non-conducting, the transistor M34 is started and turned on, the transistor M38 is turned off and non-conducting, and the transistor M39 is started and turned on. However, the transistor M35 will also be turned off because the logic input signal Y is logic low. The current will flow between the first output node 510 and the second output node 512, because the common transistor M41 is started and turned on, so the voltage at the second output node 512 will be set to logic high (for example, power supply voltage VDD). The transistor M40 is started and turned on, so the voltage at the fourth output node 516 is set to the second voltage VSS (for example, logic low). The current will not flow between the third output node 514 and the fourth output node 516 because the transistor M42 is turned off and non-conducting.

[0134] When the logic input signal Y is logic low, the inverting input signal YB is set to logic high, and the logic input signal X is logic high (e.g., "logic 1"), transistor M31 is off and non-conducting, transistor M32 is enabled and conductive, transistor M36 is off and non-conducting, and transistor M37 is enabled and conductive. However, the tail transistor M35 is off and non-conducting, so current does not flow through transistor M2, and transistor M40 is off and non-conducting, thereby setting the voltage at the third output node 514 to a logic low state (e.g., the second voltage VSS). When the logic input signal X is logic high, the inverting input signal XB is logic low.

[0135] When the logic input signal Y is logic low, the inverting input signal YB is set to logic high, and the inverting input signal XB is logic low (e.g., "logic 0"), transistor M33 is started and turned on, transistor M34 is turned off and turned on, transistor M38 is started and turned on, and transistor M39 is turned off and non-conducting. The voltage at the second output node 512 is therefore set to the power supply voltage VDD (e.g., logic high state, logic 1). Current will flow between the first output node 512 and the second output node 514 because the shared transistor M41 is started and turned on when the input signal Y is in a logic low state. The voltage at the fourth output node 516 is therefore set to a logic high state. Current will not flow between the third output node 514 and the fourth output node 516 because the shared transistor M42 is turned off when the inverting input signal YB is in a logic high state.

[0136] Figure 6 FIG. 6 is a flow chart of an example method 600 for operating a decoder circuit with shared transistors according to some embodiments of the present disclosure. The method 600 may be used to operate a word line decoder circuit (e.g., the circuit 300). For example, at least a portion of the operations described in the method 600 may use Figures 1 to 5 It should be noted that method 600 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 600 may be used in Figure 6 Additional operations are provided before, during, and after method 600, and some other operations may be described only briefly in this disclosure.

[0137] Briefly, the method 600 begins at operation 602, where a first word line clock signal, a second word line clock signal, and a block select signal are received. The method 600 then proceeds to operation 604, where the block select signal is provided to a common transistor having a first terminal coupled to a first node, a second terminal coupled to a second node, and a gate receiving the block select signal. In response to turning off the common transistor using the block select signal, the method 600 then proceeds to operation 606, where a first word line select signal and a second word line select signal are generated based on a first voltage at the first node and a second voltage at the second node.

[0138] Referring to operation 602, a first word line clock signal (e.g., input clock signal X0[0]), a second word line clock signal (e.g., input clock signal X0[1]), and a block select signal (e.g., a signal at node 316 of circuit 300) are received. The block select signal may be generated by at least one logic gate, such as NOR gate 312. In one example, the at least one logic gate may receive a plurality of block select signals (e.g., input signals X1B and X2B), and may generate an output representing whether a word line corresponding to a word line circuit is selected.

[0139] Referring to operation 604, a block selection signal is provided to a common transistor (e.g., common transistor M21, common transistor M22, etc.), the common transistor having a first terminal coupled to a first node (e.g., output node 320, output node 324), a second terminal coupled to a second node (e.g., output node 322, output node 326, etc.), and a gate receiving the block selection signal. In one embodiment, an inverter can generate an inverted block selection signal, which can be used to connect the source of the NMOS transistor to complementary NMOS and PMOS transistors, wherein the gates of the complementary NMOS and PMOS transistors are coupled to the first word line clock signal or the second word line clock signal, and the drains of the complementary NMOS and PMOS transistors are coupled to one of the first or second nodes.

[0140] Referring to operation 606, in response to turning off the common transistor using the block select signal, a first word line select signal (e.g., a word line select output signal WL[0]) and a second word line select signal (e.g., a word line select output signal WL[1]) are generated based on a first voltage at the first node and a second voltage at the second node. The first voltage at the first node and the second voltage at the second node can be generated by a plurality of sets of complementary NMOS and PMOS transistors, respectively, which are configured in series and whose gates are connected to the first word line clock signal and the second word line clock signal, respectively. The drain of each set of complementary NMOS and PMOS transistors is electrically coupled to the first node and the second node. The source of the PMOS transistor of each set of complementary NMOS and PMOS transistors is coupled to the power supply voltage.

[0141] In one aspect of the present disclosure, a decoder device is disclosed. The decoder device includes a first logic gate and a second logic gate. The first logic gate is used to receive a disable signal and a first input signal, and generate a first decoder output signal at a first output node. The second logic gate is used to receive the disable signal and a second input signal, and generate a second decoder output signal at a second output node, wherein the first logic gate and the second logic gate share a transistor, the transistor having a first terminal coupled to the first output node, a second terminal coupled to the second output node, and a gate terminal receiving the disable signal.

[0142] In some embodiments of the decoder device, the first logic gate and the second logic gate each comprise a NAND gate.

[0143] In some embodiments of the decoder device, the first logic gate and the second logic gate share a second transistor having a first terminal coupled to a ground voltage and a gate terminal receiving the disable signal.

[0144] In some embodiments of the decoder device, the first logic gate and the second logic gate each comprise a NOR gate.

[0145] In some embodiments of the decoder device, the first logic gate and the second logic gate share a second transistor having a first terminal coupled to a power supply voltage and a gate terminal receiving the disable signal.

[0146] In some embodiments of the decoder device, the deactivation signal enables the transistor such that a voltage at the first output node is approximately equal to a voltage at the second output node.

[0147] In some embodiments of the decoder device, the first logic gate and the second logic gate are each three-input gates that receive the second disable signal.

[0148] In some embodiments of the decoder device, the first logic gate and the second logic gate share a second transistor having a first terminal coupled to the first output node, a second terminal coupled to the second output node, and a gate terminal receiving the second disable signal.

[0149] In some embodiments of the decoder device, the second input signal is a logic inversion signal of the first input signal.

[0150] In some embodiments of the decoder device, the decoder device further comprises a third logic gate and a fourth logic gate. The third logic gate is used to receive a logic inversion signal of the disable signal and the first input signal, and generate a third decoder output at a third output node. The fourth logic gate is used to receive a logic inversion signal of the disable signal and the second input signal, and generate a fourth decoder output at a fourth output node. The third logic gate and the fourth logic gate share a second transistor, the second transistor having a first terminal coupled to the third output node, a second terminal coupled to the fourth output node, and a gate terminal receiving the logic inversion signal of the disable signal.

[0151] In some embodiments of the decoder device, a logic inversion signal of the disable signal activates the second transistor such that a voltage at the third output node is approximately equal to a voltage at the fourth output node.

[0152] In another aspect of the present disclosure, a word line decoder circuit is disclosed. The word line decoder circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third PMOS transistor. The gate of the first PMOS transistor receives a first word line clock signal, the gate of the second PMOS transistor receives a second word line clock signal, and the source of the first PMOS transistor and the source of the second PMOS transistor receive a power supply voltage. The gate of the first NMOS transistor receives the first word line clock signal, and the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor at a first node. The gate of the second NMOS transistor receives the second word line clock signal, and the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor at a second node. The source of the third PMOS transistor is connected to the first node, the drain of the third PMOS transistor is connected to the second node, and the gate of the third PMOS transistor receives an enable signal.

[0153] In some embodiments of the word line decoder circuit, the word line decoder circuit further includes a second inverter and a third inverter. The second inverter is used to receive a first voltage at the first node and generate a first word line selection signal. The third inverter is used to receive a second voltage at the second node and generate a second word line selection signal.

[0154] In some embodiments of the word line decoder circuit, the word line decoder circuit further includes a NOR gate, and the NOR gate is used to receive the first block selection signal and the second block selection signal and generate an enable signal.

[0155] In some embodiments of the word line decoder circuit, the word line decoder circuit further includes an inverter for receiving the enable signal and generating an inverted enable signal, wherein the source of the first NMOS transistor and the source of the second NMOS transistor receive the inverted enable signal.

[0156] In some embodiments of the word line decoder circuit, the third PMOS transistor, when activated by the enable signal, makes the voltage at the first node and the voltage at the second node equal to each other.

[0157] In some embodiments of the word line decoder circuit, the first word line clock signal and the second word line clock signal are a plurality of unique hot signals corresponding to a plurality of word lines, respectively.

[0158] In some embodiments of the word line decoder circuit, the word line decoder circuit further includes a fourth PMOS transistor, a fifth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a sixth PMOS transistor. The gate of the fourth PMOS transistor receives the third word line clock signal, the gate of the fifth PMOS transistor receives the fourth word line clock signal, and the source of the third PMOS transistor and the source of the fourth PMOS transistor are connected to the power supply voltage. The gate of the third NMOS transistor receives the third word line clock signal, and the drain of the third NMOS transistor is connected to the drain of the fourth PMOS transistor at the third node. The gate of the fourth NMOS transistor receives the fourth word line clock signal, and the drain of the fourth NMOS transistor is connected to the drain of the fifth PMOS transistor at the fourth node. The source of the sixth PMOS transistor is connected to the third node, the drain of the sixth PMOS transistor is connected to the fourth node, and the gate of the sixth PMOS transistor receives the enable signal.

[0159] In another aspect of the present disclosure, a method for operating a word line decoder circuit is disclosed. The method includes the following operations: receiving a first word line clock signal, a second word line clock signal, and a block selection signal; providing the block selection signal to a common transistor, the common transistor having a first terminal coupled to a first node, a second terminal coupled to a second node, and a gate receiving the block selection signal; and in response to turning off the common transistor using the block selection signal, generating a first word line selection signal and a second word line selection signal based on a first voltage at the first node and a second voltage at the second node.

[0160] In some embodiments of the operating method, the operating method further includes: generating a block selection signal using at least one logic gate.

[0161] In another aspect of the present disclosure, a word line decoder circuit is disclosed, comprising a first P-channel metal oxide semiconductor (PMOS) transistor, a second PMOS transistor, a first N-channel metal oxide semiconductor (NMOS) transistor, a second NMOS transistor, and a common transistor. The gate of the first PMOS transistor receives a first word line clock signal, the gate of the second PMOS transistor receives a second word line clock signal, and the source of the first PMOS transistor and the source of the second PMOS transistor receive a power supply voltage. The gate of the first NMOS transistor receives the first word line clock signal, and the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor at a first node. The gate of the second NMOS transistor receives the second word line clock signal, and the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor at a second node. The common transistor has a first terminal coupled to the first node, a second terminal coupled to the second node, and a gate for receiving a block selection signal. When the common transistor is turned off based on the block selection signal, the word line decoder circuit is used to generate a first word line selection signal and a second word line selection signal based on a first voltage at the first node and a second voltage at the second node.

[0162] As used herein, the terms "about" and "approximately" generally mean plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0163] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A decoder device, characterized in that: Include: a first logic gate for receiving a disable signal and a first input signal and generating a first decoder output signal at a first output node; and a second logic gate for receiving the disable signal and a second input signal and generating a second decoder output signal at a second output node, The first logic gate and the second logic gate share a transistor having a first terminal coupled to the first output node, a second terminal coupled to the second output node, and a gate terminal receiving the disable signal.

2. The decoder device according to claim 1, characterized in that The first logic gate and the second logic gate each include a NAND gate.

3. The decoder device according to claim 2, characterized in that The first logic gate and the second logic gate share a second transistor, and the second transistor has a first terminal coupled to a ground voltage and a gate terminal receiving the disable signal.

4. The decoder device according to claim 1, characterized in that The first logic gate and the second logic gate each include a NOR gate.

5. The decoder device according to claim 4, characterized in that The first logic gate and the second logic gate share a second transistor, and the second transistor has a first terminal coupled to a power supply voltage and a gate terminal receiving the disable signal.

6. The decoder device according to claim 1, characterized in that Also includes: a third logic gate for receiving a logic inversion signal of the disable signal and the first input signal and generating a third decoder output at a third output node; and a fourth logic gate for receiving the logic inversion signal of the disable signal and the second input signal and generating a fourth decoder output at a fourth output node, The third logic gate and the fourth logic gate share a second transistor, which has a first terminal coupled to the third output node, a second terminal coupled to the fourth output node, and a gate terminal receiving the logic inversion signal of the disable signal.

7. A word line decoder circuit, characterized in that: Include: a first P-channel metal oxide semiconductor (PMOS) transistor and a second PMOS transistor, wherein a gate of the first PMOS transistor receives a first word line clock signal, a gate of the second PMOS transistor receives a second word line clock signal, and a source of the first PMOS transistor and a source of the second PMOS transistor receive a power supply voltage; a first N-channel metal oxide semiconductor (NMOS) transistor, a gate of the first NMOS transistor receiving the first word line clock signal, a drain of the first NMOS transistor connected to a drain of the first PMOS transistor at a first node; a second NMOS transistor, a gate of the second NMOS transistor receiving the second word line clock signal, a drain of the second NMOS transistor connected to a drain of the second PMOS transistor at a second node; and A third PMOS transistor, a source of the third PMOS transistor is connected to the first node, a drain of the third PMOS transistor is connected to the second node, and a gate of the third PMOS transistor receives an enable signal.

8. The word line decoder circuit according to claim 7, wherein: Also includes: a second inverter for receiving a first voltage at the first node and generating a first word line selection signal; and A third inverter is used to receive a second voltage at the second node and generate a second word line selection signal.

9. The word line decoder circuit according to claim 7, wherein: Also includes: a fourth PMOS transistor and a fifth PMOS transistor, wherein a gate of the fourth PMOS transistor receives a third word line clock signal, a gate of the fifth PMOS transistor receives a fourth word line clock signal, and a source of the third PMOS transistor and a source of the fourth PMOS transistor are connected to a power supply voltage; a third NMOS transistor, a gate of the third NMOS transistor receiving the third word line clock signal, a drain of the third NMOS transistor connected to a drain of the fourth PMOS transistor at a third node; a fourth NMOS transistor, a gate of the fourth NMOS transistor receiving the fourth word line clock signal, a drain of the fourth NMOS transistor connected to a drain of the fifth PMOS transistor at a fourth node; and a sixth PMOS transistor, a source of the sixth PMOS transistor is connected to the third node, a drain of the sixth PMOS transistor is connected to the fourth node, and a gate of the sixth PMOS transistor receives the enable signal.

10. A word line decoder circuit, characterized in that: Include: a first P-channel metal oxide semiconductor (PMOS) transistor, a gate of the first PMOS transistor receiving a first word line clock signal, and a source of the first PMOS transistor receiving a power supply voltage; a second PMOS transistor, a gate of the second PMOS transistor receiving a second word line clock signal, and a source of the second PMOS transistor receiving the power supply voltage; a first N-channel metal oxide semiconductor (NMOS) transistor, a gate of the first NMOS transistor receiving the first word line clock signal, a drain of the first NMOS transistor connected to a drain of the first PMOS transistor at a first node; a second NMOS transistor, a gate of the second NMOS transistor receiving the second word line clock signal, a drain of the second NMOS transistor connected to a drain of the second PMOS transistor at a second node; as well as a common transistor having a first terminal coupled to the first node, a second terminal coupled to the second node, and a gate for receiving a block selection signal, When the common transistor is turned off based on the block selection signal, the word line decoder circuit is used to generate a first word line selection signal and a second word line selection signal based on a first voltage at the first node and a second voltage at the second node.

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