Semiconductor device

Abstract

The utility model provides a semiconductor device, which comprises a substrate, a photosensitive layer, a source electrode and a drain electrode, the photosensitive layer is arranged on the substrate and comprises a two-dimensional semiconductor layer and an organic semiconductor layer which are stacked, and the source electrode and the drain electrode are arranged in the photosensitive layer or on the photosensitive layer at intervals. In the utility model, the spectral response range of the photosensitive layer is the superposition of the spectral response range of the two-dimensional semiconductor layer and the spectral response range of the organic semiconductor layer, and the spectral response ranges of the two-dimensional semiconductor layer and the organic semiconductor layer are generally not completely overlapped, so that the photosensitive layer can have a wider spectral response range and better local light responsivity; moreover, the spectral response range of the two-dimensional semiconductor layer can generally cover near-infrared and infrared bands, so that the application of the semiconductor device in the aspects of military radar and medical treatment can be realized.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor device. Background Art

[0002] Organic photoresponsive organic field effect transistor (PhOFET) has attracted widespread attention due to its simple preparation process, low cost, light weight and flexibility of the prepared products. PhOFET is a type of organic semiconductor device. Compared with organic photodiode (OPD), which is also a member of the organic semiconductor device family, PhOFET integrates the detection and amplification functions of light signals, and has higher sensitivity and lower noise. Since PhOFET has a smaller effective photosensitive area (channel area), this type of device can usually obtain photocurrent gain and photoresponsivity that are hundreds to thousands of times higher than OPD, so it has more advantages in detecting weak light sources.

[0003] Generally speaking, in PhOFET, carrier transport only occurs within the organic semiconductor layer, which is a two-dimensional transmission process, and the crystal state of the organic semiconductor layer directly determines the performance of the prepared device. The organic semiconductor layer is usually amorphous or polycrystalline, which is bound to bring various traps and scattering, and the carrier mobility will be greatly reduced, resulting in a decrease in the transmission and collection efficiency of the photogenerated carriers of PhOFET, thereby reducing the local light response. In addition, for the organic semiconductor layer, there are very few materials that absorb light in the near-infrared and infrared bands, which also seriously limits the application of PhOFET in military radar and medical fields. Utility Model Content

[0004] The utility model aims to provide a semiconductor device to improve the spectral response range and local light response of existing semiconductor devices.

[0005] In order to achieve the above object, the utility model provides a semiconductor device, comprising:

[0006] substrate;

[0007] a photosensitive layer, located on the substrate, comprising a stacked two-dimensional semiconductor layer and an organic semiconductor layer; and

[0008] The source electrode and the drain electrode are arranged at intervals in or on the photosensitive layer.

[0009] Optionally, the two-dimensional semiconductor layer and the organic semiconductor layer are arranged in sequence from bottom to top.

[0010] Optionally, the source electrode and the drain electrode are located between the two-dimensional semiconductor layer and the organic semiconductor layer.

[0011] Optionally, there is a first gate electrode layer and a first gate dielectric layer disposed in sequence from bottom to top between the substrate and the photosensitive layer; and / or there is a second gate dielectric layer and a second gate electrode layer disposed in sequence from bottom to top on the photosensitive layer.

[0012] Optionally, the substrate is a bottom semiconductor layer and a buried oxide layer in a semiconductor-on-insulator substrate, and the first gate electrode layer is a top semiconductor layer in the semiconductor-on-insulator substrate.

[0013] Optionally, the first gate dielectric layer is an oxide layer naturally generated on the top semiconductor layer.

[0014] Optionally, the second gate dielectric layer and the second gate electrode layer are both transparent film layers.

[0015] Optionally, the material of the second gate dielectric layer is an organic high polymer, and the material of the second gate electrode layer is ITO.

[0016] Optionally, the material of the two-dimensional semiconductor layer includes transition metal chalcogenides, black phosphorus, silicene, germanene or graphene.

[0017] Optionally, the material of the organic semiconductor layer includes phthalocyanine metal compounds, naphthalocyanine metal compounds or pentacene.

[0018] The utility model provides a semiconductor device, including a substrate, a photosensitive layer, a source electrode and a drain electrode. The photosensitive layer is located on the substrate, including a stacked two-dimensional semiconductor layer and an organic semiconductor layer. The source electrode and the drain electrode are arranged in the photosensitive layer or on the photosensitive layer at intervals. In the utility model, the spectral response range of the photosensitive layer is the superposition of the spectral response ranges of the two-dimensional semiconductor layer and the organic semiconductor layer. Since the spectral response ranges of the two are usually not completely overlapped, the photosensitive layer can have a wider spectral response range and better local light responsiveness; and the spectral response range of the two-dimensional semiconductor layer can usually cover the near-infrared and infrared bands, which can realize the application of the semiconductor device in military radar and medical fields. Correspondingly, the utility model also provides a method for preparing a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A flow chart of a method for preparing a semiconductor device provided by an embodiment of the utility model;

[0020] Figure 2A schematic structural diagram of a semiconductor-on-insulator substrate provided in an embodiment of the utility model;

[0021] Figure 3 A schematic diagram of a structure for transferring a two-dimensional semiconductor layer onto a first gate dielectric layer using a wet transfer process provided in an embodiment of the utility model;

[0022] Figure 4 A schematic diagram of a structure in which an organic semiconductor material is evaporated on a source electrode, a drain electrode and an exposed two-dimensional semiconductor layer provided in an embodiment of the utility model;

[0023] Figure 5 A schematic diagram of the structure of a semiconductor device provided by an embodiment of the utility model;

[0024] Wherein, the accompanying drawings are marked as follows:

[0025] 100 - semiconductor substrate on insulator; 101 - bottom semiconductor layer; 102 - buried oxide layer; 103 - top semiconductor layer; 201 - first gate electrode layer; 202 - second gate electrode layer; 301 - first gate dielectric layer; 302 - second gate dielectric layer; 401 - two-dimensional semiconductor layer; 402 - organic semiconductor layer; 501 - source electrode; 502 - drain electrode. DETAILED DESCRIPTION

[0026] The following will describe the specific implementation of the utility model in more detail with reference to the schematic diagram. The advantages and features of the utility model will become clearer according to the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model.

[0027] Figure 5 Schematic diagram of the structure of the semiconductor device provided in this embodiment. Figure 5 As shown, in this embodiment, the semiconductor device is an organic photosensitive field effect transistor (PhOFET) for photoelectric detection, and the semiconductor device includes a substrate, a buried oxide layer 102, a first gate electrode layer 201, a first gate dielectric layer 301, a photosensitive layer, a source electrode 501, a drain electrode 502, a second gate dielectric layer 302 and a second gate electrode layer 202, wherein the substrate, the buried oxide layer 102, the first gate electrode layer 201, the first gate dielectric layer 301, the photosensitive layer, the second gate dielectric layer 302 and the second gate electrode layer 202 are arranged in sequence from bottom to top.

[0028] Specifically, the substrate can be a semiconductor substrate (such as a silicon substrate, a germanium substrate, a germanium silicon substrate, a gallium arsenide substrate, etc.), an insulating substrate (such as sapphire, aluminum nitride, etc.) or a flexible substrate (such as a substrate made of polyimide, epoxy resin or silicone resin).

[0029] In this embodiment, the substrate is a bottom semiconductor layer 101 and a buried oxide layer 102 in a semiconductor-on-insulator substrate 100, and the buried oxide layer 102 is located on the bottom semiconductor layer 101; the semiconductor-on-insulator substrate 100 also includes a top semiconductor layer 103, and the top semiconductor layer 103 is located on the buried oxide layer 102, and the top semiconductor layer 103 also serves as the first gate electrode layer 201.

[0030] In some embodiments, the substrate and the first gate electrode layer 201 are not formed using the semiconductor-on-insulator substrate 100. For example, the substrate may also be a silicon substrate, and the first gate electrode layer 201 may be a metal electrode or a semiconductor electrode formed on the substrate.

[0031] Further, in this embodiment, the first gate dielectric layer 301 is an oxide layer naturally generated on the top semiconductor layer 103. For example, the semiconductor-on-insulator substrate 100 may be a silicon-on-insulator substrate, and the material of the first gate dielectric layer 301 is silicon oxide, but the invention should not be limited thereto. In some embodiments, in order to improve the film quality of the first gate dielectric layer 301, or when the first gate electrode layer 201 is a metal electrode, the first gate dielectric layer 301 may also be an oxide layer formed by a furnace oxidation process or a deposition process, for example.

[0032] Optionally, the material of the first gate dielectric layer 301 can be an insulating oxide, such as silicon oxide, silicon oxynitride, etc., and the material of the first gate electrode layer 201 can be a semiconductor material such as silicon, polysilicon, or a metal material such as gold, silver, aluminum, copper, platinum, chromium and their alloys.

[0033] Please continue reading Figure 5 The photosensitive layer is located on the first gate dielectric layer 301, and includes a stacked two-dimensional semiconductor layer 401 and an organic semiconductor layer 402. The source electrode 501 and the drain electrode 502 are arranged in the photosensitive layer or on the photosensitive layer at intervals. It can be understood that the spectral response range of the photosensitive layer is the superposition of the spectral response ranges of the two-dimensional semiconductor layer 401 and the organic semiconductor layer 402. The spectral response range of the two-dimensional semiconductor layer 401 is usually 400nm to 1500nm, and the spectral response range of the organic semiconductor layer 402 is usually 200nm to 980nm. The spectral response ranges of the two are not completely overlapped, so the photosensitive layer can achieve a wide spectral response range of 200nm to 1500nm, and has better local light responsivity in the band of 400nm to 980nm. At this time, the spectral response range of the photosensitive layer also covers the near-infrared and infrared bands, so the semiconductor device can be used in military radar and medical fields.

[0034] In this embodiment, the two-dimensional semiconductor layer 401 and the organic semiconductor layer 402 are sequentially arranged from bottom to top, and the preparation is simpler. The source electrode 501 and the drain electrode 502 are arranged in the photosensitive layer at intervals, and are located between the two-dimensional semiconductor layer 401 and the organic semiconductor layer 402. Specifically, the two-dimensional semiconductor layer 401 is located on the first gate dielectric layer 301, the source electrode 501 and the drain electrode 502 are arranged at intervals on the two-dimensional semiconductor layer 401, and the organic semiconductor layer 402 covers the source electrode 501 and the drain electrode 502, and fills the gap between the source electrode 501 and the drain electrode 502. At this time, the two-dimensional semiconductor layer 401 and the organic semiconductor layer 402 are distributed on the upper and lower sides of the source electrode 501 and the drain electrode 502. The two-dimensional semiconductor layer 401 and the organic semiconductor layer 402 are very close to the conductive channel between the source electrode 501 and the drain electrode 502. The two-dimensional semiconductor layer 401 and the organic semiconductor layer 402 can play a roughly equivalent role in light absorption, and the semiconductor device can make use of the two-dimensional semiconductor layer 401 and the organic semiconductor layer 402 as much as possible.

[0035] Optionally, the material of the two-dimensional semiconductor layer 401 may be a transition metal chalcogenide, black phosphorus, silicene, germanene or graphene, and the material of the organic semiconductor layer 402 may be a phthalocyanine metal compound (such as lead phthalocyanine, copper phthalocyanine, nickel phthalocyanine, zinc phthalocyanine, cobalt phthalocyanine, iron phthalocyanine, etc.), a naphthalocyanine metal compound or pentacene.

[0036] Optionally, the source electrode 501 and the drain electrode 502 may be made of semiconductor materials such as silicon and polysilicon, or metal materials such as gold, silver, aluminum, copper, platinum, chromium and alloys thereof.

[0037] In some embodiments, the two-dimensional semiconductor layer 401 and the organic semiconductor layer 402 may also be swapped, that is, the organic semiconductor layer 402 may be located on the first gate dielectric layer 301, the source electrode 501 and the drain electrode 502 may be spaced apart on the organic semiconductor layer 402, and the two-dimensional semiconductor layer 401 may cover the source electrode 501 and the drain electrode 502, and fill the gap between the source electrode 501 and the drain electrode 502.

[0038] In some embodiments, the source electrode 501 and the drain electrode 502 may also be disposed on the photosensitive layer at intervals. For example, Figure 5In the embodiment, the source electrode 501 and the drain electrode 502 may also be disposed at intervals on the organic semiconductor layer 402. That is to say, the specific positions of the source electrode 501 and the drain electrode 502 do not affect the implementation of the present invention, and when the preparation process allows, the source electrode 501 and the drain electrode 502 may even be disposed in the two-dimensional semiconductor layer 401 or in the organic semiconductor layer 402.

[0039] Please continue reading Figure 5 , the second gate dielectric layer 302 is located on the photosensitive layer, and the second gate electrode layer 202 is located on the second gate dielectric layer 302. At this time, the semiconductor device has two gates, and the first gate electrode layer 201 and the second gate electrode layer 202 form a top-bottom double-gate structure. The double-gate structure can better control the conductive channel of the semiconductor device and obtain a larger output current at a lower operating voltage. Compared with the single-gate structure, the field effect mobility and current switching ratio are higher.

[0040] It should be noted that the top surface of the second gate electrode layer 202 is a light incident surface, so the second gate dielectric layer 302 and the second gate electrode layer 202 are preferably transparent film layers to avoid adverse effects on the light responsivity of the semiconductor device.

[0041] Optionally, the material of the second gate dielectric layer 302 may be an organic polymer, such as Parylene C, polymethyl methacrylate (PMMA), polyimide, polyvinyl alcohol, etc., so as to simplify the preparation process of the second gate dielectric layer 302. Of course, the material of the second gate dielectric layer 302 may also be an insulating oxide, such as silicon oxide, silicon oxynitride, etc.

[0042] Optionally, the material of the second gate electrode layer 202 may be ITO material.

[0043] In some embodiments, the semiconductor device may also be a single-gate structure. In this case, the first gate electrode layer 201 and the first gate dielectric layer 301 may be omitted, or the second gate electrode layer 202 may be omitted.

[0044] Based on this, this embodiment also provides a method for preparing a semiconductor device. Figure 1 A flow chart of a method for preparing a semiconductor device provided in this embodiment, such as Figure 1 As shown, the method for preparing the semiconductor device includes:

[0045] Step S100: providing a substrate;

[0046] Step S200: forming a photosensitive layer on the substrate, wherein the photosensitive layer comprises a stacked two-dimensional semiconductor layer and an organic semiconductor layer; and,

[0047] Step S300: forming a source electrode and a drain electrode that are spaced apart in or on the photosensitive layer.

[0048] Figure 2 to Figure 5 The following is a schematic diagram of the structure corresponding to the corresponding steps of the method for preparing a semiconductor device provided in this embodiment. Figure 2 to Figure 5 The method for preparing the semiconductor device provided in this embodiment is described in detail.

[0049] like Figure 2 As shown, step S100 is performed, first providing a semiconductor-on-insulator substrate 100, the semiconductor-on-insulator substrate 100 comprising a bottom semiconductor layer 101, a buried oxide layer 102 and a top semiconductor layer 103 arranged in sequence from bottom to top, and an oxide layer is naturally grown on the top semiconductor layer 103. The semiconductor-on-insulator substrate 100 is washed in sequence with acetone, ethanol and deionized water for about 10 minutes, and then the semiconductor-on-insulator substrate 100 is placed in a vacuum drying oven, and the semiconductor-on-insulator substrate 100 is dried in an environment of about 60° C. for about 30 minutes and then taken out.

[0050] Afterwards, the bottom semiconductor layer 101 and the buried oxide layer 102 can be used as the substrate of the semiconductor device, the top semiconductor layer 103 can be used as the first gate electrode layer 201 of the semiconductor device, and the oxide layer naturally grown on the top semiconductor layer 103 can be used as the first gate dielectric layer 301 of the semiconductor device.

[0051] As an optional embodiment, a silicon substrate or the like may be directly used as the substrate of the semiconductor device, and then the first gate electrode layer 201 and the first gate dielectric layer 301 are sequentially formed on the substrate.

[0052] Next, step S200 and step S300 are performed, as shown in FIG. Figure 3 As shown, the two-dimensional semiconductor layer 401 is transferred to the first gate dielectric layer 301 by a wet transfer process. For example, the material of the two-dimensional semiconductor layer 401 may be black phosphorus, and the wet transfer process may be a wet transfer process based on PMMA. The specific steps of the wet transfer process may be: using PMMA to support the black phosphorus film, and then transferring the black phosphorus film to the first gate dielectric layer 301, and finally removing PMMA, that is, forming the two-dimensional semiconductor layer 401 on the first gate dielectric layer 301.

[0053] Please continue reading Figure 3, a metal material is evaporated on the two-dimensional semiconductor layer 401 to form the source electrode 501 and the drain electrode 502. When evaporating the metal material, the area on the two-dimensional semiconductor layer 401 that does not need to be covered with the metal material needs to be blocked with a mask, and the mask can limit the length of the conductive channel and the area of ​​the source electrode 501 and the drain electrode 502. After the evaporation is completed, the mask is removed.

[0054] like Figure 4 As shown, an organic semiconductor material is evaporated on the source electrode 501, the drain electrode 502 and the exposed two-dimensional semiconductor layer 401 to form the organic semiconductor layer 402. After the evaporation is completed, the organic semiconductor layer 402 will cover the source electrode 501, the drain electrode 502 and fill the gap between the source electrode 501 and the drain electrode 502. The two-dimensional semiconductor layer 401 and the organic semiconductor layer 402 together constitute the photosensitive layer of the semiconductor device.

[0055] like Figure 5 As shown, a second gate dielectric layer 302 is formed on the photosensitive layer, and a second gate electrode layer 202 is formed on the second gate dielectric layer 302. In this embodiment, the material of the second gate dielectric layer 302 is polyparaxylene, and the material of the second gate electrode layer 202 is ITO. Therefore, the second gate dielectric layer 302 and the second gate electrode layer 202 can be formed by a magnetron sputtering process, so there is no need to change the machine, which simplifies the semiconductor device preparation process.

[0056] It should be noted that, when the semiconductor device has a single-gate structure, the step of preparing the second gate electrode layer 202 or the step of preparing the first gate electrode layer 201 and the first gate dielectric layer 301 may be omitted.

[0057] In summary, the semiconductor device provided in the embodiment of the present utility model includes a substrate, a photosensitive layer, a source electrode 501 and a drain electrode 502. The photosensitive layer is located on the substrate, including a stacked two-dimensional semiconductor layer 401 and an organic semiconductor layer 402. The source electrode 501 and the drain electrode 502 are arranged in the photosensitive layer or on the photosensitive layer at intervals. In the present utility model, the spectral response range of the photosensitive layer is the superposition of the spectral response ranges of the two-dimensional semiconductor layer 401 and the organic semiconductor layer 402. Since the spectral response ranges of the two are usually not completely overlapped, the photosensitive layer can have a wider spectral response range and better local light responsiveness; and the spectral response range of the two-dimensional semiconductor layer 401 can usually cover the near-infrared and infrared bands, which can realize the application of the semiconductor device in military radar and medical fields. Correspondingly, the present utility model also provides a method for preparing a semiconductor device.

[0058] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0059] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the above disclosed technical content can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0060] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0061] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not used to limit the scope of the utility model. It must be noted that the singular forms "one" and "a kind" used herein and in the appended claims include plural references unless the context clearly indicates the opposite meaning. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have a logical "or" definition, rather than a logical "exclusive or" definition, unless the context clearly indicates the opposite meaning. In addition, the implementation of the method and / or device in the embodiment of the utility model may include performing the selected task manually, automatically, or in combination.

Claims

1. A semiconductor device, characterized in that: include: substrate; A photosensitive layer, located on the substrate, comprising a stacked two-dimensional semiconductor layer and an organic semiconductor layer; as well as, The source electrode and the drain electrode are arranged at intervals in or on the photosensitive layer.

2. The semiconductor device according to claim 1, wherein The two-dimensional semiconductor layer and the organic semiconductor layer are arranged in sequence from bottom to top.

3. The semiconductor device according to claim 1 or 2, characterized in that The source electrode and the drain electrode are located between the two-dimensional semiconductor layer and the organic semiconductor layer.

4. The semiconductor device according to claim 1, wherein There are also a first gate electrode layer and a first gate dielectric layer arranged in sequence from bottom to top between the substrate and the photosensitive layer; and / or there are also a second gate dielectric layer and a second gate electrode layer arranged in sequence from bottom to top on the photosensitive layer.

5. The semiconductor device according to claim 4, wherein: The substrate is a bottom semiconductor layer and a buried oxide layer in a semiconductor-on-insulator substrate, and the first gate electrode layer is a top semiconductor layer in the semiconductor-on-insulator substrate.

6. The semiconductor device according to claim 5, characterized in that The first gate dielectric layer is an oxide layer naturally generated on the top semiconductor layer.

7. The semiconductor device according to any one of claims 4 to 6, characterized in that The second gate dielectric layer and the second gate electrode layer are both transparent film layers.

8. The semiconductor device according to claim 4, wherein: The material of the second gate dielectric layer is an organic high polymer, and the material of the second gate electrode layer is ITO.

9. The semiconductor device according to claim 1, wherein: The material of the two-dimensional semiconductor layer is transition metal chalcogenide, black phosphorus, silicene, germanene or graphene.

10. The semiconductor device according to claim 1, wherein The material of the organic semiconductor layer is a phthalocyanine metal compound, a naphthalocyanine metal compound or pentacene.

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