Semiconductor structure

Abstract

A semiconductor structure includes a substrate, an isolation structure, a vertical stack of first nanostructures, a plurality of first source / drain structures, a dielectric layer, and a first gate structure. The substrate comprises a first mesa structure and a second mesa structure; the isolation structure extends between the first mesa structure and the second mesa structure. A vertical stack of first nanostructures directly on the first mesa structure; a plurality of first source / drain structures coupled to the vertical stack of first nanostructures; the dielectric layer includes a first portion over the isolation structure and a second portion between the first source / drain structure and the substrate. The first gate structure encapsulates each of the vertically stacked nanostructures of the first nanostructures.

Description

Technical Field

[0001] The embodiments of the utility model relate to a semiconductor structure, and more particularly to a thin dielectric layer separating a fin-shaped structure, and a bottom isolation layer between a source / drain structure and a substrate. Background Art

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (such as the number of interconnect devices per unit chip area) generally increases as geometric size (such as the smallest component or circuit that can be produced by the manufacturing process used) decreases. The process of shrinking size generally increases production capacity and reduces the associated costs. The shrinking size also increases the complexity of processing and manufacturing integrated circuits.

[0003] For example, as integrated circuit technology moves toward smaller technology nodes, multi-gate metal oxide semiconductor field effect transistors (or multi-gate devices) have been introduced to increase gate-channel coupling, reduce off-state current, and reduce short channel effects to improve gate control. Multi-gate devices are generally considered to be devices having gate structures or portions thereof located on multiple sides of a channel region. Multi-bridge channel transistors are examples of multi-gate devices that are popular and strong candidates for high-performance and low-leakage current applications. The gate structure of the multi-bridge channel transistor may extend partially or completely around the channel region to contact two or more sides of the channel region. Since the gate structure surrounds the channel region, the multi-bridge channel transistor may also be considered a wrap-around gate transistor or a fully wrapped gate transistor. Although existing fully wrapped gate transistors are generally suitable for general purposes, they cannot meet all requirements. Utility Model Content

[0004] The purpose of the present invention is to provide a semiconductor structure to solve at least one of the above problems.

[0005] The present invention relates to a semiconductor structure. The semiconductor structure includes a substrate, including a first mesa structure and a second mesa structure; an isolation structure extending between the first mesa structure and the second mesa structure; a vertical stack of first nanostructures directly located on the first mesa structure; a plurality of first source / drain structures coupled to the vertical stack of the first nanostructures; a dielectric layer including a first portion located on the isolation structure and a second portion located between the first source / drain structure and the substrate; and a first gate structure covering each nanostructure of the vertical stack of the first nanostructures.

[0006] According to one embodiment of the utility model, it also includes: an inner spacer structure, located between the bottommost nanostructure of the vertical stack of the first nanostructure and the first mesa structure, wherein the second portion of the dielectric layer directly contacts the inner spacer structure, and the upper surface of the second portion of the dielectric layer is lower than the upper surface of the inner spacer structure.

[0007] According to one embodiment of the present invention, the thickness of the inner spacer structure is 3 nm to 8 nm.

[0008] According to one embodiment of the present invention, a ratio of a thickness of the isolation structure to a thickness of a topmost nanostructure of the vertical stack of the first nanostructures is between about 1 and 2.

[0009] According to one embodiment of the present invention, the thickness of the isolation structure is 10 nm to 15 nm.

[0010] According to one embodiment of the present invention, the thickness of the topmost nanostructure of the vertical stack of the first nanostructures is 6 nm to 10 nm.

[0011] According to one embodiment of the present invention, the thickness of the isolation structure is less than or equal to the height of the first mesa structure or the second mesa structure.

[0012] According to one embodiment of the present invention, the plurality of first source / drain structures do not have an undoped semiconductor layer.

[0013] According to one embodiment of the present invention, a height of the first mesa structure or the second mesa structure is 10 nm to 20 nm.

[0014] According to one embodiment of the present invention, it also includes: a vertical stack of second nanostructures directly located on the second mesa structure; a plurality of second source / drain structures coupled to the vertical stack of the second nanostructures; and a second gate structure covering each nanostructure of the vertical stack of the second nanostructures, wherein the plurality of second source / drain structures include an undoped semiconductor layer located on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The figure is a flow chart of an exemplary method for manufacturing a semiconductor structure in various embodiments of the present invention.

[0016] Figure 2A , Figure 4A , Figure 5A , Fig. 6A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig.13A , Fig.15A , Fig.17A , Fig.19A and Fig. 20C In one or more embodiments of the present invention, an exemplary workpiece is Figure 1 During the various production stages of the method, Figure 3 A partial cross-sectional view taken along the section line AA' is shown.

[0017] Figure 2B , Figure 4B , Figure 5B , Figure 6B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 13B , Fig. 17B , Fig. 20B , Fig.21B and Fig. 22B In one or more embodiments of the present invention, an exemplary workpiece is Figure 1 During the various production stages of the method, Figure 3 A partial cross-sectional view taken along the section line BB' is shown.

[0018] Figure 3 , Figure 7 , Fig.12 , Fig.14 , Fig.16 and Fig.18 In one or more embodiments of the present invention, an exemplary workpiece is Figure 1 Partial top view of the various stages of production.

[0019] Figure 8C In one or more embodiments of the present invention, the workpiece is along Figure 7 Partial cross-sectional view along the section line CC' is shown.

[0020] Fig.8D In one or more embodiments of the present invention, the workpiece is along Figure 7 A partial cross-sectional view along the section line DD' is shown.

[0021] Fig. 15B and Fig.19B In one or more embodiments of the present invention, the workpieces are respectively along Fig.14 and 18 A partial cross-sectional view taken along line EE' is shown.

[0022] Fig. 20A , Fig.21A and Fig.22A In one or more embodiments of the present invention, the workpiece Figure 1 The various production stages of the method are as follows Fig.18 Partial cross-sectional view along line FF' is shown.

[0023] Fig.23 It is a flow chart of another method for manufacturing another semiconductor structure in various embodiments of the present invention.

[0024] Fig.24A , Fig.25A , Fig.26A , Fig.27A and Fig.28A In one or more embodiments of the present invention, an exemplary workpiece is Fig.23 The various production stages of the method are as follows Fig.12 A partial cross-sectional view taken along the section line AA' is shown.

[0025] Fig. 24B , Fig.25B and Fig.26B In one or more embodiments of the present invention, an exemplary workpiece is Fig.23 The various production stages of the method are as follows Fig.12 A partial cross-sectional view taken along the section line BB' is shown.

[0026] Fig.27B and Fig.28B In one or more embodiments of the present invention, an exemplary workpiece is Fig.23 The various production stages of the method are as follows Fig.12 A partial cross-sectional view taken along line EE' is shown.

[0027] Fig.29 The flowchart is a method for manufacturing an isolation structure in a semiconductor structure in one or more embodiments of the present invention.

[0028] Fig.30 , Fig.31 , Fig.32 , Fig.33 , Fig.34 and Fig.35 In one or more embodiments of the present invention, an exemplary workpiece is Fig.29 The various production stages of the method are as follows Figure 3 A partial cross-sectional view taken along the section line AA' is shown.

[0029] The reference numerals are as follows:

[0030] A-A',B-B',C-C',D-D',E-E',F-F': hatching line

[0031] D1: Height

[0032] D2: Distance

[0033] T: Total thickness

[0034] T1, T2, T3, T4, T5, T6: thickness

[0035] 100,300,500: Method

[0036] 102,104,106,106a,106b,106c,106d,106e,106f,108,110,

[0037] 112,114,116,118,120,122,124,126,128,302,304,308: Step 200,400: Workpiece

[0038] 200A: Zone 1

[0039] 200B: Zone 2

[0040] 202:Substrate

[0041] 202t: Top

[0042] 202t': table structure

[0043] 202ts: Top surface

[0044] 204: Vertical Stacking

[0045] 206b, 206m, 206t: Sacrificial layer

[0046] 208b, 208m, 208t: channel layer

[0047] 209: Hard mask layer

[0048] 210a, 210b: Fin-like structure

[0049] 210C: Channel area

[0050] 210SD: Source / Drain Region

[0051] 212: Groove

[0052] 214,214': Dielectric layer

[0053] 214a,214b,214c,226i,226t,290':Part

[0054] 214c',214i': Isolation structure

[0055] 216: Virtual Gate Stack

[0056] 216a: dummy dielectric layer

[0057] 216b: dummy electrode

[0058] 216c: Gate top hard mask layer

[0059] 218: Gate spacer

[0060] 220a, 220b: source / drain trenches

[0061] 222: medial spacer depression

[0062] 224: Inner spacer structure

[0063] 226,226': Bottom isolation layer

[0064] 226ts: Upper surface

[0065] 228: first patterned mask layer

[0066] 230N, 230P, 230P': Source / drain structure

[0067] 230P0: Undoped semiconductor layer

[0068] 230P1: Doped semiconductor layer

[0069] 232: Contact etching stop layer

[0070] 234: Interlayer dielectric layer

[0071] 236: Gate trench

[0072] 238: Opening

[0073] 240: Gate structure

[0074] 290: Mask layer DETAILED DESCRIPTION

[0075] The following detailed description may be accompanied by the accompanying drawings to facilitate understanding of various aspects of the present invention. It is worth noting that the various structures are only for illustrative purposes and are not drawn to scale, as is common in the industry. In fact, the dimensions of the various structures may be increased or decreased arbitrarily for the sake of clarity.

[0076] It is understood that the different embodiments or examples provided below may implement different structures of the embodiments of the present invention. The embodiments of specific components and arrangements are used to simplify the present disclosure and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes direct contact between the two, or there are other additional components between the two instead of direct contact. In addition, the same reference numerals may be repeatedly used in various examples of the present invention for simplicity, but the elements with the same reference numerals in various embodiments and / or settings do not necessarily have the same corresponding relationship.

[0077] In addition, spatially relative terms such as "below," "beneath," "below," "above," "upper," or similar terms may be used to simplify the description of the relative relationship of one element to another element in a diagram. Spatially relative terms may extend to elements used in other orientations, not limited to the orientation shown. For example, if the device in the drawing is turned over, the element below or below will become the element above or above. Elements may also be rotated 90 degrees or other angles, so directional terms are only used to describe the orientation shown in the diagram.

[0078] In addition, when a value or range of values ​​is described with "about," "approximately," or similar terms, it is intended to include values ​​within a reasonable range, such as those of ordinary skill in the art taking into account the inherent variations in the manufacturing process. For example, based on the known manufacturing tolerances associated with the value, the value or range includes a reasonable range including the number, such as within + / -10% of the number. For example, when the thickness of the material layer is about 5 nm and the manufacturing tolerance of the deposited material layer is known to those of ordinary skill in the art to be 15%, the size range included is 4.25 nm to 5.75 nm.

[0079] A wrapped gate transistor includes a channel layer (region) stacked vertically or horizontally and suspended above a substrate, so that a gate structure can wrap (or surround) and engage the channel layer. The channel layer extends between the source and the drain, and a voltage can be applied to the gate structure, the source and / or the drain to control the current between the source and the drain. However, as the technology nodes of integrated circuits shrink, the leakage current of the wrapped gate transistor becomes a significant challenge. For example, parasitic transistors may be formed between the gate structure, the raised portion of the substrate (such as the mesa structure, on which the channel layer and the gate structure are located), and the epitaxial source / drain, and may cause unwanted current to flow / leak through the mesa structure between the epitaxial source / drain. Because the gate structure wraps around the mesa structure in the existing wrapped gate transistor instead of around the channel layer, the gate structure is limited to three sides (such as tri-gate control) to control the off-state leakage current in the mesa structure. As the technology nodes of integrated circuits decrease, the tri-gate control method is insufficient and induces and / or worsens the drain-induced barrier drop in the wrapped gate transistor.

[0080] In addition, a method for forming a fully wrapped gate transistor includes forming a stack containing multiple channel layers and sacrificial layers interlaced on a substrate, and the sacrificial layers can be selectively removed to release the channel layers to serve as channel components. The top of the stack and the substrate can be patterned to form an active area, and the active area is separated by a deep trench. Then, an isolation structure (such as a shallow trench isolation structure) is formed in the deep trench to separate adjacent active areas. However, the shallow trench isolation structure in the existing fully wrapped gate transistor is thick, and its formation method includes using a flowable chemical vapor deposition to form a dielectric layer, and then high-temperature annealing the dielectric layer for several hours to further solidify the dielectric layer. The annealing process has a high thermal budget, which adversely impacts the performance of the fully wrapped gate transistor. For example, germanium and / or defects in the sacrificial layer during a high thermal budget process may diffuse into the channel layer. In addition, in an embodiment where the dielectric layer contains an oxide such as silicon oxide, the germanium in the sacrificial layer may be oxidized under a high thermal budget process. Therefore, existing methods of forming shallow trench isolation structures in all-around gate transistors may disadvantageously increase defects in the channel layer, reduce carrier mobility, and reduce electrical performance.

[0081] Embodiments of the present invention provide a semiconductor structure with improved electrical performance and a method for forming the same. In one embodiment, the method includes forming a stack of staggered channel layers and sacrificial layers on a substrate, patterning the stack and portions of the substrate to form a fin structure (such as an active area) separated by a trench, forming a thin dielectric layer at the bottom of the trench to separate the fin structure, forming a bottom isolation layer in a source / drain recess, and forming a source / drain structure on the bottom isolation layer. In these embodiments, the process for forming the thin dielectric layer has a low thermal budget. For example, the thin dielectric layer of one embodiment includes silicon nitride formed by a low thermal budget process without oxygen. Therefore, the performance of a fully wrapped gate transistor can be improved. In addition, a bottom isolation layer is formed between the source / drain structure and the substrate to substantially suppress and / or eliminate any parasitic transistors between the gate stack, the source / drain structure, and the underlying mesa structure, thereby reducing and / or blocking leakage current from passing through the mesa structure. Therefore, the fully wrapped gate transistor described herein has better control of the off state and / or improved overall performance.

[0082] Various embodiments of the present invention will be further described in detail with reference to the accompanying drawings. Figure 1 Flow chart of a method 100 for forming a semiconductor structure according to an embodiment of the present invention. Figures 2A to 22B Described below are partial top views and / or cross-sectional views of a workpiece 200 during fabrication stages of an embodiment of the method 100 . Fig.23 Flow chart of a method 300 for forming other semiconductor structures according to an embodiment of the present invention. Figures 24A to 28B Described below is a partial cross-sectional view of a workpiece 400 during a manufacturing stage of an embodiment of the method 300 . Fig.29Flow chart of a method 500 for forming an isolation structure in a semiconductor structure according to an embodiment of the present invention. Figures 30 to 35 The following is a partial cross-sectional view of workpiece 200 during the manufacturing stage of an embodiment of method 500. Methods 100, 300, and 500 are merely examples and are not intended to limit the embodiments of the present invention to the description herein. Additional steps may be provided before, during, and after methods 100, 300, and 500, and additional embodiments of the methods may replace, omit, or swap some of the steps. Not all steps are described in detail here to simplify the content. As a result of the manufacturing process, workpieces 200 and 400 are manufactured into semiconductor structures, which may also be considered semiconductor structures depending on the content requirements. For the avoidance of doubt, Figures 2A to 35 The X, Y and Z directions are perpendicular to each other and Figures 2A to 35 In the embodiments of the present invention, similar reference numerals are used to indicate similar structures unless otherwise specified.

[0083] like Figure 1 , Figure 2A and Figure 2B As shown, step 102 of method 100 receives a workpiece 200 . Figure 2B The workpiece 200 is displayed along Figure 2A Partial cross-sectional view along section line BB' shown. In these embodiments, workpiece 200 includes a first region 200A for forming a p-type all-around gate transistor, and a second region 200B for forming an n-type all-around gate transistor. Workpiece 200 includes substrate 202. In one embodiment, substrate 202 is a base silicon substrate (i.e., a single crystal silicon including a base). In various embodiments, substrate 202 may include other semiconductor materials such as germanium, silicon carbide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, or a combination thereof. In some other embodiments, substrate 202 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate, and may include a carrier, an insulating layer on the carrier, and a semiconductor layer on the insulating layer. Substrate 202 may include a variety of doping regions arranged according to the design requirements of a semiconductor structure such as workpiece 200. The p-type doped region may include a p-type dopant such as boron, boron difluoride, other p-type dopant, or a combination thereof. The n-type doped region may include an n-type dopant such as phosphorus, arsenic, other n-type dopant, or a combination thereof. Various doped regions may be formed directly on and / or in the substrate 202 to provide a p-type well structure, an n-type well structure, or a combination thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes may be performed to form the various doped regions. In one embodiment, the substrate 202 includes an n-type well in the first region 200A, and a p-type well in the second region 200B.

[0084] like Figure 2A and Figure 2B As shown, the workpiece 200 also includes a vertical stack 204 of staggered semiconductor layers located on the substrate 202 and in the first area 200A and the second area 200B. In one embodiment, the vertical stack 204 includes a plurality of staggered channel layers (such as a bottom channel layer 208b, a middle channel layer 208m, and a top channel layer 208t) and a plurality of sacrificial layers (such as a bottom sacrificial layer 206b, a middle sacrificial layer 206m, and a top sacrificial layer 206t). The channel layers may each include a semiconductor material such as silicon, germanium, silicon carbide, silicon germanium, germanium tin, silicon germanium tin, other suitable semiconductor materials, or combinations thereof, and the composition of each sacrificial layer is different from the composition of the channel layer. In one embodiment, the channel layer includes silicon, and the sacrificial layer includes silicon germanium. It is worth noting that Figure 2A and Figure 2B Three sacrificial layers and three channel layers are shown in an alternating vertical configuration, but this is for illustrative purposes only and is not intended to limit the embodiments of the present invention to the present disclosure. It should be understood that any number of sacrificial layers and channel layers may be formed in the vertical stack 204. The number of layers depends on the number of channel components required for the device in the semiconductor structure, such as the workpiece 200. In some embodiments, the number of channel layers is between 2 and 10. In these embodiments, the channel layers 208b, 208m, and 208t each have the same thickness T1. The top and middle sacrificial layers 206t and 206m each have a thickness T2, and the bottom sacrificial layer 206b has a thickness T3, and the thickness T3 is greater than the thickness T2 to facilitate the formation of the bottom isolation layer 226. In one embodiment, the total thickness T of the vertical stack 204 is between about 50nm and about 60nm, the thickness T1 is between about 6nm and about 10nm, the thickness T2 is between about 8nm and about 10nm, and the thickness T3 is between about 10nm and about 20nm.

[0085] like Figure 2A and Figure 2B As shown, the workpiece 200 also includes a hard mask layer 209 formed on the vertical stack 204. The hard mask layer 209 may include any suitable material such as a semiconductor material or a dielectric material, as long as its composition is different from that of the channel layer, the sacrificial layer, and the dielectric layer 214 (e.g., Figure 5A In one embodiment, the hard mask layer 209 comprises silicon oxide.

[0086] like Figure 1 , Figure 3 , Figure 4A and Figure 4B As shown, step 104 of method 100 patterns the vertical stack 204 and the top portion 202 t of the substrate 202 to form a fin structure 210 a in the first region 200A and a fin structure 210 b in the second region 200B. Figure 3A partial top view of a workpiece 200 having a fin structure 210a and a fin structure 210b is shown. It is worth noting that Figure 3 The patterned hard mask layer 209 is omitted. Figure 3 As shown, the fin structures 210a and 210b each extend longitudinally along the X direction and include a channel region 210C and a source / drain region 210SD. The source / drain region can be considered as a source region or a drain region separately or together, depending on the context. The channel region 210C is located between the two source / drain regions 210SD. It is worth noting that Figure 3 It is shown that one fin structure is formed in the first region 200A and one fin structure is formed in the second region 200B, but this is only for illustration purposes and does not limit the embodiments of the present invention described herein.

[0087] Figure 4A The workpiece 200 is displayed along Figure 3 The partial cross-sectional view of the section line AA' is shown. Figure 4B The workpiece 200 is displayed along Figure 3 Partial cross-sectional view of the section line BB' shown. Figure 4A and Figure 4B As shown, the hard mask layer 209 is patterned to expose a portion of the vertical stack 204. The patterning process may include a photolithography process (such as optical lithography or electron beam lithography), which may further include applying a photoresist (such as spin coating), soft baking, aligning a photomask, exposing, post-exposure baking, developing the photoresist, rinsing, drying (such as spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. Using the patterned hard mask layer 209 as an etching mask, an etching process may be performed to etch the exposed portion of the vertical stack 204 and a portion of the top of the substrate 202 thereunder to form fin structures 210a and 210b and trenches 212 isolating the fin structures 210a and 210b. The patterned top 202t of the substrate 202 in the fin structures 210a and 210b may also be considered as a mesa structure 202t'. The mesa structures 202t' may each have a height D1 along the Z direction. In one embodiment, in order to facilitate the formation of an appropriate isolation structure between the fin structure 210a and the fin structure 210b, and substantially not introduce defects into the channel layer or substantially affect the electrical performance of the final structure, the ratio of the height D1 to the thickness T1 may be between about 1 and about 2. In one embodiment, the height D1 may be between about 10 nm and about 20 nm. In one embodiment, the height D1 is equal to the thickness T3.

[0088] like Figure 1 , Figure 5A , Figure 5B , Fig. 6A and Figure 6BAs shown, step 106 of method 100 forms an isolation structure 214c' between two adjacent fin structures 210a and 210b. Figure 5A and Figure 5B As shown, a dielectric layer 214 is formed on the workpiece 200. Since the thickness of the mesa structure 202t', such as the height D1, is between about 10nm and 20nm, the depth of the trench 212 is significantly less than the trench depth (greater than 100nm) in other all-around gate transistors. These embodiments do not use a flowable chemical vapor deposition to form a dielectric layer to substantially fill the trench 212, and perform a high temperature (such as above 600°C) annealing process for several hours to further solidify the dielectric layer formed by the chemical vapor deposition; instead, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes are used to deposit the dielectric layer 214 to partially fill the trench 212, and the deposition thickness of the dielectric layer 214 can be determined by the desired thickness T4 of the bottom portion 214c of the dielectric layer 214 that directly contacts the substrate 202. The deposition temperature of the dielectric layer 214 can be less than 350°C, and no annealing process is required. Therefore, defects or diffusion caused by high thermal budget annealing processes can be significantly reduced.

[0089] In one embodiment, the deposition method of the dielectric layer 214 may adopt a physical vapor deposition process. Due to the characteristics of the physical vapor deposition process, the thickness of the dielectric layer 214 formed on the flat surface or the upper surface is greater than the thickness of the dielectric layer 214 formed on the side surface. For example, a portion 214a of the dielectric layer 214 is formed on the upper surface of the patterned hard mask layer 209, a portion 214c of the dielectric layer 214 is formed on the upper surface of the substrate 202, and a portion 214b of the dielectric layer 214 is formed on the sidewall surfaces of the fin structures 210a and 210b, and the thickness T4 of each of the portions 214a and 214c is greater than the thickness T5 of the portion 214b of the dielectric layer 214. In these embodiments, in order to achieve proper isolation between the two fin structures 210a and 210b, and not to form a thick dielectric layer that requires a high thermal budget process to provide the tolerance required for the subsequent etching process, the thickness T4 is greater than or equal to the height D1 of the mesa structure 202t'. The dielectric layer 214 may be composed of any suitable dielectric material such as a low-k dielectric material, as long as its composition is different from the composition of the channel layer, sacrificial layer, and hard mask layer 209, so that the etching process can selectively remove the dielectric layer 214. In one embodiment, the dielectric layer 214 is oxygen-free and may include silicon nitride.

[0090] like Fig. 6A and Figure 6BAs shown, after the dielectric layer 214 is deposited, a chemical mechanical polishing process can be performed on the workpiece 200 until the upper surface of the hard mask layer 209 is exposed. That is, the chemical mechanical polishing process removes a portion 214a of the dielectric layer on the patterned hard mask layer 209. Then, an etching process can be performed to selectively etch back the retained portion of the dielectric layer 214 (such as portion 214b and portion 214c). In one embodiment, the etching process is an isotropic etching process. After removing the portion 214b of the dielectric layer 214, the etching process is stopped. The etching process can also partially etch a portion 214c of the dielectric layer 124, thereby forming a dielectric layer such as an isolation structure 214c' to isolate two adjacent fin structures 210a and 210b. The dielectric layer can be regarded as an isolation structure 214c' or a shallow trench isolation structure. In order to substantially remove the sacrificial layers 206b, 206m and 206t in a subsequent etching process and provide proper isolation between two adjacent fin structures 210a and 210b, the upper surface of the isolation structure 214c' is lower than or flush with the lower surface of the sacrificial layer 206b. That is, the thickness T6 of the isolation structure 214c' is less than or equal to the thickness of the mesa structure 202t', such as the height D1. In some embodiments, the ratio between the thickness T6 of the isolation structure 214c' and the thickness T1 of the channel layer 208b, 208m, or 208t is between about 1 and 2. For example, the thickness T1 is between about 6nm and about 10nm, and the thickness T6 is between about 10nm and about 15nm. The distance D2 between the upper surface of the isolation structure 214c' and the lower surface of the sacrificial layer 206b may be between about 3nm and about 5nm.

[0091] like Figure 1 , Figure 7 , Fig. 8A and Figure 8B As shown, step 108 of the method 100 forms a dummy gate stack 216 and a gate spacer 218 on the workpiece 200 . Figure 7 A partial top view of the workpiece 200 is shown having a dummy gate stack 216 and gate spacers 218 . FIG. 8A to FIG. 8D The workpiece 200 is shown along Figure 7 Partial cross-sectional view of the sections along lines A-A', B-B', C-C' and D-D' shown. Figure 7 and Figure 8BAs shown, the dummy gate stack 216 is formed on the channel region 210C of the fin structures 210a and 210b. In this embodiment, a gate replacement process (or a gate-last process) is used, in which one or more dummy gate stacks 216 serve as placeholders for the functional gate structure. Other processes and arrangements are also possible. The dummy gate stack 216 and the gate spacer 218 extend longitudinally along the Y direction. The dummy gate stack 216 and the gate spacer 218 each have a portion formed directly on the channel region 210C of the fin structures 210a and 210b, and a portion formed directly on the shallow trench isolation structure 214c', as shown in FIG. FIG. 8A to FIG. 8D shown.

[0092] The dummy gate stack 216 includes a dummy dielectric layer 216a and a dummy electrode 216b located on the dummy dielectric layer 216a. In some embodiments, the dummy dielectric layer 216a may include silicon oxide, and the dummy electrode 216b may include polysilicon. The dummy gate stack 216 may also each include a gate top hard mask layer 216c formed on the dummy electrode 216b. The gate top hard mask layer 216c may include silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxide, silicon oxycarbide, silicon carbide, silicon oxynitride and / or a combination thereof. After forming the dummy gate stack 216, a gate spacer 218 may be formed along the sidewalls of the dummy gate stack 216. The dielectric material used for the gate spacer 218 may be selected to selectively remove the dummy gate stack 216 without substantially damaging the gate spacer 218. The gate spacer 218 may include silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, silicon oxycarbide, silicon carbide, silicon oxynitride, and / or combinations thereof.

[0093] like Figure 1 , Fig. 9A and Fig. 9BAs shown, step 110 of the method 100 can recess the source / drain regions 210SD of the fin structures 210a and 210b to form source / drain trenches 220a in the first region 200A, and form source / drain trenches 220b in the second region 200B. Using the dummy gate stack 216 and the gate spacer 218 as etching masks, the source / drain regions 210SD of the fin structures 210a and 210b of the workpiece 200 can be anisotropically etched to form source / drain trenches 220a and source / drain trenches 220b. The anisotropic etching in step 110 may include a dry etching process, and may use hydrogen, fluorine-containing gas (such as carbon tetrafluoride, sulfur hexafluoride, difluoromethane, fluoroform and / or hexafluoroethane), chlorine-containing gas (such as chlorine, chloroform, carbon tetrachloride and / or boron trichloride), bromine-containing gas (such as hydrogen bromide and / or bromoform), iodine-containing gas, other suitable gases and / or plasma and / or combinations thereof. The source / drain trenches 220a and 220b may not only extend through the channel layer and the sacrificial layer in the vertical stack 204, but may also extend into the mesa structure 202t'. In these embodiments, the mesa structures 202t' after the anisotropic etching process each have a concave upper surface.

[0094] like Figure 1 , Fig. 10A , Fig. 10B , Fig.11A and Fig. 11B As shown, step 112 of method 100 forms an inner spacer structure 224. Fig. 10B As shown, after forming the source / drain trenches 220a and 220b, the sacrificial layer (such as the sacrificial layers 206b, 206m and 206t) exposed in the source / drain trenches 220a and 220b may be selectively partially recessed to form an inner spacer recess 222, while the exposed channel layer (such as the channel layer 208b, 208m and 208t) is substantially not etched. In some embodiments, the selective recessing process may include a selective isotropic etching process (such as a selective dry etching process or a selective wet etching process), and the amount of recessing the sacrificial layer may be controlled by the time of the etching process. After forming the inner spacer recess 222, a chemical vapor deposition or atomic layer deposition may be used to conformally deposit an inner spacer material layer (not shown) on the workpiece 200, including on and in the inner spacer recess 222. The inner spacer material may include silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxide, silicon oxycarbide, silicon carbide, or silicon oxynitride. After depositing the inner spacer material layer, the inner spacer material layer may be etched back to form an inner spacer structure 224 in the inner spacer recess 222. Fig. 11B In one embodiment, the thickness of each inner spacer structure 224 may be between about 3 nm and about 8 nm.

[0095] like Figure 1 , Fig.12 , Fig.13A and Fig. 13B As shown, step 114 of method 100 forms a bottom isolation layer 226 on the workpiece 200. In one embodiment, the method of forming the bottom isolation layer 226 is similar to the method of forming the shallow trench isolation structure 214c'. For example, a dielectric material layer is deposited on the workpiece 200, including on the upper surface of the dummy gate stack 216, on the upper surface of the substrate 202 exposed in the source / drain trenches 220a / 220b, and on the channel region 210C of the fin structures 210a and 210b and the sidewall surface of the dummy gate stack 216. A planarization process such as chemical mechanical polishing may then be performed to remove a portion of the dielectric material layer on the upper surface of the dummy gate stack 216, and an etching process may then be performed to remove a portion of the dielectric material layer extending along the channel region 210C of the fin structures 210a and 210b and the sidewall surface of the dummy gate stack 216 to form the bottom isolation layer 226. The shallow trench isolation structure 214c' may also be formed by combining Fig.29 The bottom isolation layer 226 can also be formed by the method 500. In some embodiments, the shallow trench isolation structure 214c' and the bottom isolation layer 226 are formed by different methods. For example, the shallow trench isolation structure 214c' can be formed by combining FIG. 5A to FIG. 6B The bottom isolation layer 226 can be formed by using the method described above. Fig.29 The bottom isolation layer 226 is formed by the method 500 described. The composition of the bottom isolation layer 226 can be any suitable dielectric material (such as a low-k dielectric material) as long as it is different from the composition of the channel layer, the sacrificial layer, the gate spacer 218, and the gate top hard mask layer 216c, so as to facilitate the etching process to selectively etch back the bottom isolation layer 226. In one embodiment, the bottom isolation layer 226 is a nitrogen-based dielectric layer and may include silicon nitride. The thickness of the bottom isolation layer 226 is less than the thickness T1 of the channel layer 208t, and may be between about 3nm and about 10nm.

[0096] like Fig.13A As shown, the bottom isolation layer 226 includes a portion 226t formed on the mesa structure 202t' and in the source / drain trenches 220a / 220b, and a portion 226i formed on the shallow trench isolation structure 214c'. The bottom isolation layer 226 continues the shape of the mesa structure 202t' and the shape of the shallow trench isolation structure 214c'. The portion 226t of the bottom isolation layer 226 has a concave upper surface, while the portion 226i of the bottom isolation layer 226 has a substantially flat upper surface. Fig. 13BAs shown, the bottom isolation layer 226 (such as the portion 226t of the bottom isolation layer 226) is formed in the source / drain trench 220a and directly contacts the substrate 202. In order to form a fully wrapped gate transistor without forming a parasitic transistor on the gate structure 240 (such as Fig. 22B As shown), the mesa structure 202t', and the epitaxial source / drain structure (as shown Fig. 22B 208b) between the source / drain structures 230P shown in FIG. 21, the upper surface 226ts of the portion 226t of each bottom isolation layer 226 is at least partially higher than the topmost surface 202ts of the mesa structure 202t' (such as the partial upper surface of the mesa structure 202t' in the channel region 210C), and the sidewall surface of the portion 226t of the bottom isolation layer 226 at least partially directly contacts the sidewall surface of the bottommost inner spacer structure 224 between the mesa structure 202t' and the bottommost channel layer 208b. In one embodiment, the height at which the portion of the sidewall surface of the bottom isolation layer overlaps with the bottommost inner spacer structure 224 is between about 5nm and about 10nm. In one embodiment, the sidewall surface of the portion 226t of the bottom isolation layer 226 is completely in direct contact with the sidewall surface of the bottommost inner spacer structure 224. Furthermore, the sidewall surface of the portion 226t of the bottom isolation layer 226 does not contact the bottommost channel layer 208b without substantially affecting the performance of the all-around gate transistor. In one embodiment, the thickness of the bottom isolation layer 226 is between about 3 nm and about 10 nm.

[0097] like Figure 1 , Fig.14 , Fig.15A and Fig. 15BAs shown, step 116 of method 100 forms a first patterned mask layer 228 on the second area 200B of the workpiece 200. The mask layer can be conformally deposited on the workpiece 200, including the first area 200A and the second area 200B. The mask layer can include any suitable material such as a metal-based oxide, as long as its composition is different from the composition of the channel layer, the sacrificial layer, and the bottom sacrificial layer 226, so that the etching process can selectively remove the mask layer. In one embodiment, the mask layer includes aluminum oxide. The mask layer can be patterned to remove a portion of the mask layer on the first area 200A, while retaining a portion of the mask layer on the second area 200B. The patterned mask layer can be regarded as a first patterned mask layer 228. In some embodiments, in order to pattern the mask layer, a mask film such as a bottom anti-reflective coating can be formed on the workpiece 200, and the formation method can be a spin coating, a flowable chemical vapor deposition, or other suitable process. The mask film is then patterned by a patterning process. The patterning process may include a photolithography process (such as optical lithography or electron beam lithography), which may include applying photoresist, soft baking, aligning a photomask, exposing, baking after exposure, developing photoresist, rinsing, drying, other suitable photolithography techniques and / or combinations thereof. The mask layer is then patterned using the patterned mask film to form a first patterned mask layer 228. After forming the first patterned mask layer 228, the patterned mask film may be selectively removed. Fig.14 A partial top view of the workpiece 200 is shown having a first patterned mask layer 228 . Fig.15A and Fig. 15B The workpiece 200 is shown along Fig.14 Partial cross-sectional view of the section lines A-A' and E-E' shown. Fig.14 , Fig.15A and Fig. 15B In the illustrated embodiments, the first patterned mask layer 228 may cover the exposed sidewall surfaces and upper surface of the bottom isolation layer 226, the exposed sidewall surfaces of the channel layer and the sacrificial layer, the exposed upper surface and sidewall surfaces of the gate spacer 218, and the exposed upper surface of the dummy gate stack 216 in the second region 200B, and expose the sidewall surfaces of the bottom isolation layer 226, the channel layer, and the sacrificial layer in the first region 200A.

[0098] like Figure 1 , Fig.16 , Fig.17A and Fig. 17B As shown, step 118 of method 100 forms a p-type source / drain structure 230P in the first region 200A. Fig.16 A partial top view of the workpiece 200 is shown having a p-type source / drain structure 230P. Fig.17A and Fig. 17B The workpiece 200 is shown along Fig.16Partial cross-sectional views along lines AA' and BB' are shown. In these embodiments, the first patterned mask layer 228 covers the structures in the second region 200B, and the p-type source / drain structures 230P are formed in the source / drain trenches 220a in the first region 200A.

[0099] The p-type source / drain structure 230P can be selectively epitaxially formed on the exposed sidewalls of the channel layers 208b, 208m and 208t, and the epitaxial method can adopt an epitaxial process such as vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, molecular beam epitaxy and / or other suitable processes. Since the bottom isolation layer 226 covers the exposed upper surface of the substrate 202 in the first region 200A, the p-type source / drain structure 230P will not grow epitaxially from the substrate 202. In one embodiment, the p-type source / drain structure 230P continues the shape of the source / drain trench 220a and each has a protruding lower surface. The p-type source / drain structure 230P is each separated from the substrate 202 by the bottom isolation layer 226 and directly contacts all the sidewall surfaces of the bottommost channel layer 208b. In some embodiments, the p-type source / drain structure 230P also directly contacts a portion of the sidewall surface of the bottommost inner spacer structure 224. Since the p-type source / drain structure 230P is separated from the substrate 202 by the bottom isolation layer 226, the p-type source / drain structure 230P may not have an undoped semiconductor layer but only include a doped semiconductor layer. The p-type source / drain structure 230P may be coupled to the channel layer in the first region 200A, and may include gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable materials, and may introduce p-type dopants such as boron or gallium during the epitaxial process for in-situ doping, or use a junction implantation process for ex-situ doping. After forming the p-type source / drain structure 230P, the first patterned mask layer 228 may be selectively removed.

[0100] like Figure 1 , Fig.18 , Fig.19A and Fig.19B As shown, step 120 of the method 100 forms an n-type source / drain structure 230N in the second region 200B. Fig.18 A partial top view of the workpiece 200 is shown having an n-type source / drain structure 230N. Fig.19A and Fig.19B The workpiece 200 is shown along Fig.18A partial cross-sectional view along the section lines AA' and EE' is shown. After forming the p-type source / drain structure 230P, a second patterned mask layer (not shown) may be formed on the first region 200A. The composition and formation method of the second patterned mask layer may be similar to the composition and formation method of the first patterned mask layer 228. For example, the second patterned mask layer may cover the p-type source / drain structure 230P in the first region 200A and expose the sidewall surfaces of the channel layer and the sacrificial layer in the second region 200B. Since the second patterned mask layer is formed on the first region 200A, the n-type source / drain structure 230N is formed in the source / drain trench 220b in the second region 200B.

[0101] An epitaxial process such as vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, molecular beam epitaxy and / or other suitable processes may be used to selectively epitaxially form the n-type source / drain structure 230N from the exposed sidewalls of the channel layers 208b, 208m and 208t. Since the bottom isolation layer 226 covers the exposed upper surface of the substrate 202 in the second region 200B, the n-type source / drain structure 230N is not selectively epitaxially formed from the substrate 202. In one embodiment, the n-type source / drain structure 230N continues the shape of the source / drain trench 220b and each has a convex lower surface. The n-type source / drain structure 230N is each separated from the substrate 202 by the bottom isolation layer 226 and directly contacts all sidewall surfaces of the bottommost channel layer 208b. In some embodiments, the n-type source / drain structure 230N also directly contacts a portion of the sidewall surface of the bottommost inner spacer structure 224. Since the n-type source / drain structure 230N is separated from the substrate 202 by the bottom isolation layer 226, the n-type source / drain structure 230N may not have an undoped semiconductor layer but only include a doped semiconductor layer. The n-type source / drain structure 230N is coupled to the channel layers 208b, 208m, and 208t in the first region 200A, and may include phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and n-type dopants such as phosphorus, arsenic, or antimony may be introduced during the epitaxial process for in-situ doping, or a junction implantation process may be used for ex-situ doping. After the n-type source / drain structure 230N is formed, the second patterned mask layer may be selectively removed.

[0102] like Figure 1 and FIG. 20A to FIG. 20C As shown, step 122 of method 100 selectively removes the dummy gate stack 216 . Fig. 20A After selectively removing the dummy gate stack 216, the workpiece 200 is shown along Fig.18 Partial cross-sectional view along line FF' is shown. Fig. 20B After selectively removing the dummy gate stack 216, the workpiece 200 is shown along Fig.18A partial cross-sectional view taken along the section line BB' is shown. Fig. 20C After selectively removing the dummy gate stack 216, the workpiece 200 is shown along Fig.18 2. A partial cross-sectional view of the section line AA' shown. After forming the source / drain structures 230N and 230P, a contact etch stop layer 232 and an interlayer dielectric layer 234 may be deposited on the workpiece 200. The contact etch stop layer 232 may include silicon nitride, silicon oxynitride and / or other suitable materials, and its formation method may be atomic layer deposition, plasma-assisted chemical vapor deposition and / or other suitable deposition or oxidation processes. After depositing the contact etch stop layer 232, the interlayer dielectric layer 234 may be deposited on the workpiece 200, and its deposition method may be a plasma-assisted chemical vapor deposition process or other suitable deposition technology. The interlayer dielectric layer may include silicon oxide, an oxide of tetraethoxysilane, doped silicon oxide (such as borophosphosilicate glass, fluorosilicate glass, phosphosilicate glass, borosilicate glass, or the like), a low dielectric constant dielectric material (whose dielectric constant is lower than the dielectric constant of silicon oxide, such as about 3.9), other suitable materials, or a combination of the above. Then, a planarization process may be performed to remove excess materials, such as removing the gate top hard mask layer 216c in the dummy gate stack 216 and portions of the contact etch stop layer 232 and the interlayer dielectric layer 234 on the gate top hard mask layer 216c. Fig. 20C As shown, the contact etch stop layer 232 directly contacts the source / drain structures 230P and 230N and the bottom isolation layer 226. It should be understood that the profiles of the source / drain structures 230P and 230N are only examples and are not intended to limit the embodiments of the present invention described herein. The profiles of the source / drain structure 230P and / or the source / drain structure 230N can be adjusted as needed.

[0103] Afterwards FIG. 20A to FIG. 20C As shown, the dummy gate stack 216 may be selectively removed. Removing the dummy gate stack 216 may form a gate trench 236 on the channel region 210C and on the shallow trench isolation structure 214c'. The etching process may include any suitable process, such as a dry etching process, a wet etching process, or a combination thereof, and is configured to selectively remove the dummy gate stack 216 without substantially etching the shallow trench isolation structure 214c', the channel layer and the sacrificial layer, the gate spacer 218, the contact etch stop layer 232, and the interlayer dielectric layer 234.

[0104] like Figure 1 , Fig.21A and Fig.21BAs shown, step 124 of method 100 selectively removes sacrificial layers 206b, 206m, and 206t. After selectively removing dummy gate stack 216, sacrificial layers 206b, 206m, and 206t may be selectively removed and a plurality of openings 238 may be formed to intersect channel layers 208b, 208m, and 208t without substantially removing channel layers 208b, 208m, and 208t, inner spacer structures 224, and shallow trench isolation structures 214c'. In one example, the wet etching process uses an oxidant such as ammonium hydroxide, ozone, nitric acid, hydrogen peroxide, or other suitable oxidants, and a fluorine-based etchant such as hydrofluoric acid, ammonium fluoride, other suitable etchants, or a combination thereof, to selectively remove sacrificial layers 206b, 206m, and 206t and release channel layers 208b, 208m, and 208t to serve as channel elements.

[0105] like Figure 1 , Fig.22A and Fig. 22BAs shown, step 126 of method 100 forms a gate structure 240 in the opening 238 and the gate trench 236 to cover the channel layers 208b, 208m and 208t and is located on the channel layers 208b, 208m and 208t. The gate structure 240 may include an interface layer (not shown), a gate dielectric layer (not shown) located on the interface layer, and a gate layer (not shown) located on the gate dielectric layer. In some embodiments, the interface layer may include silicon oxide formed by thermal oxidation. Then, a gate dielectric layer is deposited on the interface layer, and the deposition method may be atomic layer deposition, chemical vapor deposition and / or other suitable methods. The gate dielectric layer may include a dielectric material with a high dielectric constant. The high dielectric constant dielectric material described herein may be a dielectric material having a dielectric constant greater than the dielectric constant of thermally oxidized silicon. In one embodiment, the gate dielectric layer may include hafnium oxide. The gate dielectric layer may be replaced with a dielectric layer including other high dielectric constants, such as titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium oxide, zirconium oxide silicon oxide, lanthanum oxide, aluminum oxide, yttrium oxide, strontium titanium oxide, barium titanium oxide, barium zirconium oxide, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, barium strontium titanate, silicon nitride, silicon oxynitride, combinations of the above, or other suitable materials. The gate layer is deposited on the gate dielectric layer. The gate layer may be a multilayer structure including at least one work function layer and a metal filling layer. For example, at least one work function layer may include titanium nitride, titanium aluminum, titanium aluminum nitride, tantalum nitride, tantalum aluminum, tantalum aluminum nitride, tantalum aluminum carbide, tantalum carbonitride, or tantalum carbide. The metal filling layer may include aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, tantalum silicon nitride, copper, other refractory metals, other suitable metal materials, or combinations of the above. In various embodiments, the gate layer may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes. In various embodiments, a planarization process such as a chemical mechanical polishing process may be performed to remove excess portions of these materials to provide a substantially flat upper surface of the gate structure 240. In some embodiments, a first gate structure is formed to cover each channel component in the first region 200A, and a second gate structure is formed to cover each channel component in the second region 200B, and the composition of the first gate structure is different from the composition of the second gate structure.

[0106] like Figure 1As shown, step 128 of method 100 performs other processes to complete the fabrication of a semiconductor structure such as workpiece 200. For example, method 100 may further recess gate structure 240 and form a dielectric cap layer on the recessed gate structure. These other processes may also include forming a gate isolation structure to cut the recessed gate structure 240 into portions. The gate isolation structure may extend longitudinally along a direction (e.g., an X direction) and the direction is substantially perpendicular to the longitudinal direction of the gate structure 240. These other processes may also include forming a silicide layer on the source / drain structure, forming a gate contact on the gate structure, and forming a source / drain contact on the source / drain structure. These other processes may also include forming an interconnect structure that is configured to connect multiple structures to form a functional circuit, and the functional circuit may contain different semiconductor structures. The interconnect structure may include multiple interlayer dielectric layers, and multiple metal lines, contact vias and / or power rails in each interlayer dielectric layer. The metal lines, contact vias, and power rails in each inter-layer dielectric layer may be composed of metals such as aluminum, tungsten, ruthenium, or copper.

[0107] In the above embodiment, the transistor in the first region 200A and the transistor in the second region 200B both include the bottom isolation layer 226. In some embodiments, in order to meet the different electrical performances of the n-type all-wrap gate transistor and the p-type all-wrap gate transistor, a transistor in the first region 200A and a transistor in the second region 200B may not have the bottom isolation layer 226. Fig.23 , FIG. 24A to FIG. 28A In the embodiments described in FIGS. 24B to 28B, the semiconductor structure such as the workpiece 400 only has the bottom isolation layer 226 in the second region 200B. Fig.23 A method of forming a semiconductor structure such as workpiece 400 is shown, and FIG. 24A to FIG. 28A and FIG. 24B to FIG. 28B A partial cross-sectional view of a semiconductor structure such as workpiece 400 is shown. Fig.23 As shown, method 300 is similar to method 100. The difference between method 100 and method 300 includes the following steps: Figure 1 After steps 102, 104, 106, 108, 110, 112, 114, and 116 are described, step 302 of method 300 is performed to pattern the bottom isolation layer 226 to expose a portion of the substrate 202 in the first region 200A. More specifically, as Fig.24A , Fig. 24B , Fig.25A and Fig.25BAs shown, after forming the first patterned mask layer 228 on the second region 200B, the first patterned mask layer 228 may be used as an etching mask and an etching process may be performed to pattern the bottom isolation layer 226. The etching process may selectively remove a portion of the bottom isolation layer 226 in the first region 200A and retain a portion of the bottom isolation layer 226 in the second region 200B. The portion of the bottom isolation layer 226 in the second region 200B may be regarded as a bottom isolation layer 226'. Due to the removal of the portion of the bottom isolation layer 226 in the first region 200A, the upper surface of the substrate 202 in the first region 200A previously covered by the bottom isolation layer 226 may be exposed, as shown in FIG. Fig.25A and Fig.25B shown.

[0108] like Fig.23 , Fig.26A and Fig.26BAs shown, step 304 of method 300 forms a first type of source / drain structure 230P' in the first region 200A. In these embodiments, the first type of source / drain structure 230P' includes a p-type source / drain structure. Unlike the first type of source / drain structure 230P that does not include an undoped semiconductor layer, the first type of source / drain structure 230P' includes an undoped semiconductor layer 230P0 and a doped semiconductor layer 230P1. In one embodiment, the undoped semiconductor layer 230P0 includes undoped silicon germanium, and the doped semiconductor layer 230P1 may include silicon germanium with a p-type dopant. The undoped semiconductor layer 230P0 and the doped semiconductor layer 230P1 may be formed epitaxially. Since the upper surface of the substrate 202 in the first region 200A previously covered by the bottom isolation layer 226 is exposed, the undoped semiconductor layer 230P0 and / or the doped semiconductor layer 230P1 can grow not only from the exposed sidewall surface of the channel layer, but also from the exposed upper surface of the substrate 202 in the first region 200A in a bottom-up manner. Since the first type of source / drain structure 230P' is epitaxially grown in a bottom-up manner, the subsequently formed p-type all-around gate transistor can increase carrier mobility and reduce leakage current due to the formation of the undoped semiconductor layer 230P0. In some embodiments, in addition to forming the undoped semiconductor layer 230P0, an anti-punch-through implantation process can be performed to form an anti-punch-through layer (not shown) in a portion of the substrate 202 in the first region 200A. The anti-punch-through implantation process can be performed before forming the vertical stack 204 on the substrate 202. The anti-punch-through layer is a doped region in the substrate 202 that is configured to prevent punch-through (i.e., to prevent unwanted merging and / or negligible spacing between the drain depletion region and the source depletion region, which may cause unwanted conduction paths and / or leakage current paths between the source / drain and hinder the transistor's turn-off function) and / or unwanted dopant diffusion. In the first region 200A used to form a p-type all-around gate transistor, the anti-punch-through layer may include n-type dopants such as phosphorus and / or arsenic.

[0109] like Fig.23 , Fig.27A , Fig.27B , Fig.28A and Fig.28BAs shown, step 308 of method 300 selectively removes the first patterned mask layer 228 and forms a second type of source / drain structure 230N in the second region 200B. After forming the first type of source / drain structure 230P' in the first region 200A, the first patterned mask layer 228 can be selectively removed to expose the bottom isolation layer 226' in the second region 200B. Another patterned mask layer can be formed on the first region 200A to protect the first type of source / drain structure 230P' during the subsequent epitaxial growth process. Another patterned mask layer is formed on the first region 200A, and then the second type of source / drain structure 230N is formed in the source / drain trench 220b in the second region 200B and on the bottom isolation layer 226'. After forming the second type of source / drain structure 230N, the other patterned mask layer on the first region 200A can be selectively removed. As with Fig.17A , Fig. 17B , Fig.19A and Fig.19B As described above, since the bottom isolation layer 226' covers the upper surface of the substrate 202 in the second region 200B, the second type of source / drain structure 230N does not contain an undoped semiconductor layer and can be epitaxially grown from the exposed sidewall surface of the channel layer instead of epitaxially growing from the substrate 202. After forming the first type of source / drain structure 230P' in the first region 200A and forming the second type of source / drain structure 230N in the second region 200B, the second type of source / drain structure 230N can be matched. Figure 1 Steps 122, 124, 126 and 128 are described to complete the fabrication of a semiconductor structure such as workpiece 400. Therefore, by using the bottom isolation layer 226' in the second region 200B and forming an anti-punch-through layer and / or an undoped semiconductor layer 230P0 in the first region 200A, the p-type fully wrapped gate transistor can have a high carrier mobility, and the p-type fully wrapped gate transistor and the n-type fully wrapped gate transistor can have a low leakage current. Fig.28A As shown, a portion of the contact etch stop layer 232 directly contacts and is located on the isolation structure 214c', and a portion of the contact etch stop layer 232 directly contacts and is located on the bottom isolation layer 226'.

[0110] In matching Figure 1 , Figure 5A and Fig. 6A In the above described embodiments, the isolation structure 214 c ′ may be formed by a combination of a physical vapor deposition process, a chemical mechanical polishing process, and an etch-back process. Fig.29 Another method 500 is shown to form an isolation structure 214c' in the trench 212. After performing steps 102 and 104 of the method 100, the method 500 may be performed. Fig.29 and30 As shown, step 106a of method 500 is to deposit a dielectric layer 214' on Figure 4A The dielectric layer 214' is similar to the dielectric layer 214, and repeated description is omitted to simplify the content. In one embodiment, the dielectric layer 214' includes silicon nitride, which can be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable processes.

[0111] like Fig.29 and Fig.31 As shown, step 106b of method 500 forms a mask layer 290 on the workpiece 200. In these embodiments, the mask layer 290 includes a bottom anti-reflective coating. The bottom anti-reflective coating such as the mask layer 290 is formed on the dielectric layer 214' and may include silicon oxynitride, a polymer, or a suitable material. After forming the bottom anti-reflective coating such as the mask layer 290, the dielectric layer 214' and the bottom anti-reflective coating such as the mask layer 290 may substantially fill the trench 212.

[0112] like Fig.29 and Fig.32 As shown, step 106c of method 500 etches back the mask layer 290 to retain a portion 290' of the mask layer 290 to cover a portion of the dielectric layer 214'. The portion 290' of the mask layer 290 can be regarded as a mask layer. More specifically, an etching process is performed to selectively remove the bottom anti-reflective coating, such as an upper portion of the mask layer 290, to expose a portion of the dielectric layer 214' on the patterned hard mask layer 209 and an upper portion of the portion of the dielectric layer 214' on the sidewall surface of the patterned vertical stack 204. That is, the portion 290' of the mask layer covers a lower portion of the portion of the dielectric layer 214' on the sidewall surface of the patterned vertical stack 204, and may also cover a portion of the dielectric layer 214' on the exposed surface of the substrate 202. In one embodiment, in order to substantially remove the bottom sacrificial layer 206b in a subsequent channel release process and provide sufficient isolation between the two fin structures, the upper surface of the portion 290' of the mask layer is higher than the upper surface of the mesa structure 202t' and lower than the upper surface of the bottom sacrificial layer 206b.

[0113] like Fig.29 and Fig.33 As shown, step 106d of method 500 performs a first etching process to selectively remove the portion of dielectric layer 214' not covered by mask layer 290'. Using portion 290' of mask layer as an etching mask, the first etching process can selectively etch the portion of dielectric layer 214' not covered by portion 290' of mask layer, such as Fig.33 The first etching process may be a dry etching process, a wet etching process, or a suitable etching process.

[0114] like Fig.29 and Fig.34 As shown, step 106e of method 500 selectively removes portion 290' of the mask layer. After selectively removing the portion of dielectric layer 214', a suitable etching process may be used to selectively remove portion 290' of the mask layer. Fig.34 In the illustrated embodiment, after removing portions 290 ′ of the mask layer, the dielectric layers 214 ′ each include portions on the lower sidewalls of the patterned vertical stack 204 and portions on the upper surface of the substrate 202 .

[0115] like Fig.29 and Fig.35 As shown, step 106f of method 500 performs a second etching process to selectively etch back the dielectric layer 214' and form an isolation structure 214i' on the substrate 202. In one embodiment, the second etching process includes an isotropic etching process, which is configured to selectively etch the dielectric layer 214' without substantially etching the channel layer and the sacrificial layer. The time of the isotropic etching process can be controlled to completely remove the portion of the dielectric layer 214' on the sidewall of the vertical stack 204. Due to the isotropic etching process, the portion of the dielectric layer 214' on the substrate 202 can also be slightly etched. After the isotropic etching process is performed, the portion of the dielectric layer 214' formed on the substrate 202 can be regarded as the isolation structure 214i'. After the isolation structure 214i' is formed, the patterned hard mask layer 209 can be selectively removed, and the isotropic etching process can be performed. Figure 1 Steps 108 to 128 of the method 100 are repeated to complete the manufacturing process. As described above, the method 500 used to form the isolation structure 214i' can also be used to form the bottom isolation layer 226, and repeated descriptions are omitted to simplify the content.

[0116] One or more embodiments of the present invention provide many advantages to semiconductor structures and methods of forming the same, but are not limited thereto. For example, the semiconductor structure provided by the embodiments of the present invention has a thin dielectric layer as an isolation structure between two adjacent active regions to reduce defects caused by high thermal budget processes, and a bottom isolation layer is formed between the source / drain structure and the substrate to reduce or suppress leakage current through the mesa structure, while having little or no effect on other electrical properties of the fully wrapped gate transistor, such as channel resistance. The bottom isolation layer can substantially suppress and / or eliminate any parasitic transistors between the gate structure, the epitaxial source / drain structure, and the underlying semiconductor mesa structure to reduce and / or block leakage current from passing through the semiconductor mesa structure. Therefore, the fully wrapped gate transistor disclosed herein has better off-state control and / or improved overall performance. In another embodiment, an n-type all-around gate transistor may include a bottom isolation layer, a p-type all-around gate transistor may not have a bottom isolation layer, and an undoped semiconductor layer may be formed in the source / drain trenches and on the substrate and / or an anti-punch-through layer may be formed in the corresponding mesa structure to suppress the leakage current associated with the p-type all-around gate transistor. Therefore, the carrier mobility in the p-type all-around gate transistor may be increased without substantially increasing the leakage current of the p-type all-around gate transistor. The embodiments of the utility model can be easily integrated into existing processes and technologies used to manufacture all-around gate transistors.

[0117] The present invention provides many different embodiments. A semiconductor structure and a method for making the same are disclosed herein. In an exemplary embodiment, the present invention relates to a method for forming a semiconductor structure. The method includes receiving a workpiece, which includes a first region and a second region, and the workpiece includes: a first fin located on a substrate and in the first region; and a second fin located on the substrate and in the second region, and the first fin and the second fin are separated by a groove. The method also includes forming an isolation structure on the substrate and between the first fin and the second fin; forming a dummy gate stack to join the first fin and the second fin; selectively recessing the portions of the first fin and the second fin not covered by the dummy gate stack to form a plurality of first source / drain openings in the first region, and forming a plurality of second source / drain openings in the second region; forming a first dielectric layer in the first source / drain openings and the second source / drain openings and on the isolation structure; after forming the first dielectric layer, forming a plurality of first source / drain structures in the first source / drain openings and on the first dielectric layer; forming a plurality of second source / drain structures in the second source / drain openings and on the first dielectric layer; selectively removing the dummy gate stack to form a gate trench; and forming a gate structure in the gate trench.

[0118] In some embodiments, the step of forming an isolation structure may include performing a physical vapor deposition process to form a second dielectric layer on the workpiece to partially fill the trench; performing a planarization process to remove portions of the second dielectric layer on the first fin and the second fin; and selectively recessing the retained portion of the second dielectric layer to remove portions of the second dielectric layer on the sidewall surfaces of the first fin and the second fin to form an isolation structure on the substrate. In some embodiments, the step of forming the isolation structure may include forming a second dielectric layer on the workpiece to partially fill the trench, the second dielectric layer including a first portion on the upper surface of the first fin and the second fin, a second portion on the sidewall surface of the first fin and the second fin, and a third portion on the substrate; forming a mask layer on the second dielectric layer to fill the remaining portion of the trench; recessing the mask layer to expose the upper portion of the first portion of the second dielectric layer and the second portion of the second dielectric layer; selectively removing the upper portion of the first portion and the second portion of the second dielectric layer; selectively removing the mask layer; and etching back the third portion of the second dielectric layer and the lower portion of the second portion to form the isolation structure. In some embodiments, the first fin includes a vertical stack of a plurality of staggered channel layers and the sacrificial layer, wherein the method may also include, before forming the first dielectric layer, selectively recessing the sacrificial layer to form a plurality of inner spacer recesses; forming a plurality of inner spacer structures in the inner spacer recesses; and selectively removing the sacrificial layer, wherein the gate structure further covers each of the channel layers. In some embodiments, the first dielectric layer directly contacts the sidewall surface of the inner spacer structure at the bottom of the inner spacer structure. In some embodiments, the topmost surface of the first dielectric layer may be lower than the lower surface of the bottommost channel layer of the channel layer. In some embodiments, the thickness of the bottommost sacrificial layer of the sacrificial layer may be greater than the thickness of the topmost sacrificial layer of the sacrificial layer. In some embodiments, the ratio of the thickness of the isolation structure to the thickness of the topmost channel layer of the channel layer is between about 1 and 2. In some embodiments, the first source / drain structure and the second source / drain structure may not contain an undoped semiconductor layer. In some embodiments, the step of forming the first dielectric layer may include performing a physical vapor deposition process to form a dielectric material layer on the workpiece; performing a planarization process to remove a portion of the dielectric material layer on the dummy gate stack; and etching back the dielectric material layer to remove a portion of the dielectric material layer on the sidewall surface of the dummy gate stack, the first fin, and the second fin to form a first dielectric layer.

[0119] In another exemplary embodiment, the utility model relates to a method for forming a semiconductor structure. The method includes forming a vertical stack of multiple staggered channel layers and multiple sacrificial layers on a substrate; patterning the vertical stack and the top of the substrate to form a fin structure, wherein the ratio of the thickness of the patterned top of the substrate to the thickness of one of the multiple channel layers is between about 1 and about 2; forming an isolation structure on the substrate to be adjacent to the fin structure; forming a dummy gate stack on the channel region of the fin structure; recessing the source / drain region of the fin structure to form a source / drain opening; forming a dielectric layer, the dielectric layer including a first portion in the source / drain opening and directly contacting the substrate, and a second portion on the isolation structure; epitaxially growing a doped semiconductor layer in the source / drain opening, wherein the doped semiconductor layer and the substrate are separated by a dielectric layer; selectively removing the dummy gate stack and selectively removing the sacrificial layer; and forming a gate structure to cover the channel layer and be located on the channel layer.

[0120] In some embodiments, the step of forming the isolation structure may include depositing a dielectric material layer on a substrate, wherein the dielectric material layer includes a first portion located on the substrate, a second portion extending along the sidewall surface of the fin structure, and a third portion located on the fin structure, wherein the thickness of the first portion of the dielectric material layer is greater than or equal to the thickness of the top of the patterned substrate; and removing the second portion and the third portion of the dielectric material layer to form an isolation structure on the substrate. In some embodiments, the dielectric material layer does not contain oxygen. In some embodiments, the method may also include selectively recessing the sacrificial layer to form a plurality of inner spacer recesses; and forming a plurality of inner spacer structures in the inner spacer recesses, wherein the sidewall surface of the dielectric layer may directly contact the sidewall surface of the inner spacer structure at the bottom of the inner spacer structure. In some embodiments, the upper surface of the first portion of the dielectric layer is higher than the upper surface of the top of the patterned substrate and lower than the lower surface of the bottommost channel layer of the channel layer. In some embodiments, the fin structure is a first fin structure, and the step of patterning the vertical stack and the top of the substrate further forms a second fin structure, and the method may also include: recessing the source / drain region of the second fin structure to form a source / drain trench, wherein the dielectric layer also includes a third portion in the source / drain trench; forming a patterned mask film on the third portion of the dielectric layer; selectively removing the third portion of the dielectric layer to expose the substrate in the source / drain trench; and forming an undoped semiconductor layer in the source / drain trench and on the substrate; and forming another doped semiconductor layer in the source / drain trench and on the undoped semiconductor layer.

[0121] In yet another embodiment, the present invention relates to a semiconductor structure. The semiconductor structure includes a substrate including a first mesa structure and a second mesa structure; an isolation structure extending between the first mesa structure and the second mesa structure; a vertical stack of first nanostructures directly located on the first mesa structure; a plurality of first source / drain structures coupled to the vertical stack of first nanostructures; a dielectric layer including a first portion located on the isolation structure and a second portion located between the first source / drain structure and the substrate; and a first gate structure covering each nanostructure of the vertical stack of first nanostructures.

[0122] In some embodiments, the semiconductor structure may also include an inner spacer structure located between the bottommost nanostructure of the vertical stack of the first nanostructure and the first mesa structure, wherein the second portion of the dielectric layer may directly contact the inner spacer structure, and the upper surface of the second portion of the dielectric layer is lower than the upper surface of the inner spacer structure. In some embodiments, the thickness of the inner spacer structure is 3nm to 8nm. In some embodiments, the ratio of the thickness of the isolation structure to the thickness of the topmost nanostructure of the vertical stack of the first nanostructure is between about 1 and 2. In some embodiments, the thickness of the isolation structure is 10nm to 15nm. In some embodiments, the thickness of the topmost nanostructure of the vertical stack of the first nanostructure is 6nm to 10nm. In some embodiments, the thickness of the isolation structure is less than or equal to the height of the first mesa structure or the second mesa structure. In some embodiments, the first source / drain structure does not have an undoped semiconductor layer. In some embodiments, the height of the first mesa structure or the second mesa structure is 10nm to 20nm. In some embodiments, the semiconductor structure may also include a vertical stack of second nanostructures directly located on the second mesa structure; a plurality of second source / drain structures coupled to the vertical stack of second nanostructures; and a second gate structure encapsulating each nanostructure of the vertical stack of second nanostructures, wherein the second source / drain structure includes an undoped semiconductor layer located on the substrate.

[0123] The features of the above embodiments are helpful for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, including a first mesa structure and a second mesa structure; an isolation structure extending between the first mesa structure and the second mesa structure; a vertical stack of first nanostructures directly on the first mesa structure; a plurality of first source / drain structures coupled to the vertical stack of first nanostructures; a dielectric layer including a first portion located above the isolation structure and a second portion located between the first source / drain structures and the substrate; and A first gate structure covers each nanostructure of the vertical stack of the first nanostructures.

2. The semiconductor structure according to claim 1, wherein: Also includes: an inner spacer structure located between the bottommost nanostructure of the vertical stack of the first nanostructures and the first mesa structure, The second portion of the dielectric layer directly contacts the inner spacer structure, and an upper surface of the second portion of the dielectric layer is lower than an upper surface of the inner spacer structure.

3. The semiconductor structure according to claim 2, wherein: The thickness of the inner spacer structure is 3 nm to 8 nm.

4. The semiconductor structure according to claim 1 or 2, characterized in that: The ratio of the thickness of the isolation structure to the thickness of the topmost nanostructure of the vertical stack of the first nanostructures is between 1 and 2.

5. The semiconductor structure according to claim 4, characterized in that The thickness of the isolation structure is 10 nm to 15 nm.

6. The semiconductor structure according to claim 4, characterized in that The thickness of the topmost nanostructure of the vertical stack of first nanostructures is 6 nm to 10 nm.

7. The semiconductor structure according to claim 1 or 2, characterized in that: The thickness of the isolation structure is less than or equal to the height of the first mesa structure or the second mesa structure.

8. The semiconductor structure according to claim 1 or 2, characterized in that: The plurality of first source / drain structures do not have an undoped semiconductor layer.

9. The semiconductor structure according to claim 1 or 2, characterized in that: The height of the first mesa structure or the second mesa structure is 10 nm to 20 nm.

10. The semiconductor structure according to claim 1 or 2, characterized in that: Also includes: a vertical stack of second nanostructures directly on the second mesa structure; a plurality of second source / drain structures coupled to the vertical stack of second nanostructures; as well as a second gate structure covering each nanostructure of the vertical stack of second nanostructures, The plurality of second source / drain structures include an undoped semiconductor layer located on the substrate.

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