Low-temperature polycrystalline silicon display panel and display device

Abstract

The utility model discloses a low-temperature polycrystalline silicon display panel and a display device. The low-temperature polycrystalline silicon display panel comprises a common electrode layer, an SD layer, a first insulating layer, a second insulating layer and a grid electrode layer, the first insulating layer is arranged between the common electrode layer and the SD layer; the second insulating layer is arranged between the gate layer and the SD layer; the SD layer is connected with the flat position of the common electrode layer through at least one via hole. On one hand, the SD layer and the common electrode layer are connected through the via holes at the climbing position and the flat position of the gate layer metal, the number of the via holes is increased, the resistance of the via holes is reduced, on the other hand, the common electrode layer is disconnected at the climbing position of the gate layer metal, the number of the via holes of the SD layer and the common electrode layer is increased or the length of the via holes is increased, and the resistance of the via holes is reduced. The touch resistance is also reduced, the connection degree of the two is guaranteed, and the touch effect is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of display screens, and in particular to a low-temperature polysilicon display panel and a display device. Background Art

[0002] Flat panel display devices have many advantages such as thin body, power saving, and no radiation, and have been widely used. Existing flat panel display devices mainly include liquid crystal display devices (LCD) and organic light emitting display devices (OLED). Thin film transistors (TFT) are an important component of flat panel display devices. Low temperature polysilicon (LTPS) technology is a new generation of thin film transistor liquid crystal display manufacturing technology. The biggest difference from traditional amorphous silicon displays is that low temperature polysilicon displays have faster response speeds and have advantages such as high brightness, high resolution, and low power consumption.

[0003] In addition, low-temperature polysilicon display technology has also gained favor among consumers due to its high mobility. However, in existing touch display panels, the connection vias between the touch wiring and the touch layer may have poor via connections due to process fluctuations, which reduces the touch and display effects and reduces the product yield.

[0004] refer to Figure 1 , Figure 2 and Figure 3 In the prior art, the touch line SD and the touch layer VCOM (also used as the common electrode of the display) are connected through a via just above the gate line. There is only one such via in a row of pixels. If there is a misalignment in the process, such as Figure 2 and Figure 3 That is, the via will appear at the location of the Gate metal trace where the SD metal climbs, which will deteriorate the via connection effect, or even cause the via connection to fail. At the same time, too few vias will increase the touch resistance, resulting in a poor touch effect. In addition, since VCOM is connected across the Gate trace, the coupling between the gate and the common electrode is increased, which will also deteriorate the touch effect. Utility Model Content

[0005] The existing low-temperature polysilicon display panel has poor via connection effect, increased touch resistance, and ultimately poor touch effect.

[0006] In view of the above problems, a low-temperature polysilicon display panel and a display device are proposed. By connecting the SD layer and the common electrode layer with vias at the climbing position and the flat position of the gate layer metal, the number of vias is increased and the via resistance is reduced. On the other hand, by disconnecting the common electrode layer at the climbing position of the gate layer metal and increasing the number of vias between the SD layer and the common electrode layer or lengthening the via length, the touch resistance is also reduced, the connection between the two is guaranteed, and the touch effect is improved.

[0007] In a first aspect, a low temperature polysilicon display panel comprises:

[0008] A common electrode layer;

[0009] SD layer;

[0010] a first insulating layer;

[0011] a second insulating layer;

[0012] Gate layer;

[0013] The first insulating layer is disposed between the common electrode layer and the SD layer;

[0014] The second insulating layer is disposed between the gate layer and the SD layer;

[0015] The SD layer is connected to a flat position of the common electrode layer through at least one via hole.

[0016] In combination with the low-temperature polysilicon display panel of the present invention, in a first possible implementation manner, the common electrode layer is disconnected at the metal climbing position of the gate layer and is divided into a plurality of flat touch blocks.

[0017] In combination with the first possible implementation manner of the first aspect of the utility model, in a second possible implementation manner, the SD layer is connected to the touch block through a first via hole, and the length of the first via hole is greater than half of the width of the touch block.

[0018] In combination with the second possible implementation manner of the first aspect of the utility model, in a third possible implementation manner, the length of the first via hole is equal to the width of the touch block.

[0019] In combination with the first possible implementation manner of the first aspect of the utility model, in a fourth possible implementation manner, the SD layer is connected to the touch block through a plurality of second via holes.

[0020] In combination with the fourth possible implementation manner of the first aspect of the utility model, in a fifth possible implementation manner, the number of the second via holes is 3, and the SD layer is respectively connected to the first end, the middle part and the second end via holes of the touch block through the second via holes.

[0021] In combination with the low-temperature polysilicon display panel of the present invention, in a sixth possible implementation manner, the SD layer is connected to the common electrode layer via hole through a third via hole at the climbing position of the gate layer metal.

[0022] In combination with the low-temperature polysilicon display panel of the present invention, in a seventh possible implementation manner, the display panel further includes a glass substrate bonded to the bottom of the gate layer.

[0023] In a second aspect, a display device comprises the low-temperature polysilicon display panel described in the first aspect.

[0024] By implementing the low-temperature polysilicon display panel and display device described in the utility model, the SD layer and the common electrode layer are connected through vias at the climbing position and the flat position of the gate layer metal, thereby increasing the number of vias and reducing the via resistance. On the other hand, by disconnecting the common electrode layer at the climbing position of the gate layer metal and increasing the number of vias between the SD layer and the common electrode layer or lengthening the via length, the touch resistance is also reduced, the connection between the two is guaranteed, and the touch effect is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A schematic diagram of via connection of a low-temperature polysilicon display panel in the prior art;

[0027] Figure 2 A schematic diagram of via connection when a low-temperature polysilicon display panel in the prior art has a first deviation;

[0028] Figure 3 A schematic diagram of via connection when a low-temperature polysilicon display panel in the prior art has a second deviation;

[0029] Figure 4 This is a cross-sectional diagram of via connection of the low-temperature polysilicon display panel embodiment 1 of the present utility model;

[0030] Figure 5 This is an overall schematic diagram of via connection of the low-temperature polysilicon display panel embodiment 1 of the present utility model;

[0031] Figure 6It is an enlarged schematic diagram of the via connection part of the low-temperature polysilicon display panel embodiment 1 of the present utility model;

[0032] Figure 7 This is a schematic diagram of via connection of a low-temperature polysilicon display panel embodiment 2 of the present utility model;

[0033] Figure 8 This is a schematic diagram of via connection in Example 3 of the low-temperature polysilicon display panel of the utility model. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the utility model to clearly and completely describe the technical solution in the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the utility model.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0036] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0037] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0038] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0039] The existing low-temperature polysilicon display panel has poor via connection effect, increased touch resistance, and ultimately poor touch effect.

[0040] In view of the above problems, a low-temperature polysilicon display panel and a display device are proposed.

[0041] First, as Figure 4 , Figure 4 The schematic cross-sectional view of the via connection of the low-temperature polysilicon display panel embodiment 1 of the utility model; a low-temperature polysilicon display panel, comprising a common electrode layer 100, an SD layer 300, a first insulating layer 200, a second insulating layer 400, a gate layer 700 and a glass substrate 500; the first insulating layer 200 is arranged between the common electrode layer 100 and the SD layer 300; the second insulating layer 400 is arranged between the gate layer 700 and the SD layer 300; the flat position of the SD layer 300 and the common electrode layer 100 is connected through at least one via hole. The glass substrate 500 is arranged at the bottom of the gate layer 700 in a laminated manner.

[0042] The SD layer 300 is connected to the common electrode layer 100 via 600 only at the climbing position. The number of vias 600 is small, the via resistance is large, and if the vias 600 have deviations due to the process, the via connection between the SD layer 300 and the common electrode layer 100 cannot be guaranteed, thereby deteriorating the touch effect.

[0043] Furthermore, the common electrode layer 100 is disconnected at the metal climbing position of the gate layer 700 to be divided into a plurality of flat touch blocks. Disconnecting the common electrode layer 100 at the metal climbing position of the gate layer 700 can reduce the coupling effect between the common electrode layer 100 and the gate layer 700.

[0044] Furthermore, the SD layer 300 is connected to the touch block through a first via hole 800 , and the length of the first via hole 800 is greater than half of the width of the touch block.

[0045] Preferably, the length of the first via hole 800 is equal to the width of the touch block. Figure 5 and Figure 6 , Figure 5 This is an overall schematic diagram of the via connection of the low-temperature polysilicon display panel embodiment 1 of the present utility model, Figure 6 It is an enlarged schematic diagram of the via connection part of the low-temperature polysilicon display panel embodiment 1 of the present invention.

[0046] The first via hole 800 basically runs through the entire height of the pixel, thereby improving the via hole connection effect. Even if there is a via hole alignment difference during the process, there will not be a large via hole connection difference.

[0047] By disconnecting the common electrode layer 100 at the climbing position of the gate layer 700 metal and lengthening the via length, the touch resistance is reduced, the connection between the two is guaranteed, and the touch effect is improved.

[0048] like Figure 7 , Figure 7 Schematic diagram of via connection of embodiment 2 of the low-temperature polysilicon display panel of the present invention; different from embodiment 1, in this embodiment, the SD layer 300 is connected to the touch block through a plurality of second vias 900.

[0049] Preferably, the number of the second via holes 900 is 3, and the SD layer 300 is respectively connected to the first end, the middle part and the second end via holes of the common electrode layer 100 through the second via holes 900. By disconnecting the common electrode layer 100 at the climbing position of the gate layer 700 metal and increasing the number of via holes between the SD layer 300 and the common electrode layer 100, the touch resistance is also reduced, the connection between the two is guaranteed, and the touch effect is improved.

[0050] In this embodiment, if Figure 8 , Figure 8 This is a schematic diagram of via connection of the low-temperature polysilicon display panel embodiment 3 of the utility model. The SD layer 300 is connected to the common electrode layer 100 through vias at the climbing position and the flat touch block position, and the SD layer 300 is connected to the common electrode layer 100 through a third via 910 at the climbing position of the gate layer 700 metal. By connecting the SD layer 300 to the common electrode layer 100 through vias at the climbing position and the flat position of the gate layer 700 metal, the number of vias is increased and the via resistance is reduced.

[0051] In a second aspect, a display device comprises the low-temperature polysilicon display panel of the first aspect.

[0052] The low-temperature polysilicon display panel and display device of the present invention are implemented by connecting the SD layer 300 and the common electrode layer 100 through vias at the climbing position and the flat position of the gate layer 700 metal, thereby increasing the number of vias and reducing the via resistance. On the other hand, by disconnecting the common electrode layer 100 at the climbing position of the gate layer 700 metal and increasing the number of vias between the SD layer 300 and the common electrode layer 100 or lengthening the via length, the touch resistance is also reduced, the connection between the two is guaranteed, and the touch effect is improved.

[0053] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A low-temperature polysilicon display panel, comprising: A common electrode layer; SD layer; a first insulating layer; a second insulating layer; Gate layer; The first insulating layer is disposed between the common electrode layer and the SD layer; The second insulating layer is disposed between the gate layer and the SD layer; The SD layer is connected to a flat position of the common electrode layer through at least one via hole.

2. The low-temperature polysilicon display panel according to claim 1, characterized in that: The common electrode layer is disconnected at the metal climbing position of the gate layer and is divided into a plurality of flat touch blocks.

3. The low-temperature polysilicon display panel according to claim 2, characterized in that: The SD layer is connected to the touch block through a first via hole, and the length of the first via hole is greater than half of the width of the touch block.

4. The low-temperature polysilicon display panel according to claim 3, characterized in that: The length of the first via hole is equal to the width of the touch block.

5. The low-temperature polysilicon display panel according to claim 2, characterized in that: The SD layer is connected to the touch block through a plurality of second via holes.

6. The low-temperature polysilicon display panel according to claim 5, characterized in that: The number of the second via holes is 3, and the SD layer is connected to the first end, the middle portion, and the second end via holes of the touch block respectively through the second via holes.

7. The low-temperature polysilicon display panel according to claim 1, characterized in that: The SD layer is connected to the common electrode layer via hole through a third via hole at the climbing position of the gate layer metal.

8. The low-temperature polysilicon display panel according to any one of claims 1 to 7, characterized in that: The display panel also includes a glass substrate, which is bonded to the bottom of the gate layer.

9. A display device comprising the low-temperature polysilicon display panel according to claim 8.

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