Band-gap reference voltage source with high power supply rejection ratio and low offset

Abstract

The utility model discloses a band-gap reference voltage source with high power supply rejection ratio and low offset. The reference voltage source comprises a band-gap core circuit and a pre-voltage-stabilizing circuit. The band-gap core circuit can generate a reference voltage VBG with high precision and low temperature coefficient; the pre-voltage-stabilizing circuit is used for increasing the power supply rejection ratio (PSRR) of the reference voltage VBG. The output reference voltage VBG has the advantages of high power supply rejection ratio, low temperature coefficient, low imbalance, high precision and the like, and is particularly suitable for a high-precision linear Hall sensor.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor integrated circuits, in particular to a high power supply rejection ratio and low offset bandgap reference voltage source. Background Art

[0002] In the field of integrated circuits, bandgap reference voltage sources are important components of various types of circuits such as analog-to-digital converters (ADCs), low-dropout linear regulators (LDOs), and sensors. They are designed to provide a high-precision reference voltage that does not change with temperature. With the advancement and development of technology, the integration of chips has increased, and performance requirements have become increasingly higher. Therefore, high-performance bandgap reference voltage sources have become more important. In high-precision linear Hall sensors, the reference voltage source needs to have high precision, high power supply rejection ratio, and low power consumption, so that the reference voltage source has as little impact on the sensor accuracy as possible. Utility Model Content

[0003] The utility model provides a high power supply rejection ratio and low offset bandgap reference voltage source, which adopts high-order temperature compensation technology to obtain a lower temperature coefficient, adopts an offset suppression architecture to reduce the impact of operational amplifier offset, and adopts a pre-regulator architecture to improve the power supply rejection ratio (PSRR) of the bandgap reference voltage source. Specifically, the utility model includes a bandgap core circuit and a pre-regulator circuit. The bandgap core circuit can generate a high-precision, low temperature coefficient reference voltage V BG ; The pre-regulator circuit is used to reduce the power supply voltage V DD The impact of fluctuations is reduced, and the PSRR of the circuit is improved; the high-order compensation circuit is combined with the bandgap core circuit, and no additional circuit is required for compensation, which reduces the power consumption of the circuit and the temperature coefficient of the reference voltage.

[0004] The bandgap core circuit includes two NPN BJT tubes Q1 and Q2, three PMOS tubes M1, M2 and M3, and six resistors R1, R2, R3, R4, R B And R5. Among them: the sources of M1, M2, and M3 are all connected to the output node V of the pre-regulator circuit DDL , that is, the drain of M4; the gates of M1, M2, and M3, the drain of M1 is connected to the first terminal of R1 and the first terminal of R2; the drain of M2 is connected to the first terminal of R3, R B The first terminal of M3 and the first terminal of R4 are connected; the drain of M3 is connected to the first terminal of R5; the second terminal of R1 and the collector of Q1 are connected to the non-inverting input terminal of the operational amplifier A1; the second terminal of R3, the base of Q1, and the drain of Q2 are connected to the reverse input terminal of the operational amplifier A1; the base of Q2 is connected to R BThe second terminals of R2, the emitter of Q1, the emitter of Q2, the second terminal of R4, and the second terminal of R5 are connected to ground GND.

[0005] The pre-stabilization circuit is composed of an operational amplifier A1 and a PMOS tube M4; the output of the operational amplifier is connected to the gate of M4; the source of M4 is connected to the power supply voltage V DD .

[0006] Preferably, the operational amplifier A1 is a folded cascode amplifier with a PMOS current mirror load.

[0007] Technical features and effects of this utility model:

[0008] The utility model adopts high-order temperature compensation technology to obtain a lower temperature coefficient, adopts an offset suppression architecture to reduce the impact of operational amplifier offset, and adopts a pre-regulatory architecture to improve the power supply rejection ratio of the bandgap reference voltage source. The reference voltage source provided by the utility model outputs a reference voltage of 0.7V in the range of -40°C to 125°C, with a temperature coefficient of 3.5ppm / °C and an accuracy of 0.25%. The PSRR of the output voltage is 91.9dB, and the overall power consumption of the circuit is 11.5uW. The utility model has the characteristics of high power supply rejection ratio, low offset, and high precision, and can be applied to high-precision linear Hall sensors. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is the overall circuit diagram of the utility model;

[0010] Figure 2 It is the equivalent circuit diagram of the utility model;

[0011] Figure 3 The utility model describes the reference voltage V BG Simulation results of temperature coefficient;

[0012] Figure 4 The utility model describes the reference voltage V BG Results of offset simulation (a) and temperature coefficient offset simulation (b);

[0013] Figure 5 The simulation results of the PSRR of the utility model are described. DETAILED DESCRIPTION

[0014] The technical solution of the present utility model is described in detail below with reference to the accompanying drawings and embodiments for better understanding.

[0015] The bandgap reference voltage source provided in the embodiment is as follows Figure 1As shown, it includes a bandgap core circuit and a pre-regulator circuit. In order to facilitate the layout and matching of the BJT layout and reduce the actual matching, the ratio of the number of two NPN BJT tubes Q1 and Q2 is set to 8:1.

[0016] Since the voltage at the base of Q1 is V BE1 , the voltage at the base of Q2 is V BE2 , the voltage at point Y is V BE2 +I B R B , so the voltage difference across R3 is ΔV BE +I B R B , the current flowing through R3 can be expressed as The current flowing through R4 can be expressed as The current I flowing through M1, M2, and M3 REF It can be expressed as This current flows through R5 to generate a reference voltage V BG It can be expressed as Since V BE2 There exists a higher-order nonlinear phase in And ΔV EB =V T lnn, can only compensate for the first-order phase; the current flowing into the base of Q2 can be expressed as Where β(T) is the current amplification factor of BJT, which has a positive temperature coefficient and is expressed as Therefore V BG It can be expressed as The simulation results of the temperature coefficient of the reference voltage source are as follows Figure 3 As shown, its temperature coefficient is 3.52ppm / ℃.

[0017] Since the offset voltage generated by the operational amplifier will affect V BG The accuracy of Figure 2 The circuit shown is analyzed. Figure 2 Medium R EQ1 It is the equivalent impedance of node Z, and its expression is The feedback coefficient can be expressed as The offset caused by the operational amplifier has an effect on the Z node: Since the gate and drain of M1 are connected, ΔV Z,OS The gate gain transmitted to M1 is 1, and the fluctuation of M3 source and gate is consistent, V BG,OS is the output resistance r of M3 o3 R5 vs. ΔV Z,OS The partial pressure expression is After suppressing the offset generated by the operational amplifier, the accuracy of the bandgap reference voltage source is greatly improved. The simulation results are as follows: Figure 4 As shown, the accuracy of the reference voltage is 0.25%, the average temperature coefficient is 6.899ppm / ℃, and the 1sigma error of the temperature coefficient is 3.21.

[0018] In order to increase the reference voltage V BG PSRR, a pre-regulator circuit consisting of operational amplifier A1 and M4 is designed. Since the operational amplifier uses a PMOS current mirror load architecture, it has a high sensitivity to the power supply voltage V DD The gain is approximately 1, so the gate and source of M4 tube fluctuate in the same way, V Z The PSRR of the point is the output resistance of M4 and the equivalent impedance of the bandgap core R EQ1 The partial pressure, therefore The bandgap core is also a PMOS current mirror architecture. The power supply fluctuation of the VBG node is affected by the M3 tube and R5. Z,vdd In addition to the voltage division, the branch where M1 is located will also produce a voltage affected by ΔV Z,vdd The current affected by the fluctuation is copied to the branch where M3 is located, so the PSRR of the bandgap reference voltage source can be expressed as The PSRR simulation results are as follows: Figure 5 As shown in the figure, at low frequency, its PSRR is -91.86dB, while at high frequency, the PSRR is as low as -38.26dB, that is, in the whole frequency band, the designed bandgap reference voltage source has a good power supply rejection ratio.

Claims

1. A bandgap reference voltage source with high power supply rejection ratio and low offset, comprising a pre-regulator circuit and a bandgap core circuit, characterized in that: The pre-stabilization circuit is composed of an operational amplifier A1 and a PMOS tube M4; the output of the operational amplifier is connected to the gate of M4; the source of M4 is connected to the power supply voltage V DD , the drain of M4 serves as the output node V of the pre-regulator circuit DDL ; The bandgap core circuit includes: NPN BJT tubes Q1 and Q2, PMOS tubes M1, M2 and M3, resistors R1, R2, R3, R4, R5 and R B、 ; The sources of M1, M2, and M3 are all connected to the output node V DDL The gates of M1, M2, and M3, the drain of M1, the first terminal of R1, and the first terminal of R2 are connected to each other; the drain of M2 and the first terminal of R3, R B The first terminal of R1 and the first terminal of R4 are connected to each other; the drain of M3 is connected to the first terminal of R5; the second terminal of R1, the collector of Q1 and the non-inverting input terminal of the operational amplifier A1 are connected to each other; the second terminal of R3, the base of Q1, the collector of Q2 and the reverse input terminal of the operational amplifier A1 are connected to each other; the base of Q2 is connected to R B the second terminal of R2, the emitter of Q1, the emitter of Q2, the second terminal of R4 and the second terminal of R5 are grounded GND.

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