Wideband high power supply rejection ratio bandgap reference circuit

Abstract

This application provides a wideband high power supply rejection ratio (PSRR) bandgap reference circuit. The wideband high PSRR bandgap reference circuit includes: one end of a voltage divider circuit electrically connected to a signal source, and the other end of the voltage divider circuit electrically connected to one end of a first PSRR enhancement circuit; one end of a reference voltage circuit electrically connected to the other end of the first PSRR enhancement circuit, and the other end of the reference voltage circuit electrically connected to one end of a second PSRR enhancement circuit, with the other end of the second PSRR enhancement circuit serving as the output. This method significantly improves the PSRR characteristics of the output voltage at low and medium frequencies, and better achieves a high PSRR characteristic for the output voltage over a wide frequency range.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuits, and more particularly to a wideband bandgap reference circuit with high power supply rejection ratio. Background Technology

[0002] Bandgap reference circuits are fundamental circuits in analog and mixed-signal circuits. Their output reference voltage is independent of power supply voltage and temperature, making them widely used as reference voltages in linear low-dropout regulators, analog-to-digital converters, and other circuits. Power supply rejection ratio (PSRR) is a measure of this independence from power supply voltage; therefore, improving the PSRR of the bandgap reference circuit's output reference voltage is crucial.

[0003] In existing technologies, common bandgap reference circuits have limited loop gain, which prevents the reference voltage's PSRR from being increased sufficiently at low frequencies. Furthermore, their PSRR is difficult to maintain high performance over a wide frequency range. Summary of the Invention

[0004] In view of this, one of the technical problems solved by the embodiments of the present invention is to provide a wideband high power supply rejection ratio bandgap reference circuit to overcome the problem that the common source transistor gate bias circuit resistance is too large in the prior art, which leads to a slow start-up time of the entire circuit.

[0005] In a first aspect, embodiments of this application provide a wideband high power supply rejection ratio (PSRR) bandgap reference circuit, characterized in that it includes: a signal source, a voltage divider circuit, a first PSRR enhancement circuit, a second PSRR enhancement circuit, and a reference voltage circuit; one end of the voltage divider circuit is electrically connected to the signal source, and the other end of the voltage divider circuit is electrically connected to one end of the first PSRR enhancement circuit; one end of the reference voltage circuit is electrically connected to the other end of the first PSRR enhancement circuit, and the other end of the reference voltage circuit is electrically connected to one end of the second PSRR enhancement circuit, with the other end of the second PSRR enhancement circuit serving as an output.

[0006] In another implementation of this application, the voltage divider circuit includes: a first field-effect transistor (FET), a second field-effect transistor (FET), a third field-effect transistor (FET), and a fourth field-effect transistor (FET); the source of the first FET is electrically connected to the signal source, the drain of the first FET is electrically connected to the drain of the second FET, and the source of the second FET is grounded; the source of the third FET is electrically connected to the signal source, the drain of the third FET is electrically connected to the drain of the fourth FET, and the source of the fourth FET is grounded; wherein, the gate of the first FET is electrically connected to the gate of the third FET and is also electrically connected to the drain of the first FET, and the gate of the fourth FET is electrically connected to the drain of the fourth FET and is also electrically connected to the gate of the second FET.

[0007] In another implementation of this application, the first power supply rejection ratio (PSRR) improvement circuit includes: a fifth field-effect transistor (FET), a sixth field-effect transistor (FET), and a seventh field-effect transistor (FET); the source of the fifth FET, the drain of the sixth FET, and the drain of the third FET are electrically connected; the source of the sixth FET and the source of the seventh FET are grounded; the gate of the sixth FET is electrically connected to the drain of the fifth FET and the drain of the seventh FET, respectively, wherein the gate of the seventh FET is electrically connected to the drain of the fourth FET.

[0008] In another implementation of this application, the reference voltage circuit includes an eighth field-effect transistor (FET), a ninth field-effect transistor (FET), a tenth field-effect transistor (FET), an eleventh field-effect transistor (FET), a twelfth field-effect transistor (FET), a first resistor, a second resistor, a first transistor, a second transistor, a third transistor, and an amplifier; the source of the eighth FET is electrically connected to the drain of the third FET, the drain of the eighth FET is electrically connected to the drain of the ninth FET, the source of the ninth FET is electrically connected to one end of the first resistor, the other end of the first resistor is electrically connected to the emitter of the first transistor, and the collector of the first transistor is grounded; the source of the tenth FET is electrically connected to the drain of the third FET and is also electrically connected to the sources of the twelfth FET and the eighth FET, respectively; the drain of the tenth FET is electrically connected to the drain of the eleventh FET and is also electrically connected to the gate of the eleventh FET. The source of the eleventh field-effect transistor is electrically connected to the emitter of the second transistor, and the collector of the second transistor is grounded. The gate of the eighth field-effect transistor is electrically connected to the gate of the tenth field-effect transistor and to the gate of the twelfth field-effect transistor, and is connected between the drain of the eighth field-effect transistor and the drain of the ninth field-effect transistor. The gate of the ninth field-effect transistor is electrically connected to the gate of the eleventh field-effect transistor. The base of the first transistor is electrically connected to the base of the second transistor and grounded. The drain of the twelfth field-effect transistor is electrically connected to one end of the second resistor and the positive input terminal of the amplifier. The other end of the second resistor is electrically connected to the emitter of the third transistor. The collector and base of the third transistor are grounded. The inverting input terminal of the amplifier is electrically connected to the output terminal of the amplifier. The positive input terminal of the amplifier is electrically connected to the gate of the fifth field-effect transistor.

[0009] In another implementation of this application, the second power supply rejection ratio (PSRR) improvement circuit includes a thirteenth field-effect transistor (FET), a fourteenth field-effect transistor (FET), a fifteenth field-effect transistor (FET), a first capacitor, and an output terminal of the second PSRR improvement circuit. The source of the thirteenth FET is electrically connected to the output terminal of the amplifier, and the drain of the thirteenth FET is electrically connected to the drain of the fifteenth FET. The gate and source of the fifteenth FET are grounded. The source of the fourteenth FET is electrically connected to the output terminal of the amplifier, and the drain of the fourteenth FET is electrically connected to one end of the first capacitor, the other end of the first capacitor is grounded. The gate of the thirteenth FET is electrically connected to the gate of the fourteenth FET and also electrically connected to the drain of the thirteenth FET. The drain of the fourteenth FET is electrically connected to the output terminal of the second PSRR improvement circuit.

[0010] In another implementation of this application, the wideband high power supply rejection ratio bandgap reference circuit further includes: a reference voltage fast establishment circuit; the reference voltage fast establishment circuit is electrically connected to the second power supply rejection ratio improvement circuit and is used to provide a fast charging current to the second power supply rejection ratio improvement circuit.

[0011] In another implementation of this application, the reference voltage fast establishment circuit further includes: a sixteenth field-effect transistor (FET), a seventeenth field-effect transistor (FET), an eighteenth field-effect transistor (FET), a nineteenth field-effect transistor (FET), and a second capacitor; the source of the sixteenth FET is electrically connected to the output terminal of the amplifier, the drain of the sixteenth FET is electrically connected to the drain of the fourteenth FET, and the source of the seventeenth FET is electrically connected to the drain of the third FET; the drain of the seventeenth FET is electrically connected to the gate of the sixteenth FET and one end of the second capacitor, respectively, and the other end of the second capacitor is grounded; the source of the eighteenth FET is electrically connected to the drain of the third FET, the drain of the eighteenth FET is electrically connected to the drain of the nineteenth FET, and the source of the nineteenth FET is grounded; wherein the gate of the seventeenth FET and the gate of the eighteenth FET are electrically connected and electrically connected to the drain of the eighteenth FET, and the gate of the nineteenth FET is electrically connected to the gate of the fifteenth FET.

[0012] In another implementation of this application, the voltage divider circuit further includes: a twentieth field-effect transistor and a twenty-first field-effect transistor; the first power supply rejection ratio (PSRR) improvement circuit further includes a twenty-second field-effect transistor; the drain of the twentieth field-effect transistor is electrically connected to the source of the second field-effect transistor, and the source of the twentieth field-effect transistor is grounded; the drain of the twenty-first field-effect transistor is electrically connected to the source of the fourth field-effect transistor, and the source of the twenty-first field-effect transistor is grounded; the drain of the twenty-second field-effect transistor is electrically connected to the source of the seventh field-effect transistor, and the source of the twenty-second field-effect transistor is grounded; the gate of the twentieth field-effect transistor is electrically connected to the gate of the twenty-first field-effect transistor and electrically connected to the drain of the twenty-first field-effect transistor and the gate of the twenty-second field-effect transistor.

[0013] In another implementation of this application, the voltage divider circuit further includes a 23rd field-effect transistor and a 24th field-effect transistor; the source of the 23rd field-effect transistor is electrically connected to the drain of the 3rd field-effect transistor, the drain of the 23rd field-effect transistor is electrically connected to the source of the 24th field-effect transistor, and the drain of the 24th field-effect transistor is electrically connected to the drain of the 4th field-effect transistor.

[0014] In another implementation of this application, the reference voltage circuit further includes a 25th field-effect transistor, a 26th field-effect transistor, a 27th field-effect transistor, a 28th field-effect transistor, and a 29th field-effect transistor; the source of the 25th field-effect transistor is electrically connected to the drain of the 8th field-effect transistor, the drain of the 25th field-effect transistor is electrically connected to the drain of the 27th field-effect transistor, and the source of the 27th field-effect transistor is electrically connected to the drain of the 9th field-effect transistor; the source of the 26th field-effect transistor is electrically connected to the drain of the 10th field-effect transistor, the drain of the 26th field-effect transistor is electrically connected to the drain of the 28th field-effect transistor, and the source of the 28th field-effect transistor is electrically connected to the 11th field-effect transistor. The drain of the field-effect transistor is electrically connected; the gate of the 27th field-effect transistor is electrically connected to the gate of the 28th field-effect transistor and is also electrically connected to the drain of the 28th field-effect transistor; the source of the 29th field-effect transistor is electrically connected to the drain of the 12th field-effect transistor; the drain of the 29th field-effect transistor is electrically connected to one end of the second resistor and the positive input terminal of the amplifier, respectively; the gate of the 23rd field-effect transistor is electrically connected to the drain of the 8th field-effect transistor; the gate of the 25th field-effect transistor is electrically connected to the gate of the 26th field-effect transistor and is also electrically connected to the drain of the 25th field-effect transistor, the gate of the 24th field-effect transistor, and the gate of the 29th field-effect transistor.

[0015] In another implementation of this application, in the reference voltage circuit, the gate of the eighth field-effect transistor is electrically connected to the drain of the eighth field-effect transistor, and the gates of the ninth and eleventh field-effect transistors are electrically connected to the drain of the eleventh field-effect transistor.

[0016] In another implementation of this application, the reference voltage circuit further includes a 25th field-effect transistor, a 26th field-effect transistor, a 27th field-effect transistor, a 28th field-effect transistor, a 29th field-effect transistor, a third resistor, and a fourth resistor; the source of the 25th field-effect transistor is electrically connected to the drain of the 8th field-effect transistor; the third resistor is connected between the drain of the 25th field-effect transistor and the drain of the 27th field-effect transistor; the source of the 27th field-effect transistor is electrically connected to the drain of the 9th field-effect transistor; the source of the 26th field-effect transistor is electrically connected to the drain of the 10th field-effect transistor; and the fourth resistor is connected between the drain of the 26th field-effect transistor and the drain of the 28th field-effect transistor. The source of the 28th field-effect transistor is electrically connected to the drain of the 11th field-effect transistor; the gate of the 27th field-effect transistor is electrically connected to the gate of the 28th field-effect transistor and is also electrically connected to the drain of the 26th field-effect transistor; the source of the 29th field-effect transistor is electrically connected to the drain of the 12th field-effect transistor; the drain of the 29th field-effect transistor is electrically connected to one end of the second resistor and the positive input terminal of the amplifier; the gate of the 8th field-effect transistor is electrically connected to the drain of the 25th field-effect transistor; the gate of the 25th field-effect transistor is electrically connected to the gate of the 26th field-effect transistor and is also electrically connected to the drain of the 27th field-effect transistor and the gate of the 29th field-effect transistor.

[0017] In another implementation of this application, the second power supply rejection ratio improvement circuit further includes a thirtieth field-effect transistor (FET), and the reference voltage fast setup circuit further includes a thirty-first FET and a thirty-second FET; the drain of the thirtieth FET is electrically connected to the source of the fifteenth FET, the source of the thirtieth FET is grounded, the source of the thirty-first FET is electrically connected to the drain of the seventeenth FET, the gate of the thirty-first FET is electrically connected to the gate of the seventeenth FET, and the drain of the thirty-first FET is electrically connected to the gate of the sixteenth FET and one end of the second capacitor, respectively; the drain of the thirty-second FET is electrically connected to the source of the nineteenth FET, the source of the thirty-second FET is grounded, and the gate of the thirty-second FET is electrically connected to the gate of the nineteenth FET; the gate of the thirtieth FET is electrically connected to the gate of the fifteenth FET and electrically connected to the gate of the thirty-second FET.

[0018] The wideband high power supply rejection ratio (PSRR) bandgap reference circuit provided in this application embodiment has one end of a voltage divider circuit electrically connected to the signal source, and the other end of the voltage divider circuit electrically connected to one end of a first PSRR enhancement circuit; one end of the reference voltage circuit is electrically connected to the other end of the first PSRR enhancement circuit, and the other end of the reference voltage circuit is electrically connected to one end of a second PSRR enhancement circuit, with the other end of the second PSRR enhancement circuit serving as the output. Therefore, this method can significantly improve the PSRR characteristics of the output voltage at low and medium frequencies, and better achieve a high PSRR characteristic of the output voltage over a wide frequency range. Attached Figure Description

[0019] The following sections will describe some specific embodiments of the present application in a detailed manner, by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0020] Figure 1 A structural diagram of a wideband high power supply rejection ratio bandgap reference circuit provided in an embodiment of this application;

[0021] Figure 2 A structural diagram of a wideband high power supply rejection ratio bandgap reference circuit provided in an embodiment of this application;

[0022] Figure 3 A structural diagram of a wideband high power supply rejection ratio bandgap reference circuit provided in an embodiment of this application;

[0023] Figure 4 A structural diagram of a wideband high power supply rejection ratio bandgap reference circuit provided in an embodiment of this application;

[0024] Figure 5 This is a structural diagram of a wideband high power supply rejection ratio bandgap reference circuit provided in an embodiment of this application. Detailed Implementation

[0025] The specific implementation of the embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0026] Figure 1This diagram illustrates a structural diagram of a wideband high power supply rejection ratio (PSRR) bandgap reference circuit according to an embodiment of this application. The wideband high PSRR bandgap reference circuit includes: a signal source, a voltage divider circuit, a first PSRR enhancement circuit, a second PSRR enhancement circuit, and a reference voltage circuit. One end of the voltage divider circuit is electrically connected to the signal source, and the other end of the voltage divider circuit is electrically connected to one end of the first PSRR enhancement circuit. One end of the reference voltage circuit is electrically connected to the other end of the first PSRR enhancement circuit, and the other end of the reference voltage circuit is electrically connected to one end of the second PSRR enhancement circuit. The other end of the second PSRR enhancement circuit serves as an output.

[0027] It should be noted that the reference voltage circuit is used to provide a reference voltage, the first power supply rejection ratio (PSRR) improvement circuit is used to suppress voltage ripple in the low-to-medium frequency range, and the second PSRR improvement circuit is used to suppress voltage ripple in the mid-to-high frequency range.

[0028] It should be noted that the terms "first," "second," "third," and "fourth" in this application are used to distinguish the same type of things in this embodiment, and also to distinguish the same type of things in this embodiment from those in other embodiments, and are not intended to limit the scope. In this embodiment, the presence of "first" does not necessarily imply the presence of "second," and vice versa. In this application, the signal source can output pulse signals or square wave signals; however, this is merely illustrative and does not imply that this application is limited to this. It should be noted that the field-effect transistor here can be replaced with a transistor, such as a MOSFET; again, this is merely illustrative and does not imply that this application is limited to this.

[0029] The wideband high power supply rejection ratio (PSRR) bandgap reference circuit provided in this application embodiment has one end of a voltage divider circuit electrically connected to the signal source, and the other end of the voltage divider circuit electrically connected to one end of a first PSRR enhancement circuit; one end of the reference voltage circuit is electrically connected to the other end of the first PSRR enhancement circuit, and the other end of the reference voltage circuit is electrically connected to one end of a second PSRR enhancement circuit, with the other end of the second PSRR enhancement circuit serving as the output. Therefore, this method can significantly improve the PSRR characteristics of the output voltage at low and medium frequencies, and better achieve a high PSRR characteristic of the output voltage over a wide frequency range.

[0030] In one possible implementation, such as Figure 2As shown, the voltage divider circuit includes: a first field-effect transistor (FET) M1, a second field-effect transistor (FET) M2, a third field-effect transistor (FET) M3, and a fourth field-effect transistor (FET) M4; the source of the first FET M1 is electrically connected to the signal source, the drain of the first FET M1 is electrically connected to the drain of the second FET M2, and the source of the second FET M2 is grounded; the source of the third FET M3 is electrically connected to the signal source, the drain of the third FET M3 is electrically connected to the drain of the fourth FET M4, and the source of the fourth FET M4 is grounded; wherein, the gate of the first FET M1 is electrically connected to the gate of the third FET M3 and is also electrically connected to the drain of the first FET M1, and the gate of the fourth FET M4 is electrically connected to the drain of the fourth FET and is also electrically connected to the gate of the second FET.

[0031] In one possible implementation, such as Figure 2 As shown, the first power supply rejection ratio improvement circuit includes: a fifth field-effect transistor M5, a sixth field-effect transistor M6, and a seventh field-effect transistor M7; the source of the fifth field-effect transistor M5, the drain of the sixth field-effect transistor M6, and the drain of the third field-effect transistor M3 are electrically connected; the source of the sixth field-effect transistor M6 and the source of the seventh field-effect transistor M7 are grounded; the gate of the sixth field-effect transistor M6 is electrically connected to the drain of the fifth field-effect transistor M5 and the drain of the seventh field-effect transistor M7, respectively, wherein the gate of the seventh field-effect transistor M7 is electrically connected to the drain of the fourth field-effect transistor M4.

[0032] It should be noted that the first power supply rejection ratio (PSRR) improvement circuit can employ a super source follower (SSF) structure to enhance the suppression effect of the drain voltage VREG of the third field-effect transistor on the voltage VDD ripple of the mid-to-low frequency signal source. The SSF structure of the first power supply rejection ratio improvement circuit enables the drain voltage VREG of the third field-effect transistor to achieve good mid-to-low frequency PSRR characteristics.

[0033] It should be noted that BG here stands for Bandgap, also known as bandgap reference; PSRR stands for Power Supply Rejection Ratio; SSF stands for Super source follower; and PTAT stands for Proportional To Absolute Temperature.

[0034] In one possible implementation, such as Figure 2As shown, the reference voltage circuit includes an eighth field-effect transistor (FET) M8, a ninth field-effect transistor (FET) M9, a tenth field-effect transistor (FET) M10, an eleventh field-effect transistor (FET) M11, a twelfth field-effect transistor (FET) M12, a first resistor R1, a second resistor R2, a first transistor Q1, a second transistor Q2, a third transistor Q3, and an amplifier. The source of the eighth field-effect transistor (FET) M8 is electrically connected to the drain of the third field-effect transistor (FET) M3, and the drain of the eighth field-effect transistor (FET) M8 is electrically connected to the drain of the ninth field-effect transistor (FET) M9. The source of the ninth field-effect transistor (FET) M9 is electrically connected to one end of the first resistor R1, and the other end of the first resistor R1 is electrically connected to the emitter of the first transistor Q1. The collector of the first transistor Q1 is grounded. The source of the tenth field-effect transistor (FET) M10 is electrically connected to the drain of the third field-effect transistor (FET) M3. The transistors are connected to the source of the twelfth field-effect transistor M12 and the source of the eighth field-effect transistor M8, respectively. The drain of the tenth field-effect transistor M10 is electrically connected to the drain of the eleventh field-effect transistor M11 and to its gate. The source of the eleventh field-effect transistor M11 is electrically connected to the emitter of the second transistor Q2. The collector of the second transistor Q2 is grounded. The gate of the eighth field-effect transistor M8 is electrically connected to the gate of the tenth field-effect transistor M10 and to the gate of the twelfth field-effect transistor M12. The gate of the eighth field-effect transistor M8 is electrically connected to the gate of the tenth field-effect transistor M10 and is also electrically connected between the drain of the eighth field-effect transistor M8 and the drain of the ninth field-effect transistor M9, for example, the drain of the eighth field-effect transistor M8. The gate of the ninth field-effect transistor M9 is electrically connected to the gate of the eleventh field-effect transistor M11. The base of the first transistor Q1 is electrically connected to the base of the second transistor and grounded. The drain of the twelfth field-effect transistor M12 is electrically connected to one end of the second resistor R2 and the positive input terminal of the amplifier. The other end of the second resistor R2 is electrically connected to the emitter of the third transistor Q3. The collector and base of the third transistor are grounded. The inverting input terminal of the amplifier is electrically connected to the output terminal of the amplifier. The positive input terminal of the amplifier is electrically connected to the gate of the fifth field-effect transistor.

[0035] It should be noted that the reference voltage circuit uses VREG as the power supply and adopts a classic cascaded current mirror structure. It generates a reference voltage VBG that does not change with the power supply voltage and temperature by superimposing positive and negative temperature coefficient voltages. This is the drain voltage VBG of the twelfth field-effect transistor.

[0036] In one possible implementation, such as Figure 2As shown, the second power supply rejection ratio (PSRR) improvement circuit includes a thirteenth field-effect transistor (FET) M13, a fourteenth field-effect transistor (FET) M14, a fifteenth field-effect transistor (FET) M15, a first capacitor C1, and a second PSRR improvement circuit output terminal VREF. The source of the thirteenth FET M13 is electrically connected to the output terminal of the amplifier, and the drain of the thirteenth FET M13 is electrically connected to the drain of the fifteenth FET M15. The gate and source of the fifteenth FET M15 are grounded. The source of the fourteenth FET M14 is electrically connected to the output terminal of the amplifier, and the drain of the fourteenth FET M14 is electrically connected to one end of the first capacitor C1. The other end of the first capacitor C1 is grounded. The gate of the thirteenth FET M13 is electrically connected to the gate of the fourteenth FET M14 and is also electrically connected to the drain of the thirteenth FET M13. The fourteenth FET M14 is electrically connected to the output terminal of the second PSRR improvement circuit.

[0037] It should be noted that the second power supply rejection ratio (PSRR) improvement circuit uses VBG as its power source. It primarily enhances the suppression of power supply voltage ripple in the mid-to-high frequency range by using the first filter capacitor C1 to improve the output voltage VREF (i.e., the reference voltage VREF, also known as the output voltage). The reference voltage fast-setup circuit provides a fast charging current during VREF setup, accelerating VREF establishment, and then exits after VREF setup is complete. By adjusting the value of the filter capacitor C1, the reference voltage VREF achieves a high PSRR characteristic in the mid-to-high frequency range.

[0038] In one possible implementation, the wideband high power supply rejection ratio bandgap reference circuit further includes: a reference voltage fast establishment circuit; the reference voltage fast establishment circuit is electrically connected to the second power supply rejection ratio improvement circuit and is used to provide a fast charging current to the second power supply rejection ratio improvement circuit.

[0039] In one possible implementation, such as Figure 3As shown, the reference voltage fast establishment circuit further includes: a sixteenth field-effect transistor M16, a seventeenth field-effect transistor M17, an eighteenth field-effect transistor M18, a nineteenth field-effect transistor M19, and a second capacitor C2; the source of the sixteenth field-effect transistor M16 is electrically connected to the output terminal of the amplifier, the drain of the sixteenth field-effect transistor M16 is electrically connected to the drain of the fourteenth field-effect transistor M14, the source of the seventeenth field-effect transistor M17 is electrically connected to the drain of the third field-effect transistor M3, and the drain of the seventeenth field-effect transistor M17 is connected to the source of the sixteenth field-effect transistor M16. The gate of the transistor is electrically connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded. The source of the eighteenth field-effect transistor M18 is electrically connected to the drain of the third field-effect transistor M3, the drain of the eighteenth field-effect transistor M18 is electrically connected to the drain of the nineteenth field-effect transistor, and the source of the nineteenth field-effect transistor is grounded. The gate of the seventeenth field-effect transistor M17 is electrically connected to the gate of the eighteenth field-effect transistor M18 and is also electrically connected to the drain of the eighteenth field-effect transistor M18. The gate of the nineteenth field-effect transistor is electrically connected to the gate of the fifteenth field-effect transistor M15.

[0040] It should be noted that the first and second power supply rejection ratio (PSRR) enhancement circuits enable the output voltage VREF to have a high PSRR over a wide frequency range. The super source follower structure of the first PSRR enhancement circuit provides VREG with extremely low impedance to ground, thus enabling VREG to achieve extremely high mid-to-low frequency PSRR. In this case, VREG can be regarded as a pre-regulated power supply, powering the reference voltage circuit. The reference voltage circuit clamps the voltages at points a and b to be equal through a cascaded current mirror structure, generating a PTAT current. This current flows through resistor R2 via the current mirror copy, generating a positive temperature coefficient voltage. This voltage is superimposed on the third transistor VBE3, which has a negative temperature coefficient, to generate a zero-temperature voltage VBG. To improve the load-driving capability of VBG, VBG needs to be output through a unity negative feedback buffer composed of amplifiers. The improvement of PSRR in the mid-to-high frequency band is mainly achieved by the first capacitor C1. C1 is charged through the slow charging path M14 and the fast charging path M16, which enables the reference voltage VREF to be established quickly. After VREF is established, M16 is turned off and the fast charging path is exited, which can meet the requirements of fast start-up and low power consumption.

[0041] It should be noted that, in order to improve the PSRR characteristics in the mid-frequency band, the value of the first capacitor C1 here will be relatively large. Therefore, the reference voltage VREF can be quickly established by the reference voltage establishment circuit to meet the startup time requirements. At the same time, the static power consumption of the overall circuit is not affected by the timely shutdown after establishment.

[0042] In one possible implementation, the voltage divider circuit further includes a twentieth field-effect transistor (FET) M20 and a twenty-first field-effect transistor (FET) M21, and the first power supply rejection ratio (PSRR) improvement circuit further includes a twenty-second field-effect transistor (FET) M22. The drain of the twentieth FET M20 is electrically connected to the source of the second FET M2, and the source of the twentieth FET M20 is grounded. The drain of the twenty-first FET M21 is electrically connected to the source of the fourth FET M4, and the source of the twenty-first FET M21 is grounded. The drain of the twenty-second FET M22 is electrically connected to the source of the seventh FET M7, and the source of the twenty-second FET M22 is grounded. The gate of the twentieth FET M20 is electrically connected to the gate of the twenty-first FET M21 and is also electrically connected to the drain of the twenty-first FET M21 and the gate of the twenty-second FET M22.

[0043] In one possible implementation, such as Figure 4 As shown, the voltage divider circuit also includes a 23rd field-effect transistor M23 and a 24th field-effect transistor M24; the source of the 23rd field-effect transistor is electrically connected to the drain of the 3rd field-effect transistor M3, the drain of the 23rd field-effect transistor is electrically connected to the source of the 24th field-effect transistor, and the drain of the 24th field-effect transistor is electrically connected to the drain of the 4th field-effect transistor M4.

[0044] Furthermore, the reference voltage circuit also includes a 25th field-effect transistor (FET) M25, a 26th field-effect transistor (FET) M26, a 27th field-effect transistor (FET) M27, a 28th field-effect transistor (FET) M28, and a 29th field-effect transistor (FET) M29. The source of the 25th FET is electrically connected to the drain of the 8th FET M8; the drain of the 25th FET is electrically connected to the drain of the 27th FET; the source of the 27th FET is electrically connected to the drain of the 9th FET M9; the source of the 26th FET is electrically connected to the drain of the 10th FET M10; the drain of the 26th FET is electrically connected to the drain of the 28th FET; the source of the 28th FET is electrically connected to the drain of the 11th FET M11; and the gate of the 27th FET is electrically connected to the gate of the 28th FET M28 and is also electrically connected to the 29th FET M29. The drain of the eighth field-effect transistor M28; the source of the twenty-ninth field-effect transistor M29 is electrically connected to the drain of the twelfth field-effect transistor M12, and the drain of the twenty-ninth field-effect transistor M29 is electrically connected to one end of the second resistor R2 and the positive input terminal of the amplifier; the gate of the twenty-third field-effect transistor M23 is electrically connected to the gate of the eighth field-effect transistor M8 and the gate of the tenth field-effect transistor M10; the gate of the twenty-fifth field-effect transistor M25 is electrically connected to the gate of the twenty-sixth field-effect transistor M26 and is electrically connected to the drain of the twenty-fifth field-effect transistor M25, the gate of the twenty-fourth field-effect transistor M24, and the gate of the twenty-ninth field-effect transistor M29.

[0045] It should be understood that, as an example, such as Figure 4 As shown, the gate of the eighth field-effect transistor M8 is connected to the drain of the eighth field-effect transistor M8, and the gates of the ninth field-effect transistor M9 and the eleventh field-effect transistor M11 are electrically connected to the drain of the eleventh field-effect transistor M11. It should also be understood that, in this example, the drain of the twenty-fifth field-effect transistor M25 is connected to the drain of the twenty-seventh field-effect transistor M27, and the drain of the twenty-sixth field-effect transistor M26 is connected to the drain of the twenty-eighth field-effect transistor M28.

[0046] Alternatively, as another example, such as Figure 5As shown, the reference voltage circuit also includes a 25th field-effect transistor (FET) M25, a 26th field-effect transistor (FET) M26, a 27th field-effect transistor (FET) M27, a 28th field-effect transistor (FET) M28, a 29th field-effect transistor (FET) M29, a third resistor R3, and a fourth resistor R4. The source of the 25th field-effect transistor (FET) M25 is electrically connected to the drain of the 8th field-effect transistor (FET) M8. The third resistor R3 is connected between the drain of the 25th field-effect transistor (FET) M25 and the drain of the 27th field-effect transistor (FET) M27. The source of the 27th field-effect transistor (FET) M27 is electrically connected to the drain of the 9th field-effect transistor (FET) M9. The source of the 26th field-effect transistor M26 is electrically connected to the drain of the 10th field-effect transistor M10. The fourth resistor R4 is connected between the drain of the 26th field-effect transistor M26 and the drain of the 28th field-effect transistor M28. The source of the 28th field-effect transistor M28 is electrically connected to the drain of the 11th field-effect transistor M11. The gate of the 27th field-effect transistor M27 is electrically connected to the gate of the 28th field-effect transistor M28 and then to the drain of the 26th field-effect transistor M26. The source of the 29th field-effect transistor M29 is electrically connected to the drain of the 12th field-effect transistor M12. The drain of the 29th field-effect transistor M29 is electrically connected to one end of the second resistor R2 and the positive input terminal of the amplifier. The gate of the 8th field-effect transistor M8 is electrically connected to the drain of the 25th field-effect transistor M25. The gate of the 25th field-effect transistor M25 is electrically connected to the gate of the 26th field-effect transistor M26 and then to the drain of the 27th field-effect transistor M27 and the gate of the 29th field-effect transistor M29.

[0047] In one possible implementation, such as Figure 4 As shown, the second power supply rejection ratio improvement circuit further includes a thirtieth field-effect transistor M30, and the reference voltage fast establishment circuit further includes a thirty-first field-effect transistor M31 and a thirty-second field-effect transistor M32; the drain of the thirtieth field-effect transistor M30 is electrically connected to the source of the fifteenth field-effect transistor M15, the source of the thirtieth field-effect transistor M30 is grounded, the source of the thirty-first field-effect transistor M31 is electrically connected to the drain of the seventeenth field-effect transistor M17, and the gate of the thirty-first field-effect transistor M31 is electrically connected to the gate of the seventeenth field-effect transistor M17. The drain of the thirty-first field-effect transistor M31 is electrically connected to the gate of the sixteenth field-effect transistor M16 and one end of the second capacitor C2, respectively; the drain of the thirty-second field-effect transistor is electrically connected to the source of the nineteenth field-effect transistor M19; the source of the thirty-second field-effect transistor M32 is grounded; the gate of the thirty-second field-effect transistor M32 is electrically connected to the gate of the nineteenth field-effect transistor M19; the gate of the thirtyth field-effect transistor M30 is electrically connected to the gate of the fifteenth field-effect transistor M15 and is also electrically connected to the gate of the thirty-second field-effect transistor M32.

[0048] Specifically, in combination Figure 4The circuit principle of this invention is explained below. In the following formula derivation, gmx represents the small-signal transconductance of MOS transistor Mx, rbsx represents the small-signal drain-source channel resistance of MOS transistor Mx, rbex represents the small-signal transmitter-base resistance of transistor Qx, and VBEx represents the transmitter-base DC voltage difference of transistor Qx.

[0049] The bias voltage of the wideband high power supply rejection ratio bandgap reference circuit is mainly generated by a self-dividing voltage divider circuit. In the first power supply rejection ratio improvement circuit, MOSFETs M5, M6, M7, and M22 form a super source follower structure, which can significantly reduce V. REG The impedance to ground, its impedance req to ground, can be expressed as:

[0050] Therefore V REG The rejection ratio to the power supply voltage VDD can be expressed as:

[0051]

[0052] From equation (2), we can see that V REG It has extremely high mid-to-low frequency PSRR, and its PSRR can be increased by increasing parameters such as the transconductance of M5 and M6.

[0053] The reference voltage circuit uses V REG For power supply, reference voltage V BG The expression is:

[0054]

[0055]

[0056]

[0057] From equation (5), it can be seen that, according to V BE negative temperature characteristics and V T The positive temperature characteristic can be obtained by appropriately adjusting the values ​​of M, N, and R2 / R1 to obtain a reference voltage V with zero temperature characteristics. BG .

[0058] V BG For V REG The inhibition ratio can be expressed as:

[0059]

[0060] From equation (6), it can be seen that the M12 and M29 pipes in the sleeve-type cascade are V BG It provides extremely high mid-to-low frequency PSRR.

[0061] In addition, to improve V BGThe load-carrying capacity, generating V BG The output is fed to subsequent circuits via a unity negative feedback buffer formed by the amplifier. The gain of the amplifier is denoted by Av, V. BG To V BG_buffer The small-signal gain can be expressed as:

[0062]

[0063] In the second power supply rejection ratio improvement circuit, to reduce the overall circuit power consumption, M15 and M30 are used to generate a small quiescent current, which is copied from M14 to form a slow charging branch to charge the first capacitor C1. However, the small slow charging current cannot meet the reference voltage V. REF The need for rapid setup necessitates the introduction of a reference voltage fast setup circuit. Similarly, M19 and M32 generate a smaller quiescent current, which is copied by M17 and M31 to charge the second capacitor C2. The upper plate of C2 is initially at a low level, at which point transistor M16 conducts, forming a fast charging path, enabling the reference voltage to be set. REF Rapid charging is achieved to meet the requirements of rapid startup. As the upper plate of C2 is gradually charged, the M16 transistor will be gradually turned off, the fast charging branch will exit, and no additional static power consumption will be generated. Generally, the rise rate of the upper plate potential of C2 is required to be less than that of C1. Therefore, when C1 = C2, the charging current of C2 must be less than the charging current of C1 to ensure V... REF The rapid establishment of [the system / mechanism].

[0064] After passing through the second power supply rejection ratio enhancement circuit, the reference voltage V REF For V BG_buffer The inhibition ratio is:

[0065]

[0066] According to equation (8), when other parameters are constant, V increases at higher frequencies. REF For V BG_buffer The higher the rejection ratio, the better the PSRR of the reference voltage at mid-to-high frequencies.

[0067] Therefore, the reference voltage V REF For power supply voltage V DD The final PSRR expression is:

[0068]

[0069] As can be seen from equation (10), the reference voltage of the circuit in this application has extremely high mid-to-low frequency PSRR, and can achieve the characteristic of high PSRR of the reference voltage over a wide frequency range.

[0070] Specific embodiments of the subject matter have now been described. Other embodiments are within the scope of the appended claims. In some cases, the actions described in the claims can be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing can be advantageous.

[0071] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0072] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0073] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this application should be included within the scope of the claims of this application.

Claims

1. A bandgap reference circuit with wide frequency band and high power supply rejection ratio, characterized in that include: Signal source, voltage divider circuit, first power supply rejection ratio (PSRR) improvement circuit, second power supply rejection ratio (PSRR) improvement circuit, reference voltage circuit; One end of the voltage divider circuit is electrically connected to the signal source, and the other end of the voltage divider circuit is electrically connected to one end of the first power supply rejection ratio improvement circuit. One end of the reference voltage circuit is electrically connected to the other end of the first power supply rejection ratio (PSRR) improvement circuit, and the other end of the reference voltage circuit is electrically connected to one end of the second power supply rejection ratio (PSRR) improvement circuit. The other end of the second power supply rejection ratio (PSRR) improvement circuit serves as the output. The reference voltage circuit includes an amplifier; The second power supply rejection ratio (PSRR) improvement circuit includes a thirteenth field-effect transistor (FET), a fourteenth field-effect transistor (FET), a fifteenth field-effect transistor (FET), a first capacitor, and the output terminal of the second PSRR improvement circuit. The source of the thirteenth field-effect transistor is electrically connected to the output terminal of the amplifier, the drain of the thirteenth field-effect transistor is electrically connected to the drain of the fifteenth field-effect transistor, and the gate and source of the fifteenth field-effect transistor are grounded. The source of the fourteenth field-effect transistor is electrically connected to the output terminal of the amplifier, the drain of the fourteenth field-effect transistor is electrically connected to one end of the first capacitor, and the other end of the first capacitor is grounded. The gate of the thirteenth field-effect transistor is electrically connected to the gate of the fourteenth field-effect transistor and is also electrically connected to the drain of the thirteenth field-effect transistor. The drain of the fourteenth field-effect transistor is electrically connected to the output terminal of the second power supply rejection ratio improvement circuit. The voltage divider circuit includes: a third field-effect transistor; The wideband high power supply rejection ratio bandgap reference circuit also includes a reference voltage fast establishment circuit, which includes: a sixteenth field-effect transistor, a seventeenth field-effect transistor, an eighteenth field-effect transistor, a nineteenth field-effect transistor, and a second capacitor. The source of the sixteenth field-effect transistor is electrically connected to the output terminal of the amplifier, the drain of the sixteenth field-effect transistor is electrically connected to the drain of the fourteenth field-effect transistor, and the source of the seventeenth field-effect transistor is electrically connected to the drain of the third field-effect transistor. The drain of the seventeenth field-effect transistor is electrically connected to the gate of the sixteenth field-effect transistor and one end of the second capacitor, and the other end of the second capacitor is grounded. The source of the eighteenth field-effect transistor is electrically connected to the drain of the third field-effect transistor, the drain of the eighteenth field-effect transistor is electrically connected to the drain of the nineteenth field-effect transistor, and the source of the nineteenth field-effect transistor is grounded. The gate of the seventeenth field-effect transistor and the gate of the eighteenth field-effect transistor are electrically connected and connected to the drain of the eighteenth field-effect transistor. The gate of the nineteenth field-effect transistor is electrically connected to the gate of the fifteenth field-effect transistor.

2. The bandgap reference circuit with wideband and high power supply rejection ratio according to claim 1, wherein The voltage divider circuit further includes: a first field-effect transistor, a second field-effect transistor, and a fourth field-effect transistor; The source of the first field-effect transistor is electrically connected to the signal source, the drain of the first field-effect transistor is electrically connected to the drain of the second field-effect transistor, and the source of the second field-effect transistor is grounded. The source of the third field-effect transistor is electrically connected to the signal source, the drain of the third field-effect transistor is electrically connected to the drain of the fourth field-effect transistor, and the source of the fourth field-effect transistor is grounded. The gate of the first field-effect transistor is electrically connected to the gate of the third field-effect transistor and is also electrically connected to the drain of the first field-effect transistor. The gate of the fourth field-effect transistor is electrically connected to the drain of the fourth field-effect transistor and is also electrically connected to the gate of the second field-effect transistor.

3. The bandgap reference circuit with wideband and high power supply rejection ratio according to claim 2, characterized in that, The first power supply rejection ratio improvement circuit includes: a fifth field-effect transistor, a sixth field-effect transistor, and a seventh field-effect transistor; The source of the fifth field-effect transistor, the drain of the sixth field-effect transistor, and the drain of the third field-effect transistor are electrically connected; the source of the sixth field-effect transistor and the source of the seventh field-effect transistor are grounded. The gate of the sixth field-effect transistor is electrically connected to the drain of the fifth field-effect transistor and the drain of the seventh field-effect transistor, wherein the gate of the seventh field-effect transistor is electrically connected to the drain of the fourth field-effect transistor.

4. The bandgap reference circuit with wideband and high power supply rejection ratio according to claim 3, characterized in that, The reference voltage circuit includes an eighth field-effect transistor, a ninth field-effect transistor, a tenth field-effect transistor, an eleventh field-effect transistor, a twelfth field-effect transistor, a first resistor, a second resistor, a first transistor, a second transistor, and a third transistor; The source of the eighth field-effect transistor is electrically connected to the drain of the third field-effect transistor, the drain of the eighth field-effect transistor is electrically connected to the drain of the ninth field-effect transistor, the source of the ninth field-effect transistor is electrically connected to one end of the first resistor, the other end of the first resistor is electrically connected to the emitter of the first transistor, and the collector of the first transistor is grounded. The source of the tenth field-effect transistor is electrically connected to the drain of the third field-effect transistor and is also electrically connected to the source of the twelfth field-effect transistor and the source of the eighth field-effect transistor, respectively. The drain of the tenth field-effect transistor is electrically connected to the drain of the eleventh field-effect transistor and is also electrically connected to the gate of the eleventh field-effect transistor. The source of the eleventh field-effect transistor is electrically connected to the emitter of the second transistor. The collector of the second transistor is grounded. The gate of the eighth field-effect transistor is electrically connected to the gate of the tenth field-effect transistor and is also electrically connected to the gate of the twelfth field-effect transistor. Furthermore, the gate of the eighth field-effect transistor is connected between the drain of the eighth field-effect transistor and the drain of the ninth field-effect transistor. The gate of the ninth field-effect transistor is electrically connected to the gate of the eleventh field-effect transistor. The base of the first transistor is electrically connected to the base of the second transistor and is grounded. The drain of the twelfth field-effect transistor is electrically connected to one end of the second resistor and the positive input terminal of the amplifier, respectively. The other end of the second resistor is electrically connected to the emitter of the third transistor. The collector and base of the third transistor are grounded. The inverting input terminal of the amplifier is electrically connected to the output terminal of the amplifier. The positive input terminal of the amplifier is electrically connected to the gate of the fifth field-effect transistor.

5. The bandgap reference circuit with wideband and high power supply rejection ratio according to claim 1, wherein The reference voltage fast establishment circuit is electrically connected to the second power supply rejection ratio (PSRR) improvement circuit and is used to provide a fast charging current to the second PSRR improvement circuit.

6. The bandgap reference circuit with wideband and high power supply rejection ratio according to claim 4, wherein The voltage divider circuit further includes a twentieth field-effect transistor and a twenty-first field-effect transistor, and the first power supply rejection ratio improvement circuit further includes a twenty-second field-effect transistor. The drain of the twentieth field-effect transistor is electrically connected to the source of the twentieth field-effect transistor, and the source of the twentieth field-effect transistor is grounded; The drain of the 21st field-effect transistor is electrically connected to the source of the 4th field-effect transistor, and the source of the 21st field-effect transistor is grounded. The drain of the 22nd field-effect transistor is electrically connected to the source of the 7th field-effect transistor, the source of the 22nd field-effect transistor is grounded, and the gate of the 20th field-effect transistor is electrically connected to the gate of the 21st field-effect transistor and electrically connected to the drain of the 21st field-effect transistor and the gate of the 22nd field-effect transistor.

7. The bandgap reference circuit with wideband high power supply rejection ratio according to claim 6, characterized in that, The voltage divider circuit also includes a twenty-third field-effect transistor and a twenty-fourth field-effect transistor; The source of the 23rd field-effect transistor is electrically connected to the drain of the 3rd field-effect transistor, the drain of the 23rd field-effect transistor is electrically connected to the source of the 24th field-effect transistor, and the drain of the 24th field-effect transistor is electrically connected to the drain of the 4th field-effect transistor.

8. The bandgap reference circuit with broadband high power supply rejection ratio according to claim 7, characterized in that, The reference voltage circuit also includes a 25th field-effect transistor, a 26th field-effect transistor, a 27th field-effect transistor, a 28th field-effect transistor, and a 29th field-effect transistor; The source of the 25th field-effect transistor is electrically connected to the drain of the 8th field-effect transistor, the drain of the 25th field-effect transistor is electrically connected to the drain of the 27th field-effect transistor, and the source of the 27th field-effect transistor is electrically connected to the drain of the 9th field-effect transistor. The source of the 26th field-effect transistor is electrically connected to the drain of the 10th field-effect transistor, the drain of the 26th field-effect transistor is electrically connected to the drain of the 28th field-effect transistor, the source of the 28th field-effect transistor is electrically connected to the drain of the 11th field-effect transistor, and the gate of the 27th field-effect transistor is electrically connected to the gate of the 28th field-effect transistor and electrically connected to the drain of the 28th field-effect transistor. The source of the 29th field-effect transistor is electrically connected to the drain of the 12th field-effect transistor, and the drain of the 29th field-effect transistor is electrically connected to one end of the second resistor and the positive input terminal of the amplifier, respectively. The gate of the 23rd field-effect transistor is electrically connected to the drain of the 8th field-effect transistor, and the gate of the 25th field-effect transistor is electrically connected to the gate of the 26th field-effect transistor and electrically connected to the drain of the 25th field-effect transistor, the gate of the 24th field-effect transistor, and the gate of the 29th field-effect transistor.

9. The bandgap reference circuit with wideband and high power supply rejection ratio according to any one of claims 4, 6 to 8, characterized in that, In the reference voltage circuit, the gate of the eighth field-effect transistor is electrically connected to the drain of the eighth field-effect transistor, and the gates of the ninth and eleventh field-effect transistors are electrically connected to the drain of the eleventh field-effect transistor.

10. The bandgap reference circuit with wideband and high power supply rejection ratio according to any one of claims 4, 6, and 7, wherein The reference voltage circuit also includes a 25th field-effect transistor, a 26th field-effect transistor, a 27th field-effect transistor, a 28th field-effect transistor, a 29th field-effect transistor, a third resistor, and a fourth resistor. The source of the 25th field-effect transistor is electrically connected to the drain of the 8th field-effect transistor, the third resistor is connected between the drain of the 25th field-effect transistor and the drain of the 27th field-effect transistor, and the source of the 27th field-effect transistor is electrically connected to the drain of the 9th field-effect transistor. The source of the 26th field-effect transistor is electrically connected to the drain of the 10th field-effect transistor, the fourth resistor is connected between the drain of the 26th field-effect transistor and the drain of the 28th field-effect transistor, and the source of the 28th field-effect transistor is electrically connected to the drain of the 11th field-effect transistor. The gate of the 27th field-effect transistor is electrically connected to the gate of the 28th field-effect transistor and electrically connected to the drain of the 26th field-effect transistor; The source of the 29th field-effect transistor is electrically connected to the drain of the 12th field-effect transistor, and the drain of the 29th field-effect transistor is electrically connected to one end of the second resistor and the positive input terminal of the amplifier, respectively. The gate of the eighth field-effect transistor is electrically connected to the drain of the twenty-fifth field-effect transistor. The gate of the twenty-fifth field-effect transistor is electrically connected to the gate of the twenty-sixth field-effect transistor and to the drain of the twenty-seventh field-effect transistor and the gate of the twenty-ninth field-effect transistor.

11. The wideband high power supply rejection ratio bandgap reference circuit according to any one of claims 1 to 9, characterized in that, The second power supply rejection ratio improvement circuit also includes a thirtieth field-effect transistor, and the reference voltage fast establishment circuit also includes a thirty-first field-effect transistor and a thirty-second field-effect transistor; The drain of the 30th field-effect transistor is electrically connected to the source of the 15th field-effect transistor, the source of the 30th field-effect transistor is grounded, the source of the 31st field-effect transistor is electrically connected to the drain of the 17th field-effect transistor, the gate of the 31st field-effect transistor is electrically connected to the gate of the 17th field-effect transistor, and the drain of the 31st field-effect transistor is electrically connected to the gate of the 16th field-effect transistor and one end of the second capacitor, respectively. The drain of the 32nd field-effect transistor is electrically connected to the source of the 19th field-effect transistor, the source of the 32nd field-effect transistor is grounded, and the gate of the 32nd field-effect transistor is electrically connected to the gate of the 19th field-effect transistor. The gate of the thirtieth field-effect transistor is electrically connected to the gate of the fifteenth field-effect transistor and is also electrically connected to the gate of the thirty-second field-effect transistor.

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