Display panel and display device

Abstract

The utility model provides a display panel and a display device, and relates to the technical field of display, the display panel comprises a first display area and at least one second display area, and the transmittance of the second display area is greater than that of the first display area; the first display area comprises a plurality of first sub-pixels arranged in an array, and the second display area comprises a plurality of second sub-pixels arranged in an array; the first sub-pixel comprises a first pixel circuit, the second sub-pixel comprises a second pixel circuit, and the transmittance of the second pixel circuit is larger than that of the first pixel circuit. The display panel is suitable for preparing a display device with an under-screen face recognition function and / or an under-screen camera shooting function.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] As living standards gradually improve, people have higher and higher requirements for the performance of display products. At present, improving the screen-to-body ratio has become one of the core themes of mobile phone product innovation. Although the existing solutions for improving the screen-to-body ratio can already place the camera under the display area by externalizing the pixel circuit,

[0003] However, for a type of products with facial recognition functions, since the facial recognition sensor or infrared projector occupies a large space, when the facial recognition sensor or infrared projector is set below the display area, the limitation of the design space can no longer meet the requirements of the layout of the external pixel circuit, which makes it particularly difficult to set the facial recognition sensor or infrared projector below the display area. Utility Model Content

[0004] This application adopts the following technical solutions:

[0005] In a first aspect, an embodiment of the present application provides a display panel, the display panel comprising a first display area and at least one second display area, the transmittance of the second display area is greater than the transmittance of the first display area; the first display area comprises a plurality of first sub-pixels arranged in an array, and the second display area comprises a plurality of second sub-pixels arranged in an array;

[0006] The first sub-pixel includes a first pixel circuit, and the second sub-pixel includes a second pixel circuit, and the transmittance of the second pixel circuit is greater than the transmittance of the first pixel circuit.

[0007] In at least one display panel provided by an embodiment of the present application, the first sub-pixel includes a first light-emitting area and a first non-light-emitting area except the first light-emitting area, and the second sub-pixel includes a second light-emitting area and a second non-light-emitting area except the second light-emitting area;

[0008] The transmittance of the second light-emitting area is greater than or equal to the transmittance of the first light-emitting area, and the transmittance of the second non-light-emitting area is greater than the transmittance of the first non-light-emitting area.

[0009] In at least one display panel provided in an embodiment of the present application, the first pixel circuit and the second pixel circuit each include a first type transistor and a plurality of second type transistors, the first type transistor is a polysilicon transistor, and the second type transistor is an oxide transistor; an orthographic projection of the first type transistor on a substrate of the display panel at least partially falls into a light emitting area, and an orthographic projection of the second type transistor on the substrate at least partially falls into a non-light emitting area;

[0010] The transmittance of the first type transistor is less than or equal to the transmittance of the second type transistor.

[0011] In at least one display panel provided in an embodiment of the present application, the first sub-pixel and the second sub-pixel each include a gate line, a light emitting control signal line, a reset signal line, an initialization signal line, a data signal line, and a first power signal line; the gate line, the light emitting control signal line, and the reset signal line are electrically connected to gates of different second-type transistors, respectively, and the initialization signal line, the data signal line, and the first power signal line are electrically connected to sources or drains of different second-type transistors, respectively;

[0012] The transmittance of at least one of the data signal line and the first power signal line is less than or equal to the transmittance of the gate line, the light emitting control signal line, the reset signal line and the initialization signal line.

[0013] In at least one display panel provided in an embodiment of the present application, the display panel includes:

[0014] a first semiconductor layer on the substrate, the first semiconductor layer comprising an active portion of the first type transistor;

[0015] A first gate layer, located on a side of the first semiconductor layer away from the substrate, comprising a gate of the first type transistor and a first electrode of a storage capacitor;

[0016] A second gate layer, located on a side of the first gate layer away from the substrate, comprising a second electrode of the storage capacitor and at least a portion of the first gate of the second type transistor;

[0017] A second semiconductor layer, located on a side of the second gate layer away from the substrate, including an active portion of each of the second type transistors;

[0018] A third gate layer, located on a side of the second semiconductor layer away from the substrate, including at least a portion of the second gate of the second type transistor;

[0019] A first source-drain conductive layer, located on a side of the third gate layer away from the substrate, comprising a source and a drain of each transistor;

[0020] Among them, the gate line, the light-emitting control signal line, the reset signal line and the initialization signal line are respectively located on at least one layer among the first gate layer, the second gate layer and the third gate layer, and the data signal line and the first power signal line are respectively located on at least one layer among the first source-drain conductive layer and the second source-drain conductive layer.

[0021] In at least one display panel provided by an embodiment of the present application, the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the first display area all include a first sublayer and a second sublayer;

[0022] The material of one of the first sub-layer and the second sub-layer includes a light-transmitting conductive material, and the material of the other sub-layer includes a metal.

[0023] In at least one display panel provided in an embodiment of the present application, the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer are located in the second light-emitting area of ​​the second display area and all include the first sublayer and the second sublayer;

[0024] The first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer and the second source-drain conductive layer located in the second non-luminescent area of ​​the second display area all include a third sublayer, and the material of the third sublayer includes a light-transmitting conductive material.

[0025] In at least one display panel provided by an embodiment of the present application, the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area all include a fourth sublayer;

[0026] Parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second non-luminescent area of ​​the second display area all include a third sublayer;

[0027] Wherein, the materials of the third sub-layer and the fourth sub-layer both include light-transmitting conductive materials.

[0028] In at least one display panel provided by an embodiment of the present application, the first gate layer, the second gate layer, and the third gate layer located in the first display area all include a first sublayer and a second sublayer; a material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and a material of the other includes a metal; and portions of the first source-drain conductive layer and the second source-drain conductive layer located in the first display area both include a metal;

[0029] The first gate layer, the second gate layer, and the third gate layer located in the second non-luminescent area of ​​the second display area all include light-transmitting conductive materials; the first source-drain conductive layer and the second source-drain conductive layer located in the second non-luminescent area of ​​the second display area all include metals;

[0030] The first source-drain conductive layer and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area both include metal.

[0031] In at least one display panel provided in the embodiments of the present application, the first gate layer, the second gate layer, and the portion of the third gate layer located in the second light-emitting area of ​​the second display area all include a first sublayer and a second sublayer; the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes a metal.

[0032] In at least one display panel provided by an embodiment of the present application, portions of the first gate layer, the second gate layer, and the third gate layer located in the second light-emitting area of ​​the second display area all include metal.

[0033] In at least one display panel provided by an embodiment of the present application, portions of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the first display area all include metal.

[0034] In at least one display panel provided by an embodiment of the present application, portions of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second display area all include light-transmitting conductive materials.

[0035] In at least one display panel provided by an embodiment of the present application, the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second non-luminescent area of ​​the second display area include a light-transmitting conductive material;

[0036] Parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area include metal; or, parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area include a first sublayer and a second sublayer, and the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes metal.

[0037] In at least one display panel provided in an embodiment of the present application, the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area all include metal;

[0038] The first gate layer, the second gate layer and the third gate layer located in the second non-luminous area of ​​the second display area all include light-transmitting conductive materials, and the first source-drain conductive layer and the second source-drain conductive layer located in the second non-luminous area of ​​the second display area all include metals.

[0039] In at least one display panel provided in an embodiment of the present application, the display panel further includes a passivation layer and a first planarization layer located between the first source-drain conductive layer and the second source-drain conductive layer and sequentially arranged in a direction away from the substrate, and a light-transmitting conductive layer located between the passivation layer and the first planarization layer;

[0040] Partial line segments of the data signal line and partial line segments of the first power signal line are arranged on the light-transmitting conductive layer.

[0041] In at least one display panel provided by an embodiment of the present application, when the materials of the first gate layer, the second gate layer and the third gate layer include light-transmitting conductive materials, the portions of the first gate layer, the second gate layer and the third gate layer used as gates of transistors include a light-transmitting sublayer and a light-shielding sublayer, and the light-shielding sublayer is located on a side of the light-transmitting sublayer away from the active portion of the transistor.

[0042] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel as described in any one of the first aspects.

[0043] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1A A schematic diagram of a cross-sectional structure of a display panel in the related art provided by an embodiment of the present application;

[0046] Figure 1B and Figure 1C The diagrams respectively illustrate the characteristics of low-temperature polysilicon transistors and oxide transistors;

[0047] Figure 2A (1) Figure, Figure 2A Middle (2) Figure, Figure 2B (1) Figure and Figure 2B Figure (2) is a schematic diagram of a top view of four display panels provided in an embodiment of the present application;

[0048] Figure 3 An illustrative diagram of an arrangement of pixel circuits in a first display area and a second display area of ​​a display panel provided in an embodiment of the present application;

[0049] Figure 4A to Figure 11 Schematic diagrams of cross-sectional structures of ten display panels provided in the embodiments of the present application;

[0050] Fig.12 A simplified structural diagram of a gate position of a transistor in a display panel provided in an embodiment of the present application;

[0051] Figure 13 to Figure 16 Structural schematic diagrams of four pixel circuits provided in embodiments of the present application;

[0052] Fig.17 and Fig.18 Two simplified schematic diagrams of circuit distribution in the peripheral area of ​​the display panel are provided for the embodiments of the present application;

[0053] Figure 19 to Figure 23B Schematic diagram of intermediate structures during the preparation process of seven display panels provided in the embodiments of the present application. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0055] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0056] In the embodiments of the present application, words such as "first" and "second" are used to indicate parts of identical or similar items having substantially the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application and shall not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0057] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0058] In this specification, "electrically connected" and "coupled" include the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0059] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0060] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0061] The "same layer" in the embodiments of the present application refers to the relationship between multiple film layers formed by the same material after the same step (e.g., a one-step patterning process). The "same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same. The polygons in this specification are not strictly defined, and can be approximate triangles, parallelograms, trapezoids, pentagons or hexagons, etc., and there may be some small deformations caused by tolerances.

[0062] In the embodiment of the present application, since the source and drain of the transistor are symmetrical, the source and drain can be interchanged. In the embodiment of the present application, one of the source and drain of the transistor can also be called the first electrode, and the other of the source and drain can be called the second electrode.

[0063] Figure 1A A schematic cross-sectional structure diagram of a display panel in a related art is provided. Figure 1A It can be seen that a pixel circuit is arranged in the display area of ​​the display panel. Since the overall transmittance of the wiring between the pixel circuits is very low, it is impossible to arrange sensors (such as ambient light sensors, distance sensors, sensors for face recognition), cameras and other devices below the display area. For this reason, for smaller sensors, the related technology adopts the method of relocating the pixel circuit in the display area above the sensor (for example, externalizing the pixel circuit in the area corresponding to the sensor to the display area outside the area corresponding to the sensor) to improve the transmittance of the area corresponding to the sensor, thereby increasing the screen-to-body ratio of the display product, and improving the aesthetics and user experience of the display product.

[0064] However, for a type of products with face recognition function, since the space occupied by the face recognition sensor or infrared projector is large, when the face recognition sensor or infrared projector is set below the display area, the limitation of the design space can no longer meet the arrangement of the external pixel circuit, and it is difficult to reduce the transmittance of the local area of ​​the display area corresponding to the face recognition sensor or infrared projector, which makes it particularly difficult to set the face recognition sensor or infrared projector below the display area.

[0065] Based on this, an embodiment of the present application provides a display panel and a display device, wherein the display panel includes a first display area and at least one second display area, the transmittance of the second display area is greater than the transmittance of the first display area; the first display area includes a plurality of first sub-pixels arranged in an array, and the second display area includes a plurality of second sub-pixels arranged in an array; the first sub-pixel includes a first pixel circuit, and the second sub-pixel includes a second pixel circuit, the circuit structures of the first pixel circuit and the second pixel circuit are the same, and the transmittance of the second pixel circuit is greater than the transmittance of the first pixel circuit.

[0066] Among them, by also setting a second pixel circuit in the second sub-pixel of the second display area, the circuit structures of the first pixel circuit and the second pixel circuit are set to be the same, and the transmittance of the second pixel circuit is greater than the transmittance of the first pixel circuit. In this way, sensors (such as ambient light sensors, distance sensors, sensors for face recognition), cameras and other devices can be set in the area below the second display area in the display panel, thereby realizing the preparation of a display device with a high screen-to-body ratio.

[0067] Below, the display panel and the display device provided in the embodiments of the present application will be specifically described and introduced in conjunction with the accompanying drawings.

[0068] The embodiment of the present application provides a display panel, such as Figure 2A Figure (1) and Figure (2) Figure 2B As shown in Figures (1) and (2), the display panel includes a first display area AA1 and at least one second display area AA2, and the transmittance of the second display area AA2 is greater than the transmittance of the first display area AA1; Figure 3 As shown, the first display area AA1 includes a plurality of first sub-pixels P1 arranged in an array, and the second display area AA2 includes a plurality of second sub-pixels P2 arranged in an array;

[0069] The first sub-pixel P1 includes a first pixel circuit, and the second sub-pixel P2 includes a second pixel circuit, wherein the transmittance of the second pixel circuit is greater than the transmittance of the first pixel circuit.

[0070] Exemplarily, the structures of the equivalent circuits of the first pixel circuit and the second pixel circuit are the same (in Figure 3 are marked as Pixel Circuit in the figure).

[0071] This does not limit the shape of the plane figure of the above-mentioned second display area AA2. For example, the shape of the plane figure of the above-mentioned second display area AA2 may include a polygon, an arc, or a combination of a polygon and an arc, wherein the combination of a polygon and an arc refers to a figure of a spliced ​​shape of a polygon and an arc, or a figure formed by removing a local area on a polygon or an arc.

[0072] In some embodiments, the first display area AA1 may surround the second display area AA2; in other embodiments, the first display area AA1 may partially surround the second display area AA2, that is, a portion of the outer contour of the second display area AA2 serves as the outer contour of the display area.

[0073] The display area AA includes a first display area AA1 and a second display area AA2 , and both the first display area AA1 and the second display area AA2 can emit display light.

[0074] The first display area AA1 includes a first pixel unit, and the second display area AA2 includes a second pixel unit, wherein the display colors of the first pixel unit and the second pixel unit are the same.

[0075] The display colors of the above-mentioned multiple sub-pixels are not limited here.

[0076] In some embodiments, the display colors of each sub-pixel in the above-mentioned display panel are the same; in some embodiments, the above-mentioned display panel simultaneously includes multiple sub-pixels that display different colors, for example, simultaneously including red sub-pixels, green sub-pixels and blue sub-pixels; that is, multiple first sub-pixels P1 simultaneously include red sub-pixels, green sub-pixels and blue sub-pixels, and multiple second sub-pixels P2 simultaneously include red sub-pixels, green sub-pixels and blue sub-pixels.

[0077] In some embodiments, the number of the second sub-pixels is less than the number of the first sub-pixels.

[0078] In an exemplary embodiment, the display panel may be an organic light emitting diode (OLED) display panel, wherein each sub-pixel includes a light emitting device, and the light emitting device may include an OLED light emitting device.

[0079] The light emitting device Q includes a light emitting functional layer 21 and an anode 18 and a cathode 22 located on both sides of the light emitting functional layer 21 .

[0080] In an exemplary embodiment, the light emitting colors of all light emitting devices are the same, for example, all light emitting devices emit blue light; for another example, all light emitting devices emit white light; in this case, when used for display, a color conversion layer needs to be set on the light emitting side of the light emitting device, for example, a color filter (Color Filter) can be set on the light emitting side of the light emitting device, such as a red filter, a green filter and a blue filter; for another example, different color quantum dot layers (QD Film) can be set on the light emitting side of the light emitting device, such as a red quantum dot layer, a green quantum dot layer and a white resin layer, the blue light emitted by the light emitting functional layer passes through the red quantum dot layer and then emits red light, the blue light emitted by the light emitting functional layer passes through the green quantum dot layer and then emits green light, and the blue light emitted by the light emitting functional layer passes through the white resin layer and then emits blue light, thereby realizing a color display.

[0081] In an exemplary embodiment, the display panel includes a plurality of light emitting devices with different light emitting colors, for example, a red light emitting device, a green light emitting device and a blue light emitting device.

[0082] The first sub-pixel P1 includes a first pixel circuit, the second sub-pixel P2 includes a second pixel circuit, and the circuit structures of the first pixel circuit and the second pixel circuit are the same (in Figure 3 Both are marked as Pixel Circuit), and the first pixel circuit and the second pixel circuit are collectively referred to as pixel circuits here.

[0083] The specific circuit structure of the above-mentioned pixel circuit is not limited here. For example, the pixel circuit may include two transistors and one capacitor (2T1C); or, the pixel circuit may include four transistors and two capacitors (4T2C); or, the pixel circuit may include five transistors and two capacitors (5T2C); or, the pixel circuit may include six transistors and two capacitors (6T1C); or, the pixel circuit may include seven transistors and one capacitor (7T1C); or, the pixel circuit may include eight transistors and one capacitor (8T1C). The embodiments of the pixel circuit in the present application are not limited thereto. In other embodiments, the pixel circuit may also include more transistors, more capacitors, or other devices.

[0084] In addition, the type of transistor in the above pixel circuit is not limited here. Exemplarily, the transistor may include an N-type transistor; or, the transistor may include a P-type transistor; or, the transistor may include both an N-type transistor and a P-type transistor.

[0085] Wherein, in the case where the circuit structures of the first pixel circuit and the second pixel circuit are the same, the transmittance of the second pixel circuit is greater than the transmittance of the first pixel circuit, which can be achieved by at least one of the following methods:

[0086] First, by setting the transmittance of the material of the wiring and the material of the device in the second pixel circuit, the transmittance of at least a part of the material of the wiring and the material of the device in the second pixel circuit is greater than the transmittance of the material of the wiring and the material of the device in the first pixel circuit.

[0087] Second, by setting the thickness and line width of the routing in the second pixel circuit, the routing in the second pixel circuit has a higher transmittance while maintaining the same electrical properties as the routing in the first pixel circuit; for example, the thickness of the routing in the second pixel circuit is less than the thickness of the routing in the first pixel circuit, and the line width of the routing in the second pixel circuit is greater than or equal to the line width of the routing in the first pixel circuit; generally, the smaller the thickness of the film layer, the higher the transmittance;

[0088] Among them, the increase in resistivity caused by the reduction in wiring thickness can be balanced by selecting conductive materials with different resistivities.

[0089] Third, by setting the planar dimensions of the devices in the second pixel circuit so that while the second pixel circuit and the first pixel circuit maintain the same electrical properties, the planar dimensions of at least one device in the second pixel circuit are smaller than the planar dimensions of the corresponding device in the first pixel circuit, wherein the difference in electrical properties caused by the difference in planar dimensions can be compensated and balanced by the dimensions in the substrate direction perpendicular to the display panel.

[0090] In an exemplary embodiment, the transmittance of the routing lines in the second pixel circuit is greater than or equal to the transmittance of each routing line in the first pixel circuit. The routing lines may include signal lines (such as data signal lines, reset signal lines, light emission control signal lines, etc.) and connecting lines (such as connecting lines between two transistors, etc.).

[0091] It should be noted that the “transmittance” in this specification includes the transmittance of visible light and / or the transmittance of infrared light.

[0092] In the display panel provided by the embodiment of the present application, the display panel includes a first display area AA1 and at least one second display area AA2, the first display area AA1 includes a plurality of first sub-pixels P1 arranged in an array, and the second display area AA2 includes a plurality of second sub-pixels P2 arranged in an array; the first sub-pixel P1 includes a first pixel circuit, the second sub-pixel P2 includes a second pixel circuit, and the circuit structures of the first pixel circuit and the second pixel circuit are the same (in Figure 3In this way, by embedding the second pixel circuit in the second display area AA2 and setting the transmittance of the second pixel circuit to be greater than the transmittance of the first pixel circuit, it is possible to set sensors (such as ambient light sensors, distance sensors, sensors for face recognition, fingerprint sensors, etc.), cameras and other devices in the area below the second display area AA2 in the display panel, thereby realizing the preparation of a display device with a high screen-to-body ratio, and also facilitating the preparation of a display device with a high PPI (Pixels Per Inch, image resolution, also called pixel density).

[0093] In at least one display panel provided in an embodiment of the present application, Figure 4A , Fig. 6A and Figure 8 As shown, the first sub-pixel P1 includes a first light-emitting area KK1 and a first non-light-emitting area FKK1 except the first light-emitting area KK1. Figure 4B , Figure 5 , Figure 6B , Figure 7 , Figures 9 to 11 As shown, the second subpixel P2 includes a second light-emitting area KK2 and a second non-light-emitting area FKK2 except the second light-emitting area KK2; wherein the transmittance of the second light-emitting area KK2 is greater than or equal to the transmittance of the first light-emitting area KK1, and the transmittance of the second non-light-emitting area FKK2 is greater than the transmittance of the first non-light-emitting area FKK1.

[0094] In this specification, the meanings of the luminous area and the non-luminous area are as follows: the luminous area refers to the area in the sub-pixel that cannot emit display light (including the area where circuits and wiring are set).

[0095] In practical applications, Figure 4B For example, the area of ​​the light-emitting region is consistent with the area occupied by the pixel opening in the pixel definition layer 19, the light-emitting functional layer 21 is arranged in the pixel opening, and the area of ​​the anode 18 is usually larger than the area of ​​the pixel opening.

[0096] In addition, in some embodiments, in combination Figure 4A and Figure 4BAs shown, the transmittance of the overlapped portion of the anode 18 electrically connected to the second pixel circuit is greater than or equal to the transmittance of the overlapped portion of the anode 18 electrically connected to the first pixel circuit; the transmittance of the non-overlapped region of the anode 18 electrically connected to the second pixel circuit is greater than the transmittance of the non-overlapped region of the anode 18 electrically connected to the first pixel circuit. That is, the overall transmittance of the structure below the anode 18 in the second display area AA2 is greater than or equal to the overall transmittance of the structure below the anode 18 in the first display area AA1; the overall transmittance of the structure outside the anode 18 in the second display area AA2 is greater than the overall transmittance of the structure outside the anode 18 in the first display area AA1.

[0097] In practical applications, in order to improve the transmittance of the second display area AA2 and take into account the display effect of the display panel, it is prioritized to ensure that the transmittance in the second light-emitting area KK2 remains as unchanged as possible, and the purpose of improving the transmittance of the second display area AA2 is achieved by adjusting the part of the second pixel circuit located in the second non-light-emitting area FKK2 as much as possible.

[0098] It should be noted that in actual applications, the area where display light is actually emitted in the same sub-pixel is less than or equal to the planar area where the anode 18 is located, and the area where the anode 18 is in direct contact with the light-emitting functional layer 21 of the light-emitting device Q is the area where display light is actually emitted in the sub-pixel.

[0099] In an exemplary embodiment, the transmittance of the second light-emitting area KK2 is greater than the transmittance of the first light-emitting area KK1, and the transmittance of the second non-light-emitting area FKK2 is greater than the transmittance of the first non-light-emitting area FKK1;

[0100] In an exemplary embodiment, the transmittance of the second light emitting area KK2 is equal to the transmittance of the first light emitting area KK1 , and the transmittance of the second non-light emitting area FKK2 is greater than the transmittance of the first non-light emitting area FKK1 .

[0101] In an embodiment of the present application, by setting the transmittance of the second light-emitting area KK2 to be greater than or equal to the transmittance of the first light-emitting area KK1, and the transmittance of the second non-light-emitting area FKK2 to be greater than the transmittance of the first non-light-emitting area FKK1, it is possible to ensure the consistency of the display picture effects in the first display area AA1 and the second display area AA2 as much as possible while improving the transmittance of the second display area AA2. While taking into account the display picture effects of different areas of the display panel, sensors (such as ambient light sensors, distance sensors, sensors for face recognition), cameras and other devices can be set in the area below the second display area AA2 in the display panel, thereby realizing the preparation of a display device with a high screen-to-body ratio, and is also conducive to the preparation of a high PPI (Pixels Per Inch, image resolution, also called pixel density) display device.

[0102] In at least one display panel provided in an embodiment of the present application, Figure 13 to Figure 16 As shown, the first pixel circuit and the second pixel circuit each include a first type transistor (eg, transistor T3) and a plurality of second type transistors ( Figure 13 to Figure 16 In the circuit diagram shown, except for the transistor T3, the first type transistor is a polysilicon transistor, and the second type transistor is an oxide transistor; the orthographic projection of the first type transistor on the substrate 1 of the display panel at least partially falls into the light-emitting area (KK1 or KK2), and the orthographic projection of the second type transistor on the substrate 1 at least partially falls into the non-light-emitting area (FKK1 or FKK2); wherein the transmittance of the first type transistor is less than or equal to the transmittance of the second type transistor.

[0103] In an exemplary embodiment, the first type transistor may be a driving transistor, and the second transistor may be at least one of a light emission control transistor, a reset transistor, and an initialization transistor.

[0104] In an exemplary embodiment, the polysilicon type transistor may include a low temperature polysilicon type transistor (LTPS, Low Temperature Poly-silicon); the oxide type transistor may include a metal oxide type transistor (MOS, Metal-Oxide-Semiconductor).

[0105] Figure 1B and Figure 1C The transistor characteristics of polysilicon transistors and oxide transistors are illustrated in the figure. Compared with polysilicon transistors, oxide transistors have better light transmittance. In addition, for infrared light, the source-drain current of polysilicon transistors changes greatly under infrared light, and the transistor characteristics are unstable; while the source-drain current of oxide transistors changes little under infrared light, and the transistor characteristics are stable. Oxide transistors have poor stability under visible light.

[0106] Based on the difference in stability between polysilicon transistors (such as low-temperature polysilicon transistors) and oxide transistors to visible light and infrared light, low-temperature polysilicon transistors are more sensitive to infrared light. When an infrared sensor for face recognition is set below the second display area AA2, the orthographic projection of the first type of transistor on the substrate 1 of the display panel is set to at least partially fall into the light-emitting area (KK1 or KK2). The anode 18 in the light-emitting area usually has a low transmittance. Providing a shading structure 2 on the side of the first type of transistor away from the anode 18 will hardly reduce the transmittance of the light-emitting area, and will have little effect on the overall transmittance of the second display area AA2. In this way, the anode 18 can block light above the first type of transistor, and the shading structure 2 can block light below the first type of transistor. In this way, the orthographic projection of the first type of transistor on the substrate 1 of the display panel is set to at least partially fall into the light-emitting area, which can avoid the first type of transistor from being irradiated with light as much as possible, thereby preventing the characteristics of the low-temperature polysilicon transistor from being shifted.

[0107] Herein, at least partially falling within means that part of the area falls within or the entire area falls within.

[0108] In an embodiment of the present application, the first type transistor is set to be a polysilicon transistor, and the second type transistor is set to be an oxide transistor; the orthographic projection of the first type transistor on the substrate 1 of the display panel at least partially falls into the light-emitting area (KK1 or KK2), and the orthographic projection of the second type transistor on the substrate 1 at least partially falls into the non-light-emitting area (FKK1 or FKK2); wherein the transmittance of the first type transistor is less than or equal to the transmittance of the second type transistor, so that the transmittance of the second display area AA2 in the display panel can be increased as much as possible while ensuring the consistency of the display picture effects in the first display area AA1 and the second display area AA2 as much as possible, and taking into account the display picture effects in different areas of the display panel, so that the transmittance of the second display area AA2 in the display panel can be improved as much as possible, so that a sensor or a camera and other devices can be set in the area below the second display area AA2, thereby realizing the preparation of a display device with a high screen-to-body ratio, and is also conducive to the preparation of a high PPI (Pixels Per Inch, image resolution, also called pixel density) display device.

[0109] In at least one display panel provided in an embodiment of the present application, Figure 13 to Figure 16As shown, the first sub-pixel and the second sub-pixel both include a gate line (also called a scan line Scan), a light emitting control signal line EM, a reset signal line Reset, an initialization signal line Vinit, a data signal line Data, and a first power signal line VDD or ELVDD; the gate line Scan, the light emitting control signal line EM, and the reset signal line Reset are electrically connected to the gates of different second-type transistors, respectively, and the initialization signal line Vinit, the data signal line Data, and the first power signal line VDD or ELVDD are electrically connected to the sources or drains of different second-type transistors, respectively;

[0110] The transmittance of at least one of the data signal line Data and the first power signal line VDD or ELVDD is less than or equal to the transmittance of the gate line Scan, the light control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0111] In an exemplary embodiment, the transmittance of the data signal line Data is less than or equal to the transmittance of the gate line Scan, the emission control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0112] In an exemplary embodiment, the transmittance of the first power signal line VDD or ELVDD is less than or equal to the transmittance of the gate line Scan, the emission control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0113] In an exemplary embodiment, the transmittances of the data signal line Data and the first power signal line VDD or ELVDD are less than or equal to the transmittances of the gate line Scan, the emission control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0114] In an exemplary embodiment, the first power signal line VDD or ELVDD refers to a positive voltage signal line. Typically, the pixel circuit also includes a negative voltage signal line, such as a VSS or ELVSS signal line, which is electrically connected to the cathode 22 of the light-emitting device Q.

[0115] In addition, in practical applications, when the impedance of the data signal line Data and the first power signal line VDD or ELVDD is large, it is very easy to have a large signal difference in different areas of the display panel, resulting in uneven brightness of the display screen, so the conductivity requirement is relatively high, so the data signal line Data and the first power signal line VDD or ELVDD can be set to be usually metal materials, such as titanium aluminum titanium Ti / Al / Ti, copper (Cu), etc. with high conductivity, while the impedance of the gate line Scan, the light control signal line EM, the reset signal line Reset, and the initialization signal line Vinit has a small negative impact on the display effect of the display panel, so at least part of the light-transmitting conductive material can be used. In this way, the transmittance has the following rule: the transmittance of the data signal line Data and the first power signal line VDD or ELVDD is less than or equal to the transmittance of the gate line Scan, the light control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0116] In at least one display panel provided in an embodiment of the present application, Figure 4A , Fig. 6A and Figure 8 As shown, or Figure 4B , Figure 5 , Figure 6B , Figure 7 , Figures 9 to 11 The display panel shown includes:

[0117] A first semiconductor layer 4, a first gate insulating layer 5, a first gate layer 6 (including 6A, 6B and 6C), a second gate insulating layer 7, a second gate layer 8 (including 8A, 8B and 8C), a third gate insulating layer 9, a second semiconductor layer 10, a fourth gate insulating layer 11, a third gate layer 12 (including 12A and 12B), an interlayer dielectric layer 13, a first source-drain conductive layer 14 (including at least 14A, 14B and 14C), a passivation layer 28, a first planar layer 15, a second source-drain conductive layer 16 (including 16A and 16B), a second planar layer 17 and an anode layer 18 are sequentially arranged on the substrate 1;

[0118] The first semiconductor layer 4 includes an active portion of a first type transistor, the first gate layer 6 includes a gate 6C of the first type transistor and a first electrode 6B of a storage capacitor Cst, the second gate layer 8 includes a second electrode 8B of the storage capacitor Cst and at least part of the first gate 8C of the second type transistor, the second semiconductor layer 10 includes an active portion of each second type transistor, the third gate layer 12 includes at least part of the second gate 12B of the second type transistor, and the first source-drain conductive layer 14 includes a source and a drain of each transistor;

[0119] The gate line Scan, the light emitting control signal line EM, the reset signal line Reset, and the initialization signal line Vinit are respectively located on at least one layer among the first gate layer 6, the second gate layer 8, and the third gate layer 12, and the data signal line Data and the first power signal line VDD or ELVDD are respectively located on at least one layer among the first source-drain conductive layer 14 and the second source-drain conductive layer 16.

[0120] In an exemplary embodiment, some of the second type transistors are dual-gate transistors and may include a first gate 8C and a second gate 12B.

[0121] In some embodiments, the conductive structure 6A in the first gate layer 6 may be one of the gate line Scan, the light emitting control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0122] In some embodiments, the conductive structure 8A in the second gate layer 8 may be one of the gate line Scan, the light emitting control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0123] In an exemplary embodiment, the conductive structure 12A in the third gate layer 12 may be one of the gate line Scan, the light emitting control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0124] In at least one display panel provided in an embodiment of the present application, Figure 4A As shown, the first gate layer 6, the second gate layer 8 and the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the first display area AA1 all include a first sublayer and a second sublayer (in order to avoid clarity caused by too many labels in the drawings, the first sublayer and the second sublayer are drawn in the drawings but not labeled); wherein the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes a metal.

[0125] In an exemplary embodiment, the portion of any one of the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14, and the second source-drain conductive layer 16 located in the first display area AA1 includes a first sublayer and a second sublayer. The first sublayer (e.g., a light-transmitting conductive material) is located on a side of the second sublayer (e.g., a metal) away from the substrate 1 (i.e., the first sublayer is arranged away from the substrate); or, Figure 4A As shown, the second sublayer (eg metal) is located on a side of the first sublayer (eg light-transmitting conductive material) away from the substrate 1 (ie, the second sublayer is arranged away from the substrate).

[0126] Exemplarily, the light-transmitting conductive material includes, but is not limited to, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0127] Exemplarily, the light-transmitting conductive material may also include graphene, PEDOT [polymer of EDOT (3,4-ethylenedioxythiophene monomer)], metal grid, carbon nanotube, carbon nanorod (carbon nanobud), silver nanowire (SNW, silver nanowire), etc.

[0128] Exemplarily, the metal may include any one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), nickel (Ni) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb).

[0129] In at least one display panel provided in an embodiment of the present application, Figure 5 As shown, the first gate layer 6, the second gate layer 8 and the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 are located in the second light-emitting area KK2 of the second display area AA2 and include the first sublayer and the second sublayer; the first gate layer 6, the second gate layer 8 and the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 are located in the second non-light-emitting area FKK2 of the second display area AA2 and include the third sublayer, and the material of the third sublayer includes a light-transmitting conductive material.

[0130] In at least one display panel provided in an embodiment of the present application, Figure 4B As shown, the first gate layer 6, the second gate layer 8 and the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 are located in the second light-emitting area KK2 of the second display area AA2, and the fourth sublayer ( Figure 4B The first gate layer 6, the second gate layer 8 and the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 are located in the second non-luminous area FKK2 of the second display area AA2, and the third sublayer ( Figure 4B Not marked in the figure); wherein the materials of the third sublayer and the fourth sublayer both include light-transmitting conductive materials.

[0131] Exemplarily, the light-transmitting conductive material includes, but is not limited to, metal oxides, such as indium tin oxide and indium zinc oxide.

[0132] Exemplarily, the light-transmitting conductive material may also include graphene, PEDOT [polymer of EDOT (3,4-ethylenedioxythiophene monomer)], metal grid, carbon nanotube, carbon nanorod (carbon nanobud), silver nanowire (SNW, silver nanowire), etc.

[0133] There is no limitation on whether the materials of the third sub-layer and the fourth sub-layer are the same, which can be determined based on product design and preparation process.

[0134] In at least one display panel provided in an embodiment of the present application, Fig. 6A As shown, the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the first display area AA1 all include a first sublayer and a second sublayer; the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes a metal; the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the first display area AA1 both include a metal; Figure 7 As shown, the first gate layer 6, the second gate layer 8 and the third gate layer 12 are located in the second non-luminous area FKK2 of the second display area AA2, and the portion thereof includes a light-transmitting conductive material; the first source-drain conductive layer 14 and the second source-drain conductive layer 16 are located in the second non-luminous area FKK2 of the second display area AA2, and the portion thereof includes a metal; Figure 7 As shown, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 both include metal in the portion located in the second light emitting area KK2 of the second display area AA2.

[0135] In at least one display panel provided in an embodiment of the present application, Figure 7 As shown, the first gate layer 6 , the second gate layer 8 and the third gate layer 12 are all located in the second light emitting area KK2 of the second display area AA2 and include metal.

[0136] In at least one display panel provided in an embodiment of the present application, based on Figure 7 In the structure shown, the film layers of the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second light-emitting area KK2 of the second display area AA2 are adjusted, and the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second light-emitting area KK2 of the second display area AA2 can also be arranged to include a first sublayer and a second sublayer; the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes a metal.

[0137] In at least one display panel provided in an embodiment of the present application, Figure 8 As shown, the first gate layer 6 , the second gate layer 8 , the third gate layer 12 , the first source-drain conductive layer 14 , and the second source-drain conductive layer 16 located in the first display area AA1 all include metal.

[0138] In at least one display panel provided in an embodiment of the present application, Figure 4B As shown, the first gate layer 6 , the second gate layer 8 , the third gate layer 12 , the first source-drain conductive layer 14 , and the second source-drain conductive layer 16 located in the second display area AA2 all include light-transmitting conductive materials.

[0139] In the display panel provided in the embodiment of the present application, the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 are located in the first display area AA1, and the parts thereof include metal, and the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 are located in the second display area AA2, and the parts include light-transmitting conductive material, so that the overall transmittance of the second display area AA2 of the display panel is improved as much as possible, which is beneficial to improve the light transmittance of the sensor or camera when the sensor or camera and other devices are set in the area below the second display area AA2, thereby realizing the preparation of a display device with a high screen-to-body ratio, and is also beneficial to the preparation of a display device with a high PPI (Pixels Per Inch, image resolution, also called pixel density).

[0140] In at least one display panel provided in an embodiment of the present application, Fig. 9 As shown, the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the second non-luminous area FKK2 of the second display area AA2 include a light-transmitting conductive material; the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the second luminous area KK2 of the second display area AA2 include a metal.

[0141] Alternatively, the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14, and the second source-drain conductive layer 16 located in the second non-luminous area FKK2 of the second display area AA2 include a light-transmitting conductive material; the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14, and the second source-drain conductive layer 16 located in the second luminous area KK2 of the second display area AA2 include a first sublayer and a second sublayer, and the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes a metal.

[0142] In at least one display panel provided in an embodiment of the present application, Fig.11 As shown, the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the second light-emitting area KK2 of the second display area AA2 all include metal; the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second non-light-emitting area FKK2 of the second display area AA2 all include light-transmitting conductive material, and the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the second non-light-emitting area FKK2 of the second display area AA2 all include metal.

[0143] In at least one display panel provided in an embodiment of the present application, Figure 6Band Fig.10 As shown, the display panel also includes a light-transmitting conductive layer 27 (including 27A, 27B and 27C) located between the passivation layer 28 and the first flat layer 15; partial line segments of the data signal line Data and partial line segments of the first power signal line ELVDD or VDD are arranged on the light-transmitting conductive layer 27.

[0144] Exemplarily, the material of the light-transmitting conductive layer 27 includes, but is not limited to, metal oxides, such as indium tin oxide and indium zinc oxide.

[0145] Exemplarily, the material of the light-transmitting conductive layer 27 may also include graphene, PEDOT [polymer of EDOT (3,4-ethylenedioxythiophene monomer)], metal grid, carbon nanotube, carbon nanorod (carbon nanobud), silver nanowire (SNW, silver nanowire), etc.

[0146] Exemplarily, the light-transmitting conductive layer 27 may further include other wirings and leads, such as a conductive structure 27C for connecting the drain and the anode 18 of the second type transistor, and a wiring 27B for connecting the first type transistor and the second type transistor.

[0147] Exemplarily, a partial line segment of the first power signal line ELVDD or VDD disposed on the light-transmitting conductive layer 27 is the conductive structure 27A.

[0148] In at least one display panel provided in an embodiment of the present application, Fig.12 As shown, in the case where the materials of the first gate layer 6, the second gate layer 8 and the third gate layer 12 include light-transmitting conductive materials, the portions of the first gate layer 6, the second gate layer 8 and the third gate layer 12 used as the gate Gate of the transistor include a light-transmitting sublayer TG and a light-shielding sublayer ZG, and the light-shielding sublayer ZG is located on the side of the light-transmitting sublayer TG away from the active portion of the transistor.

[0149] In an exemplary embodiment, when the transistor is a dual-gate transistor, the two gates Gate of the transistor can be set to include a light-transmitting sublayer TG and a light-shielding sublayer ZG. The light-shielding sublayer ZG in the gate Gate close to the substrate 1 can be used to block the light emitted by the infrared projector below, and the light-shielding sublayer ZG in the gate Gate close to the light-emitting functional layer 21 can be used to block the light emitted by the light-emitting functional layer 21 or ambient light.

[0150] In an exemplary embodiment, the material of the light-shielding sublayer ZG in the gate Gate may include an organic light-shielding material, such as a black resin; or, the material of the light-shielding sublayer ZG in the gate Gate may include a metal or a metal compound, such as titanium nitride (TiNx), etc., wherein the metal can not only block light, but also increase the resistivity of the gate Gate, improve the electrical properties of the transistor, and prevent hydrogen elements in other film layers from diffusing into the channel of the transistor during the preparation process.

[0151] It should be noted that the display panel provided in the embodiment of the present application also includes a support portion 20 arranged on the pixel definition layer 19, and the support portion 20 is used to support the mask plate in the evaporation process (BP process) to prevent scratches between the mask plate and the film layer on the display panel; in some embodiments, the display panel also includes an encapsulation layer 29, a touch layer 23, an anti-reflection layer 24 (used to reduce reflectivity, which may include multiple sub-layers), an adhesive layer 25 and a cover plate 26.

[0152] Of course, the display panel may also include other structures and components. This specification only introduces structures and components related to the utility model. For other structures and components included in the display panel, reference may be made to the introduction in the relevant technology.

[0153] An embodiment of the present application provides a display device, comprising the display panel as described above.

[0154] The specific structure of the display panel can be referred to in the previous description and will not be repeated here.

[0155] The display device provided in the embodiments of the present application may be an OLED display device, wherein the OLED display device may include a glass-based OLED display device and a silicon-based OLED display device.

[0156] In addition, the display device may be a display device such as an OLED display, as well as any product or component with a display function such as a television, a digital camera, a mobile phone, a tablet computer, etc. that includes these display devices.

[0157] An embodiment of the present application provides a method for preparing a display panel as described above, wherein the method comprises:

[0158] S1, forming Fig. 20A and Fig. 20B The first gate layer 6 shown (including 6A, 6B and 6C);

[0159] S2. Formation Fig. 20A and Fig. 20B The second gate layer 8 shown (including 8A, 8B and 8C);

[0160] S3, forming Fig.23A and Fig. 23B The third gate layer 12 shown; the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the first display area AA1 and the second light-emitting area KK2 located in the second display area AA2 all include stacked light-transmitting sub-layers and metal sub-layers, and the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second non-light-emitting area FKK2 of the second display area AA2 include light-transmitting sub-layers.

[0161] In at least one method for manufacturing a display panel provided by an embodiment of the present application, S1, forming a third gate layer 12 includes:

[0162] S11, forming a light-transmitting film;

[0163] The light-transmitting film is a light-transmitting material film that is continuous over the entire surface, and is a film layer of the light-transmitting sub-layer before patterning.

[0164] S12, forming a metal thin film;

[0165] The metal thin film is a continuous light-transmitting material film over the entire surface, and is the film layer of the metal sublayer before patterning.

[0166] S13, patterning the light-transmitting film and the metal film to obtain Fig.19 The light-transmitting sublayer and the metal sublayer shown;

[0167] For example, the light-transmitting film and the metal film can be patterned at the same time to obtain Fig.19 As shown in the light-transmitting sub-layer and the metal sub-layer, the same mask plate can be used to pattern the light-transmitting film and the metal film, saving a preparation process step; in addition, by simultaneously patterning the light-transmitting sub-layer and the metal sub-layer, compared with the method of preparing the light-transmitting sub-layer and the metal sub-layer by two patternings, the position deviation of the light-transmitting sub-layer and the metal sub-layer can be effectively reduced, and the position deviation (such as misalignment) of the light-transmitting sub-layer and the metal sub-layer can be avoided, thereby improving the accuracy of the preparation process and avoiding wiring problems (such as short circuit problems, etc.) caused by deviations in the accuracy of the preparation process.

[0168] Among them, Fig.19 In the embodiment, the portion of the third gate layer 12 located in the first display area AA1 and the portion of the third gate layer 12 located in the second display area AA2 have the same structure.

[0169] Fig. 20A and Fig. 20B They are Fig.19 The top view shown corresponds to a schematic diagram of a cross-sectional structure in the first display area AA1 and the second display area AA2.

[0170] In order to obtain a second display area AA2 with high light transmittance, the metal sublayer of the third gate layer 12 in the second display area AA2 is etched away, and only the light-transmitting sublayer is retained. The following is a description of the etching process of the metal sublayer of the third gate layer 12 in the second display area AA2:

[0171] S14, forming a photoresist film PR film, wherein the photoresist film PR film covers the metal sublayer;

[0172] The photoresist film PR film covers the first display area AA1 and the second display area AA2.

[0173] S15, using the first mask to pattern the photoresist film PR film, to obtain Fig.21 The photoresist pattern PR mask shown in FIG. Fig.21 In the embodiment, the photoresist pattern PR mask covers the portion of the metal sublayer located in the first display area AA1 and the portion of the metal sublayer located in the second light emitting area KK2 of the second display area AA2 (it should be noted that in order to avoid Fig.21 It is not clear, the portion of the photoresist pattern PR mask covering the second light-emitting area KK2 of the second display area AA2 is not drawn);

[0174] S16, using the photoresist pattern PR mask as a second mask, etching the portion of the metal sublayer located in the second non-luminous area FKK2 of the second display area AA2 to obtain Fig. 22 The third gate layer 12 is shown.

[0175] in, Fig. 22 is a simplified top view of the third gate layer 12, Fig.23A is a schematic diagram of a cross-sectional structure of the third gate layer 12 in the first display area AA1; Fig. 23B FIG. 1 is a schematic diagram of a cross-sectional structure of the third gate layer 12 in the second display area AA2 .

[0176] In at least one method for preparing a display panel provided in an embodiment of the present application, the method for forming the first gate layer 6, the second gate layer 8 and the third gate layer 12 is the same, and the first mask used to form the first gate layer 6, the second gate layer 8 and the third gate layer 12 is the same mask.

[0177] The first mask is a mask used when patterning the photoresist film PR film. When the first gate layer 6, the second gate layer 8, and the third gate layer 12 located in the first display area AA1 and the second light-emitting area KK2 located in the second display area AA2 all include a stacked transparent sub-layer and a metal sub-layer, and the first gate layer 6, the second gate layer 8, and the third gate layer 12 located in the second non-light-emitting area FKK2 of the second display area AA2 include a transparent sub-layer, the same first mask can be used to pattern the photoresist film PR film to obtain the following: Fig.21 The photoresist pattern PR mask shown covers a portion of the metal sublayer located in the first display area AA1 and a portion of the metal sublayer located in the second light emitting area KK2 of the second display area AA2;

[0178] In the subsequent etching process, the photoresist pattern PR mask protects the portion of the metal sublayer located in the first display area AA1 and the portion of the metal sublayer located in the second light-emitting area KK2 of the second display area AA2, thereby etching away the portion of the metal sublayer of the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second non-light-emitting area FKK2 of the second display area AA2, so that the portion of the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second non-light-emitting area FKK2 of the second display area AA2 includes a light-transmitting sublayer.

[0179] In this way, when preparing the first gate layer 6 , the second gate layer 8 and the third gate layer 12 , the same first mask can be shared, thereby greatly saving the manufacturing cost of the display panel.

[0180] Of course, in some embodiments, the above-mentioned preparation method provided in the embodiments of the present application can also be used to prepare the first source-drain conductive layer 14 and the second source-drain conductive layer 16. When the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the first display area AA1 and the second source-drain conductive layer 16 located in the second light-emitting area KK2 of the second display area AA2 both include a stacked transparent sub-layer and a metal sub-layer, and the first source-drain conductive layer and the second source-drain conductive layer located in the second non-light-emitting area FKK2 of the second display area AA2 include a transparent sub-layer, a similar method as mentioned above can also be used for preparation, so that the same first mask can be used in the preparation of the first source-drain conductive layer 14 and the second source-drain conductive layer 16, thereby further saving the preparation cost of the display panel.

[0181] The preparation process of the above-mentioned display panel may also include other processes and steps. Only the steps related to the utility model are introduced here. For other preparation processes and steps of the display panel, please refer to the introduction in the relevant technology, which will not be repeated here.

[0182] An embodiment of the present application provides a pixel circuit, such as Figure 13 to Figure 16 As shown, the pixel circuit of the nth row includes:

[0183] The driving sub-circuit M1 is electrically connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to conduct the path between the second node N2 and the third node N3 under the control of the voltage of the first node N1, and generate a current in the path for making the light-emitting device Q emit light;

[0184] A first reset sub-circuit M2 is electrically connected to the first node N1, the first reset signal line Reset(n) or Reset1(n) and the first initialization signal line Vinit1, respectively, and is configured to write the first initialization signal transmitted by the first initialization signal line Vinit1 into the first node N1 under the control of the first reset signal transmitted by the first reset signal line Reset(n) or Reset1(n);

[0185] The second reset sub-circuit M3 is electrically connected to the second node N2 and the data signal line Data(m), and is configured to reset the voltage of the second node N2;

[0186] The third reset sub-circuit M4 is electrically connected to the fourth node N4, the anode of the light-emitting device Q and the second initialization signal line Vinit2, respectively, and is configured to write the second initialization signal transmitted by the second initialization signal line Vinit2 into the anode; the fourth node N4 is electrically connected to the anode of the light-emitting device Q;

[0187] The light-emitting control subcircuit M5 is electrically connected to the light-emitting control signal line EM(n), the first power signal line ELVDD or VDD, the second node N2, the third node N3 and the fourth node N4, respectively, and is configured to transmit a current used to make the light-emitting device Q emit light to the anode under the control of the light-emitting control signal transmitted by the light-emitting control signal line EM(n); wherein the anode is electrically connected to the fourth node N4, and the cathode of the light-emitting device is electrically connected to the second power signal line ELVSS or VSS;

[0188] The storage sub-circuit M6 is electrically connected to the first power signal line ELVDD or VDD and the first node N1, respectively, and is configured to store the voltage of the first node N1; wherein m and n are positive integers.

[0189] In an exemplary embodiment, if Figure 13 to Figure 16As shown, the first reset sub-circuit M2 includes a first transistor T1 and a second transistor T2; the gate of the first transistor T1 is electrically connected to the first reset signal line Reset(n) or Reset1(n), and the second electrode of the first transistor T1 is electrically connected to the first initialization signal line Vinit1; the gate of the second transistor T2 is electrically connected to the first scan signal line Scan(n) or Scan1(n), the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3;

[0190] like Fig.13 , Fig.14 As shown, the first electrode of the first transistor T1 is electrically connected to the first node N1; or Fig.15 , Fig.16 As shown, the first electrode of the first transistor T1 is electrically connected to the third node N3.

[0191] In an exemplary embodiment, if Figure 13 to Figure 16 As shown, the second reset sub-circuit M3 includes a fourth transistor T4; a first electrode of the fourth transistor T4 is electrically connected to the second node N2, and a second electrode of the fourth transistor T4 is electrically connected to the data signal line Data(m); wherein, Fig.13 , Fig.14 As shown, the gate of the fourth transistor T4 is electrically connected to the first scan signal line Scan(n) or Scan1(n); or, as shown Fig.15 , Fig.16 As shown, the gate of the fourth transistor T4 is electrically connected to the second scan signal line Scan2(n).

[0192] In an exemplary embodiment, if Fig.14 and Fig.16 As shown, the second reset sub-circuit M3 also includes an eighth transistor T8, a gate of the eighth transistor T8 is electrically connected to the second reset signal line Reset2(n), a first electrode of the eighth transistor T8 is electrically connected to the third initialization signal line Vinit3, and a second electrode of the eighth transistor T8 is electrically connected to the second node N2.

[0193] In an exemplary embodiment, if Figure 13 to Figure 16 As shown, the third reset sub-circuit M4 includes a seventh transistor T7, a first electrode of the seventh transistor T7 is electrically connected to the fourth node N4, and a second electrode of the seventh transistor T7 is electrically connected to the second initialization signal line Vinit2; wherein, Fig.13 As shown, the gate of the seventh transistor T7 is electrically connected to the first scan signal line Scan(n); or, Figure 14 to Figure 16 As shown, the gate of the seventh transistor T7 is electrically connected to the second reset signal line Reset2 (n).

[0194] In an exemplary embodiment, if Figure 13 to Figure 16 As shown, the light emitting control sub-circuit M5 includes a fifth transistor T5 and a sixth transistor T6;

[0195] The gate of the fifth transistor T5 and the gate of the sixth transistor T6 are both electrically connected to the light emitting control signal line EM(n), the first electrode of the fifth transistor T5 is electrically connected to the first power supply signal line ELVDD or VDD, the second electrode of the fifth transistor T5 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.

[0196] In an exemplary embodiment, if Figure 13 to Figure 16 As shown, the driving sub-circuit M1 includes a third transistor T3, a gate of the third transistor T3 is electrically connected to the first node N1, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3;

[0197] The storage sub-circuit M6 includes a storage capacitor Cst, one end of the storage capacitor Cst is electrically connected to the first power signal line ELVDD or VDD, and the other end of the storage capacitor Cst is electrically connected to the first node N1.

[0198] In an exemplary embodiment, if Fig.13 and Fig.15 As shown, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7; Fig.14 and Fig.16 As shown, the pixel circuit further includes an eighth transistor T8. The third transistor T3 is a polysilicon transistor, and the other transistors are oxide transistors.

[0199] In an exemplary embodiment, the third transistor T3 is a P-type transistor, and the other transistors are N-type transistors.

[0200] Among them, Figure 4A to Figure 11 In the embodiment, the transistor located below the anode 21 is a first type transistor (ie, a third transistor, a driving transistor), and the transistor electrically connected to the anode 18 of the light emitting device Q is a sixth transistor T6.

[0201] The above four pixel circuits can be used simultaneously in the first display area AA1 and the second display area AA2 ( Figure 13 to Figure 16 )

[0202] in addition, Fig.17 and Fig.18The schematic diagram of the arrangement of the shift register and the driving chip (IC) in the peripheral area of ​​the display panel is shown, wherein Fig.17 In the embodiment, the display panel includes a group of EM shift registers (EM GOA, EOA), a group of NMOS TFT GOA (N Reset & N Gate), and a group of PMOS TFT GOA (P Gate); Fig.18 Relative to Fig.17 A group of GOA is omitted in the display panel. The design and arrangement of GOA in the display panel can refer to the introduction in the relevant technology, which will not be repeated here.

[0203] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A display panel, wherein: The display panel includes a first display area and at least one second display area, the transmittance of the second display area is greater than the transmittance of the first display area; the first display area includes a plurality of first sub-pixels arranged in an array, and the second display area includes a plurality of second sub-pixels arranged in an array; The first sub-pixel includes a first pixel circuit, and the second sub-pixel includes a second pixel circuit, and the transmittance of the second pixel circuit is greater than the transmittance of the first pixel circuit.

2. The display panel according to claim 1, wherein: The first sub-pixel includes a first light-emitting area and a first non-light-emitting area except the first light-emitting area, and the second sub-pixel includes a second light-emitting area and a second non-light-emitting area except the second light-emitting area; The transmittance of the second light-emitting area is greater than or equal to the transmittance of the first light-emitting area, and the transmittance of the second non-light-emitting area is greater than the transmittance of the first non-light-emitting area.

3. The display panel according to claim 2, wherein: The first pixel circuit and the second pixel circuit each include a first type transistor and a plurality of second type transistors, the first type transistor is a polysilicon transistor, and the second type transistor is an oxide transistor; the orthographic projection of the first type transistor on the substrate of the display panel at least partially falls into the light emitting area, and the orthographic projection of the second type transistor on the substrate at least partially falls into the non-light emitting area; The transmittance of the first type transistor is less than or equal to the transmittance of the second type transistor.

4. The display panel according to claim 3, wherein: The first sub-pixel and the second sub-pixel each include a gate line, a light emitting control signal line, a reset signal line, an initialization signal line, a data signal line and a first power signal line; The transmittance of at least one of the data signal line and the first power signal line is less than or equal to the transmittance of the gate line, the light emitting control signal line, the reset signal line and the initialization signal line.

5. The display panel according to claim 4, wherein: The display panel comprises: a first semiconductor layer on the substrate, the first semiconductor layer comprising an active portion of the first type transistor; A first gate layer, located on a side of the first semiconductor layer away from the substrate, comprising a gate of the first type transistor and a first electrode of a storage capacitor; A second gate layer, located on a side of the first gate layer away from the substrate, comprising a second electrode of the storage capacitor and at least a portion of the first gate of the second type transistor; A second semiconductor layer, located on a side of the second gate layer away from the substrate, including an active portion of each of the second type transistors; A third gate layer, located on a side of the second semiconductor layer away from the substrate, including at least a portion of the second gate of the second type transistor; A first source-drain conductive layer, located on a side of the third gate layer away from the substrate, comprising a source and a drain of each transistor; Among them, the gate line, the light-emitting control signal line, the reset signal line and the initialization signal line are respectively located on at least one layer among the first gate layer, the second gate layer and the third gate layer, and the data signal line and the first power signal line are respectively located on at least one layer among the first source-drain conductive layer and the second source-drain conductive layer.

6. The display panel according to claim 5, wherein: Portions of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the first display area all include a first sublayer and a second sublayer; The material of one of the first sub-layer and the second sub-layer includes a light-transmitting conductive material, and the material of the other sub-layer includes a metal.

7. The display panel according to claim 6, wherein: Parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area all include the first sublayer and the second sublayer; The first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer and the second source-drain conductive layer located in the second non-luminescent area of ​​the second display area all include a third sublayer, and the material of the third sublayer includes a light-transmitting conductive material.

8. The display panel according to claim 6, wherein: Parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area all include a fourth sublayer; Parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second non-luminescent area of ​​the second display area all include a third sublayer; Wherein, the materials of the third sub-layer and the fourth sub-layer both include light-transmitting conductive materials.

9. The display panel according to claim 5, wherein: The first gate layer, the second gate layer, and the third gate layer in the first display area all include a first sublayer and a second sublayer; the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes a metal; the first source-drain conductive layer and the second source-drain conductive layer in the first display area both include a metal; The first gate layer, the second gate layer, and the third gate layer located in the second non-luminescent area of ​​the second display area all include light-transmitting conductive materials; the first source-drain conductive layer and the second source-drain conductive layer located in the second non-luminescent area of ​​the second display area all include metals; The first source-drain conductive layer and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area both include metal.

10. The display panel according to claim 9, wherein: The first gate layer, the second gate layer, and the third gate layer located in the second light-emitting area of ​​the second display area all include a first sublayer and a second sublayer; the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes a metal.

11. The display panel according to claim 9, wherein: Portions of the first gate layer, the second gate layer, and the third gate layer located in the second light emitting area of ​​the second display area all include metal.

12. The display panel according to claim 5, wherein: Portions of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the first display area all include metal.

13. The display panel according to claim 12, wherein: Portions of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second display area all include a light-transmitting conductive material.

14. The display panel according to claim 12, wherein: Parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second non-luminescent area of ​​the second display area include a light-transmitting conductive material; Parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area include metal; or, parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area include a first sublayer and a second sublayer, and the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes metal.

15. The display panel according to claim 12, wherein: The first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer are all located in the second light-emitting area of ​​the second display area and include metal; The first gate layer, the second gate layer and the third gate layer located in the second non-luminous area of ​​the second display area all include light-transmitting conductive materials, and the first source-drain conductive layer and the second source-drain conductive layer located in the second non-luminous area of ​​the second display area all include metals.

16. The display panel according to any one of claims 10, 11 and 14, wherein: The display panel further includes a passivation layer and a first planarization layer located between the first source-drain conductive layer and the second source-drain conductive layer and sequentially arranged in a direction away from the substrate, and a light-transmitting conductive layer located between the passivation layer and the first planarization layer; Partial line segments of the data signal line and partial line segments of the first power signal line are arranged on the light-transmitting conductive layer.

17. The display panel according to any one of claims 6 to 15, wherein: In the case where the materials of the first gate layer, the second gate layer and the third gate layer include light-transmitting conductive materials, the portions of the first gate layer, the second gate layer and the third gate layer used as gates of transistors include a light-transmitting sublayer and a light-shielding sublayer, and the light-shielding sublayer is located on a side of the light-transmitting sublayer away from the active portion of the transistor.

18. A display device, wherein: The invention comprises the display panel according to any one of claims 1 to 17.

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