Anti-overvoltage protection circuit formed by MOS (Metal Oxide Semiconductor) tubes

Abstract

The utility model discloses an anti-overvoltage protection circuit formed by utilizing an MOS (Metal Oxide Semiconductor) tube, which relates to the technical field of anti-overvoltage protection and comprises an ESD (Electro-Static Discharge) protection circuit, an MOS switch tube, an overvoltage detection circuit, a logic circuit and a gate driver which are connected with one another, wherein the positive electrode and the negative electrode of the power supply are sequentially connected with the two ends of the ESD protection circuit and the two ends of the overvoltage detection circuit respectively, the end, connected with the positive electrode of the power supply, of the overvoltage detection circuit is connected with the drain electrode of the MOS switch tube, the overvoltage detection circuit is further sequentially connected with the logic circuit and the gate driver, and the output end of the gate driver is connected with the gate electrode of the MOS switch tube. The source electrode of the MOS switch tube and the cathode of the power supply are respectively connected with the anode and cathode of a load; the circuit is simple in composition, high in stability and strong in over-current capability, can be applied to power supply protection of most low-voltage electric appliances or modules, and can still protect devices sensitive to high voltage from being damaged under long-time over-range over-high voltage input.

Description

Technical Field

[0001] The utility model relates to the technical field of overvoltage protection, and more specifically, to an overvoltage protection circuit formed by using a MOS tube. Background Art

[0002] When using distributed IO, PLC, switches, inverters, motor drives and other different devices in industrial sites, there will be DC power supplies of different voltage levels such as DC12V, DC24V, and DC60V. When installing and using, personnel are very likely to connect high-voltage power supplies to low-voltage power supply equipment, and the power supply may also be damaged during operation, causing the output voltage to increase: in this case, excessive power supply voltage input will cause permanent damage to the equipment, and even serious accidents such as fire. In order to ensure the reliable operation of the power supply system in the circuit, ensure the stability of the equipment and extend the life of the equipment, it has a certain fault tolerance. Overvoltage protection circuits have become standard for power supply systems. Under existing technologies, overvoltage protection circuits have integrated protection chips, but the integrated overvoltage protection chips have low power, low overcurrent capability, and complex peripheral circuits, and cannot be used in high current applications and scenarios with high overvoltage values. Utility Model Content

[0003] The purpose of the utility model is to provide an overvoltage protection circuit formed by a MOS tube. The overvoltage protection circuit has a simple composition, high stability, and strong overcurrent capacity. It can be applied to the power supply protection of most low-voltage electrical appliances or modules, and can still protect devices that are sensitive to high voltage from damage under long-term over-range and over-high voltage input.

[0004] The above technical objectives of the utility model are achieved through the following technical solutions:

[0005] The present application provides an overvoltage protection circuit formed by a MOS tube, including an ESD protection circuit, a MOS switch tube, an overvoltage detection circuit, a logic circuit and a gate driver having a connection relationship, wherein:

[0006] The positive and negative poles of the power supply are connected to the two ends of the ESD protection circuit and the two ends of the overvoltage detection circuit respectively. The end of the overvoltage detection circuit connected to the positive pole of the power supply is connected to the drain of the MOS switch tube. The overvoltage detection circuit is also connected to the logic circuit and the gate driver in sequence. The output end of the gate driver is connected to the gate of the MOS switch tube. The source of the MOS switch tube and the negative pole of the power supply are connected to the positive and negative poles of the load respectively.

[0007] On the basis of the above technical solution, the present invention can also be improved as follows.

[0008] Furthermore, the above-mentioned ESD protection circuit includes a bidirectional TVS tube, one end of the bidirectional TVS tube is connected to the positive electrode of the power supply, and the other end is connected to the negative electrode of the power supply.

[0009] Furthermore, the overvoltage detection circuit includes a protective resistor and a voltage regulator, one end of the protective resistor is connected to the negative end of the voltage regulator, the other end of the protective resistor is connected to the positive electrode of the power supply, and the positive end of the voltage regulator is connected to the negative electrode of the power supply.

[0010] Furthermore, the above-mentioned logic circuit includes a logic resistor and a PNP transistor, one end of the logic resistor is connected to the negative end of the voltage regulator tube, the other end of the logic resistor is connected to the base of the PNP transistor, the emitter of the PNP transistor is connected to the drain of the MOS switch tube, and the collector of the PNP transistor is connected to the gate driver.

[0011] Furthermore, the above-mentioned ESD protection circuit includes a TVS tube D6, the overvoltage detection circuit includes a resistor R2 and a voltage regulator tube D2, the logic circuit includes a resistor R3 and a transistor Q2, and the gate driver includes a capacitor C2 and a voltage regulator tube D1, wherein:

[0012] The positive electrode of the power supply is connected to one end of the TVS tube D6 and one end of the resistor R2 in sequence, the other end of the resistor R2 is connected to the negative end of the voltage regulator tube D2, and the other end of the TVS tube D6 and the positive end of the voltage regulator tube D2 are both connected to the GND-F end; the negative end of the voltage regulator tube D2 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the base of the transistor Q2, the emitter of the transistor Q2 is connected to the drain of the MOS switch tube, the collector of the transistor Q2 is connected to one end of the capacitor C2, the negative end of the voltage regulator tube D1 and the gate of the MOS switch tube, and the other end of the capacitor C2 and the positive end of the voltage regulator tube D1 are connected to the drain of the MOS switch tube.

[0013] Furthermore, the above-mentioned overvoltage protection circuit further includes a resistor R4, a resistor R5, and a resistor R6, wherein:

[0014] One end of the resistor R4 is connected to one end of the resistor R6 , the other end of the resistor R4 is connected to the collector of the transistor Q2 , and the other end of the resistor R6 is connected to the GND-F terminal.

[0015] Furthermore, the above-mentioned overvoltage protection circuit further includes a resistor R1, a capacitor C1, a polarity capacitor C3 and a capacitor C5, wherein:

[0016] One end of capacitor C1 is connected to the drain of the MOS switch tube, one end of resistor R1 is connected to the source of the MOS switch tube, and the other end of capacitor C1 is connected to the other end of resistor R1; the positive electrode of polar capacitor C3 and one end of capacitor C5 are respectively connected to the source of the MOS switch tube, and the negative electrode of polar capacitor C3 and the other end of capacitor C5 are connected to the GND-F end.

[0017] Furthermore, the above-mentioned ESD protection circuit includes a TVS tube D5, the overvoltage detection circuit includes a resistor R7 and a voltage regulator tube D4, the logic circuit includes a resistor R8 and a transistor Q4, and the gate driver includes a voltage regulator tube D3, wherein:

[0018] The positive electrode of the power supply is connected to one end of the TVS tube D5 and one end of the resistor R7 in sequence, the other end of the resistor R7 is connected to the positive end of the voltage regulator tube D4, the other end of the TVS tube D5 and the negative end of the voltage regulator tube D4 are both connected to the GND-F end; the positive end of the voltage regulator tube D4 is connected to one end of the resistor R8, the other end of the resistor R8 is connected to the base of the transistor Q4, the emitter of the transistor Q4 is connected to the drain of the MOS switch tube, the collector of the transistor Q4 is connected to the positive end of the voltage regulator tube D3 and the gate of the MOS switch tube, and the negative end of the voltage regulator tube D3 is connected to the drain of the MOS switch tube.

[0019] Furthermore, the above-mentioned overvoltage protection circuit further includes a resistor R9 and a resistor R10, wherein:

[0020] One end of the resistor R9 and one end of the resistor R10 are both connected to the collector of the transistor Q4, one end of the resistor R9 is connected to the collector of the transistor Q4 and one end of the resistor R10, the other end of the resistor R9 is connected to the positive end of the voltage regulator tube D3 and the gate of the MOS switch tube, and the other end of the resistor R10 is connected to the GND-F end.

[0021] Furthermore, the above-mentioned overvoltage protection circuit further includes a polarity capacitor C7 and a capacitor C8, wherein:

[0022] The positive electrode of the polarity capacitor C7 and one end of the capacitor C8 are respectively connected to the source of the MOS switch tube, and the negative electrode of the polarity capacitor C7 and the other end of the capacitor C8 are connected to the GND-F terminal.

[0023] Compared with the prior art, the utility model has at least the following beneficial effects:

[0024] In the present application, an ESD protection circuit is used to filter surges and electrostatic pulses generated by the front-stage power input, an overvoltage detection circuit is used to monitor out-of-range power input, and a logic circuit connected to the overvoltage detection circuit is responsible for processing the overvoltage signal output by the overvoltage detection circuit. When overvoltage is detected, the logic circuit will output it to the gate driver, and the gate driver controls the rapid opening and closing of the MOS switch tube.

[0025] In the present application, the overvoltage detection circuit is used to judge the out-of-range voltage and feed it back to the gate driver; the gate driver turns on the MOS tube in the normal range, and turns off the MOS tube when the input exceeds the voltage range, thereby quickly cutting off the overvoltage input and protecting the subsequent devices; when the voltage range of the power input is within the normal range, the overvoltage monitoring circuit will not trigger the overvoltage alarm signal to the logic circuit, and the logic circuit will send a normal signal to the gate driver to drive the MOS tube to turn on and provide normal power input for the subsequent load; if the voltage range of the power input is within the abnormal range, the overvoltage monitoring circuit will trigger the overvoltage alarm signal to the logic circuit, and the logic circuit will send an overvoltage signal to the gate driver, and the gate driver will quickly drive the MOS tube to turn off and disconnect the main circuit power supply. The subsequent load will be without power input. When the input power returns to normal, the MOS is turned on and the load is powered again, thereby achieving the protection purpose and protecting the load from damage when the overvoltage input occurs.

[0026] In the present application, the overvoltage protection circuit can sample the power supply circuit in the power supply system through a terminal to realize output voltage overvoltage detection protection, and use the same terminal to realize input surge filtering; the circuit can realize overvoltage detection and protection through a simple module, so that the overvoltage protection structure of the power supply system is simple, and the power supply system loop current is larger through high-voltage and high-current devices. The input is not only protected against surges, but also uses high-power Zener tube detection, so that overvoltage protection can be achieved even at high input voltages; overvoltage detection is performed in the first cycle of two adjacent cycles, and logic conversion and Gate drive are performed in the second cycle; the circuit can realize the overvoltage protection function in a shorter time using a simpler circuit structure, and the circuit only needs two cycles to complete the overvoltage protection, and the detection cycle is short, which effectively reduces the number of devices in the power supply system and has strong real-time performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are used to provide a further understanding of the embodiments of the present utility model, constitute a part of this application, and do not constitute a limitation of the embodiments of the present utility model. In the drawings:

[0028] Figure 1 This is a system block diagram of an overvoltage protection circuit in an embodiment of the utility model;

[0029] Figure 2 This is a circuit schematic diagram of an overvoltage protection circuit in an embodiment of the utility model;

[0030] Figure 3 This is a timing diagram of the overvoltage protection circuit in the embodiment of the utility model;

[0031] Figure 4 A connection diagram of an overvoltage protection circuit of a 24V power supply provided in an embodiment of the utility model;

[0032] Figure 5 This is a connection diagram of the overvoltage protection circuit of the 12V power supply provided in the embodiment of the utility model. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Generally, the components of the embodiments of the utility model described and shown in the drawings here can be arranged and designed in various different configurations.

[0034] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the present invention to be protected, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0036] In the description of the embodiments of the present utility model, it should be noted that if the terms "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the utility model product is usually placed when used. It is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model.

[0037] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components must be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0038] In the description of the embodiments of the present utility model, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0039] Embodiment 1: This embodiment provides an overvoltage protection circuit formed by a MOS tube, such as Figure 1 and Figure 2 As shown, it includes an ESD protection circuit, a MOS switch tube, an overvoltage detection circuit, a logic circuit and a gate driver with a connection relationship, wherein: the positive and negative electrodes of the power supply are respectively connected to the two ends of the ESD protection circuit and the two ends of the overvoltage detection circuit, one end of the overvoltage detection circuit connected to the positive electrode of the power supply is connected to the drain of the MOS switch tube, the overvoltage detection circuit is also connected to the logic circuit and the gate driver in sequence, the output end of the gate driver is connected to the gate of the MOS switch tube, and the source of the MOS switch tube and the negative electrode of the power supply are respectively connected to the positive and negative electrodes of the load.

[0040] Optionally, the above-mentioned ESD protection circuit includes a bidirectional TVS tube; the above-mentioned overvoltage detection circuit includes a protection resistor and a voltage regulator tube, one end of the protection resistor is connected to the negative end of the voltage regulator tube, the other end of the protection resistor is connected to the positive electrode of the power supply, and the positive end of the voltage regulator tube is connected to the negative electrode of the power supply. The above-mentioned logic circuit includes a logic resistor and a PNP transistor, one end of the logic resistor is connected to the negative end of the voltage regulator tube, the other end of the logic resistor is connected to the base of the PNP transistor, the emitter of the PNP transistor is connected to the drain of the MOS switch tube, and the collector of the PNP transistor is connected to the gate driver.

[0041] Among them, the overvoltage protection circuit can sample the power supply circuit in the power supply system through a terminal to realize output voltage overvoltage detection protection, and use the same terminal to realize input surge filtering; the circuit can realize overvoltage detection and protection through a simple module, so that the overvoltage protection structure of the power supply system is simple, and the power supply system loop current is larger through high-voltage and high-current devices. The input is not only protected against surges, but also uses high-power voltage regulator detection, so that overvoltage protection can be achieved at high input voltages; overvoltage detection is performed in the first cycle of two adjacent cycles, and logic conversion and Gate drive are performed in the second cycle; the circuit can realize the overvoltage protection function in a shorter time with a simpler circuit structure. At the same time, the circuit only needs two cycles to complete the overvoltage protection, and the detection cycle is short, which effectively reduces the number of devices in the power supply system and has strong real-time performance.

[0042] Embodiment 2: This embodiment provides an overvoltage protection circuit formed by a MOS tube, including an ESD protection circuit, a MOS switch tube, an overvoltage detection circuit, a logic circuit and a gate driver having a connection relationship, such as Figure 4 As shown, wherein: the ESD protection circuit includes a TVS tube D6, the overvoltage detection circuit includes a resistor R2 and a voltage regulator tube D2, the logic circuit includes a resistor R3 and a transistor Q2, and the gate driver includes a capacitor C2 and a voltage regulator tube D1, wherein: the positive electrode of the power supply is connected to one end of the TVS tube D6 and one end of the resistor R2 in sequence, the other end of the resistor R2 is connected to the negative end of the voltage regulator tube D2, and the other end of the TVS tube D6 and the positive end of the voltage regulator tube D2 are both connected to the GND-F end; the negative end of the voltage regulator tube D2 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the base of the transistor Q2, the emitter of the transistor Q2 is connected to the drain of the MOS switch tube, the collector of the transistor Q2 is connected to one end of the capacitor C2, the negative end of the voltage regulator tube D1 and the gate of the MOS switch tube, and the other end of the capacitor C2 and the positive end of the voltage regulator tube D1 are connected to the drain of the MOS switch tube. The above-mentioned overvoltage protection circuit also includes a resistor R4, a resistor R5, and a resistor R6, wherein: one end of the resistor R4 is connected to one end of the resistor R6, the other end of the resistor R4 is connected to the collector of the transistor Q2, and the other end of the resistor R6 is connected to the GND-F terminal. The above-mentioned overvoltage protection circuit also includes a resistor R1, a capacitor C1, a polar capacitor C3, and a capacitor C5, wherein: one end of the capacitor C1 is connected to the drain of the MOS switch tube, one end of the resistor R1 is connected to the source of the MOS switch tube, and the other end of the capacitor C1 is connected to the other end of the resistor R1; the positive electrode of the polar capacitor C3 and one end of the capacitor C5 are respectively connected to the source of the MOS switch tube, and the negative electrode of the polar capacitor C3 and the other end of the capacitor C5 are connected to the GND-F terminal.

[0043] Specifically, the ESD protection circuit and the input end of the overvoltage detection circuit share a terminal, are connected in parallel at both ends of the power supply, and are installed close to the input side and in front of the protection stage, wherein the overvoltage detection circuit and the logic circuit are connected in parallel, and the input end of the overvoltage detection circuit and the input end of the logic circuit share a terminal; the output end of the overvoltage detection circuit and the input end of the logic circuit are both connected, the output end of the logic circuit is connected to the gate driver, and the gate driver outputs the drive signal of the MOS switch tube in the power supply system.

[0044] Furthermore, the ESD protection circuit is configured as a 90V bidirectional TVS to complete surge pulse filtering within one time period of the surge pulse; the overvoltage detection circuit is configured as a 27V trigger to complete overvoltage detection within one cycle after overvoltage; the logic circuit is configured to complete logic conversion within an adjacent cycle of the overvoltage trigger signal; the gate driver is configured to be within 50% of the Vsg range of the MOS to complete overvoltage protection within an adjacent cycle of the logic conversion signal.

[0045] Specifically, refer to Figure 4 The ESD protection circuit shown includes a bidirectional 90V-TVS, D6 (model: 5.0SMDJ90CA, peak pulse power consumption Pppm=5000W, filtering 10 / 1000us) connected in parallel to the positive and negative poles of the 24V power supply; the overvoltage detection circuit includes a 10K current limiting resistor with one end connected to the positive pole of the power supply and the other end connected to the voltage regulator, a 27V power voltage regulator (Pd=1W, Fv=1.2V), one end connected to the current limiting resistor and the other end connected to the power ground; the logic circuit includes a 1K current limiting resistor, one end connected to the overvoltage detection output, one end connected to the base of the transistor, a PNP transistor, the emitter is connected to the positive pole of the power supply, and the collector is output; the gate driver includes a MOS switch tube, a Gate pull-down 10K resistor, one end connected to the negative voltage regulator and the gate between Vsg, and a MOS switch tube (model: 2P50G-TN3-R, Vdss=500, I=20A).

[0046] Among them, the overvoltage detection circuit starts to work after the input power exceeds 27V, the internal current of the D2 voltage regulator tube increases, the voltage at both ends is stable, the current of the R2 resistor increases, and the voltage becomes larger; the base voltage of the logic circuit Q2 transistor is stable, the emitter voltage is higher than 27V, the transistor EC is turned on, Vc = VCC-IN; the MOS switch tube Vsg of the gate driver is 0, and the MOS switch tube is turned off. The path between VCC-IN and VCC-OUT is disconnected, and the circuit loses power; after the power supply circuit loses power, the overvoltage detection circuit works, and the logic circuit works. After the overvoltage disappears, the MOS switch tube Vsg = 13V; the path between VCC-IN and VCC-OUT is opened. The triggering works in a cycle.

[0047] Specifically, see Figure 3 , GATE is the driving signal of the switch tube in the power supply system, VCC-IN is the time domain waveform of the terminal Power, and VCC-OUT is the output power signal of the power supply system; the trigger overvoltage threshold set by VZ is the reference point for the protection of the time domain waveform signal of Power. The VCC-IN input is above the reference set by VZ. The Gate gate drive signal will trigger the shutdown of PMOS after a short delay of ton, cutting off the output power signal of the VCC-OUT power supply system. The Gate gate drive signal will trigger the opening of PMOS after a short delay of toff, turning on the output power signal of the VCC-OUT power supply system. In this process, the power system is overvoltage and protected.

[0048] Embodiment 3: This embodiment provides an overvoltage protection circuit formed by a MOS tube, including an ESD protection circuit, a MOS switch tube, an overvoltage detection circuit, a logic circuit and a gate driver having a connection relationship, such as Figure 5As shown, wherein: the above-mentioned ESD protection circuit includes a TVS tube D5, the overvoltage detection circuit includes a resistor R7 and a voltage regulator tube D4, the logic circuit includes a resistor R8 and a transistor Q4, and the gate driver includes a voltage regulator tube D3, wherein: the positive electrode of the power supply is connected to one end of the TVS tube D5 and one end of the resistor R7 in sequence, the other end of the resistor R7 is connected to the positive end of the voltage regulator tube D4, and the other end of the TVS tube D5 and the negative end of the voltage regulator tube D4 are both connected to the GND-F end; the positive end of the voltage regulator tube D4 is connected to one end of the resistor R8, the other end of the resistor R8 is connected to the base of the transistor Q4, the emitter of the transistor Q4 is connected to the drain of the MOS switch tube, the collector of the transistor Q4 is connected to the positive end of the voltage regulator tube D3 and the gate of the MOS switch tube, and the negative end of the voltage regulator tube D3 is connected to the drain of the MOS switch tube. The above-mentioned overvoltage protection circuit also includes a resistor R9 and a resistor R10, wherein: one end of the resistor R9 and one end of the resistor R10 are both connected to the collector of the transistor Q4, one end of the resistor R9 is connected to the collector of the transistor Q4 and one end of the resistor R10, the other end of the resistor R9 is connected to the positive end of the voltage regulator tube D3 and the gate of the MOS switch tube, and the other end of the resistor R10 is connected to the GND-F terminal. The above-mentioned overvoltage protection circuit also includes a polar capacitor C7 and a capacitor C8, wherein: the positive electrode of the polar capacitor C7 and one end of the capacitor C8 are respectively connected to the source of the MOS switch tube, and the negative electrode of the polar capacitor C7 and the other end of the capacitor C8 are connected to the GND-F terminal.

[0049] Specifically, this embodiment provides an overvoltage protection circuit for a 12V power supply system using a MOS tube as the main component, including an ESD protection circuit, a 15V overvoltage detection circuit, a logic circuit and a gate driver; the ESD protection circuit shares a terminal with the input end, is connected in parallel at both ends of the power supply, and is installed close to the input side, in front of the protection stage; the overvoltage detection circuit and the logic circuit are connected in parallel, and the input end of the overvoltage detection circuit and the input end of the logic circuit share a terminal; the output end of the overvoltage detection circuit and the input end of the logic circuit are both connected, the output end of the logic circuit is connected to the gate driver, and the gate driver outputs a drive signal for the MOS switch tube in the power supply system; the system connection relationship is similar to that of Example 2.

[0050] Among them, the ESD protection circuit is configured as a 30V bidirectional TVS to complete surge pulse filtering within a time period of the surge pulse; the overvoltage detection circuit is configured to be triggered by 15V, and completes overvoltage detection within a cycle after overvoltage; the logic circuit is configured to complete logic conversion within the adjacent cycle of the overvoltage trigger signal; the gate driver is configured to be within 50% of the Vsg range of MOS, and completes overvoltage protection within the adjacent cycle of the logic conversion signal; the working principle is basically the same as the working process and Example 2, the device power selection is relatively low, and it is suitable for overvoltage protection of the power supply system of low-voltage circuits with small current loads. The ESD protection circuit includes a D5-TVS, the 15V overvoltage detection circuit includes an R7 resistor and a D4 voltage regulator tube, the logic circuit includes an R8 resistor and a PNP transistor, and the gate driver includes a MOS switch tube.

[0051] Specifically, refer to Figure 5 The ESD protection circuit shown includes a bidirectional 30V-TVS, D6 (model: 5.0SMDJ30CA, peak pulse power consumption Pppm=5000W, filtering 10 / 1000us) connected in parallel to the positive and negative electrodes of the 12V power supply; the overvoltage detection circuit includes a 10K current limiting resistor with one end connected to the positive electrode of the power supply and the other end connected to the voltage regulator, a 15V power voltage regulator (Pd=0.5W, Fv=1.2V), one end connected to the current limiting resistor and the other end connected to the power ground; the logic circuit includes a 1K current limiting resistor, one end connected to the overvoltage detection output and the other end connected to the base of the transistor, a PNP transistor, the emitter is connected to the positive electrode of the power supply, and the collector is output; the gate driver includes a MOS switch tube, a Gate pull-down 10K resistor, one end connected to the negative voltage regulator and the gate between Vsg, and a MOS switch tube (model: UTT30P06L-TN3-R, Vdss=60, I=30A).

[0052] Among them, the overvoltage detection circuit starts to work after the input power exceeds 15V, the internal current of the D4 voltage regulator increases, the voltage at both ends is stable, the current of the R7 resistor increases, and the voltage becomes larger; the base voltage of the logic circuit Q4 transistor is stable, the emitter voltage is higher than 15V, the transistor EC is turned on, Vc = VCC-IN; the MOS switch tube of the gate driver Vsg = 0, the MOS switch tube is turned off. The path between VCC-IN and VCC-OUT is disconnected, and the circuit loses power.

[0053] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the utility model in detail. It should be understood that the above description is only the specific implementation method of the utility model and is not used to limit the protection scope of the utility model. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the utility model should be included in the protection scope of the utility model.

Claims

1. An overvoltage protection circuit formed by a MOS tube, characterized in that: It includes an ESD protection circuit, a MOS switch tube, an overvoltage detection circuit, a logic circuit and a gate driver with a connection relationship, wherein: The positive and negative electrodes of the power supply are connected to the two ends of the ESD protection circuit and the two ends of the overvoltage detection circuit respectively. The end of the overvoltage detection circuit connected to the positive electrode of the power supply is connected to the drain of the MOS switch tube. The overvoltage detection circuit is also connected to the logic circuit and the gate driver in sequence. The output end of the gate driver is connected to the gate of the MOS switch tube. The source of the MOS switch tube and the negative electrode of the power supply are connected to the positive and negative electrodes of the load respectively.

2. The overvoltage protection circuit formed by using a MOS tube according to claim 1, characterized in that: The ESD protection circuit includes a bidirectional TVS tube.

3. The overvoltage protection circuit formed by using a MOS tube according to claim 2, characterized in that: The overvoltage detection circuit includes a protection resistor and a voltage regulator tube, one end of the protection resistor is connected to the negative end of the voltage regulator tube, the other end of the protection resistor is connected to the positive electrode of the power supply, and the positive end of the voltage regulator tube is connected to the negative electrode of the power supply.

4. The overvoltage protection circuit formed by using a MOS tube according to claim 3, characterized in that: The logic circuit includes a logic resistor and a PNP transistor, one end of the logic resistor is connected to the negative end of the voltage regulator tube, the other end of the logic resistor is connected to the base of the PNP transistor, the emitter of the PNP transistor is connected to the drain of the MOS switch tube, and the collector of the PNP transistor is connected to the gate driver.

5. The overvoltage protection circuit formed by using MOS tube according to claim 4, characterized in that: The ESD protection circuit includes a TVS tube D6, the overvoltage detection circuit includes a resistor R2 and a voltage regulator tube D2, the logic circuit includes a resistor R3 and a transistor Q2, and the gate driver includes a capacitor C2 and a voltage regulator tube D1, wherein: The positive electrode of the power supply is connected to one end of the TVS tube D6 and one end of the resistor R2 in sequence, the other end of the resistor R2 is connected to the negative end of the voltage regulator tube D2, the other end of the TVS tube D6 and the positive end of the voltage regulator tube D2 are both connected to the GND-F end; the negative end of the voltage regulator tube D2 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the base of the transistor Q2, the emitter of the transistor Q2 is connected to the drain of the MOS switch tube, the collector of the transistor Q2 is connected to one end of the capacitor C2, the negative end of the voltage regulator tube D1 and the gate of the MOS switch tube, the other end of the capacitor C2 and the positive end of the voltage regulator tube D1 are connected to the drain of the MOS switch tube.

6. The overvoltage protection circuit formed by using a MOS tube according to claim 5, characterized in that: The overvoltage protection circuit also includes resistors R4, R5 and R6, wherein: One end of the resistor R4 is connected to one end of the resistor R6 , the other end of the resistor R4 is connected to the collector of the transistor Q2 , and the other end of the resistor R6 is connected to the GND-F terminal.

7. The overvoltage protection circuit formed by using a MOS tube according to claim 5, characterized in that: The overvoltage protection circuit also includes a resistor R1, a capacitor C1, a polarity capacitor C3 and a capacitor C5, wherein: One end of capacitor C1 is connected to the drain of the MOS switch tube, one end of resistor R1 is connected to the source of the MOS switch tube, and the other end of capacitor C1 is connected to the other end of resistor R1; the positive electrode of polar capacitor C3 and one end of capacitor C5 are respectively connected to the source of the MOS switch tube, and the negative electrode of polar capacitor C3 and the other end of capacitor C5 are connected to the GND-F end.

8. The overvoltage protection circuit formed by using a MOS tube according to claim 4, characterized in that: The ESD protection circuit includes a TVS tube D5, the overvoltage detection circuit includes a resistor R7 and a voltage regulator tube D4, the logic circuit includes a resistor R8 and a transistor Q4, and the gate driver includes a voltage regulator tube D3, wherein: The positive electrode of the power supply is connected to one end of the TVS tube D5 and one end of the resistor R7 in sequence, the other end of the resistor R7 is connected to the positive end of the voltage regulator tube D4, the other end of the TVS tube D5 and the negative end of the voltage regulator tube D4 are both connected to the GND-F end; the positive end of the voltage regulator tube D4 is connected to one end of the resistor R8, the other end of the resistor R8 is connected to the base of the transistor Q4, the emitter of the transistor Q4 is connected to the drain of the MOS switch tube, the collector of the transistor Q4 is connected to the positive end of the voltage regulator tube D3 and the gate of the MOS switch tube, and the negative end of the voltage regulator tube D3 is connected to the drain of the MOS switch tube.

9. The overvoltage protection circuit formed by using a MOS tube according to claim 8, characterized in that: The overvoltage protection circuit also includes a resistor R9 and a resistor R10, wherein: One end of the resistor R9 and one end of the resistor R10 are both connected to the collector of the transistor Q4, one end of the resistor R9 is connected to the collector of the transistor Q4 and one end of the resistor R10, the other end of the resistor R9 is connected to the positive end of the voltage regulator tube D3 and the gate of the MOS switch tube, and the other end of the resistor R10 is connected to the GND-F end.

10. The overvoltage protection circuit formed by using MOS tube according to claim 8, characterized in that: The overvoltage protection circuit also includes a polarity capacitor C7 and a capacitor C8, where: The positive electrode of the polarity capacitor C7 and one end of the capacitor C8 are respectively connected to the source of the MOS switch tube, and the negative electrode of the polarity capacitor C7 and the other end of the capacitor C8 are connected to the GND-F terminal.

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