Semiconductor element

Abstract

The utility model provides a semiconductor element. The semiconductor element comprises a dielectric layer; and an optical modulator structure in the dielectric layer and including: a first region including a first dopant type; and a second region on a top surface of the first region and including a second dopant type, where the first region and the second region correspond to a PN junction diode of the light modulator structure. An optical modulator structure in a photonic integrated circuit includes an L-shaped PN junction located in an optical mode of the optical modulator structure (e.g., a region in the optical modulator structure that produces light). Compared with other types of junctions, such as horizontal junctions or I-shaped junctions, the L-shaped PN junctions increase the PN junction overlapping area at the optical mode. The increased overlapping area enables the optical modulator structure to achieve higher modulation efficiency.

Description

Technical Field

[0001] The utility model relates to a semiconductor element. Background Art

[0002] The semiconductor element may include a photonic integrated circuit configured to use optical signals for high-speed and secure data transmission between integrated circuits and / or between semiconductor dies of the semiconductor element. Optical signals may enable high-performance computing systems to continue to rapidly scale performance to meet the growing demands for telecommunications (e.g., 5G, 6G and beyond), machine learning, artificial intelligence, and / or data center applications. Utility Model Content

[0003] A semiconductor element of some embodiments of the utility model includes a dielectric layer. The semiconductor element includes a light modulator structure in the dielectric layer. The light modulator structure includes a first region, the first region includes a first dopant type. The light modulator structure includes a second region on a top surface of the first region, the second region includes a second dopant type. The first region and the second region correspond to a PN junction diode of the light modulator structure.

[0004] A semiconductor element of some other embodiments of the utility model includes a dielectric layer. The semiconductor element includes a light modulator structure in the dielectric layer. The light modulator structure includes a first portion of a PN junction diode of the light modulator structure, the first portion includes a first dopant type. The light modulator structure includes a second portion of the PN junction diode, the second portion includes a second dopant type. The second portion includes a first segment on a top surface of the first portion, a second segment on a side surface of the first portion, and a third segment connecting the first segment and the second segment.

[0005] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, the features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a diagram of an example environment in which the systems and / or methods described herein may be implemented;

[0008] Figure 2 is a diagram of an example semiconductor component described herein;

[0009] Figure 3A and Figure 3B is a diagram of an example implementation of a light modulator structure described herein;

[0010] FIG. 4A to FIG. 4N are diagrams of example implementations of forming semiconductor elements (or portions thereof) described herein;

[0011] Figure 5 is a diagram of an example semiconductor component described herein;

[0012] Figure 6 are diagrams of example components of the elements described herein;

[0013] Figure 7 is a flow chart of an example manufacturing process associated with forming a semiconductor element. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not restrictive. For example, forming a first feature above or on a second feature in the following description may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0016] Optical signals can be transmitted through waveguide structures in photonic integrated circuits. Waveguide structures are able to confine optical signals, which can reduce optical losses and improve the propagation efficiency of optical signals. Data can be encoded into optical signals by modulating light into optical pulses in an optical modulator structure in a photonic integrated circuit. The optical modulator structure can include a PN junction, and voltage signal modulation is applied to the PN junction, which converts the electrical signal into an optical signal. When a voltage is applied to the PN junction, the junction depletion width changes, resulting in changes in the concentration of electrons and holes within the waveguide structure. Changes in the concentration of electrons and holes may result in changes in the effective refractive index of the waveguide structure, thereby modulating the light intensity within the waveguide structure, which in turn enables the voltage signal to be converted into an optical signal.

[0017] Increasing the modulation speed of a photonic integrated circuit can increase the bandwidth of an optical signal and / or the data transmission rate. In some cases, the optical bandwidth and / or electrical bandwidth of a photonic integrated circuit can be increased by reducing the electron / hole lifetime in a waveguide structure and / or introducing a high dose of impurities into a region optically connecting the waveguide structure and the optical modulator structure.

[0018] However, reducing the electron / hole lifetime in the waveguide structure may result in a reduced Q factor of the photonic integrated circuit, which may increase the full width at half maximum (FWHM) resonant wavelength line shape of the optical modulator structure. The increased FWHM resonant wavelength line shape of the optical modulator structure may reduce the optical modulation amplitude of the optical modulator structure, which may result in an increased bit error rate at a receiver receiving an optical signal generated by the optical modulator structure.

[0019] In some embodiments described herein, an optical modulator structure in a photonic integrated circuit includes an L-shaped PN junction in an optical mode of the optical modulator structure (e.g., a region in the optical modulator structure where light is generated). The L-shaped PN junction includes a first portion, the first portion including a first dopant type (e.g., a p-type dopant or an n-type dopant) overlapping with a second portion, the second portion including a second dopant type different from the first dopant type. A first segment of the first portion extends along a side of the second portion. A second segment of the first portion extends along a top of the second portion.

[0020] Relative to other types of junctions, such as horizontal junctions or I-shaped junctions, L-shaped PN junctions increase the PN junction overlap area at the optical mode. Due to the change in charge carrier concentration around the L-shaped PN junction, the increased overlap area can enable the optical modulator structure to achieve higher modulation efficiency. Higher modulation efficiency can result in an increase in the modulation amplitude of the optical modulator structure. This may reduce the bit error rate at the receiver that receives the optical signal generated by the optical modulator structure, especially in high-bandwidth applications such as telecommunications (e.g., 5G, 6G and higher), machine learning, artificial intelligence and / or data center applications, etc. The L-shaped PN junction can be formed using complementary metal oxide semiconductor (CMOS) manufacturing technology, which may include the use of self-aligned ion implantation.

[0021] Figure 1 1 is a diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1As shown, environment 100 may include multiple semiconductor processing tools (e.g., 102-114) and wafer / die transfer tools 116. Multiple semiconductor processing tools (e.g., 102-114) may include deposition tools 102, exposure tools 104, development tools 106, etching tools 108, planarization tools 110, plating tools 112, ion implantation tools 114, and / or other types of semiconductor processing tools. The tools included in the example environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and / or a manufacturing facility, etc.

[0022] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more components capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high density plasma CVD (HDP-CVD) tool, a sub-atmospheric pressure CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma enhanced atomic layer deposition (PEALD) tool, or other types of CVD tools. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other types of PVD tools. In some embodiments, the example environment 100 includes multiple types of deposition tools 102.

[0023] The exposure tool 104 is a semiconductor processing tool capable of exposing the photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., a deep UV light source, an extreme ultraviolet (EUV) source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor element layer patterns for forming one or more semiconductor elements, may include patterns for forming one or more structures of a semiconductor element, may include patterns for etching various portions of a semiconductor element, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0024] The developing tool 106 is a semiconductor processing tool that is capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

[0025] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor element. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and / or the like. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may use plasma etching or plasma assisted etching to etch one or more portions in the substrate, which may involve using an ionized gas to etch the one or more portions isotropically or directionally.

[0026] The planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing individual layers of a wafer or semiconductor element. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or other types of planarization tools that polish or planarize layers or surfaces of deposited or plated materials. The planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and free grinding polishing) to polish or planarize the surface of the semiconductor element. The planarization tool 110 may use abrasive and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor element). The polishing pad and the semiconductor element may be pressed together by a dynamic polishing head and fixed in place by a retaining ring. The dynamic polishing head may rotate at different rotation axes to remove material and flatten any irregular topography of the semiconductor element to make the semiconductor element flat or planar.

[0027] The electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor component, and / or the like) or a portion thereof with one or more metals. For example, the electroplating tool 112 may include copper plating elements, aluminum plating elements, nickel plating elements, tin plating elements, composite materials or alloys (e.g., tin-silver, tin-lead, and / or the like) plating elements, and / or plating elements for one or more other types of conductive materials, metals, and / or the like.

[0028] The ion implantation tool 114 is a semiconductor processing tool capable of implanting ions into a substrate. The ion implantation tool 114 can generate ions from a source material such as a gas or a solid in an arc chamber. The source material can be provided into the arc chamber, and an arc voltage is released between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed to the substrate so that the ions are implanted below the surface of the substrate.

[0029] The wafer / die transport tool 116 may be included in a cluster tool or in other types of tools including multiple processing chambers, and the wafer / die transport tool 116 may be configured to transport substrates and / or semiconductor components between multiple processing chambers, between a processing chamber and a buffer area, between a processing chamber and an interface tool (e.g., an equipment front end module (EFEM)), and / or between a processing chamber and a transport carrier (e.g., a front opening pod (FOUP)), etc. In some embodiments, the wafer / die transport tool 116 may be included in a multi-chamber (or cluster) deposition tool 102, which may include pre-cleaning process chambers (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from substrates and / or semiconductor components) and other types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations).

[0030] In some embodiments, one or more of the semiconductor processing tools (such as 102-114) and / or the wafer / die transport tool 116 can perform one or more semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools (such as 102-114) and / or the wafer / die transport tool 116 can use a first implantation mask to dope a first region of a semiconductor structure of an optical modulator structure with a first dopant type; and can use a second implantation mask to dope a second region of the semiconductor structure of the optical modulator structure with a second dopant type, the second region is adjacent to the first region, and use a second implantation mask to dope a third region of the semiconductor structure of the optical modulator structure with the first dopant type, wherein the third region is above the second region and the first region, wherein the second region and the third region correspond to a PN junction diode of the optical modulator structure, and wherein the first region, the second region, and the third region form an L-shaped interface of the PN junction diode, and so on. One or more of the semiconductor processing tools (such as 102-114) and / or the wafer / die transport tool 116 can perform other semiconductor processing operations described herein, such as in combination with FIG. 4A to FIG. 4N and / or Figure 7 ,etc.

[0031] Figure 1 The number and arrangement of elements shown in the drawings are provided as one or more examples. Figure 1 There may be more elements, fewer elements, different elements, or differently arranged elements than those shown. Figure 1 Two or more of the elements shown in may be implemented in a single element, or Figure 1 A single element shown in the example environment 100 may be implemented as multiple distributed elements. Additionally or alternatively, one or more elements of the example environment 100 may perform one or more functions described as being performed by another set of elements of the example environment 100.

[0032] Figure 2 is a diagram of a semiconductor component 200 of an example described herein. In particular, Figure 2 A top view of a semiconductor component 200 is shown. The semiconductor component 200 may include a semiconductor photonic component and / or other types of semiconductor components including one or more photonic integrated circuits.

[0033] The semiconductor component 200 can be configured to use optical signals to perform high-speed and secure data transmission between integrated circuits and / or semiconductor dies of the semiconductor component 200. Therefore, the semiconductor component 200 can include an optical modulator structure 202 and a waveguide structure 204 coupled to the optical modulator structure 202 in a coupling region 206. The optical signal can be transmitted through the waveguide structure 204 in the semiconductor component 200. The waveguide structure 204 can confine the optical signal, which can reduce optical loss and improve the propagation efficiency of the optical signal. By modulating the light into optical pulses in the optical modulator structure 202, data can be encoded into the optical signal. The optical pulses are then transmitted to the waveguide structure 204 to propagate to other areas of the semiconductor component 200. The optical modulator structure 202 and the waveguide structure 204 can be adjacent and / or side by side in the semiconductor component 200 to achieve coupling of the optical signal from the optical modulator structure 202 to the waveguide structure 204 (for demodulation of the optical signal, coupling of the optical signal from the waveguide structure 204 to the optical modulator structure 202 is achieved).

[0034] The optical modulator structure 202 may include an approximately circular structure or an approximately ring structure and may be referred to as a micro-ring modulator (MRM). The optical modulator structure 202 may function as a resonant cavity and may modulate an input signal from an optical mode to generate an optical signal (e.g., a modulated optical signal). Based on the optical signal satisfying a threshold modulation frequency and / or based on the optical signal satisfying a threshold signal strength, the optical signal may be coupled to the waveguide structure 204 in the coupling region 206. The waveguide structure 204 may facilitate propagation of the optical signal to another element or region in the semiconductor element 200.

[0035] like Figure 2 As further shown, the light modulator structure 202 may include multiple regions. For example, the light modulator structure 202 may include a contact region 208 and an opposing contact region 210. The contact region 208 may be located at an outer periphery of the light modulator structure 202, and the contact region 210 may be located at an inner periphery of the light modulator structure 202. The contact region 208 and the contact region 210 may be regions of the light modulator structure 202 that are electrically and / or physically coupled to contacts of the semiconductor device 200.

[0036] The light modulator structure 202 may further include a connection region 212 and a connection region 214. The connection region 212 may be electrically and / or physically coupled to the contact region 208 and the PN junction diode 216 of the light modulator structure 202. The connection region 212 may electrically couple the PN junction diode 216 to the contact region 208. The connection region 214 may be electrically and / or physically coupled to the contact region 210 and the PN junction diode 216 of the light modulator structure 202. The connection region 214 may electrically couple the PN junction diode 216 to the contact region 210.

[0037] The PN junction diode 216 is located in the optical mode of the optical modulator structure 202. The PN junction diode 216 includes a p-type region and an n-type region coupled at an interface. As described herein, the interface may be referred to as an L-shaped interface. The interface may be referred to as an L-shaped interface because the interface includes at least two directional segments. For example, the interface may include an approximately vertical segment in which the p-type region and the n-type region are coupled, and an approximately horizontal segment in which the p-type region and the n-type region are coupled. The connection between the approximately vertical segment and the approximately horizontal segment may be an approximately 90-degree interface or another angle such that in the approximately horizontal segment, the n-type region overlaps the p-type region (e.g., above the p-type region) (or the p-type region overlaps the n-type region). The L-type interface increases the overlapping area of ​​the n-type region and the p-type region (e.g., increases the overlapping area of ​​the PN junction diode 216 and the optical mode), which may enable the optical modulator structure 202 to achieve greater modulation efficiency due to changes in charge carrier concentrations around the L-shaped interface. Greater modulation efficiency may result in an increase in the modulation amplitude of the optical modulator structure 202. This may result in a reduced bit error rate at a receiver that receives the optical signal generated by the optical modulator structure 202 .

[0038] like Figure 2 As further shown, in the coupling region 206, the optical modulator structure 202 may include a contact region 210, a connection region 218 coupling the contact region 210 with the optical modulator structure 202, a connection region 220 coupling the optical modulator structure 202 with the waveguide structure 204, and a connection region 222 coupling the waveguide structure 204 with an external region 224.

[0039] The semiconductor element 200 may include a substrate 226 and a dielectric region 228, and the optical modulator structure 202 and the waveguide structure 204 are included in the dielectric region 228. The substrate 226 may be formed of silicon (Si), a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), and / or other types of semiconductor materials. The dielectric region 228 may include one or more dielectric materials, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials. The waveguide structure 204 can include an undoped semiconductor structure (e.g., an undoped silicon structure) in the dielectric region 228. The optical modulator structure 202 can include one or more doped semiconductor regions in the dielectric region, such as one or more p-type regions (e.g., semiconductor regions, such as silicon regions, which include one or more p-type dopants) and one or more n-type regions (e.g., semiconductor regions, such as silicon regions, which include one or more n-type dopants).

[0040] As mentioned above, Figure 2 are provided as examples. Other examples may differ from those described in Figure 2 The content described.

[0041] Figure 3A and Figure 3B 2 is a diagram of an example implementation 300 of an optical modulator structure 202 as described herein. The optical modulator structure 202 may include a semiconductor photonic element (e.g., Figure 2 The semiconductor element 200 or Figure 5 In a semiconductor photonic circuit having a semiconductor element 500, etc.

[0042] Figure 3A 2 illustrates a cross-sectional view of a light modulator structure 202. Figure 3A As shown, the light modulator structure 202 may include contact regions 208 and 210, connection regions 212 and 214, and a PN junction diode 216. The light modulator structure 202 may be included in a dielectric region 228. The dielectric region 228 may be included above and / or on a substrate 226 and may include one or more dielectric layers, one or more shallow trench isolation (STI) regions, one or more etch stop layers (ESLs), and / or one or more other dielectric structures.

[0043] like Figure 3AAs further shown, the optical modulator structure 202 may include a plurality of doped semiconductor regions. The plurality of doped semiconductor regions may facilitate and / or promote the flow of electrons and holes in the optical modulator structure 202 from the contact region 208 and the contact region 210 to the PN junction diode 216, and / or facilitate and / or promote the formation of an optical signal from an electrical signal in an optical mode that includes the interface 302 of the PN junction diode 216.

[0044] The plurality of doped regions may include silicon (and / or another semiconductor material) doped with one or more dopants (e.g., n-type dopants and / or p-type dopants). The light modulator structure 202 may include a region 304 of the PN junction diode 216, the region 304 including a first dopant type. The light modulator structure 202 may include a region 306 of the PN junction diode 216, the region 306 including a second dopant type (e.g., different from the first dopant type). The region 306 may be located above and / or on the region 304 and may be coupled to the region 304 at the interface 302. The top surface of the region 304 and the bottom surface of the region 306 may correspond to a first segment of the interface 302. The first segment of the interface 302 may be referred to as a horizontal segment and may be approximately parallel to the surface of the substrate 226.

[0045] The light modulator structure 202 may include a region 308 of the PN junction diode 216. The region 308 may be adjacent to the region 306 and may include a second dopant type. The light modulator structure 202 may include a region 310 of the PN junction diode 216. The region 310 may include a second dopant type. The region 310 may be located adjacent to the region 304 such that a segment (e.g., a vertical segment) of the interface 302 corresponds to the sides of the region 304 and the region 310. The region 308 may be located above and / or on the region 310 and may connect the region 306 and the region 310.

[0046] Region 304 may correspond to a first region of PN junction diode 216, and region 306, region 308, and region 310 may be segments of a second region of PN junction diode 216. For example, region 304 may include a p-type region (wherein the first dopant type may be a p-type dopant), and region 306, region 308, and region 310 may include an n-type region (wherein the second dopant type may be an n-type dopant), such that the n-type region overlaps the p-type region. The p-type dopant may include a p-type ion of a p-type material (e.g., boron (B) or germanium (Ge), etc.). The n-type dopant may include an n-type ion of an n-type material (e.g., phosphorus (P) or arsenic (As), etc.). Alternatively, region 304 may include an n-type region (wherein the first dopant type may be an n-type dopant), and region 306, region 308, and region 310 may include a p-type region (wherein the second dopant type may be a p-type dopant), such that the p-type region overlaps the n-type region. The interface 302 may be an L-shaped interface (or a two-dimensional interface) between the first region and the second region of the PN junction diode 216 , and the interface 302 includes a first section between the region 304 and the region 310 , and a second section between the region 304 and the region 306 .

[0047] The light modulator structure 202 may also include a region 312 that is physically and / or electrically coupled to the region 310. The region 312 may include a second dopant type such that the regions 306, 308, 310, and 312 include the same dopant type (e.g., an n-type dopant or a p-type dopant). The region 312 may be included in the connection region 212 of the light modulator structure 202. The light modulator structure 202 may also include a region 314 that is physically and / or electrically coupled to the region 304. The region 314 may include a first dopant type such that the regions 304 and 314 include the same dopant type (e.g., an n-type dopant or a p-type dopant). The region 314 may be included in the connection region 214 of the light modulator structure 202.

[0048] The light modulator structure 202 may also include a region 316 that is physically and / or electrically coupled to the region 312. The region 316 may include a second dopant type such that the regions 306, 308, 310, 312, and 316 include the same dopant type (e.g., an n-type dopant or a p-type dopant). The region 316 may be included in the contact region 208 of the light modulator structure 202. The light modulator structure 202 may also include a region 318 that is physically and / or electrically coupled to the region 314. The region 318 may include a first dopant type such that the regions 304, 314, and 318 include the same dopant type (e.g., an n-type dopant or a p-type dopant). The region 318 may be included in the contact region 210 of the light modulator structure 202. The dopant concentrations in region 306, region 308, region 210, region 312, and region 316 may be configured to facilitate and / or promote the passage of charge carriers (e.g., electrons, holes) from region 316 through region 312, region 310, and region 308 to region 306. The different dopant concentrations result in a dopant gradient between the contact region 208 and the PN junction diode 216 of the light modulator structure 202. The dopant concentration in region 316 may be greater than the dopant concentration in region 312, and the dopant concentration in region 312 may be greater than the dopant concentration in regions 310, region 308, and region 306. For example, region 312 may include a dopant concentration of approximately 3xE. 18 Dopant ions / cm3 3 ) to approximately 1xE 20 Dopant ions / cm 3 The dopant concentration in the range of 1xE and the regions 310 and 306 may include a dopant concentration in the range of 1xE 18 Dopant ions / cm 3 to about 3xE 19 Dopant ions / cm 3 The dopant concentration may be within a range of 100 Å to 100 Å. These ranges may achieve relatively low resistance in the light modulator structure 202, which may reduce the resistance-capacitance (RC) time delay of the light modulator structure 202 and may increase the cutoff frequency of the light modulator structure 202. If the dopant concentration is outside of these ranges, the RC time delay may increase, which may reduce the cutoff frequency of the light modulator structure 202 and may result in a lower bandwidth of the light modulator structure 202. However, other values ​​of these ranges are also within the scope of the present disclosure.

[0049] The dopant concentrations in regions 304, 314, and 318 may be configured to facilitate and / or promote the flow of charge carriers (e.g., electrons, holes) from region 318 through region 314 to region 304. The different dopant concentrations result in a dopant gradient between the contact region 210 and the PN junction diode 216 of the light modulator structure 202. The dopant concentration in region 318 may be greater than the dopant concentration in region 314, and the dopant concentration in region 314 may be greater than the dopant concentration in region 304. For example, region 314 may include a dopant concentration of approximately 3xE. 18 Dopant ions / cm 3 to about 1xE 20 Dopant ions / cm 3 range, and region 304 may include a dopant concentration contained within approximately 1xE 18 Dopant ions / cm 3 to about 3xE 19 Dopant ions / cm 3 The dopant concentration may be within a range of 100 Å to 100 Å. These ranges may achieve relatively low resistance in the light modulator structure 202, which may reduce the RC time delay of the light modulator structure 202 and may increase the cutoff frequency of the light modulator structure 202. If the dopant concentration is outside these ranges, the RC time delay may increase, which may reduce the cutoff frequency of the light modulator structure 202 and may result in a lower bandwidth of the light modulator structure 202. However, other values ​​of these ranges are also within the scope of the present disclosure.

[0050] like Figure 3A As further shown in FIG. 3 , contact structure 320 may be included above region 316 in dielectric region 228. Silicide layer 322 may be included above region 316 and / or on region 316. Contact structure 324 may be included above region 318 in dielectric region 228. Silicide layer 326 may be included above region 318 and / or on region 318. Contact structure 320 and contact structure 324 may each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu) or gold (Au) and other examples of conductive materials. Contact structure 320 and contact structure 324 may each include a through hole, a trench, a contact plug and / or other types of conductive structures. Silicide layer 322 may include a metal silicide layer, such as titanium silicide and / or other types of metal silicides, to provide a relatively low contact resistance between region 316 and contact structure 320 electrically coupled to region 316. The silicide layer 326 may include a metal silicide layer, such as titanium silicide and / or other types of metal silicides, to provide a relatively low contact resistance between the region 318 and the contact structure 324 electrically coupled to the region 318 .

[0051] In some embodiments described herein, a semiconductor element (e.g., semiconductor element 200, semiconductor element 500) includes a dielectric layer (e.g., dielectric region 228) and an optical modulator structure 202 in the dielectric layer, wherein the optical modulator structure 202 includes a first region (e.g., region 304) and a second region (e.g., region 306) on a top surface of the first region, the first region includes a first dopant type, the second region includes a second dopant type, wherein the first region and the second region correspond to a PN junction diode 216 of the optical modulator structure 202.

[0052] In some embodiments described herein, a semiconductor component (e.g., semiconductor component 200, semiconductor component 500) includes a dielectric layer (e.g., dielectric region 228) and an optical modulator structure 202 in the dielectric layer, wherein the optical modulator structure 202 includes a first portion (e.g., region 304) of a PN junction diode 216 of the optical modulator structure 202 and a second portion (e.g., region 306, region 308, and region 310) of the PN junction diode 216, wherein the first portion includes a first dopant type and the second portion includes a second dopant type. The second portion includes a first segment (e.g., region 306) on a top surface of the first portion, a second segment (e.g., region 310) on a side surface of the first portion, and a third segment (e.g., region 308) connecting the first segment and the second segment.

[0053] Figure 3B Several example dimensions of a portion of the light modulator structure 202 are shown. In particular, Figure 3B Several example dimensions for the PN junction diode 216 are shown.

[0054] like Figure 3B As shown, the PN junction diode 216 may include an example dimension D1. The dimension D1 may correspond to the cross-sectional width of the PN junction diode 216 (e.g., between the outer edge of the region 308 and the outer edge of the region 306). In some embodiments, the dimension D1 is included in the range of about 300 nanometers to about 500 nanometers to enable the PN junction diode 216 to operate in a single-mode wavelength range of about 1310 nanometers to about 1550 nanometers. However, other values ​​of the range are within the scope of the present disclosure.

[0055] like Figure 3BAs shown, the PN junction diode 216 may include an example dimension D2. The dimension D2 may correspond to the cross-sectional height of the PN junction diode 216 (e.g., between the bottom surface of the region 304 and the top surface of the region 306). In some embodiments, the dimension D2 is included in the range of about 200 nanometers to about 300 nanometers to enable the PN junction diode 216 to operate in a single-mode wavelength range of about 1310 nanometers to about 1550 nanometers. However, other values ​​of the range are within the scope of the present disclosure.

[0056] like Figure 3B As further shown, the PN junction diode 216 may include an example dimension D3. The dimension D3 may correspond to the thickness of the region 304 and the length of the vertical segment of the interface 302. In some embodiments, the dimension D3 is within a range of ± approximately 50 nanometers of half the dimension D2. In other words, the dimension D3 may be equal to:

[0057] D3=0.5*D2±50nm

[0058] If the dimension D3 is outside this range, the light modulator structure 202 may experience lower modulation efficiency because the modulation efficiency of the light modulator structure 202 is proportional to the overlap of the optical modes of the interface 302 and the PN junction diode 216. If the dimension D3 is within this range, the light modulator structure 202 may experience higher modulation efficiency. However, other values ​​within this range are also within the scope of the present disclosure.

[0059] like Figure 3B As further shown, the PN junction diode 216 may include an example dimension D4. The dimension D4 may correspond to the width or thickness of the region 308 and the width or thickness of the region 310. In some embodiments, the dimension D4 is included in the range of about 50 nanometers to about 200 nanometers. If the dimension D4 is outside this range, the light modulator structure 202 may experience a greater resistance and lower modulation efficiency relative to the dimension D4 included in this range, because the modulation efficiency of the light modulator structure 202 is proportional to the overlap of the optical modes of the interface 302 and the PN junction diode 216. However, other values ​​of this range are also within the scope of the present disclosure.

[0060] like Figure 3B As further shown, the PN junction diode 216 can include an example dimension D5. Dimension D5 can correspond to the thickness of region 306. In some embodiments, dimension D5 is approximately equal to dimension D4. In some embodiments, dimension D3 is greater than dimension D5. In some embodiments, dimension D5 is approximately equal to:

[0061] D5=D2–D3

[0062] However, other values ​​of D5 are also within the scope of the present disclosure.

[0063] like Figure 3B As further shown, the PN junction diode 216 may include an exemplary dimension D6. The dimension D6 may correspond to the width of the region 306 and the length of the horizontal segment of the interface 302. In some embodiments, the dimension D6 is approximately equal to:

[0064] D6=D1–D4

[0065] However, other values ​​of D6 are also within the scope of the present disclosure.

[0066] As mentioned above, providing Figure 3A and Figure 3B As an example. Other examples may differ from Figure 3A and Figure 3B as described.

[0067] FIG. 4A to FIG. 4N is a diagram of an example implementation 400 of forming a semiconductor element (or portion thereof) described herein. In particular, example implementation 400 may include an example of forming optical modulator structure 202 in semiconductor element 200 and / or semiconductor element 500, etc. In some implementations, one or more semiconductor processing operations described in connection with example implementation 400 may be performed by one or more of semiconductor processing tools (e.g., 102-114) and / or by wafer / die transfer tool 116. In some implementations, one or more semiconductor processing operations described in connection with example implementation 400 may be performed by another semiconductor processing tool.

[0068] Steering Figure 4A , a substrate 402 may be provided. The substrate 402 may include a silicon-on-insulator (SOI) substrate, which includes a substrate 226 (e.g., a silicon (Si) substrate and / or another type of semiconductor substrate), a dielectric region 228 (e.g., a buried oxide or bottom oxide (BOX) layer and / or other type of insulator layer) above and / or on the substrate 226, and a semiconductor layer 404 (e.g., a silicon (Si) layer and / or other type of semiconductor layer) above and / or on the dielectric region 228. In some embodiments, before forming the light modulator structure 202, the thickness of the dielectric region 228 (e.g., the BOX layer) may be included in the range of about 0.5 microns to about 3 microns. However, other values ​​of this range are also within the scope of the present disclosure.

[0069] Alternatively, the substrate 226 may be provided as a semiconductor wafer, and the deposition tool 102 may form the dielectric region 228 over and / or on the substrate 226, and may form the semiconductor layer 404 over and / or on the dielectric region 228. The deposition tool 102 may use a CVD technique, a PVD technique, an oxidation technique (e.g., a thermal oxidation technique), and / or other types of deposition techniques to form the dielectric region 228. The deposition tool 102 may use a CVD technique, a PVD technique, an epitaxy technique, and / or another type of deposition technique to form the semiconductor layer 404.

[0070] like Figure 4B As shown, a hard mask layer 406 can be formed over and / or on the semiconductor layer 404, and the pattern in the hard mask layer 406 can be used to form a semiconductor structure 408 (e.g., a silicon structure) of the light modulator structure 202 from the semiconductor layer 404. The deposition tool 102 can form the hard mask layer 406 on the semiconductor layer 404 (e.g., using a CVD technique, a PVD technique, and / or other types of deposition techniques), and can form a photoresist layer on the hard mask layer 406 (e.g., using a spin coating technique and / or other types of deposition techniques). The hard mask layer 406 can include silicon nitride (Si x N y , such as Si3N4) material or another hard mask material. In some embodiments, the hard mask layer 406 is formed to have a thickness in the range of about 500 angstroms to about 1500 angstroms. However, other values ​​of this range are also within the scope of the present disclosure.

[0071] The exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern in the photoresist layer. The development tool 106 may develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 may etch the hard mask layer 406 to transfer the pattern from the photoresist layer to the hard mask layer 406. The etching tool 108 then etches the semiconductor layer 404 based on the pattern in the hard mask layer 406 to remove portions of the semiconductor layer 404 based on the pattern to form a semiconductor structure 408 of the light modulator structure 202. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0072] like Figure 4CAs shown, a photoresist layer 410 can be formed over and / or on the semiconductor structure 408 of the light modulator structure 202. The deposition tool 102 can use a spin coating technique and / or other types of deposition techniques to form the photoresist layer 410. The exposure tool 104 can expose the photoresist layer 410 to a radiation source, and the development tool 106 can develop and remove portions of the photoresist layer 410 to form a pattern 412 in the photoresist layer 410.

[0073] like Figure 4C As further shown, one or more portions of the semiconductor structure 408 of the light modulator structure 202 may be doped with one or more types of dopants to form one or more doped semiconductor regions in the light modulator structure 202. The ion implantation tool 114 may perform one or more doping operations or ion implantation operations using a combination of the hard mask layer 406 and the pattern 412 in the photoresist layer 410 as an implantation mask. The ion implantation tool 114 may use ion implantation techniques and / or other types of doping techniques to implant a dopant of a first dopant type (e.g., an n-type dopant, a p-type dopant) into a region 414 of the semiconductor structure 408 of the light modulator structure 202 that is exposed through the hard mask layer 406 and the pattern 412 in the photoresist layer 410. A photoresist removal tool may then remove the remaining portion of the photoresist layer 410 (e.g., using a chemical stripper, plasma ashing, and / or another technique).

[0074] In some embodiments, the first dopant type includes an n-type dopant, such as phosphorus (P). In these embodiments, an implantation energy in the range of about 50 kiloelectronvolts (keV) to about 160 keV is used to implant the phosphorus ions into the semiconductor structure 408 of the optical modulator structure, and a dose of the phosphorus ions used may include about 1xE 14 Phosphorus ion / cm 3 to about 6xE 14 Phosphorus ion / cm 3 However, other values ​​of these ranges are also within the scope of the present disclosure.

[0075] In some embodiments, the first dopant type includes an n-type dopant, such as arsenic (As). In these embodiments, arsenic ions are implanted into the semiconductor structure 408 of the optical modulator structure using an implantation energy in the range of about 20 keV to about 60 keV, and the dose of arsenic ions used may include about 5xE 13 Arsenic ion / cm 3 to about 5xE 14 Arsenic ion / cm 3 However, other values ​​of these ranges are also within the scope of the present disclosure.

[0076] In some embodiments, the ion implantation tool 114 bombards the surface of the semiconductor structure 408 of the light modulator structure 202 at one or more angles to implant ions in the exposed sidewalls of the semiconductor structure 408. Here, the ion implantation in the sidewalls of the semiconductor structure 408 is self-aligned with the hard mask layer 406, meaning that the hard mask layer 406 acts as an implantation barrier on top of the semiconductor structure 408. The ion implantation tool 114 can implant ions in the sidewalls of the semiconductor structure 408 at a tilt angle included in the range of about 45 degrees to about -45 degrees. However, other values ​​of this range are also within the scope of the present disclosure. The tilt angle can refer to the bombardment angle relative to an angle approximately perpendicular to the substrate 226. The ion implantation tool 114 can implant ions in the sidewalls of the semiconductor structure 408 to a depth included in the range of about 50 nanometers to about 150 nanometers. However, other values ​​of this range are also within the scope of the present disclosure.

[0077] like Figure 4D As shown, another photoresist layer 416 can be formed over and / or on the semiconductor structure 408 of the light modulator structure 202. The deposition tool 102 can use a spin coating technique and / or other types of deposition techniques to form the photoresist layer 416. The exposure tool 104 can expose the photoresist layer 416 to a radiation source, and the development tool 106 can develop and remove portions of the photoresist layer 416 to form a pattern 418 in the photoresist layer 416.

[0078] like Figure 4D As further shown, one or more portions of the semiconductor structure 408 of the light modulator structure 202 may be doped with one or more types of dopants to form one or more doped semiconductor regions in the light modulator structure 202. The ion implantation tool 114 may perform one or more doping operations or ion implantation operations using a combination of the hard mask layer 406 and the pattern 418 in the photoresist layer 416 as an implantation mask. The ion implantation tool 114 may use ion implantation techniques and / or other types of doping techniques to implant a dopant of a first dopant type into a region 420 of the semiconductor structure 408 of the light modulator structure 202, the region 420 being exposed through the hard mask layer 406 and the pattern 418 in the photoresist layer 416. The region 420 may be included within the region 414 such that the dopant concentration in the region 420 is greater than the dopant concentration in the region 414. The photoresist removal tool may then remove the remaining portion of the photoresist layer 416 (e.g., using a chemical stripper, plasma ashing, and / or another technique).

[0079] In some embodiments, the first dopant type includes an n-type dopant, such as phosphorus (P). In these embodiments, an implantation energy in the range of about 10 keV to about 50 keV is used to implant the phosphorus ions into the semiconductor structure 408 of the optical modulator structure, and a dose of the phosphorus ions used may be in the range of about 5xE 13 Phosphorus ion / cm 3 to about 3xE 15 Phosphorus ion / cm 3 However, other values ​​of these ranges are also within the scope of the present disclosure.

[0080] In some embodiments, the ion implantation tool 114 bombards the surface of the semiconductor structure 408 of the light modulator structure 202 at one or more angles to implant ions in the exposed sidewalls of the semiconductor structure 408. Here, the ion implantation in the sidewalls of the semiconductor structure 408 is self-aligned with the hard mask layer 406, meaning that the hard mask layer 406 acts as an implantation barrier on top of the semiconductor structure 408. The ion implantation tool 114 can implant ions in the sidewalls of the semiconductor structure 408 at a tilt angle included in a range of about 0 degrees to about 30 degrees. However, other values ​​of this range are also within the scope of the present disclosure.

[0081] like Figure 4E As shown, another photoresist layer 422 can be formed over and / or on the semiconductor structure 408 of the light modulator structure 202. The deposition tool 102 can use a spin coating technique and / or other types of deposition techniques to form the photoresist layer 422. The exposure tool 104 can expose the photoresist layer 422 to a radiation source, and the development tool 106 can develop and remove portions of the photoresist layer 422 to form a pattern 424 in the photoresist layer 422. The region 414 and the region 420 doped with the first dopant type can remain covered by the photoresist layer 422 so that a dopant of the second dopant type can be implanted into another region of the semiconductor structure 408 of the light modulator structure 202.

[0082] like Figure 4EAs further shown in FIG. 1 , one or more portions of the semiconductor structure 408 of the light modulator structure 202 may be doped with one or more types of dopants to form one or more doped semiconductor regions in the light modulator structure 202. The ion implantation tool 114 may perform one or more doping operations or ion implantation operations using a combination of the hard mask layer 406 and the pattern 424 in the photoresist layer 422 as an implantation mask. The ion implantation tool 114 may use ion implantation techniques and / or other types of doping techniques to implant dopants of a second dopant type into regions 426 of the semiconductor structure 408 of the light modulator structure 202, the regions 426 being exposed through the hard mask layer 406 and the pattern 424 in the photoresist layer 422. A photoresist removal tool may then remove the remaining portions of the photoresist layer 422 (e.g., using a chemical stripper, plasma ashing, and / or another technique).

[0083] In some embodiments, the second dopant type includes a p-type dopant, such as boron (B). In these embodiments, the boron ions are implanted into the semiconductor structure 408 of the optical modulator structure using an implantation energy in the range of about 5 keV to about 30 keV, and the dose of the boron ions used may be in the range of about 5xE 13 Boron ion / cm 3 to about 3xE 15 Boron ion / cm 3 However, other values ​​of these ranges are also within the scope of the present disclosure.

[0084] In some embodiments, the ion implantation tool 114 bombards the surface of the semiconductor structure 408 of the light modulator structure 202 at one or more angles to implant ions in the exposed sidewalls of the semiconductor structure 408. Here, the ion implantation in the sidewalls of the semiconductor structure 408 is self-aligned with the hard mask layer 406, meaning that the hard mask layer 406 acts as an implantation barrier on top of the semiconductor structure 408. The ion implantation tool 114 can implant ions in the sidewalls of the semiconductor structure 408 at a tilt angle included in a range of about 0 degrees to about 30 degrees. However, other values ​​of this range are also within the scope of the present disclosure.

[0085] like Figure 4FAs shown, additional material for the dielectric region 228 may be deposited to encapsulate the semiconductor structure 408 of the light modulator structure 202 in the dielectric region 228. The deposition tool 102 may use a CVD technique, a PVD technique, an oxidation technique (e.g., a thermal oxidation technique), and / or other types of deposition techniques to deposit the STI region 428 as the additional material for the dielectric region 228. In some embodiments, one or more additional semiconductor processing operations may be performed to deposit the additional material for the dielectric region 228. For example, the deposition tool 102 may perform an STI liner oxidation operation and / or a high density plasma (HDP) deposition operation to deposit the additional material for the dielectric region 228. As another example, the planarization tool 110 may perform a CMP operation and / or other types of planarization operations to planarize the dielectric region 228 after depositing the additional material for the dielectric region 228. The planarization tool 110 may perform a CMP operation and / or other types of planarization operations to planarize the dielectric region 228 such that the top surface of the light modulator structure 202 is exposed through the dielectric region 228. The CMP operation may remove the hard mask layer 406 from the light modulator structure 202. Additionally and / or alternatively, the etching tool 108 may remove the hard mask layer 406 by dry etching and / or wet / chemical etching.

[0086] like Figure 4G As shown, another photoresist layer 430 can be formed over and / or on the semiconductor structure 408 of the light modulator structure 202. The deposition tool 102 can use a spin coating technique and / or other types of deposition techniques to form the photoresist layer 430. The exposure tool 104 can expose the photoresist layer 430 to a radiation source, and the development tool 106 can develop and remove portions of the photoresist layer 430 to form a pattern 432 in the photoresist layer 430. The area of ​​the light modulator structure 202 where the PN junction diode 216 is to be formed can be exposed through the pattern 432.

[0087] like Figure 4GAs further shown in FIG. 1 , one or more portions of the semiconductor structure 408 of the light modulator structure 202 may be doped with one or more types of dopants to form the PN junction diode 216 in the light modulator structure 202. The ion implantation tool 114 may perform one or more doping operations or ion implantation operations using the pattern 432 in the photoresist layer 430 as an implantation mask. The ion implantation tool 114 may use an ion implantation technique and / or another type of doping technique to implant a dopant of a second dopant type into the region 304 of the light modulator structure 202. The ion implantation tool 114 may use an ion implantation technique and / or another type of doping technique to implant a dopant of a first dopant type into the region 306 of the light modulator structure 202 above and / or on the region 304. The doping of the region 306 may result in additional dopants being implanted into portions of the adjacent region 414, which may result in the formation of the region 308 and the region 310. Because the region 308 is exposed to multiple doping operations, the dopant concentration in the region 308 may be greater than the dopant concentration in the region 306 and the region 310. A photoresist removal tool may then remove remaining portions of photoresist layer 430 (eg, using a chemical stripper, plasma ashing, and / or another technique).

[0088] In some embodiments, region 304 is doped in multiple doping operations. For example, portion 304a of region 304 may be doped in a first doping operation, and portion 304b above portion 304a may be doped in a second doping operation after the first doping operation. A third doping operation may be performed after the second doping operation to dope region 306 and region 308. Portion 304a may be coupled to region 426, and portion 304b may be coupled to region 306. The use of the first doping operation may improve the connection between region 304 and region 426 (which may subsequently be formed as region 314). The location of interface 302 between region 304 and region 306 may be precisely controlled using the second and third doping operations.

[0089] In some embodiments, the first doping operation (e.g., a first ion implantation operation) may include doping the region 304 with a p-type dopant, such as boron (B). In these embodiments, the boron ions are implanted into the semiconductor structure 408 of the optical modulator structure using an implantation energy in the range of about 30 keV to about 50 keV, and the dose of the boron ions used may be in the range of about 5xE. 13 Boron ion / cm 3 to about 5xE 14 Boron ion / cm 3However, other values ​​of these ranges are also within the scope of the present disclosure. In some embodiments, a tilt angle of about 0 degrees is used in the first doping operation. However, other values ​​are also within the scope of the present disclosure.

[0090] In some embodiments, the second doping operation (e.g., a second ion implantation operation) may include doping the region 304 with a p-type dopant, such as boron (B). In these embodiments, the boron ions are implanted into the semiconductor structure 408 of the optical modulator structure using an implantation energy in the range of about 50 keV to about 70 keV, and the dose of the boron ions used may be in the range of about 5xE. 13 Boron ion / cm 3 to about 5xE 14 Boron ion / cm 3 However, other values ​​of these ranges are also within the scope of the present disclosure. In some embodiments, a tilt angle of about 0 degrees is used in the second doping operation. However, other values ​​are also within the scope of the present disclosure.

[0091] In some embodiments, the third doping operation (e.g., a third ion implantation operation) may include doping the region 304 with an n-type dopant, such as phosphorus (P). In these embodiments, an implantation energy in the range of about 30 keV to about 50 keV is used to implant the phosphorus ions into the semiconductor structure 408 of the optical modulator structure, and a dose of the phosphorus ions used may be in the range of about 8xE 13 Phosphorus ion / cm 3 to about 8xE 14 Phosphorus ion / cm 3 However, other values ​​of these ranges are also within the scope of the present disclosure. In some embodiments, a tilt angle of about 0 degrees is used in the third doping operation. However, other values ​​are also within the scope of the present disclosure.

[0092] Generally, the dopant concentration in regions 310, 308, and 306 may be greater than the dopant concentration in region 304. In some embodiments, a rapid thermal annealing (RTA) operation and / or a furnace heat activation operation is used to anneal the semiconductor structure 408 of the light modulator structure 202 to promote activation and / or absorption of dopants in regions 304, 306, 308, and / or 310.

[0093] like Figure 4HAs further shown in FIG. 2 , one or more portions of the semiconductor structure 408 of the light modulator structure 202 may be doped with one or more dopants to form regions 312 and regions 316 in the light modulator structure 202. Region 312 may include at least a portion of region 414, at least a portion of region 420, and / or an undoped portion of the semiconductor structure 408 of the light modulator structure. Region 316 may include at least a portion of region 414 and / or an undoped portion of the semiconductor structure 408 of the light modulator structure.

[0094] The ion implantation tool 114 may use the photoresist layer 434 including the pattern 436 to perform one or more doping operations or ion implantation operations. The photoresist layer 434 may be used as an implantation mask. The ion implantation tool 114 may use ion implantation techniques and / or other types of doping techniques to implant dopants of a first dopant type (e.g., n-type dopants such as phosphorus (P) or arsenic (As), etc.). A photoresist removal tool may then remove the remaining portion of the photoresist layer 434 (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a rapid thermal annealing (RTA) operation and / or a furnace thermal activation operation is used to anneal the semiconductor structure 408 of the optical modulator structure 202 to promote activation and / or absorption of dopants in the region 312 and / or region 316.

[0095] like Fig. 4I As further shown in FIG. 2 , one or more portions of the semiconductor structure 408 of the light modulator structure 202 may be doped with one or more dopants to form regions 314 and regions 318 in the light modulator structure 202. Region 314 may include at least a portion of region 426 and / or an undoped portion of the semiconductor structure 408 of the light modulator structure. Region 318 may include at least a portion of region 426 and / or an undoped portion of the semiconductor structure 408 of the light modulator structure.

[0096] The ion implantation tool 114 may use the photoresist layer 438 including the pattern 440 to perform one or more doping operations or ion implantation operations. The photoresist layer 438 may be used as an implantation mask. The ion implantation tool 114 may use ion implantation techniques and / or other types of doping techniques to implant dopants of a second dopant type (e.g., a p-type dopant such as boron (B), etc.). A photoresist removal tool may then remove the remaining portion of the photoresist layer 438 (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a rapid thermal annealing (RTA) operation and / or a furnace thermal activation operation is used to anneal the semiconductor structure 408 of the light modulator structure 202 to promote activation and / or absorption of dopants in the region 314 and / or region 318.

[0097] like Figure 4JAs shown, silicide layer 322 may be formed on and / or on the top surface of region 316, and silicide layer 326 may be formed on and / or on the top surface of region 318. Silicide layer 322 and silicide layer 326 may each include a metal silicide layer. Deposition tool 102 may deposit silicide layer 322 and silicide layer 326 using a CVD technique, a PVD technique, an ALD technique, a silicidation technique, and / or another deposition technique. In some embodiments, deposition tool 102 may perform a pre-cleaning operation to remove oxide (e.g., native oxide) from the top surface of region 316 and the top surface of region 318 before forming silicide layer 322 and silicide layer 326.

[0098] like Figure 4K As shown, one or more additional layers of the dielectric region 228 may be formed after forming the light modulator structure 202. For example, one or more additional layers of the dielectric region 228 may be formed (e.g., using the above combined Figure 4F The light modulator structure 202 is encapsulated in the dielectric region 228 by one or more techniques described herein. In some embodiments, the planarization tool 110 planarizes the dielectric region 228 after the deposition tool 102 deposits one or more additional layers of the dielectric region 228.

[0099] like Figure 4L As shown, contact structure 320 and contact structure 324 can be formed in dielectric region 228. Contact structure 320 can be formed above region 316 and on silicide layer 322. Contact structure 324 can be formed above region 318 and on silicide layer 326. Contact structure 320 and contact structure 324 can be formed in grooves formed in region 318 and above region 318, respectively. In some embodiments, the pattern in the photoresist layer is used to etch dielectric region 228 to form a groove in dielectric region 228. In these embodiments, deposition tool 102 forms a photoresist layer on dielectric region 228. Exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 develops and removes portions of the photoresist layer to expose the pattern. Etching tool 108 etches dielectric region 228 based on the pattern to form a groove in dielectric region 228. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of the dielectric region 228.

[0100] The deposition tool 102 and / or the electroplating tool 112 may deposit the contact structure 320 and the contact structure 324 in the groove. The deposition tool 102 and / or the electroplating tool 112 may use CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 Another deposition technique as described and / or another suitable deposition technique is used to deposit contact structure 320 and contact structure 324 .

[0101] like Figure 4M As shown, dielectric region 442 may be formed over and / or on dielectric region 228. Deposition tool 102 may deposit one or more dielectric layers of dielectric region 442 using CVD techniques, PVD techniques, oxidation techniques (eg, thermal oxidation techniques), and / or other types of deposition techniques.

[0102] like Figure 4M As further shown in FIG. 1 , one or more metallization layers 444 may be formed in (and included in) the dielectric region 442. The metallization layer 444 may include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au), as well as other examples of conductive materials. The metallization layer 444 may include vias, trenches, contact plugs, and / or other types of metallization layers. The deposition tool 102 and / or the electroplating tool 112 may be in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, or a combination of the above. Figure 1 One or more metallization layers 444 are deposited in another deposition operation as described and / or another suitable deposition operation. In some embodiments, a seed layer is deposited first, and the metallization layer 444 is deposited on the seed layer. In some embodiments, the planarization tool 110 planarizes the metallization layer 444 after depositing the metallization layer 444.

[0103] In some embodiments, dielectric region 442 includes multiple layers of metallization 444. For example, deposition tool 102 may form a first dielectric layer of dielectric region 442 on dielectric region 228. Etching tool 108 may remove a portion of the first layer of dielectric region 442 to expose contact structure 320 and contact structure 324, and deposition tool 102 and / or electroplating tool 112 may form first layer of metallization 444 over and / or on contact structure 320 and contact structure 324. Deposition tool 102 may form a second dielectric layer of dielectric region 442 on the first dielectric layer of dielectric region 442. Etching tool 108 may remove a portion of the second layer of dielectric region 442 to expose first layer of metallization 444, and deposition tool 102 and / or electroplating tool 112 may form second layer of metallization 444 over and / or on first layer of metallization 444. Additional dielectric layers and / or additional metallization layers 444 of the dielectric region 442 may be formed until a sufficient or target number of metallization layers 444 are formed.

[0104] like Figure 4N As shown, dielectric region 446 may be formed over and / or on dielectric region 442. Deposition tool 102 may deposit one or more dielectric layers of dielectric region 446 using CVD techniques, PVD techniques, oxidation techniques (eg, thermal oxidation techniques), and / or other types of deposition techniques.

[0105] like Figure 4N As further shown, one or more metallization layers 448 may be formed in (and included in) the dielectric region 446. The metallization layer 448 may include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au), etc. The metallization layer 448 may include vias, trenches, contact plugs, conductive pads, and / or other types of metallization layers. The deposition tool 102 and / or the electroplating tool 112 may be operated in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, or a combination of the above. Figure 1 One or more metallization layers 448 are deposited in another deposition operation as described and / or other suitable deposition operations. In some embodiments, a seed layer is deposited first, and the metallization layer 448 is deposited on the seed layer. In some embodiments, the planarization tool 110 planarizes the metallization layer 448 after depositing the metallization layer 448.

[0106] In some embodiments, the dielectric region 446 includes multiple metallization layers 448. For example, the deposition tool 102 can form a first dielectric layer of the dielectric region 446 on the dielectric region 442. The etching tool 108 can remove a portion of the first layer of the dielectric region 446 to expose the uppermost metallization layer 444 in the dielectric region 442, and the deposition tool 102 and / or the electroplating tool 112 can form a first metallization layer 448 over and / or on the uppermost metallization layer 444. The deposition tool 102 can form a second dielectric layer of the dielectric region 446 on the first dielectric layer of the dielectric region 446. The etching tool 108 can remove a portion of the second layer of the dielectric region 446 to expose the first metallization layer 448, and the deposition tool 102 and / or the electroplating tool 112 can form a second metallization layer 448 over and / or on the first metallization layer 448. Additional dielectric layers of the dielectric region 446 and / or additional metallization layers 448 may be formed until a sufficient or target number of metallization layers 448 are formed.

[0107] As mentioned above, FIG. 4A to FIG. 4N are provided as examples. Other examples may differ from those described in FIG. 4A to FIG. 4N as described.

[0108] Figure 5 is a diagram of an example semiconductor component 500 described herein. In particular, Figure 5 A top view of a semiconductor component 500 is shown. The semiconductor component 500 may include a semiconductor photonic component and / or other types of semiconductor components including one or more photonic integrated circuits. In particular, the semiconductor component 500 may include an optical modulator structure 202 coupled to an input waveguide 204a and an output waveguide 204b. The optical modulator structure 202 may include a Mach-Zehnder modulator (MZM) structure. In addition, the optical modulator structure 202 may be configured according to the example embodiment 300 to include an L-shaped interface 302 in a PN junction diode 216 of the optical modulator structure 202. The optical modulator structure 202 included in the semiconductor component 500 may use a combination of FIG. 4A to FIG. 4N and / or Figure 6 Described technical formation.

[0109] The MZM structure of the optical modulator structure 202 enables the optical modulator structure 202 to generate a modulated light output from input light provided to the optical modulator structure 202 through the input waveguide 204a. The input light may be split and provided to different arms of the optical modulator structure 202 and modulated in the optical mode of the PN junction diode 216. This enables the input light to be phase modulated by a plurality of phase shifters in the optical modulator structure 202 and then recombined in the output waveguide 204b to form a modulated light output.

[0110] As mentioned above, Figure 5 are provided as examples. Other examples may differ from those described in Figure 5 The content described.

[0111] Figure 6 600 described herein. In some embodiments, one or more semiconductor processing tools (such as 102-114) and / or wafer / die transport tool 116 may include one or more elements 600 and / or one or more components of element 600. Figure 6 As shown, element 600 may include a bus 610 , a processor 620 , a memory 630 , an input component 640 , an output component 650 , and / or a communication component 660 .

[0112] The bus 610 may include one or more components that enable wired and / or wireless communication between components of the element 600. The bus 610 may include: Figure 6 Two or more components of a processor 610 are coupled together, for example, via operational coupling, communication coupling, electronic coupling and / or electrical coupling. For example, bus 610 may include electrical connectors (e.g., wires, traces and / or leads) and / or wireless buses. Processor 620 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable logic gate array, an application-specific integrated circuit and / or other types of processing components. Processor 620 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 620 may include one or more processors that can be programmed to perform one or more operations or manufacturing processes described elsewhere herein.

[0113] The memory 630 may include volatile and / or non-volatile memory. For example, the memory 630 may include random access memory (RAM), read-only memory (ROM), hard disk drive (HDD), and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 630 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 630 may be a non-transitory computer-readable medium. The memory 630 may store information, one or more instructions, and / or software (e.g., one or more software applications) related to the operation of the element 600. In some embodiments, the memory 630 may include, for example, one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 620) via bus 610. The communicative coupling between the processor 620 and the memory 630 may enable the processor 620 to read and / or process information stored in the memory 630 and / or store information in the memory 630.

[0114] Input member 640 can enable element 600 to receive input, such as user input and / or sensed input. For example, input member 640 can include touch screen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, GNSS sensor, accelerometer, gyroscope and / or actuator. Output member 650 can enable element 600 to provide output, such as via display, loudspeaker and / or light emitting diode. Communication member 660 can enable element 600 to communicate with other elements via wired connection and / or wireless connection. For example, communication member 660 can include receiver, transmitter, transceiver, modem, network card and / or antenna.

[0115] Element 600 can perform one or more operations or manufacturing processes described herein. For example, a non-temporary computer-readable medium (e.g., memory 630) can store a set of instructions (e.g., one or more instructions or codes) for execution by processor 620. Processor 620 can execute a set of instructions to perform one or more operations or manufacturing processes described herein. In some embodiments, execution of a set of instructions by one or more processors 620 causes one or more processors 620 and / or element 600 to perform one or more operations or manufacturing processes described herein. In some embodiments, hard-wired circuits can be used to replace or combine instructions to perform one or more operations or manufacturing processes described herein. Additionally or alternatively, processor 620 can be configured to perform one or more operations or manufacturing processes described herein. Therefore, the embodiments described herein are not limited to any specific combination of hardware circuits and software.

[0116] Figure 6 The number and arrangement of components in are provided as examples. The apparatus 600 may include Figure 6 600. In addition or alternatively, one or more components of the component 600 (eg, one or more components) may perform one or more functions described as being performed by another group of components of the component 600.

[0117] Figure 7 is a flow chart of an example manufacturing process 700 associated with forming a semiconductor photonic element. In some embodiments, Figure 7 One or more manufacturing process blocks of are performed by one or more semiconductor processing tools (e.g., one or more semiconductor processing tools (e.g., 102-116)). Additionally or alternatively, Figure 7 One or more manufacturing process blocks of the device 600 may be performed by one or more components of the element 600 , such as the processor 620 , the memory 630 , the input component 640 , the output component 650 , and / or the communication component 660 .

[0118] like Figure 7 As shown, the manufacturing process 700 may include doping a first region of a semiconductor structure of the light modulator structure with a first dopant type using a first implantation mask (block 710). For example, one or more of the semiconductor processing tools (e.g., 102-116) may dope the first region 310 of the semiconductor structure 408 of the light modulator structure 202 with a first dopant type using a first implantation mask (e.g., photoresist layer 410), as described herein.

[0119] like Figure 7 As further shown, the manufacturing process 700 may include doping a second region of the semiconductor structure of the light modulator structure with a second dopant type and a third region of the semiconductor structure of the light modulator structure with a first dopant type using a second implantation mask (block 720). For example, one or more of the semiconductor processing tools (e.g., 102-116) may dope the second region 304 of the semiconductor structure 408 of the light modulator structure 202 with a second dopant type and dope the third region 306 of the semiconductor structure 408 of the light modulator structure 202 with a first dopant type using a second implantation mask (e.g., photoresist layer 416), as described herein. In some embodiments, the second region 304 is adjacent to the first region 310. In some embodiments, the third region 306 is above the second region 304. In some embodiments, the first region 310, the second region 304, and the third region 310 correspond to the PN junction diode 216 of the light modulator structure 202. In some embodiments, the first region 310, the second region 304, and the third region 306 form an L-shaped interface 302 of the PN junction diode 216.

[0120] Manufacturing process 700 may include additional embodiments, such as any single embodiment or any combination of the embodiments described below and / or be associated with one or more other manufacturing processes described elsewhere herein.

[0121] In the first embodiment, doping the second region 304 and the third region 306 includes doping the second region 304 using the second implantation mask in a first implantation operation and doping the third region 306 using the second implantation mask in a second implantation operation subsequent to the first implantation operation.

[0122] In a second embodiment, alone or in combination with the first embodiment, doping the second region 304 and the third region 306 includes doping a first portion 304a in the second region 304 using a second implantation mask in a first implantation operation, doping a second portion 304b in the second region 304 using a second implantation mask in a second implantation operation after the first implantation operation, wherein the second portion 304b is above the first portion 304a, and doping the third region 306 using the second implantation mask in a third implantation operation after the second implantation operation.

[0123] In a third embodiment, alone or in combination with one or more of the first and second embodiments, the implantation energy in the second implantation operation is greater than the implantation energy in the first implantation operation.

[0124] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, doping the first region 310 includes doping the first region 310 while the hard mask layer 406 is above the semiconductor structure 408 of the optical modulator structure 202, and doping the second region 304 and the third region 306 includes doping the second region 304 and the third region 306 after removing the hard mask layer 406 from the semiconductor structure 408 of the optical modulator structure 202.

[0125] In a fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, doping the first region 310 includes doping the first region 310 before forming the STI region 428 around the semiconductor structure 408 of the optical modulator structure 202, and doping the second region 304 and the third region 306 includes doping the second region 304 and the third region 306 after forming the STI region 428 around the semiconductor structure 408 of the optical modulator structure 202.

[0126] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the first dopant type includes a p-type dopant and the second dopant type includes an n-type dopant.

[0127] In a seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, the first dopant type includes n n-type dopants, and the second dopant type includes a p-type dopant.

[0128] although Figure 7 Example blocks of manufacturing process 700 are shown, but in some embodiments, manufacturing process 700 includes Figure 7 Additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. Additionally or alternatively, two or more of the blocks or manufacturing processes 700 may be performed in parallel.

[0129] Thus, an optical modulator structure in a photonic integrated circuit includes an L-shaped PN junction at an optical mode of the optical modulator structure (e.g., a region of the optical modulator structure that generates light). The L-shaped PN junction includes a first portion that includes a first dopant type (e.g., a p-type dopant or an n-type dopant) that overlaps with a second portion that includes a second dopant type that is different from the first dopant type. A first segment of the first portion extends along a side of the second portion. A second segment of the first portion extends along a top of the second portion. The L-shaped PN junction increases the PN junction overlap area at the optical mode relative to other types of junctions, such as a horizontal junction or an I-shaped junction. The increased overlap area can enable the optical modulator structure to achieve higher modulation efficiency.

[0130] As described in more detail above, some embodiments described herein provide a semiconductor element. The semiconductor element includes a dielectric layer. The semiconductor element includes an optical modulator structure in the dielectric layer. The optical modulator structure includes a first region, the first region including a first dopant type. The optical modulator structure includes a second region on a top surface of the first region, the second region including a second dopant type. The first region and the second region correspond to a PN junction diode of the optical modulator structure. In some embodiments, the semiconductor element also includes a third region, the third region is adjacent to one side of the first region and includes a second dopant type, wherein the first region, the second region, and the third region correspond to a PN junction diode of the optical modulator structure. In some embodiments, the semiconductor element also includes a fourth region, the fourth region connects the second region and the third region and includes a second dopant type. In some embodiments, the first dopant type includes a p-type dopant, and the second dopant type includes an n-type dopant. In some embodiments, the first dopant type includes n n-type dopants, and the second dopant type includes a p-type dopant. In some embodiments, the optical modulator structure includes a microring modulator (MRM) structure. In some embodiments, the optical modulator structure includes a Mach-Zehnder modulator (MZM) structure.

[0131] As described in more detail above, some embodiments described herein provide methods. The method includes doping a first region of a semiconductor structure of an optical modulator structure with a first dopant type using a first implantation mask. The method includes doping a second region of the semiconductor structure of the optical modulator structure with a second dopant type and doping a third region of the semiconductor structure of the optical modulator structure with the first dopant type using a second implantation mask. The second region is adjacent to the first region. The third region is above the second region. The first region, the second region, and the third region correspond to a PN junction diode of the optical modulator structure. The first region, the second region, and the third region form an L-type interface of the PN junction diode. In some embodiments, doping the second region and the third region includes: in a first implantation operation, doping the second region using a second implantation mask; and in a second implantation operation after the first implantation operation, doping the third region using a second implantation mask. In some embodiments, doping the second region and the third region includes: in a first implantation operation, doping a first portion of the second region using a second implantation mask; in a second implantation operation after the first implantation operation, doping a second portion of the second region using a second implantation mask, wherein the second portion is above the first portion; and in a third implantation operation after the second implantation operation, doping the third region using the second implantation mask. In some embodiments, the injection energy in the second injection operation is greater than the injection energy in the first injection operation. In some embodiments, doping the first region includes: doping the first region when the hard mask layer is above the semiconductor structure of the optical modulator structure; and doping the second region and the third region includes: doping the second region and the third region after removing the hard mask layer from the semiconductor structure of the optical modulator structure. In some embodiments, doping the first region includes: doping the first region before forming a shallow trench isolation (STI) region around the semiconductor structure of the optical modulator structure; and doping the second region and the third region includes: doping the second region and the third region after forming a shallow trench isolation region around the semiconductor structure of the optical modulator structure. In some embodiments, the first dopant type includes a p-type dopant, and the second dopant type includes an n-type dopant. In some embodiments, the first dopant type includes n n-type dopants, and the second dopant type includes a p-type dopant.

[0132] As described in more detail above, some embodiments described herein provide a semiconductor element. The semiconductor element includes a dielectric layer. The semiconductor element includes an optical modulator structure in the dielectric layer. The optical modulator structure includes a first portion of a PN junction diode of the optical modulator structure, the first portion including a first dopant type. The optical modulator structure includes a second portion of the PN junction diode, the second portion including a second dopant type. The second portion includes a first segment on a top surface of the first portion, a second segment on a side of the first portion, and a third segment connecting the first segment and the second segment. In some embodiments, the semiconductor element also includes an L-shaped interface, the L-shaped interface between the first portion and the second portion. In some embodiments, the thickness of the first portion is greater than the thickness of the first segment of the second portion. In some embodiments, the dopant concentration of the second dopant type in the third segment is greater than the dopant concentration of the second dopant type in the first segment, and the dopant concentration of the second dopant type in the third segment is greater than the dopant concentration of the second dopant type in the second segment. In some embodiments, the carrier concentration in the first segment of the second portion is greater than the carrier concentration in the first portion.

[0133] As used herein, “satisfying a threshold value” may refer to a value greater than a threshold value, greater than or equal to a threshold value, less than a threshold value, less than or equal to a threshold value, equal to a threshold value, not equal to a threshold value, etc., depending on the context.

[0134] The features of several embodiments are summarized above so that those with ordinary knowledge in the art can better understand the aspects of the present disclosure. Those with ordinary knowledge in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other manufacturing processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications to it without departing from the spirit and scope of the present disclosure.

[0135] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A semiconductor element, characterized in that: include: Dielectric layer; as well as a light modulator structure in the dielectric layer and comprising: a first region comprising a first dopant type; as well as a second region on top of the first region and comprising a second dopant type, The first region and the second region correspond to the PN junction diodes of the optical modulator structure.

2. The semiconductor device according to claim 1, characterized in that Also includes: a third region adjacent to one side of the first region and comprising the second dopant type, The first region, the second region and the third region correspond to the PN junction diode of the optical modulator structure.

3. The semiconductor device according to claim 2, characterized in that Also includes: A fourth region connects the second region and the third region and includes the second dopant type.

4. The semiconductor device according to claim 1, wherein: The first dopant type comprises a p-type dopant; and The second dopant type includes n-type dopants.

5. The semiconductor device according to claim 1, wherein: The first dopant type includes n n-type dopants; and The second dopant type includes p-type dopants.

6. A semiconductor element, characterized in that: include: Dielectric layer; as well as a light modulator structure in the dielectric layer and comprising: The first part of the PN junction diode of the optical modulator structure, wherein the first portion comprises a first dopant type; and The second part of the PN junction diode, wherein the second portion comprises a second dopant type, and The second part includes: a first section, on a top surface of the first portion; a second section on the side of the first portion; and The third segment connects the first segment and the second segment.

7. The semiconductor device according to claim 6, characterized in that Also includes: An L-shaped interface is between the first portion and the second portion.

8. The semiconductor device according to claim 6, characterized in that The thickness of the first portion is greater than the thickness of the first section of the second portion.

9. The semiconductor device according to claim 6, characterized in that a dopant concentration of the second dopant type in the third segment is greater than a dopant concentration of the second dopant type in the first segment; and Wherein the dopant concentration of the second dopant type in the third segment is greater than the dopant concentration of the second dopant type in the second segment.

10. The semiconductor device according to claim 6, characterized in that The carrier concentration in the first section of the second portion is greater than the carrier concentration in the first portion.

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