Semiconductor package

Abstract

The utility model provides a semiconductor packaging piece. The semiconductor package includes at least a redistribution layer, a semiconductor die, an interconnect block, and a molding compound. A semiconductor die is disposed on the redistribution layer, and an interconnect block is disposed on the redistribution layer and alongside the semiconductor die. The interconnect block includes an insulative encapsulation and a through insulator via penetrating the insulative encapsulation. A molding compound disposed on the redistribution layer laterally surrounds the semiconductor die and the interconnect block. The interconnect block is spaced apart from the semiconductor die by a molding compound therebetween. The through insulator vias are isolated from the molding compound by the insulating encapsulation.

Description

Technical Field

[0001] The embodiment of the utility model relates to a semiconductor package. Background Art

[0002] Following the development of 3D integration technology for wafer-level packaging, in order to meet the demand for smaller size matching, it is necessary to continue to develop interconnect components with smaller size and high performance that can be used in high-density integrated packages. Utility Model Content

[0003] An embodiment of the utility model provides a semiconductor package including a first redistribution layer, a semiconductor die, an interconnection block and a molding compound. The semiconductor die is arranged on the first redistribution layer, and the active surface of the semiconductor die faces the first redistribution layer. The interconnection block is arranged on the first redistribution layer, next to the semiconductor die. The interconnection block includes an insulating encapsulation and a first through-insulator via (TIV) penetrating the insulating encapsulation. The molding compound is arranged on the first redistribution layer and laterally surrounds the semiconductor die and the interconnection block. The interconnection block is separated from the semiconductor die by the molding compound located therebetween. The first TIVs is isolated from the molding compound by the insulating encapsulation. The first TIVs is electrically connected to the first redistribution layer.

[0004] The present invention provides a semiconductor package including a first redistribution layer, a semiconductor die, an interconnection block and a molding compound. The first redistribution layer includes a plurality of wiring layers. The semiconductor die is located above the first redistribution layer. The interconnection block is arranged next to the semiconductor die and is located above the first redistribution layer. The interconnection block includes an encapsulation body and a through-insulator via extending through the encapsulation body. The through-insulator via directly contacts at least one of the plurality of wiring layers of the first redistribution layer. The molding compound is arranged between the semiconductor die and the interconnection block.

[0005] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 4 are schematic cross-sectional views of various stages in a method of manufacturing an interconnect block according to some exemplary embodiments of the present invention.

[0008] Figure 5 is a schematic cross-sectional view of a semiconductor die provided according to some exemplary embodiments of the present disclosure.

[0009] Figures 6 to 13 are schematic cross-sectional views of various stages in a method of manufacturing a semiconductor package according to some exemplary embodiments of the present disclosure.

[0010] FIG. 14A to FIG. 14F FIG. 1 is a schematic top view of an interconnection block of a semiconductor package according to some exemplary embodiments of the present invention.

[0011] Fig.15 and Fig.16 is a schematic top view illustrating a portion of a semiconductor package according to some exemplary embodiments of the present disclosure.

[0012] Fig.17 is a schematic cross-sectional view illustrating a semiconductor package according to some exemplary embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a second feature on or on a first feature may include an embodiment in which the second feature and the first feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the second feature and the first feature so that the second feature and the first feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than itself representing the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "on," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] In addition, for the convenience of description, terms such as "first", "second", "third", "fourth", etc. may be used herein to describe similar or different components or features as illustrated, and may be used interchangeably according to the order of appearance or the context of description.

[0016] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) component. The test structure may include, for example, a test pad formed in a redistribution layer or formed on a substrate, which enables the 3D package or 3DIC to be tested, the use of probes and / or probe cards, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods that incorporate intermediate verification of known good dies to improve yield and reduce costs.

[0017] Figures 1 to 4 Schematic cross-sectional views of various stages in a method of manufacturing an interconnect block according to some exemplary embodiments of the present invention.

[0018] refer to Figure 1 In some embodiments, a carrier 102 is provided on which a buffer layer 104 is coated. The carrier 102 may be a glass carrier or any suitable carrier for carrying a semiconductor wafer or a reconstructed wafer for a semiconductor packaging manufacturing method. In some embodiments, the buffer layer 104 includes a peeling layer. The material of the peeling layer may be any material suitable for bonding and separating the carrier 102 from the upper layer or wafer. In some embodiments, the buffer layer 104 includes, for example, a light-to-heat conversion layer (LTHC), which can be peeled off from the carrier at room temperature by using laser irradiation. Figure 1 In some embodiments, the buffer layer 104 includes a dielectric material layer made of a dielectric material including benzocyclobutene (BCB), polybenzoxazole (PBO) or any other suitable polymer dielectric material. In an embodiment, a seed layer 106 is formed on the buffer layer 104. In some embodiments, the seed layer 106 includes a metal layer formed by at least sputtering or deposition. In an embodiment, the seed layer 106 includes a copper layer. A mask pattern 107 is then formed directly on the seed layer 106, and the opening S1 of the mask pattern 107 exposes a portion of the seed layer 106 at a position corresponding to the position of the through-insulator via (TIVs) to be formed. In some embodiments, the mask pattern 107 is formed by spin coating a photoresist layer (not shown) and then patterning the photoresist layer by photolithography and etching processes to form the opening S1. In some embodiments, the openings S1 are substantially the same size and have approximately the same top view shape (top view shape). In some embodiments, the openings S1 can be divided into different types, with different cross-sectional area sizes and / or various top-view shapes. It should be understood that the number of openings and the opening-related sizes / shapes shown in the figures or described in the embodiments are only exemplary and illustrative, and are not intended to further limit the scope of the present disclosure.

[0019] refer to Figure 2 In some embodiments, after removing the mask pattern 107, TIVs (through-insulator vias) 120 are formed on the buffer layer 104 on the substrate 102. In some embodiments, together with the fan-out redistribution layer formed subsequently, the TIVs 120 can serve as through-integrated fan-out (InFO) vias. In some embodiments, as Figure 1 and Figure 2 As shown in , the formation of TIVs 120 includes forming a mask pattern 107 with an opening S1 on the seed layer 106, and the opening S1 exposes a portion of the seed layer 106 at a predetermined position. Afterwards, with the seed layer 106 as a seed, a metal-like material 109 is electroplated in and on the opening S1 to fill the opening S1. Alternatively, the metal-like material 109 is deposited in the opening S1 and fills the opening S1. Subsequently, the mask pattern 107 is removed by performing an etching process or a stripping process, and an etching process is performed using the TIVs 120 as a mask to partially remove the seed layer 106. That is, the seed layer 106 not covered by the metal-like material 109 is removed, leaving the seed pattern 106P (the remaining seed layer 106 is located under the metal-like material 109). In some embodiments, when the seed layer 106 is partially removed to form the seed pattern 106P, the mask pattern 107 is removed at the same time. Refer to Figure 1 and Figure 2 , TIVs 120 are formed in the opening S1 ( Figure 1 ). In some embodiments, each TIV 120 includes a seed pattern 106P and a metal-like material 109 directly on the seed pattern 106P. Even if the seed layer 106 is partially removed or patterned, the buffer layer 104 still exists.

[0020] In some embodiments, the material of the seed layer 106 depends on the metal type material of the TIVs to be formed later. In an embodiment, the seed layer 106 includes a copper layer. In some embodiments, the seed layer 106 ( Figure 1 ) is first formed on the buffer layer 104 on the carrier 102 by sputtering to form a composite layer of a titanium layer and a copper layer, and the metal material 109 is then filled in the opening S1 of the mask pattern 107 by electroplating copper or a copper alloy. However, it should be understood that the scope of the present disclosure is not limited to the materials and descriptions disclosed above. In some embodiments, the TIVs 120 are metal columns or tubes with a circular, oval or elliptical top view, or even a polygonal shape from a top view. In some embodiments, the TIVs 120 are plated copper columns with a size (or diameter) ranging from about 10 microns to about 200 microns.

[0021] refer to Figure 3In some embodiments, an encapsulant 130 is formed on the carrier 102 to cover the TIVs 120 on the buffer layer 104 to form a molded structure 13, and the TIVs 120 on the carrier 102 are completely encapsulated and molded in the encapsulant 130. In some embodiments, the encapsulant 130 covers the buffer layer 104 and fills between the TIVs 120, and the molded structure 13 is in the form of a wafer or a panel. In some embodiments, the encapsulant 130 completely covers all the TIVs 120 and at least laterally encapsulates the entire sidewall of the TIVs 120, and the surface 120T ( Figure 3 In some embodiments, the encapsulant 130 is formed to encapsulate the TIVs 120 and completely cover the top surface 120T of the TIVs 120, and a trimming process including a planarization process is performed to remove excess encapsulant material on the top surface 120T of the TIVs 120.

[0022] In some embodiments, the encapsulant 130 is formed by a molding technique such as injection molding, transfer molding, compression molding or overmolding. In an exemplary embodiment, the molding technique uses a mold with a release film coated on its inner surface to control the solidified molding material to cover the TIVs 120. In an exemplary embodiment, the material of the encapsulant 130 includes a polymer material without filler particles, and the polymer material is selected from a low-temperature curable polyimide material, an epoxy resin, BCB, PBO or any other suitable polymer dielectric material. Since the polymer material without filler particles has better fluidity, the encapsulant formed by such a polymer material provides better coverage and filling capacity for TIVs 120. In some embodiments, the material of the encapsulant 130 is an insulating material, comprising at least one resin containing a filler. In an exemplary embodiment, the resin includes an epoxy resin, a phenolic resin or a silicon-containing resin, and the filler is a particle composed of a non-melting inorganic material. For example, the filler includes metal oxide particles, silica particles or silicate particles, and the average particle size ranges from about 3 microns to about 20 microns. If zero filler or fine filler particles are used, the encapsulation can have better surface smoothness and flatness.

[0023] In some embodiments, the trimming process includes performing a planarization process, such as a chemical mechanical polishing (CMP) process, a mechanical grinding process, a laser ablation process, and / or a combination thereof, to remove excess material of the encapsulant 130 above the top surface 120T of the TIVs 120 until the top surface 120T of the TIVs 120 is exposed. That is, the top surface 120T of the TIVs 120 is flush with the ground surface 130T of the encapsulant 130. In some embodiments, if the top surface 120T of the TIVs 120 has been exposed from the encapsulant 130, the trimming process or planarization can be omitted. Afterwards, an inspection process is performed to check whether the TIVs 120 are intact (without pores or defective points) by inspecting the exposed surface 120T and verifying whether the TIVs 120 have substantially the same height and whether the top surface 120T of the TIVs 120 is substantially completely exposed from the encapsulant 130. If any TIVs are found to be defective or unusable, they will be flagged and excluded from subsequent use.

[0024] refer to Figure 3 and Figure 4 , transfer the molded structure 13 to another carrier C1. In some embodiments, the carrier C1 is a film-type carrier. In certain embodiments, the carrier C1 is attached to the surface of the molded structure 13, and the carrier C1 contacts the exposed surface 120T of the TIVs 120 and the surface 130T of the encapsulant 130. The entire structure including the carrier 102, C1 and the molded structure 13 is then flipped (inverted), the molded structure 13 is separated from the carrier 102, and the carrier 102 is removed together with the buffer layer 104. As the molded structure 13 is flipped and separated from the carrier 102, the surface 120B (opposite to the surface 120T) of the TIVs 120 is exposed, and the surface 120T is covered by the carrier C1. As shown Figure 4 As shown in FIG. 1 , the seed pattern 106P of the TIVs 120 is exposed from the encapsulation body 130. In some embodiments, a cutting process is performed to cut the molded structure 13 along cutting streets (indicated by dotted lines) into a plurality of interconnected blocks 135. In some embodiments, the cutting process includes performing mechanical sawing or laser cutting. Figure 4 In FIG. 1 , the dotted lines indicate that a subsequent sawing process is performed on sawing streets of the entire structure, and some TIVs 120 are close to but not on the sawing streets, and the sidewalls of these TIVs 120 will be exposed after the sawing process.

[0025] After that, an inspection process is performed to check whether any TIVs 120 are incomplete or have voids or damage by inspecting the exposed surface 120B, and whether the surface 120B of the TIVs 120 is exposed from the encapsulation 130. If any TIVs are found to be defective or lacking in function during any inspection process, the block containing the defective TIVs will be rejected and excluded. That is, after passing the inspection process, the remaining interconnection blocks 135 contain through-hole structures that are known to be good.

[0026] In some embodiments, each interconnect block 135 includes a plurality of TIVs 120 laterally encapsulated by the encapsulant 130. In some embodiments, opposite surfaces 120B / 120T of the columnar TIVs 120 are exposed from the encapsulant 130, while the sidewalls of the TIVs 120 are completely encapsulated by the encapsulant 130.

[0027] FIG. 14A to FIG. 14F FIG. 1 is a top view schematic diagram of an interconnection block suitable for a semiconductor package according to some exemplary embodiments of the present invention. Fig.14A , the interconnect block 135A includes a plurality of TIVs 1202A embedded in the package 1200, and the TIVs 1202A are arranged in an array. Fig.14A In the interconnect block 135A, each TIV 1202A is circular with a diameter d1 in a top view, and the TIVs 1202A are arranged in two columns along the Y-direction and in five rows along the X-direction perpendicular to the Y-direction. In some embodiments, the TIVs 1202A in the same column are separated by the same pitch P1, and the TIVs 1202A in the same row are separated by the same pitch P2.

[0028] exist Fig. 14B In FIG. 1 , for interconnect block 135B, TIVs 1202B are arranged in an array and arranged in three columns along the Y-direction. Fig. 14B As shown, the TIVs 1202B in one column are arranged offset from the TIVs 1202B in the next column, so that the TIVs 1202B in the left and right columns are arranged in six rows along the X-direction, and there are 7 TIVs 1202B in the middle column. In some embodiments, the TIVs 1202B in the same column are separated by the same pitch P3. For example, the top view shape of each TIV 1202B is an ellipse, and has substantially the same size (for example, the major axis of the ellipse has the same length a1, and the minor axis has the same width b1). Fig.14A and Fig. 14B From the top view of FIG. 1 , interconnect blocks 135A and 135B are symmetrical blocks because the arrangement of the TIVs is symmetrical about the middle line (dashed line) of the blocks.

[0029] refer to Fig. 14C, the interconnect block 135C includes TIVs 1202C1 (circular top view shape) and larger TIVs 1202C2 (circular top view shape) embedded in the encapsulation 1200 . Fig. 14C In the figure, five TIVs 1202C1 (each circular TIVs 1202C1 has the same diameter d2) are aligned and arranged in a row along the Y-direction (left column), and four TIVs 1202C2 (each circular TIVs 1202C2 has the same diameter d3, d3>d2) are aligned and arranged in a row along the Y-direction (right column). Fig. 14C As shown in FIG. 1 , TIVs 1202C1 in one column are spaced apart from each other by the same pitch P4, while TIVs 1202C2 in the next column are spaced apart from each other by the same pitch P5.

[0030] refer to Fig.14D , the interconnect block 135D includes TIVs 1202D1 (oval top view shape), larger TIVs 1202D2 (circular top view shape) and largest TIVs 1202D3 (oval top view shape) embedded in the package 1200 . Fig.14D In the figure, seven TIVs 1202D1 are aligned in a row along the Y-direction (left row), five TIVs 1202D2 (each circular TIV 1202D2 has the same diameter d4) are aligned in a row along the Y-direction (middle row), and four TIVs 1202D3 are aligned in a row along the Y-direction (right row). Fig.14D As shown in , each TIVs 1202D1 has an elliptical top view shape and has substantially the same size (e.g., the ellipse has the same length a2 on the major axis (X-direction) and the same width b2 on the minor axis (Y-direction)), and each TIVs 1202D3 has an elliptical top view shape and has substantially the same size (e.g., the same length a3 on the major axis (Y-direction) of the ellipse and the same width b2 on the minor axis (X-direction)). That is, the elliptical TIVs 1202D1 in the column are arranged with the major axis parallel to the X-direction, while the TIVs 1202D3 are arranged with the major axis parallel to the Y-direction. In some embodiments, since a3>b3≥d4, each TIVs 1202D3 is larger than TIVs 1202D2. In some embodiments, since a3 is greater than a2 (a3>a2) and b3 is greater than b2 (b3>b2), each TIVs 1202D3 is greater than TIVs 1202D1. Fig. 14C and Fig.14D From the top view of FIG. 1 , interconnection blocks 135C and 135D are asymmetric blocks because the arrangement of the TIVs is not symmetrical about the midline of the blocks.

[0031] See also Fig.14EIn the top view, the interconnection block 135E includes a plurality of TIVs 1202E (elliptical top view shape) embedded in the encapsulation body 1200, and the spaced TIVs 1202E are arranged in parallel to form two inverted L shapes. Fig.14E In the interconnect block 135E, the TIVs 1202E in the same row or column are spaced apart from each other at the same pitch P6, and each TIV 1202E has the same top view shape and size (eg, the major axis has the same length a4 and the minor axis has the same width b4 in an ellipse).

[0032] exist Fig.14F In some embodiments, interconnect block 135F includes TIVs 1202F arranged in four columns along the Y-direction, and TIVs 1202F in one column are arranged offset from TIVs 1202F in the next column, so that the TIVs in the left column and the TIVs in the next column below it are aligned in four rows along the X-direction, and the TIVs in the right column and the TIVs in the next column below it are aligned in three rows along the X-direction. In some embodiments, each TIV 1202F is oval or stadium-shaped when viewed from a top view, and has substantially the same top view area (i.e., the same cross-sectional area size). In some embodiments, interconnect blocks 135E and 135F can be used as corner blocks, and can also be disposed at or near the corners of the package.

[0033] By forming interconnect blocks 135 and 135A-135F, through-hole vias that penetrate the insulating material can be prepared in different groups in a pre-formed and pre-packaged manner and provided in the form of a block. In addition, according to the design of the integrated circuit component or part, various types of TIVs, including TIVs of different sizes (cross-sectional area size or diameter), shapes or spacings, can be combined and integrated to obtain a better interconnection structure.

[0034] Figure 5 is a schematic cross-sectional view of a semiconductor die provided according to some exemplary embodiments of the present disclosure.Herein, chip and die may be used interchangeably throughout the context of the present disclosure.

[0035] refer to Figure 5 In some embodiments, a semiconductor die 200 including a semiconductor component or an integrated circuit component is formed on the temporary carrier C2. In some embodiments, the semiconductor die 200 may be formed from a wafer or a reconstructed wafer (not shown), which includes a plurality of semiconductor dies 200 arranged in an array, and the wafer is singulated to form individual semiconductor dies 200.

[0036] In some embodiments, reference Figure 5, each die 200 includes a semiconductor substrate 202, a plurality of conductive pads 204, a passivation layer 206, a post-passivation layer 208, a plurality of conductive pillars 210, and a protective layer 212. In some embodiments, the conductive pad 204 is disposed on the semiconductor substrate 202, and the passivation layer 206 is formed on the semiconductor substrate 202 and has a contact opening to expose the conductive pad 204. For example, the semiconductor substrate 202 may be a silicon substrate or an insulating layer-coated silicon substrate, and the semiconductor substrate 202 includes active components (such as transistors, diodes, or the like) and / or passive components (such as resistors, capacitors, inductors, or the like) formed therein. The conductive pad 204 may be an aluminum pad, a copper pad, or other suitable metal pad. The passivation layer 206 may be or include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials. The post passivation layer 208 formed on the passivation layer 208 may be or include a polyimide (PI) layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed by other suitable polymers. In addition, the conductive pillar 210 is formed on the conductive pad 204 by plating. In some embodiments, the conductive pillar 210 is electrically connected to the conductive pad 204 as a contact end. The protective layer 212 is formed on the post passivation layer 208 to completely cover the conductive pillar 210. In other words, the conductive pillar 210 is not exposed and is protected by the protective layer 212. The protective layer 212 may be or include a polymer material, such as PI, PBO or other inorganic dielectric materials. The conductive pillar 210 may be or include a copper pillar, a copper alloy pillar or other suitable metal pillar. In some embodiments, the top surface 200T of the semiconductor die 200, which is away from the carrier C2, can be regarded as the active surface of the die 200, and the back surface 200B of the semiconductor die 200 is covered by the carrier C2.

[0037] Figures 6 to 13 1 is a schematic cross-sectional view of various stages in a method for manufacturing a semiconductor package according to some exemplary embodiments of the present disclosure. In exemplary embodiments, the method for manufacturing a semiconductor package may be part of a wafer-level packaging process. In some embodiments, a single chip (or die) represents one or more chips (or dies) in a wafer, and one or more packages 10 represent multiple semiconductor packages obtained after the semiconductor manufacturing method.

[0038] Reference Figure 6 , a carrier 602 coated with a buffer layer 604 is provided, and the carrier 602 and the buffer layer 604 are similar to the carrier 102 and the buffer layer 104 described in the previous paragraph. In some embodiments, the buffer layer 604 includes a release layer, such as a LTHC layer. Figure 6 In some embodiments, a die attach film 606 is formed on the buffer layer 604 to provide better adhesion for subsequent placement or installation of components.

[0039] Reference Figure 6 , one or more semiconductor dies 200 (taking a single die as an example) are provided and disposed on a die attach film 606 on a carrier 602 and a buffer layer 604. In addition, an interconnection block 400 is disposed on the die attach film 606 and around the semiconductor die 200. In some embodiments, the semiconductor die 200 and the interconnection block 400 are placed on the die attach film 606 by a pick-up method. In an exemplary embodiment, at least one semiconductor die 200 and the interconnection block 400 are placed on the die attach film 606. Figure 5 The semiconductor die 200 shown in FIG. 1 is similar or substantially the same as the semiconductor die 200 shown in FIG. 1 and may include Figure 5 , the semiconductor substrate 202, the conductive pad 204, the passivation layer 206, the post-passivation layer 208, the conductive pillar 210 and the protective layer 212 shown in . However, it should be understood that the same type of chips or different types of chips can be provided in the plurality of semiconductor chips provided, and more than one semiconductor chip can be provided. In some embodiments, the semiconductor die 200 includes one or more selected from logic chips, memory chips, voltage regulator chips, digital chips, analog chips or mixed signal chips, such as application specific integrated circuits ("ASIC") chips, sensor chips, wireless and radio frequency chips. In some embodiments, the semiconductor die 200 includes an integrated circuit (IC) integrated central processing unit (CPU), a graphics processing unit (GPU), a single chip system (SoC), an application processor (AP) and a microcontroller, etc. In an exemplary embodiment, the interconnection block 400 may be similar to the interconnection blocks 135 and 135A-135F described in the previous paragraph. For example, the interconnection block 400 includes TIVs 420 embedded in the encapsulation body 430, and the TIVs 420 include a seed pattern 406. As previously described, encapsulant 430 includes an insulating polymer material having a different dielectric constant than silicon.

[0040] In some embodiments, Figure 6 In the embodiment, the semiconductor die 200 is disposed on the die bonding film 606, with its front / active surface 200T contacting the die bonding film 606, and the other surface 200B (semiconductor substrate 202) of the semiconductor die 200 facing upward and exposed. Therefore, the front surface 200T of the semiconductor die 200 is bonded to the die bonding film 606. In some embodiments, the interconnect block 400 is directly placed on the die bonding film 606, with its back surface 400B contacting the die bonding film 606, and the front surface 400T of the interconnect block 400 facing upward and exposed. In some embodiments, the interconnect block 400 is bonded to the die bonding film 606, with the seed pattern 406 of the TIVs 420 bonded to the die bonding film 606. As shown in FIG. Figure 6 As shown, the conductive pillars 210 of the die 200 are separated from the die attach film 606 by the protection layer 212 .

[0041] In some embodiments, the interconnect block 400 is disposed beside and around the semiconductor die 200 on the substrate 602. In some embodiments, the interconnect block 400 is arranged such that the TIVs 420 in the interconnect block 400 surround the semiconductor die 200. Figure 6 As shown, interconnect block 400 is located beside and spaced apart from semiconductor die 200. In some embodiments, interconnect block 400 is spaced apart from semiconductor die 200 by a distance dd1. In some embodiments, interconnect block 400 is disposed beside and adjacent to semiconductor die 200.

[0042] refer to Figure 6 In some embodiments, the semiconductor die 200 and the interconnection block 400 have different heights (thickness in the Z-direction). In an exemplary embodiment, the height h2 of the semiconductor die 200 is less than the height h1 of the interconnection block 400. That is, the surface 200B of the semiconductor die 200 is lower than the surface 400T of the interconnection block 400.

[0043] In alternative embodiments, semiconductor die 200 and interconnect block 400 may have substantially the same height. In other embodiments, semiconductor die 200 is thicker than interconnect block 400 .

[0044] Reference Figure 7 In some embodiments, a molding compound 230 is formed on the carrier 602 to cover the semiconductor die 200 and the interconnection block 400 (including TIVs 420) located on the carrier 602, so that the interconnection block 400 and the semiconductor die 200 are encapsulated in the molding compound 230 to form a molding structure 17. In some embodiments, the molding compound 230 covers the die bonding film 606, fills between the semiconductor die 200 and the interconnection block 400, and fills the space between the semiconductor die 200 and the interconnection block 400. In certain embodiments, the molding structure 17 is in the form of a wafer or a panel. Since there may be a height difference between the semiconductor die 200 and the interconnection block 400, the molding compound 230 at least completely covers the lowest component among the molded components. As in Figure 7 As shown in FIG. 4 , the mold compound 230 surrounds the entire sidewalls of the semiconductor die 200 and the interconnect block 400 , while the cover surrounds the entire sidewalls.

[0045] In some embodiments, the molding compound 230 is formed by a molding technique such as injection molding, transfer molding, compression molding, or overmolding. In an exemplary embodiment, the molding technique ensures that the cured material covers the interconnect block 400 and the semiconductor die 200. In some embodiments, the material of the molding compound 230 is an insulating material, comprising at least one resin containing a filler. In an exemplary embodiment, the resin comprises an epoxy resin, a phenolic resin, or a silicon-containing resin, and the filler is a particle non-melting inorganic material, and the filler comprises metal oxide particles, silicon dioxide particles, or silicate particles, and the average particle size is about 3 microns to about 20 microns.

[0046] In some embodiments, the material of the mold compound 230 is substantially the same as the material of the encapsulant 430 of the interconnection block 400. In some embodiments, the material of the mold compound 230 is different from the material of the encapsulant 430 of the interconnection block 400. In some embodiments, the material in the encapsulant 430 includes an epoxy resin without filler particles, and the material in the mold compound 230 includes an epoxy resin with filler particles (such as metal oxide particles or silicon dioxide particles). In some embodiments, the material of the encapsulant 430 includes an epoxy resin and a first filler, and the material of the mold compound 230 includes an epoxy resin and a second filler having a larger particle size than the first filler.

[0047] In some embodiments, for Figure 7 The molded structure 17 shown has an interface SF between the sidewalls of the interconnect block 400 and the mold compound 230. Regardless of the choice of material, the interface SF exists between the encapsulant 430 and the mold compound 230 because the interconnect block 400 is preformed before the mold compound 230 is formed.

[0048] In an exemplary embodiment, the molding compound 230 is formed to completely cover the surface 400T of the interconnect block 400 and the surface 200B of the semiconductor die 200 (i.e., overmolding), and then a trimming process including a planarization process is performed to remove excess molding compound. In some embodiments, since the semiconductor die 200 is lower (due to the smaller height / thickness of the semiconductor die 200), a planarization process is performed to remove the portion of the interconnect block 400 located above the surface 200B, and to remove excess molding compound material located above the surface 200B to achieve the same thickness (same horizontal plane). In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process, a mechanical grinding process, a laser ablation process, and / or a combination thereof. After the grinding or grinding process, a cleaning step may be optionally performed to clean and remove residues produced by grinding or cutting. However, the present disclosure is not limited thereto, and the planarization process may be performed by any other suitable method.

[0049] In some embodiments, during the trimming process, the interconnection block 400 is trimmed to the same level as the semiconductor die 200 (e.g., having the same height h2), and the excess molding compound 230 material located above the surface 200B of the semiconductor die 200 is removed until the surface 200B is exposed. That is, the ground surface 400T′ of the interconnection block 400 is flush and at the same level as the surface 200B of the semiconductor die 200. In some embodiments, as the interconnection block 400 is trimmed to be thinner, portions of the encapsulant 430 and portions of the TIVs 420 are removed (through polishing or grinding), but the ends of the TIVs 420 are still exposed from the encapsulant 430 to further achieve electrical connection.

[0050] In some embodiments, when the interconnection bump 400 and the semiconductor die 200 have substantially the same height / thickness, a trimming process can still be performed to remove excess material of the molding compound 230 located above the surfaces of the semiconductor die 200 and the interconnection bump 400 so that the TIVs 420 are exposed for further electrical connection.

[0051] In some embodiments, the active surface 200T of the semiconductor die 200 faces downward and is covered by the die attach film 606, and the trimming process is performed on the back side of the semiconductor die 200. Since the trimming process is performed on the semiconductor substrate 202 (i.e., toward the backside surface 200B), the process margin of the trimming process becomes larger because a slight over-grinding at the back side of the semiconductor substrate is acceptable. In addition, by pre-forming and providing the interconnect block 400, the TIVs 420 are fixed in the encapsulation body 430 before forming the molding compound 230, ensuring that the TIVs 420 will not tilt or collapse during the molding process. Therefore, the reliability of the TIVs 420 is further improved.

[0052] like Figure 7 As shown, the surface 200B of the semiconductor die 200 and the surface 400T′ of the interconnect block are exposed from the mold compound 230. Figure 7 In the molded structure 17 shown, there is an interface SF between the sidewall of the interconnection block 400 and the mold compound 230. Here, the interface SF exists between the encapsulant 430 and the mold compound 230 because the interconnection block 400 including the TIVs 420 wrapped by the encapsulant 430 is pre-formed and provided before the molding process of the mold compound 230. Since the interconnection block 400 with the known good TIVs 420 is pre-formed and provided before the mold compound 230 is formed, the possibility of rework due to TIVs failure is greatly reduced, the product yield is increased, and the product cost is correspondingly reduced.

[0053] refer to Figure 8In some embodiments, a redistribution layer 500 is formed on the mold compound 230, on the semiconductor die 200, and on the interconnection block 400. In some embodiments, the redistribution layer 500 is formed on the surface 400T' of the interconnection block 400 and the surface 200B of the semiconductor die 200. The formation of the redistribution layer 500 includes successively and alternately forming one or more layers of dielectric material and one or more layers of metallization (wiring) layers. In some embodiments, the redistribution layer 500 includes at least a wiring pattern 510 and a metallization pattern 520 sandwiched between the dielectric material 502. Figure 8 In the embodiment of the present invention, at least the bottom wiring pattern 512 of the wiring pattern 510 is physically and electrically connected to the TIVs 420 of the interconnect block 400. In some embodiments, the metallization pattern 520 including the bottom thermal via 522 is physically in contact with the substrate 202 of the semiconductor die 200, and the metallization pattern 520 is electrically floating and can serve as a heat dissipation component. It can be understood that the bottom thermal via 522 and the bottom wiring pattern 512 can be formed simultaneously when forming the bottom metallization layer (or wiring layer) of the redistribution layer 500, and the bottom thermal via 522 and the bottom wiring pattern 512 can both be part of the bottom wiring layer.

[0054] In some embodiments, the wiring pattern 510 and the metallization pattern 520 are part of a metallization layer, and the material in the metallization layer includes copper, titanium, nickel, aluminum, tungsten, silver and / or an alloy. In some embodiments, the material of the dielectric material 502 includes polyimide, BCB or PBO. In some embodiments, since the redistribution layer 500 is formed on the back side of the semiconductor die 200, the redistribution layer 500 can be regarded as a backside redistribution layer, which is electrically connected to the TIVs 420 of the interconnection block 400. In some embodiments, the molding structure 17 (including the molding compound 230, the semiconductor die 200 and the interconnection block 400) as the bottom layer provides better flatness and uniformity. For the redistribution layer 500 formed later, especially the metallization pattern with fine line width or tight spacing, a uniform line width or smooth profile can be formed on the flat and flush molding structure 17, thereby improving the wire / wiring reliability.

[0055] Reference Fig. 9 After forming the redistribution layer 500, a carrier 612 having a buffer layer 614 and a die attach film 616 thereon is provided and attached to the redistribution layer 500. For example, the carrier 612, the buffer layer 614, and the die attach film 616 are similar or substantially the same as the carrier 602, the buffer layer 604, and the die attach film 606 described in the previous paragraph. In some embodiments, the die attach film 616 is attached to the top surface 500T of the redistribution layer 500.

[0056] refer to Fig.10, the entire structure including the carriers 602 and 612 and the molded structure 17 is flipped (inverted), the molded structure 17 is separated from the carrier 602, and then the carrier 602 is removed. With the flipping of the molded structure 17 and the separation of the carrier 602, the surface 400B (opposite to the surface 400T') of the interconnect block 400 is exposed, and the surface 200T of the semiconductor die 200 is exposed. Fig.10 In some embodiments, the seed pattern 406 of the TIVs 420 of the interconnect block 400 is exposed from the encapsulation body 430 , and the protection layer 212 of the semiconductor die 200 is exposed.

[0057] refer to Fig.10 and Fig.11 , a planarization process is performed to remove part of the molded structure 17 to form a molded structure 17' having a uniform height h3 (thickness in the Z-direction). In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process, a mechanical grinding process, or a combination thereof. After the grinding or grinding process, a cleaning step may be selectively performed. In some embodiments, a planarization process is performed on the semiconductor die 200 to remove the protective layer 212 and expose the conductive pillar 210. At the same time, in the planarization process, the interconnect block 400 is also partially removed. Fig.11 As shown, after the planarization process, the conductive pillar 210 is exposed from the polished surface 200T', and the remaining protective layer surrounds the conductive pillar 210. In some embodiments, the end of the TIVs 420 is exposed from the polished surface 400B' of the interconnect block 400, but the seed pattern 406 (see Fig.10 ) are removed after the planarization process. During the planarization process, excess molding compound material above the surface 200T' of the semiconductor die 200 and the surface 400B' of the interconnection block 400 is removed to reach the same level. After the planarization process, the ground surface 400B' of the interconnection block 400 is coplanar and flush with the surface 200T' of the semiconductor die 200 and the top surface 230T of the molding compound 230. In some embodiments, as the interconnection block 400 is planarized and becomes thinner, portions of the encapsulant 430 and portions of the TIVs 420 are removed (polished or ground), but the ends of the TIVs 420 are still exposed from the encapsulant 430 for further electrical connection. Through the trimming process and the planarization process, the semiconductor die 200 and the interconnection block 400 in the molding structure 17' have approximately the same height (or thickness) in the thickness direction (Z-direction). As Fig.11 As shown, the molding compound 230 surrounds and encapsulates the entire sidewalls of the interconnect block 400 and the semiconductor die 200 , and the TIVs 420 of the interconnect block 400 are laterally encapsulated by the encapsulant 430 , but the TIVs 420 are separated from the molding compound 230 by the encapsulant 430 .

[0058] refer to Fig.12 In some embodiments, a redistribution layer 700 is formed on the mold compound 230, on the semiconductor die 200, and on the interconnect block 400. In some embodiments, the redistribution layer 700 is formed on the surface 400B' of the interconnect block 400 and the surface 200T' of the semiconductor die 200. Similarly, the formation of the redistribution layer 700 includes successively and alternately forming one or more layers of dielectric material and one or more layers of metallization. In certain embodiments, the redistribution layer 700 includes at least a wiring layer 710 sandwiched between dielectric materials 702. In some embodiments, the bottommost wiring layer 712 of the wiring layer 710 includes metal vias 714, which are respectively connected to the conductive pillars 210 of the semiconductor die 200 and the TIVs 420 of the interconnect block. In Fig.12 In FIG. 4 , the bottommost wiring layer 712 of the wiring layer 710 is physically and electrically connected to the TIVs 420 of the interconnect block 400 and the conductive pillars 210 of the semiconductor die 200 .

[0059] In some embodiments, the contact pad 718 is formed on the topmost wiring layer 716 of the wiring layer 710, and the contact terminal 720 is formed on the contact pad 718. In some embodiments, the material in the wiring layer 710 includes copper, titanium, nickel, aluminum, tungsten, silver and / or alloys thereof. In some embodiments, the material of the dielectric material 702 includes polyimide, BCB or PBO. In some embodiments, the contact terminal 720 includes a micro bump, a ball grid array (BGA) connector, a controlled collapse chip connection (C4) bump, an electroless nickel palladium immersion gold (ENEPIG) formed bump, etc. As shown in the figure for example, the contact terminal 720 may include a metal material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin or a combination thereof. In some embodiments, the contact terminal 720 is formed by evaporation, electroplating, printing, solder transfer, ball planting, etc. In an embodiment, the material in the contact pad 718 may include titanium, copper, nickel, tungsten, gold or a combination thereof.

[0060] In some embodiments, since the redistribution layer 700 is formed on the active surface of the semiconductor die 200, the redistribution layer 700 can be considered as a front-side redistribution layer, electrically connected to the TIVs 420 of the interconnect block 400, and electrically connected to the semiconductor die 200. In some embodiments, the redistribution layers 500 and 700 are electrically connected through the TIVs 420 of the interconnect block 400, and the semiconductor die and the redistribution layers 500 and 700 are electrically connected, and are electrically connected to the TIVs 420.

[0061] refer to Fig.12 and Fig.13, the entire structure is turned upside down, and the molded structure 17' is separated from the carrier 612 to expose the surface 500T of the redistribution layer 500. Then, in some embodiments, the opening S2 formed in the dielectric material 502 of the redistribution layer 500 exposes the uppermost layer of the wiring pattern 510. Fig.13 As shown, to form a connector 800, a bottom bump metal (UBM) pattern 802 is first formed on the top layer of the wiring pattern 510 and in the opening S2, and a bump 804 is formed on the bottom bump metal pattern 802. In some embodiments, the connector 800 includes a controlled collapse chip connection (C4) bump, a solder bump, a ball grid array (BGA) ball, etc. In some embodiments, the arrangement and architecture of the connector 800 can be determined according to the circuit design. In an embodiment, the bottom bump metal pattern 802 includes three layers of metal materials, such as a titanium layer / copper layer / nickel layer. Other materials and arrangements of different layers, such as an arrangement of chromium / chromium-copper alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper, or an arrangement of copper / nickel / gold, can be used to form the bottom bump metal pattern 802.

[0062] In some embodiments, a singulation process is performed along the scribe lines (indicated by dashed lines) to at least cut through the redistribution layers 500 and 700 and the molding compound 230 to singulate the individual semiconductor packages 10. In one embodiment, the singulation process is a wafer dicing process, including mechanical sawing or laser dicing. Fig.13 As shown, in some embodiments, the cutting process is performed to cut through the mold compound 230 of the molded structure 17 ′ but does not cut into the interconnection block 400 (ie, does not cut into the encapsulation body 430 of the interconnection block 400 ).

[0063] In an exemplary embodiment, the above manufacturing method is a part of a packaging process, and after a wafer cutting process, a plurality of semiconductor packages 10 can be obtained. During the packaging process, the semiconductor package structure 10 can be further installed with additional packages, chips / dies or other electronic components.

[0064] According to the present disclosure, different types of interconnect blocks or interconnect blocks having more than one type of TIVs can be applied or assembled into a package structure. Fig.15 and Fig.16 1 is a schematic top view illustrating a portion of a semiconductor package according to some exemplary embodiments of the present disclosure. To show the arrangement of interconnect blocks relative to the semiconductor die, other components such as redistribution layers and connectors will be omitted for illustration.

[0065] from Fig.15In some embodiments, the molded structure of package 15 includes semiconductor die 1500, interconnect blocks 1510 and 1520 arranged around it, and a molding compound 1530 that laterally encapsulates semiconductor die 1500 and interconnect blocks 1510 and 1520. In some embodiments, interconnect block 1510 is similar to interconnect block 135A described in the previous paragraph, and interconnect block 1520 is similar to interconnect block 135E described in the previous paragraph. Fig.15 In the embodiment, interconnect block 1510 including TIVs 1510V is arranged in an array and is encapsulated by encapsulation body 1510E. Interconnect block 1520 includes TIVs 1520V1, 1520V2, and 1520V3, which are arranged in columns and are encapsulated by encapsulation body 1520E. Fig.15 In some embodiments, interconnection blocks 1510 are disposed on two opposite sides of semiconductor die 1500, and interconnection blocks 1520 are disposed on two other opposite sides of semiconductor die 1500. From a top view, TIVs 1510V, 1520V1, 1520V2, and 1520V3 are arranged in a ring to surround four sides of semiconductor die 1500.

[0066] In some embodiments, Fig.16 As shown in the top view of FIG. 1 , the package 16 includes at least a first semiconductor die 1600A, a second semiconductor die 1600B, a third semiconductor die 1600C, interconnection blocks 1610, 1620, 1630, 1640, 1650, 1660, 1670 arranged around the semiconductor die 1600A, 1600B, 1600C, and a mold compound 1690 laterally wrapping the semiconductor die 1600A, 1600B, 1600C and the interconnection blocks 1610, 1620, 1630, 1640, 1650, 1660, 1670. The interconnection blocks may be similar to Figure 14A-14F and the interconnection blocks described in the previous paragraph. In some embodiments, interconnection block 1610 including L-shaped TIVs 1610V is disposed near a corner of semiconductor die 1600A, and interconnection blocks 1620 and 1630 including TIVs 1620V and 1630V are disposed on four sides of semiconductor die 1600A. From a top view, TIVs 1610V, 1620V, 1630V are arranged in a ring surrounding the four sides of semiconductor die 1600A. Fig.16 In FIG. 1 , semiconductor die 1600B is disposed between interconnection blocks 1640 and 1650 and between interconnection blocks 1610 , 1620 , and 1670 . Fig.16In the schematic top view, semiconductor die 1600B and 1600C are disposed between interconnect blocks 1650 and 1660, and are located between interconnect blocks 1670, 1620, and 1610. In some embodiments, interconnect block 1650 includes TIVs 1650V1 and larger TIVs 1650V2 (having a larger diameter), and interconnect block 1670 includes TIVs 1670V1 and larger TIVs 1670V2 (having a larger diameter). From the schematic top view, semiconductor die 1600B and 1600C are surrounded by TIVs 1610V, 1620V, 1640V, 1650V1, 1650V2, 1660V, 1670V1, and 1670V2.

[0067] Fig.17 is a schematic cross-sectional view showing a semiconductor package according to some exemplary embodiments. Fig.17 , a semiconductor package structure 3 is described, including a top package 40 mounted on a bottom package 30 and a conductive connector 35 electrically connecting the two. In some embodiments, the bottom package 30 is an integrated fan-out (InFO) package, and the semiconductor package structure 3 is an InFO-package-on-package (InFO-PoP) structure. Fig.13 As shown, the InFO-PoP structure 3 includes an underfill material 36 filled between the top package 40 and the bottom package 30. In some embodiments, the top package 40 includes stacked dies 410 and 420 wire-bonded to contact points of the substrate 400', and a mold layer 440 is formed on the substrate 400' to encapsulate the semiconductor dies 410 and 420. In some embodiments, the dies 410 and 420 include different types of chips, which may include memory chips and logic chips. It should be understood that the dies 410 and 420 can be bonded to the substrate 400' using suitable methods such as connecting wires, bumps, or ball grid array (BGA) balls. In some embodiments, the dies 410, 420 are electrically coupled to the bottom package 30 below through the substrate 400' and the conductive connectors 35.

[0068] In some embodiments, the bottom package 30 can be manufactured according to the manufacturing process described in the previous paragraph, similar to Fig.13 The package structure shown in . Fig.17In an exemplary embodiment, the semiconductor package 30 includes a first semiconductor die 310, a second semiconductor die 320, a first interconnection block 330, and a second interconnection block 340 that are laterally wrapped by a mold compound 350. In some embodiments, the package 30 includes an upper redistribution layer 360 and a lower redistribution layer 370 located on two opposite sides of the mold compound 350, and a connector 380 located on the lower redistribution layer 370. In some embodiments, the first semiconductor die 310 and the second semiconductor die 320 have different functions or include different types of chips. In some embodiments, the conductive pillars (contact points) 312 of the first semiconductor die 310 have a smaller critical dimension than the conductive pillars (contact points) 322 of the second semiconductor die 320. In some embodiments, the size (e.g., diameter) of the TIVs 332 in the first interconnection block 330 is smaller than the size (e.g., diameter) of the TIVs 342 in the second interconnection block 340. In some embodiments, different types of TIVs (different cross-sectional area sizes, shapes, or pitches) or different types of interconnection blocks may be arranged to match the contact point layout or contact point size of nearby dies. In some embodiments, the TIVs 332 and 342 penetrating the interconnection blocks 330 and 340 are in physical contact with the upper metallization layer 360 and the lower redistribution layer 370. In some embodiments, the upper redistribution layer 360 includes a metal heat dissipation grid pattern 365 located above the first semiconductor die 310 and the second semiconductor die 320, and the heat dissipation pattern 365 is electrically floating and can be used to assist the first semiconductor die 310 and the second semiconductor die 320 in dissipating heat.

[0069] In some embodiments, the material of the mold compound 350 is different from the material of the insulating encapsulant 334 of the first interconnection block 330 and different from the material of the insulating encapsulant 344 of the second interconnection block 340. In some embodiments, the material of the mold compound 350 includes a filler, while the material of the insulating encapsulant 334 and / or the material of the insulating encapsulant 344 does not include a filler or includes a filler with a smaller particle size. In some embodiments, an interface SF exists between the interconnection blocks 330, 340 and the mold compound 350.

[0070] By forming the interconnection block and the molding compound separately, a greater process margin and flexible material selection are provided for the trimming process and the planarization process, and the reliability of the package is improved. Corresponding to the particle size of the filler contained in the material of the molding compound and the material of the encapsulation body in the interconnection block, the insulating molding material without filler provides better filling ability, provides a better flat surface after the planarization process, and further improves the structural warpage problem.

[0071] According to some embodiments of the present disclosure, a semiconductor package is provided that includes a first redistribution layer, a semiconductor die, an interconnect block, and a molding compound. The semiconductor die is disposed on the first redistribution layer, and an active surface of the semiconductor die faces the first redistribution layer. The interconnect block is disposed on the first redistribution layer, next to the semiconductor die. The interconnect block includes an insulating encapsulation and a first through-insulator via (TIV) penetrating the insulating encapsulation. The molding compound is disposed on the first redistribution layer and laterally surrounds the semiconductor die and the interconnect block. The interconnect block is separated from the semiconductor die by the molding compound located therebetween. The first TIVs are isolated from the molding compound by the insulating encapsulation. The first TIVs are electrically connected to the first redistribution layer.

[0072] According to some embodiments of the present disclosure, the material of the insulating encapsulant is different from the material of the molding compound. According to some embodiments, the molding compound completely covers the sidewalls of the interconnection block, and an interface exists between the insulating encapsulant of the interconnection block and the molding compound around the insulating encapsulant. According to some embodiments, the semiconductor package further includes a second redistribution layer disposed on the back surface of the semiconductor die opposite to the active surface, on the interconnection block and on the molding compound, and the semiconductor die and the first redistribution layer and the second redistribution layer are electrically connected through the first through-insulator via of the interconnection block located therebetween. According to some embodiments, the second redistribution layer includes a semiconductor substrate of a heat dissipation pattern disposed on the semiconductor die and contacting the semiconductor die. The material of the molding compound includes a first filler, the material in the insulating encapsulant includes a second filler, and the particle size of the first filler is larger than the particle size of the second filler.

[0073] According to some embodiments of the present disclosure, at least one of the first through-insulator vias in the interconnect block directly contacts a wiring layer of the first redistribution layer. According to some embodiments, at least one of the first through-insulator vias in the interconnect block directly contacts a topmost through-insulator via of the first redistribution layer. According to some embodiments, the semiconductor package further comprises an additional interconnect block, the additional interconnect block comprising second through-insulator vias, wherein the first through-insulator vias and the second through-insulator vias have substantially the same height, and each first through-insulator via has a different cross-sectional area size than each second through-insulator via.

[0074] According to some embodiments of the present disclosure, a semiconductor package is provided that includes a first redistribution layer, a semiconductor die, an interconnection block, and a molding compound. The first redistribution layer includes a plurality of wiring layers. The semiconductor die is located above the first redistribution layer. The interconnection block is disposed adjacent to the semiconductor die and is located above the first redistribution layer. The interconnection block includes an encapsulation and a through-insulator via extending through the encapsulation. The through-insulator via directly contacts at least one of the plurality of wiring layers of the first redistribution layer. The molding compound is disposed between the semiconductor die and the interconnection block.

[0075] According to some embodiments of the present disclosure, the semiconductor die includes a first semiconductor die and a second semiconductor die having a different function from the first semiconductor die. According to some embodiments, the interconnection block includes a first interconnection block having a first through-insulator via and a second interconnection block having a second through-insulator via, the first interconnection block and the second interconnection block are arranged beside and around the semiconductor die, and the cross-sectional area size of the first through-insulator via is different from the cross-sectional area size of the second through-insulator via. According to some embodiments, the through-insulator via includes a first through-insulator via and a second through-insulator via in the interconnection block, the first through-insulator via has a cross-sectional area size different from the second through-insulator via. According to some embodiments, the molding compound laterally wraps the semiconductor die and the interconnection block, and an interface exists between the interconnection block and the molding compound.

[0076] According to some embodiments of the present disclosure, the semiconductor package further comprises a second redistribution layer having a heat dissipation pattern, wherein the heat dissipation pattern is disposed above the semiconductor die and directly contacts a semiconductor substrate of the semiconductor die. According to some embodiments, the molding compound laterally wraps the semiconductor die and the interconnection block, and an interface exists between the interconnection block and the molding compound.

[0077] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor package is disclosed. Interconnection blocks are formed, each of which includes a through-insulator via laterally wrapped by an encapsulant. A semiconductor die is provided on a first carrier, with an active surface of the semiconductor die facing the first carrier. An interconnection block is provided on the first carrier and is located next to the semiconductor die. A molding compound is formed on the first carrier, encapsulating the semiconductor die and the interconnection block to form a molded structure. A first trimming process is performed on the molded structure until the through-insulator via is exposed. A first redistribution layer is formed on the semiconductor die and the interconnection block. The first redistribution layer is electrically connected to the through-insulator via. A second carrier is attached to the first redistribution layer, and the molded structure is separated from the first carrier. A second trimming process is performed on the molded structure until the through-insulator via is exposed. A second redistribution layer is formed on the semiconductor die and the interconnection block. The second redistribution layer is electrically connected to the through-insulator via.

[0078] It will be apparent to those skilled in the art that various modifications and changes may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In summary, the present disclosure is intended to cover the modifications and changes provided within the scope of the above claims and their equivalents.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A semiconductor package, characterized in that: include: The first redistribution layer; a semiconductor die disposed on the first redistribution layer, wherein the semiconductor die faces an active surface of the first redistribution layer; an interconnect block disposed on the first redistribution layer and beside the semiconductor die, wherein the interconnect block comprises an insulating encapsulation and a first through-insulator via penetrating the insulating encapsulation; and a molding compound disposed on the first redistribution layer and laterally wrapping around the semiconductor die and the interconnect block, wherein the interconnect block is separated from the semiconductor die by the molding compound therebetween, the first through-insulator via is separated from the molding compound by the insulating encapsulation, and The first through-insulator via is electrically connected to the first redistribution layer.

2. The semiconductor package according to claim 1, wherein: The material of the insulating encapsulation is different from the material of the molding compound.

3. The semiconductor package according to claim 1, wherein: The molding compound completely covers the sidewall of the interconnection block, and an interface exists between the insulating encapsulation of the interconnection block and the molding compound around the insulating encapsulation.

4. The semiconductor package according to claim 1, wherein: It further includes a second redistribution layer disposed on a backside surface of the semiconductor die opposite to the active surface, above the interconnect block and above the molding compound, the semiconductor die and the first redistribution layer and the second redistribution layer being electrically connected through the first through-insulator via of the interconnect block located therebetween.

5. The semiconductor package according to claim 4, wherein: The second redistribution layer includes a semiconductor substrate with a heat dissipation pattern disposed above the semiconductor die and contacting the semiconductor die.

6. A semiconductor package, characterized in that: include: a first redistribution layer comprising a plurality of wiring layers; a semiconductor die located on the first redistribution layer; an interconnect block disposed adjacent to the semiconductor die and above the first redistribution layer, wherein the interconnect block comprises an encapsulation and a through-insulator via extending through the encapsulation, and the through-insulator via directly contacts at least one of the plurality of wiring layers of the first redistribution layer; as well as A molding compound is disposed between the semiconductor die and the interconnect block.

7. The semiconductor package according to claim 6, wherein: The interconnection block includes a first interconnection block having a first through-insulator via and a second interconnection block having a second through-insulator via, the first interconnection block and the second interconnection block are arranged beside and around the semiconductor tube core, and the cross-sectional area size of the first through-insulator via is different from the cross-sectional area size of the second through-insulator via.

8. The semiconductor package according to claim 6, wherein: The through-insulator vias include a first through-insulator via and a second through-insulator via within the interconnect block, the first through-insulator via having a different cross-sectional area size than the second through-insulator via.

9. The semiconductor package according to claim 6, wherein: The molding compound laterally wraps around the semiconductor die and the interconnect block, with an interface existing between the interconnect block and the molding compound.

10. The semiconductor package according to claim 6, wherein: The method further includes a second redistribution layer having a heat dissipation pattern, wherein the heat dissipation pattern is disposed above the semiconductor die and directly contacts a semiconductor substrate of the semiconductor die.

Images