Semiconductor device

Abstract

The utility model discloses a semiconductor device which comprises a substrate, a plurality of wire structures, a dielectric layer, a plurality of plug structures, a plurality of gap walls and a barrier layer. The substrate includes a plurality of active regions and a plurality of shallow trench isolations. The lead structures extend on the substrate in parallel and are staggered with the active region and the shallow trench isolation. The dielectric layer is disposed on the substrate and includes a composite layer structure between the substrate and a portion of the wire structure. The spacer is disposed on a sidewall of the wire structure. The barrier layer includes a first portion disposed on the gap wall and a second portion extending into the composite layer structure. Therefore, the semiconductor device has more optimized component structure and efficiency, thereby improving operation performance.

Description

Technical Field

[0001] The utility model relates to a semiconductor device, in particular to a semiconductor device with a conductor structure. Background Art

[0002] As various electronic products develop towards miniaturization, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally speaking, a dynamic random access memory with a recessed gate structure is composed of a large number of memory cells gathered to form an array area for storing information, and each memory cell can be composed of a transistor component and a capacitor component connected in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the density of memory cells in the array area must be continuously improved, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, the existing technology or structure needs to be further improved to effectively improve the performance and reliability of related memory devices. Utility Model Content

[0003] One purpose of the utility model is to provide a semiconductor device, in which a barrier layer is arranged on the spacer and partially extends into the composite layer structure of the dielectric layer, thereby increasing the contact area between the plug structure and the components on both sides, thereby improving the structural reliability of the storage node plug. As a result, the semiconductor device of the utility model can have a more optimized component structure and performance, thereby improving the operating performance of the semiconductor device.

[0004] One of the purposes of the utility model is to provide a method for manufacturing a semiconductor device, wherein a barrier layer extending into a dielectric layer is formed on a spacer, and the barrier layer is used as a mask layer when manufacturing a plug hole. Thus, the manufacturing method of the utility model can form a plug structure with a relatively large contact area with components on both sides, so as to improve the structural reliability of the storage node plug, thereby improving the operating performance of the semiconductor device.

[0005] To achieve the above-mentioned purpose, one embodiment of the utility model provides a semiconductor device, including a substrate, a plurality of wire structures, a dielectric layer, a plurality of plug structures, a plurality of spacers and a barrier layer. The substrate includes a plurality of active areas and a plurality of shallow trench isolations. A plurality of wire structures extend on the substrate in parallel with each other and are interlaced with the active areas and the shallow trench isolations. A dielectric layer is located between the substrate and the wire structure, and the dielectric layer includes a composite layer structure. A plurality of spacers are arranged on the side walls of the wire structure. The barrier layer includes a first portion arranged on the spacers and a second portion extending into the composite layer structure.

[0006] To achieve the above-mentioned purpose, one embodiment of the utility model provides a method for manufacturing a semiconductor device, comprising the following steps. Provide a substrate, including a plurality of active areas and a plurality of shallow trench isolations. Form a plurality of wire structures on the substrate, the wire structures extending parallel to each other and interlaced with the active areas and the shallow trench isolations. Form a dielectric layer on the substrate, located between the substrate and the wire structure, the dielectric layer comprising a composite layer structure. Form a plurality of spacers on the sidewalls of the wire structure. Form a barrier layer on the substrate, including a first portion disposed on the spacers, and a second portion extending into the composite layer structure.

[0007] In general, the semiconductor device of the present invention is to set a barrier layer on the bit line gap wall that partially extends into the composite layer structure of the dielectric layer, thereby increasing the contact area between the storage node plug and the components on both sides, improving the structural reliability of the storage node plug, and at the same time improving the electrical isolation between the storage node plug and the adjacent bit line. As a result, the semiconductor device of the present invention can have a more optimized component structure and performance, thereby improving the operating performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings provide a deeper understanding of the embodiments of the utility model and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and the relative sizes and proportions have been adjusted for the purpose of illustration and drawing convenience. The same symbols represent corresponding or similar features in different embodiments.

[0009] Figure 1 to Figure 2 FIG. 1 is a schematic diagram of a semiconductor device according to a first embodiment of the present invention, wherein:

[0010] Figure 1 is a schematic top view of a semiconductor device; and

[0011] Figure 2 for Figure 1 A schematic cross-sectional view taken along section line AA' in FIG.

[0012] Figures 3 to 7 The figure is a schematic diagram of a method for manufacturing a semiconductor device according to a preferred embodiment of the utility model, wherein:

[0013] Figure 3 It is a cross-sectional schematic diagram of a semiconductor device after a spacer material layer is formed;

[0014] Figure 4 is a schematic cross-sectional view of a semiconductor device after a wet etching process;

[0015] Figure 5 is a schematic cross-sectional view of a semiconductor device after a barrier material layer is formed;

[0016] Figure 6 is a schematic cross-sectional view of a semiconductor device after a barrier layer is formed; and

[0017] Figure 7 It is a cross-sectional schematic diagram of the semiconductor device after forming a plug structure.

[0018] Figure 8 FIG. 1 is a schematic diagram of a semiconductor device according to a second embodiment of the present invention.

[0019] Fig. 9 FIG. 1 is a schematic diagram of a semiconductor device according to a third embodiment of the present invention.

[0020] The reference numerals are described as follows:

[0021] 10, 20, 30 Semiconductor devices

[0022] 100 Substrate

[0023] 110 Shallow Trench Isolation

[0024] 112 Active Area

[0025] 120 Insulation layer

[0026] 122 first dielectric layer

[0027] 122a first dielectric material layer

[0028] 124 second dielectric layer

[0029] 124a Second dielectric material layer

[0030] 126 third dielectric layer

[0031] 130 Wire structure

[0032] 130a Contact

[0033] 132 Semiconductor layer

[0034] 134 Barrier Layer

[0035] 136 Metal Layer

[0036] 138 Covering layer

[0037] 140 gap wall

[0038] 142 First spacer

[0039] 144 Second spacer

[0040] 150, 250, 350 Barrier layer

[0041] 150a Barrier material layer

[0042] 152 Part 1

[0043] 154, 354 Part II

[0044] 154a First groove

[0045] 156, 256, 356 Part 3

[0046] 156a Second groove

[0047] 160 plug structure

[0048] 160a plug hole

[0049] 162 first protrusion

[0050] 164 Second protrusion

[0051] 170 Isolation Structure

[0052] 172 Contact pads

[0053] 174 Insulation layer

[0054] 176 Capacitor Structure

[0055] 176a Vertical Capacitor

[0056] D1 First direction

[0057] D2 Second direction

[0058] D3 third direction

[0059] D4 Vertical

[0060] E Wet Etching Process

[0061] h1, h2 concave holes

[0062] W1 First thickness

[0063] W2 Second thickness

[0064] W3 Third Thickness DETAILED DESCRIPTION

[0065] In order to enable those skilled in the art to further understand the present invention, the following lists the preferred embodiments of the present invention, and with the accompanying drawings, describes in detail the composition and intended effects of the present invention. It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present invention.

[0066] Please refer to Figure 1 and Figure 2 As shown, it is a schematic diagram of a semiconductor device 10 of the first embodiment of the utility model. The semiconductor device 10 includes a substrate 100, a dielectric layer 120, a plurality of conductive line structures 130, a plurality of spacers 140 and a barrier layer 150. The substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate or a substrate composed of other suitable materials, and the details include a plurality of shallow trench isolations 110 (for example, including silicon oxide) and a plurality of active regions 112 disposed therein. As shown in FIG. Figure 1 As shown, the conductive line structures 130 extend parallel to each other on the substrate 100 in a first direction D1, and are interlaced with the plurality of active regions 112 and the plurality of shallow trench isolations 110. Figure 2 As shown, the dielectric layer 120 is disposed on the substrate 100, between the substrate 100 and the conductive line structure 130, to electrically isolate the conductive line structure 130 disposed on the substrate 100 from components such as gate lines (not shown) disposed in the substrate 100. The spacer 140 is also disposed on the substrate 100, on the sidewall of the conductive line structure 130, to electrically isolate components adjacent to the conductive line structure 130.

[0067] It should be noted that the dielectric layer 120 preferably includes a composite layer structure, and the barrier layer 150 includes a first portion 152 covering the sidewall of the spacer 140, and a second portion 154 extending into the composite layer structure of the dielectric layer 120. Thus, the barrier layer 150 is provided to improve the structural stability between the barrier layer 150 and the components on both sides, such as the spacer 140 and the dielectric layer 120, to increase the spacing between the bottoms of the adjacent wire structures 130, and to improve the electrical isolation between the wire structures 130 and the adjacent components. As a result, the semiconductor device 10 of the present invention has a more optimized component structure and performance, thereby improving the operating performance of the semiconductor device 10.

[0068] In one embodiment, the barrier layer 150, for example, includes an insulating material different from the spacer 140, such as silicon oxynitride, silicon carbonitride, etc., but is not limited thereto. Specifically, the composite layer structure of the dielectric layer 120 includes, for example, a first dielectric layer 122 (for example, including insulating materials such as silicon oxide materials), a second dielectric layer 124 (for example, including insulating materials such as silicon nitride materials), and a third dielectric layer 126 (for example, including insulating materials such as silicon oxide materials) stacked in sequence on the substrate 100, and has an oxide-nitride-oxide (ONO) structure, but is not limited thereto. Among them, the sidewalls of the first dielectric layer 122, for example, are aligned with the sidewalls of the barrier layer 150, the sidewalls of the third dielectric layer 126, for example, are aligned with the sidewalls of the conductive wire structure 130, and the sidewalls of the second dielectric layer 124, for example, are further retracted in the direction of the conductive wire structure 130, such as Figure 2 The spacer 140 also preferably includes a composite layer structure, for example, including a first spacer 142 and a second spacer 144 sequentially disposed on the sidewalls of the conductive line structure 130 and the contact 130a. In one embodiment, the first spacer 142 includes an insulating material such as silicon nitride, and the second spacer 144 includes a different insulating material such as silicon oxide, for example, but not limited thereto.

[0069] It should be noted that the second portion 154 of the barrier layer 150 is sandwiched between the top surface of the first dielectric layer 122 and the bottom surface of the spacer 140, and at the same time physically contacts the top surface of the first dielectric layer 122, the indented sidewall of the second dielectric layer 124, a portion of the bottom surface of the third dielectric layer 126, the bottom surface of the first spacer 142, and a portion of the bottom surface of the second spacer 144. In this way, the bottom surface of the second portion 154 of the barrier layer 150 is higher than the bottom surface of the composite layer structure of the dielectric layer 120. In a preferred embodiment, the second portion 154 of the barrier layer 150 extends continuously along the portion of the bottom surface of the second spacer 144, the bottom surface of the first spacer 142, the indented sidewall of the second dielectric layer 124, and the top surface of the first dielectric layer 122, and defines a first groove 154a that is recessed toward the inside of the composite layer structure in a second direction D2 perpendicular to the first direction D1. Wherein, as Figure 2 As shown, the second spacer 144 of the spacer 140 has a first thickness W1, and the first portion 152 and the second portion 154 of the barrier layer 150 have a second thickness W2 and a third thickness W3, respectively. The value of the third thickness W3 is preferably greater than the sum of the first thickness W1 and the second thickness W2, so as to maintain a certain degree of electrical isolation while expanding the bottom spacing space of the adjacent conductive line structure 130.

[0070] For example Figure 1 and Figure 2 As shown, the semiconductor device 10 further includes a plurality of plug structures 160, which are also disposed on the substrate 100 and are respectively disposed between two adjacent conductive line structures 130 in the second direction D2. Each plug structure 160 partially extends into the substrate 100, is electrically connected to the active region 112, and is electrically isolated from the conductive line structure 130 by spacers 140 respectively disposed between the conductive line structure 130 and the plug structure 160, and a barrier layer 150 disposed on the spacers 140. In one embodiment, the active regions 112 are arranged in an array along the third direction D3 in parallel with each other, for example, and the shallow trench isolation 110 surrounds the outside of all active regions 112, but is not limited thereto. Figure 2As shown, each plug structure 160 has a first protrusion 162 that fills the first groove 154a, and is able to partially extend into the composite layer structure of the dielectric layer 120, thereby increasing the contact area between the plug structure 160 and the dielectric layer 120, thereby improving the structural reliability of the plug structure 160. On the other hand, the conductive line structure 130 includes a semiconductor layer 132, a barrier layer 134, a metal layer 136, and a cap layer 138 stacked sequentially from bottom to top on the substrate 100. In addition, the conductive line structure 130 is disposed on the dielectric layer 120, and also includes a contact 130a that partially extends into the substrate 100. In this way, the contact 130a can include the same conductive material as the semiconductor layer 132 of the conductive line structure 130, and receive or transmit a signal from the substrate 100. In one embodiment, the semiconductor layer 132 includes semiconductor materials such as doped polysilicon and doped amorphous silicon, the barrier layer 134 includes conductive barrier materials such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), the metal layer 136 includes copper, aluminum, tungsten or other suitable low-resistivity conductive materials, and the cap layer 138 includes insulating materials such as silicon oxide, silicon nitride or silicon oxynitride, but is not limited thereto.

[0071] In addition, in one embodiment, the barrier layer 150 further includes a third portion 156 extending into the composite layer structure of the spacer 140, located on the sidewall of the contact 130a, and sandwiched between a portion of the second spacer 144 and the shallow trench isolation 110. Figure 2 Specifically, the third portion 156 of the barrier layer 150 extends along the spacer 140 covering the contact 130a toward the shallow trench isolation 110 in the substrate 100, thereby defining a vertical direction (i.e., Figure 1 The vertical direction D4 is toward the second groove 156a in the substrate 100. The plug structure 160 has a second protrusion 164 filling the second groove 156a, thereby increasing the contact area between the plug structure 160 and the spacer 140 and further improving the structural reliability of the plug structure 160.

[0072] Although the gate line disposed in the substrate 100 is not specifically depicted in the drawings of the present embodiment, a person skilled in the art can easily understand that the extension directions of the active region 112, the gate line and the conductive line structure 130 are all different, and the extension direction of the gate line should be perpendicular to the extension direction of the conductive line structure 130 (i.e. Figure 1The first direction D1 shown in the figure is interlaced with the active area 112 and the conductive line structure 130 at the same time. That is to say, the gate lines extend in parallel with each other along the second direction D2, and a plurality of isolation structures 170 are arranged on the upper part thereof to electrically isolate the adjacent conductive line structures 130 and / or plug structures 160, so that the contacts 130a are respectively arranged between adjacent isolation structures 170 (or the gate lines). In one embodiment, the isolation structure 170 includes, for example, an insulating material such as silicon nitride or silicon carbonitride, but is not limited thereto. Under this arrangement, the conductive line structure 130 can be used as a bit line (BL) of the semiconductor device 10, the contact 130a can be used as a bit line plug (BLC) of the semiconductor device 10, the plug structure 160 can be used as a storage node plug (SNC) of the semiconductor device 10, and the gate line can be used as a buried word line (BWL) of the semiconductor device 10. Therefore, the semiconductor device 10 of the present embodiment can be used as a dynamic random access memory (DRAM) device, and at least one capacitor (not shown) subsequently disposed above the plug structure 160 and at least one transistor element (not shown) disposed in the substrate 100 constitute a memory cell, which is the smallest component in the dynamic random access memory array, and receives voltage information from the bit line (i.e., the conductive line structure 130) and the buried word line (i.e., the gate line).

[0073] According to the semiconductor device 10 of the present embodiment, a barrier layer 150 that can extend into the dielectric layer 120 and / or the spacer 140 is disposed between the conductive line structure 130 and the plug structure 160, so that the conductive line structure 130 and the plug structure 160 can be effectively electrically isolated under the premise of expanding the bottom spacing space of the adjacent conductive line structures 130. The barrier layer 150 includes at least one branch portion (a second portion 154 and / or a third portion 156), and the branch portion, for example, extends along the dielectric layer 120 toward the conductive line structure 160, and / or extends along the sidewall of the spacer 140 toward the substrate 100 and partially extends into the spacer 140, thereby defining a first groove 154a that is recessed in the horizontal direction (i.e., the second direction D2), and / or a second groove 156a that is recessed in the vertical direction. The plug structure 160 has a first protrusion 162 that fills the first groove 154a and / or a second protrusion 164 that fills the second groove 156a. Therefore, by setting the barrier layer 150, the contact area between the plug structure 160 and the components on both sides such as the spacer 140 and the dielectric layer 120 can be increased, while maintaining a certain degree of electrical isolation between the plug structure 160 and the adjacent wire structure 130, so that the semiconductor device 10 has a more optimized component structure and performance, thereby improving the operating performance.

[0074] Those skilled in the art can easily understand that the third portion 156 of the barrier layer 150 of the present invention can also have other different shapes according to the spacers 140 disposed on the sidewalls of the contacts 130a. For example, in other embodiments, the spacers covering the sidewalls of the contacts 130a can be disposed separately from the spacers 140 covering the sidewalls of the conductive line structure 130, so that the spacers covering the sidewalls of the contacts 130a can have multiple stacked layers or single filled layers, etc., so that the third portion of the barrier layer 150 extending into the multiple stacked layers of spacers or the single filled spacers can have various structures according to actual device requirements, so as to further increase the contact area between the plug structure 160 and the components on both sides.

[0075] In order to enable a person skilled in the art to which the present invention belongs to easily understand the semiconductor device 10 of the present invention, the manufacturing method of the semiconductor device 10 of the present invention will be further described below.

[0076] See also Figures 3 to 7 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device 10 in a first embodiment of the present invention. First, Figure 3As shown, a substrate 100 is provided, and a shallow trench isolation 110 is formed in the substrate 100 to define a plurality of active regions 112 in the substrate 100. In one embodiment, the shallow trench isolation 110 is formed by, for example, first forming a plurality of trenches (not shown) in the substrate 100 using an etching process, and then filling the trenches with at least one insulating material (such as silicon oxide, etc.) to form a shallow trench isolation 110 whose surface is flush with the top surface of the substrate 100, but the present invention is not limited thereto. Next, a plurality of gate lines (not shown) are formed in the substrate 100 and a first dielectric material layer 122a (for example, including silicon oxide material), a second dielectric material layer 124a (for example, including silicon nitride material) and a third dielectric layer 126 (for example, including silicon oxide material) are sequentially formed on the substrate 100, wherein the first dielectric material layer 122a covers the active area 112 and the shallow trench isolation 110 of the substrate 100, and the sidewalls of the second dielectric material layer 124a are, for example, aligned with the sidewalls of the spacer 140. In one embodiment, the method for manufacturing the gate line includes but is not limited to the following steps, for example, first forming a plurality of trenches (not shown) in the second direction D2 that can simultaneously pass through the active area 112 and the shallow trench isolation 110, and then, sequentially forming a dielectric layer (not shown) covering the entire surface of the trench, a gate dielectric layer (not shown) covering the surface of the lower half of the trench, a gate (not shown) filling the lower half of the trench, and a cap layer (not shown) filling the upper half of the trench in the trench, but is not limited to this.

[0077] It should be noted that before forming the conductive line structure 130, a first material layer (not shown), a second material layer (not shown) and a third material layer (not shown) are first formed to cover the substrate 100 as a whole, and then the third material layer, the second material layer and the first material layer are partially removed to form a plurality of contact openings (not shown), so that the semiconductor layer 132 subsequently filled into the contact openings simultaneously forms the contacts 130a. In one embodiment, the manufacturing process of the conductive line structure 130 and the contacts 130a includes but is not limited to the following steps. First, after the contact opening is formed, a semiconductor material (not shown, for example, semiconductor materials including polycrystalline silicon, doped amorphous silicon, etc.), a barrier material layer (not shown, for example, conductive barrier materials including titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc.), a metal material layer (not shown, for example, low resistivity conductive materials including copper, aluminum, tungsten, etc.) and a covering material layer (not shown, for example, insulating materials including silicon oxide, silicon nitride or silicon oxynitride, etc.) are sequentially formed on the substrate 100, and finally, a patterning process is performed to simultaneously form the conductive line structure 130 and the contact 130a. On the other hand, when forming the conductive line structure 130, the third material layer is partially removed to form a third dielectric layer 126 whose sidewalls are aligned with the conductive line structure 130, as shown in FIG. Figure 3 shown.

[0078] Then, two deposition processes are performed to sequentially form a first spacer material layer (not shown, for example, including silicon nitride) and a second spacer material layer (not shown, for example, including silicon oxide) on the conductive line structure 130 and the substrate 100, conformally covering the exposed surfaces of the conductive line structure 130, the insulating material layer 220, and the contact 130a, and then an etch-back process is performed to remove the second spacer material layer and the first spacer material layer located on the top surface of the conductive line structure 130 and the first dielectric material layer 122a, to form a first spacer 142 and a second spacer 144 sequentially located on the sidewalls of the conductive line structure 130 and the contact 130a. In this way, the first spacer 142 and the second spacer 144 can form the spacer 140 together. At the same time, when forming the spacer 140, the second material layer is partially removed to form the second dielectric material layer 124a whose sidewalls are aligned with the sidewalls of the spacer 140. On the other hand, after the etching back process is performed, the first dielectric material layer 122a still fully covers the active area 112 and the shallow trench isolation 110 of the substrate 100. Figure 3 shown.

[0079] like Figure 4 As shown, a wet etching process E is performed to partially remove the second dielectric material layer 124a (e.g., including silicon nitride) from the sidewall of the exposed second dielectric material layer 124a, and also to partially remove the first spacer 142 of similar material. The exposed second dielectric material layer 124a is etched laterally to form the retracted sidewall of the second dielectric layer 124, and a recessed hole h1 is formed from the sidewall of the spacer 140 toward the inside of the conductive line structure 130. On the other hand, the first spacer 142 covering the sidewall of the contact 130a is etched vertically downward to form a recessed hole h2 that is recessed toward the inside of the substrate 100. In one embodiment, the depths and opening sizes of the recessed holes h1 and h2 in the horizontal direction (i.e., the second direction D2) and the vertical direction D4 are different, respectively, and the recessed hole h1 generally presents a stepped structure because it is partially formed in the first spacer 142 and partially formed in the second dielectric material layer 124a, but the present invention is not limited thereto.

[0080] like Figure 5As shown, a deposition process is performed to form a barrier material layer 150a, which conformally covers the conductive line structure 130 and the spacer 140. Specifically, the barrier material layer 150a, for example, continuously covers the top surface of the conductive line structure 130, the top surface and sidewalls of the spacer 140, and the exposed surface of the first dielectric material layer 122a. It should be noted that the barrier material layer 150a is further formed on the exposed surfaces in the recessed holes h1 and h2, but does not fill the recessed holes h1 and h2. In one embodiment, the barrier material layer 150a, for example, includes an insulating material different from the first spacer 142 and the second spacer 144, such as silicon oxynitride, silicon carbonitride, etc., but is not limited thereto.

[0081] like Figure 6 As shown, an etching process is performed with the barrier material layer 150a as an etching mask, such as a dry etching process, a wet etching process, or a dry etching process and a wet etching process performed in sequence, to partially remove the barrier material layer 150a. In this way, the barrier material layer 150a covering the top surface of the conductive line structure 130, the top surface of the spacer 140, and the exposed surface of the first dielectric material layer 122a is removed by the etching process to form a barrier layer 150. The barrier layer 150 includes a first portion 152 covering the sidewall of the spacer 140, a second portion 154 extending into the recess h1 in the horizontal direction (i.e., the second direction D2), and a third portion 156 extending into the recess h2 in the vertical direction D4. At the same time, when performing the etching process, the first dielectric material layer 122a and the substrate 100 thereunder (including the active area 112 and the shallow trench isolation 110) are partially removed to form the first dielectric layer 122 and a plurality of plug holes 160a that partially expose part of the active area 112 and part of the shallow trench isolation 110. In this way, the first dielectric layer 122, the second dielectric layer 124 and the third dielectric layer 126 can together form the dielectric layer 120. It should be noted that, since the second portion 154 and the third portion 156 of the barrier layer 150 do not fill the recessed holes h1 and h2, only a first recessed groove 154a that is recessed inside the composite layer structure facing the dielectric layer 120 and a second recessed groove 156a that is recessed inside the composite layer structure facing the spacer 140 are defined, so that the plug hole 160a correspondingly has an extension portion connecting the first recess 154a and the second recess 156a, as shown in FIG. Figure 6 shown.

[0082] Then, a deposition process and a back etching process (not shown) are performed to form Figure 1 and Figure 2 The plug structures 160 shown in the figure respectively fill the plug holes 160a. In addition, the plug structures 160 also partially fill the extension portions to form the following: Figure 2The first protrusion 162 and the second protrusion 164 are shown to effectively increase the contact area between the plug structure 160 and components on both sides such as the dielectric layer 120 and the spacer 140 , while maintaining a certain degree of electrical isolation between the plug structure 160 and the adjacent conductive line structure 130 .

[0083] In this operation, the production is completed. Figure 2 The semiconductor device 10 shown in FIG. 1 is a semiconductor device 10. According to the manufacturing process of the semiconductor device 10 of this embodiment, a barrier material layer 150a is formed on the spacer 140, and the barrier material layer 150a is used as an etching mask for forming the plug hole 160a, and the barrier layer 150 covering the sidewalls of the spacer 140 and the contact 130a is formed simultaneously. Thus, the barrier layer 150 includes a first portion 152 covering the sidewalls of the spacer 140, a second portion 154 extending into the composite layer structure of the dielectric layer 120 in the horizontal direction (i.e., the second direction D2), and a third portion 156 extending into the composite layer structure of the spacer 140 in the vertical direction D4. Thus, by forming the second portion 154 and / or the third portion 156 of the barrier layer 150, the contact area between the plug structure 160 and the components on both sides, such as the dielectric layer 120 and / or the spacer 140, is increased, and the electrical isolation between the wire structure 130 and the plug structure 160 is effectively maintained, so that the semiconductor device 10 manufactured by the manufacturing process of this embodiment has a more optimized component structure and performance, thereby improving its operating performance.

[0084] Follow-up, as Figure 7 As shown, a plurality of contact pads 172 and a capacitor structure 176 are sequentially formed above the plug structure 160. The manufacturing process of the contact pad 172 includes, but is not limited to, the following steps: Figure 2A mask layer (not shown) is formed above the plug structure 160, and the plug structure 160 is partially removed through the mask layer, the mask layer is removed, and then a deposition and patterning process is performed to form a contact pad 172. Among them, an insulating layer 174 is set between the contact pads 172, and is partially located on the plug structure 160, and partially located on the conductive line structure 130 and the spacer 140, and physically contacts the plug structure 160. In one embodiment, the contact pad 172 includes a metal material with a low resistance value such as aluminum (aluminum, Al), titanium (titanium, Ti), copper (copper, Cu) or tungsten (tungsten, W), preferably including tungsten, but not limited thereto. In another embodiment, the manufacturing process of the contact pad 172 can integrate the manufacturing process of the aforementioned plug structure 160, so that the contact pad 172 and the plug structure 160 can include a continuous structure and the same conductive material, but not limited thereto. The capacitor structure 176 includes a plurality of vertical capacitors 176a respectively electrically connected to the contact pad 172. In this way, the semiconductor device 10 of the present embodiment can constitute a dynamic random access memory (DRAM), and the contact pad 172 serves as a storage node pad (SN pad) of the dynamic random access memory, and is electrically connected to the plug structure 160 serving as a storage node contact (SNC) of the dynamic random access memory. In this operation, the vertical capacitor 176a and at least one transistor element (not shown) formed in the substrate 100 can constitute a minimum memory cell in the dynamic random access memory array, receiving voltage information from the bit line (i.e., the conductive line structure 130) of the semiconductor device 10 and the word line (i.e., the gate line) of the semiconductor device 10.

[0085] A person skilled in the art of the present invention should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device and its manufacturing method of the present invention may also have other aspects or can be achieved by other means, and are not limited to the above. The following will further describe other embodiments or variations of the semiconductor device and its manufacturing method of the present invention. And to simplify the description, the following description mainly describes the differences between the embodiments, and will not repeat the same parts. In addition, the same components in each embodiment of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0086] Please refer to Figure 8, which are schematic diagrams of a semiconductor device 20 according to a second embodiment of the present invention. The structure of the semiconductor device 20 of this embodiment is substantially the same as that of the semiconductor device 10 of the aforementioned embodiment, and the similarities are not repeated here. The main difference between the semiconductor device 20 of this embodiment and the semiconductor device 10 of the aforementioned embodiment is that the third portion 256 of the barrier layer 250 of this embodiment still extends into the composite layer structure of the spacer 140 in the vertical direction D4, and no groove is defined.

[0087] Specifically, when the barrier layer 250 of this embodiment is formed, the operating parameters of the deposition process are adjusted so that the barrier material layer (not shown) fills the space. Figure 5 Thus, after the barrier material layer is subsequently etched, the following concave hole h2 is formed. Figure 8 The barrier layer 250 shown in detail includes a first portion 152 covering the sidewall of the spacer 140, a second portion 154 of the composite layer structure partially extending into the dielectric layer 120, and a third portion 256 of the composite layer structure partially extending into the spacer 140, and the second portion 154 defines a first groove 154a recessed toward the conductive line structure 130 in the horizontal direction (i.e., the second direction D2). In addition, the plug structure 160 may also have a first protrusion 162 filled into the first groove 154a to effectively increase the contact area between the plug structure 160 and components on both sides such as the spacer 140 and the dielectric layer 120, thereby improving the structural reliability of the storage node plug and improving the electrical isolation between the storage node plug and adjacent components. Accordingly, the semiconductor device 20 manufactured by the manufacturing process of this embodiment can also have a more optimized component structure and performance, thereby improving the operating performance.

[0088] Please refer to Fig. 9 , which are schematic diagrams of a semiconductor device 30 according to a third embodiment of the present invention. The structure of the semiconductor device 30 according to the present embodiment is substantially the same as that of the semiconductor device 10 according to the aforementioned embodiment, and the similarities are not repeated here. The main difference between the semiconductor device 30 according to the present embodiment and the semiconductor device 10 according to the aforementioned embodiment is that the second portion 354 and the third portion 356 of the barrier layer 350 according to the present embodiment still extend into the composite layer structure of the dielectric layer 120 in the horizontal direction (i.e., the second direction D2) and extend into the composite layer structure of the spacer 140 in the vertical direction D4, respectively, and no groove is defined.

[0089] Specifically, when the barrier layer 350 of this embodiment is formed, the operating parameters of the deposition process are adjusted so that the barrier material layer (not shown) is filled with the following: Figure 5Thus, after the barrier material layer is subsequently etched, the following concave holes h1 and h2 can be formed. Fig. 9 The barrier layer 350 shown in detail includes a first portion 152 covering the sidewall of the spacer 140, a second portion 354 of the composite layer structure partially extending into the dielectric layer 120, and a third portion 356 of the composite layer structure partially extending into the spacer 140. Thus, the contact area between the plug structure 160 and components on both sides such as the spacer 140 and the dielectric layer 120 is effectively increased by the provision of the barrier layer 350, thereby improving the structural reliability of the storage node plug and improving the electrical isolation between the storage node plug and adjacent components. Accordingly, the semiconductor device 30 manufactured by the manufacturing process of this embodiment can also have a more optimized component structure and performance, thereby improving the operating performance.

[0090] In general, the semiconductor device of the present invention is to set a barrier layer on the bit line gap wall that partially extends into the composite layer structure of the dielectric layer, thereby increasing the contact area between the storage node plug and the components on both sides, improving the structural reliability of the storage node plug, and at the same time improving the electrical isolation between the storage node plug and the adjacent bit line. As a result, the semiconductor device of the present invention can have a more optimized component structure and performance, thereby improving the operating performance of the semiconductor device.

[0091] The above description is only the preferred embodiment of the utility model, and is not intended to limit the utility model. For those skilled in the art, the utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A semiconductor device, characterized in that: include: A substrate including a plurality of active regions isolated by a plurality of shallow trenches; A plurality of conductive line structures extend on the substrate in parallel with each other and are isolated and interlaced with the active area and the shallow trench; A dielectric layer, located between the substrate and the conductor structure, wherein the dielectric layer comprises a composite layer structure; A plurality of spacers are arranged on the side walls of the conductor structure; as well as The barrier layer comprises a first portion arranged on the spacer and a second portion extending into the composite layer structure.

2. The semiconductor device according to claim 1, wherein: The spacer includes a first spacer and a second spacer stacked in sequence, the second spacer has a first thickness, the first portion and the second portion of the barrier layer have a second thickness and a third thickness respectively, and the third thickness is greater than the sum of the first thickness and the second thickness.

3. The semiconductor device according to claim 1, wherein: The second portion of the barrier layer physically contacts a bottom surface of the spacer.

4. The semiconductor device according to claim 3, characterized in that A bottom surface of the second portion of the barrier layer is higher than a bottom surface of the composite layer structure.

5. The semiconductor device according to claim 1, wherein: The second portion of the barrier layer has a first groove recessed toward the composite layer structure.

6. The semiconductor device according to claim 5, characterized in that Also included are a plurality of plug structures disposed between the conductive wire structures, wherein the plug structures have a first protrusion that fills the first groove.

7. The semiconductor device according to claim 5, characterized in that The barrier layer also includes a third portion extending into the spacer.

8. The semiconductor device according to claim 7, characterized in that The conductive line structure further includes a plurality of contacts respectively physically contacting the active regions, wherein the third portion of the barrier layer is located on the sidewalls of the contacts and has a second groove recessed toward the substrate.

9. The semiconductor device according to claim 8, characterized in that Also includes: A plurality of plug structures are arranged between the wire structures; The plug structure has a second protrusion that fills up the second groove.

10. The semiconductor device according to claim 1, wherein: The composite layer structure includes a first dielectric layer, a second dielectric layer and a third dielectric layer sequentially stacked on the substrate, wherein a sidewall of the third dielectric layer is aligned with a sidewall of the conductive line structure.

11. The semiconductor device according to claim 10, characterized in that The second portion of the barrier layer is sandwiched between the first dielectric layer and the spacer.

12. The semiconductor device according to claim 10, characterized in that The third dielectric layer directly contacts the top surface of the second portion of the barrier layer.

13. A semiconductor device, characterized in that: include: A substrate including a plurality of active regions isolated by a plurality of shallow trenches; A plurality of conductive line structures extend on the substrate in parallel with each other and are isolated and interlaced with the active area and the shallow trench; A dielectric layer located between the substrate and the conductive line structure; A barrier layer, disposed between adjacent conductive wire structures; A plurality of spacers are arranged between the conductive line structure and the barrier layer; The barrier layer includes a branch portion, and the branch portion extends along the dielectric layer toward the wire structure.

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