Unibus power supply

Abstract

The utility model relates to a unibus power supply, which comprises a host chip and a slave chip, the host chip comprises a PowerData output contact and a VSS output contact, the slave chip comprises a first input contact C and a second input contact D, the first input contact C is connected with the output contact PowerData of the host chip, the first input contact D is connected with the output contact VSS of the host chip, and the second input contact C is connected with the output contact VSS of the host chip. Or the first input contact D is connected with the output contact PowerData of the host chip, and the first input contact C is connected with the output contact VSS of the host chip. According to the utility model, whether the slave chip is positively connected or reversely connected, the slave chip can work normally, and can transmit energy and signals.

Description

Technical Field

[0001] The utility model relates to the field of electronic applications, in particular to a single bus power supply. Background Art

[0002] The single-bus power supply system has only two contact points, through which energy and information are transmitted for interaction between the host MCU and the slave chip. One contact is usually a low ground level, and the other contact is a high level or a continuous waveform composed of high and low levels, so as to transmit energy and signals. When the two contacts are reversed, normal operation and communication cannot be achieved, and the slave may also be damaged. Utility Model Content

[0003] The utility model aims at the technical problems existing in the prior art and provides a single bus power supply, so that the slave chip can work normally and transmit energy and signals regardless of forward connection or reverse connection.

[0004] The utility model solves the above technical problems with the following technical solutions: a single bus power supply, comprising: a host chip and a slave chip, the host chip comprising two output contacts, PowerData and VSS, the slave chip comprising a first input contact C and a second input contact D, the first input contact C being connected to the output contact PowerData of the host chip, the first input contact D being connected to the output contact VSS of the host chip, or the first input contact D being connected to the output contact PowerData of the host chip, the first input contact C being connected to the output contact VSS of the host chip.

[0005] Furthermore, the slave chip is provided with a bridge rectifier circuit, a voltage stabilizer and a data recovery module;

[0006] The bridge rectifier circuit includes two inputs and two outputs, wherein the two inputs are respectively connected to the first input contact C and the second input contact D, wherein the two outputs respectively output a VREC voltage signal and a ground GND signal, and the VREC voltage signal is generated by the voltage regulator as a VREG voltage signal for providing energy to the subsequent module;

[0007] The voltage input terminal of the data recovery module is connected to the VREG voltage signal. The data recovery module includes two inputs and one output, wherein the two inputs are respectively connected to the first input contact C and the second input contact D. The output of the data recovery module is a data signal recovered from the input signal.

[0008] Furthermore, the data recovery module includes two demodulation filter judgment circuits and an OR gate circuit with the same structure; the OR gate circuit includes two input terminals and one output terminal; the inputs of the two demodulation filter judgment circuits are respectively connected to the first input contact C and the second input contact D, and the outputs are respectively connected to the two input terminals of the OR gate circuit;

[0009] The demodulation filter judgment circuit judges whether the current input is a low level according to the input signal, and if it is a low level, the output level of the current circuit is pulled down to the ground and output to the OR gate circuit;

[0010] The OR gate circuit performs an OR operation on the input signals of the two input terminals and then outputs the result.

[0011] Furthermore, the demodulation and filtering judgment circuit includes a demodulator, a filter, an inverter and an NMOS tube;

[0012] The input and output of the demodulator serve as the input and output of the demodulation filter judgment circuit, the input of the filter is connected to the input of the demodulation filter judgment circuit, the input of the inverter is connected to the output of the filter, the gate of the NMOS tube is connected to the output of the inverter, the source of the NMOS tube is grounded, and the drain of the NMOS tube is connected to the output of the demodulation filter judgment circuit.

[0013] Furthermore, the output of the filter is also used as another output of the demodulation filter judgment circuit and is output to a subsequent module of the single bus power supply.

[0014] The beneficial effect of the utility model is that in the single bus power supply provided by the utility model, the slave chip can work normally and transmit energy and signals regardless of whether it is connected forwardly or reversely. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural block diagram of the existing single bus power supply system;

[0016] Figure 2 A structural block diagram of a single bus power supply system provided by an embodiment of the utility model;

[0017] Figure 3 A schematic diagram of the circuit principle of a data recovery module provided in an embodiment of the utility model. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0019] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise clearly and specifically defined.

[0020] In the description of the present application, the term "for example" is used to mean "used as an example, illustration or description". Any embodiment described as "for example" in the present application is not necessarily to be construed as being more preferred or advantageous than other embodiments. In order to enable any technician in the field to implement and use the utility model, the following description is given. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the utility model can be implemented without using these specific details. In other examples, well-known structures and processes will not be elaborated in detail to avoid unnecessary details that make the description of the utility model obscure. Therefore, the utility model is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in the present application.

[0021] Figure 1 This is the block diagram of the existing single bus power supply system. The linear regulator generates VREG to power the entire chip, and the demodulator recovers the signal VDATA for the subsequent stage. When the two contacts of the existing single bus power supply are reversed, it cannot work and communicate normally, and may also damage the slave device.

[0022] Figure 2 The single bus power supply system structure block diagram provided in this embodiment. As shown in the figure, the single bus power supply includes: a host chip and a slave chip, and the host chip includes two output contacts, PowerData and VSS. Power_Data is a continuous waveform of a high level or a combination of high and low levels, and VSS is ground.

[0023] The slave chip includes a first input contact C and a second input contact D, the first input contact C is connected to the output contact PowerData of the host chip, the first input contact D is connected to the output contact VSS of the host chip, or the first input contact D is connected to the output contact PowerData of the host chip, the first input contact C is connected to the output contact VSS of the host chip.

[0024] The slave chip is provided with a bridge rectifier circuit, a voltage stabilizer and a data recovery module;

[0025] The bridge rectifier circuit includes two inputs and two outputs, wherein the two inputs are respectively connected to a first input contact C and a second input contact D, wherein the two outputs respectively output a VREC voltage signal and a ground GND signal, and the VREC voltage signal is generated by the voltage regulator into a VREG voltage signal for providing energy to a subsequent module.

[0026] The bridge rectifier circuit can convert AC signals into DC signals. Here, regardless of whether the master and slave devices are connected forward or reverse, the bridge rectifier generates a VREC voltage signal with large ripple and a GND signal of the slave chip. VREC generates a cleaner and more stable VREG voltage signal through a voltage regulator. Both VREC and VREG can be used as power signals to provide energy for the subsequent modules. Here we choose the cleaner and more stable VREG as the main power voltage signal. The data recovery module is hung under the VREG voltage.

[0027] The voltage input terminal of the data recovery module is connected to the VREG voltage signal. The data recovery module includes two inputs and one output, wherein the two inputs are respectively connected to the first input contact C and the second input contact D. The output of the data recovery module is a data signal recovered from the input signal.

[0028] like Figure 3 As shown, the data recovery module includes two demodulation filter judgment circuits and an OR gate circuit with the same structure; the OR gate circuit includes two input terminals and one output terminal; the inputs of the two demodulation filter judgment circuits are respectively connected to the first input contact C and the second input contact D, and the outputs are respectively connected to the two input terminals of the OR gate circuit;

[0029] The demodulation filter judgment circuit judges whether the current input is a low level according to the input signal, and if it is a low level, the output level of the current circuit is pulled down to the ground and output to the OR gate circuit;

[0030] The OR gate circuit performs an OR operation on the input signals of the two input terminals and then outputs the result.

[0031] Specifically, the demodulation and filtering judgment circuit includes a demodulator, a filter, an inverter and an NMOS tube;

[0032] The input and output of the demodulator serve as the input and output of the demodulation filter judgment circuit, the input of the filter is connected to the input of the demodulation filter judgment circuit, the input of the inverter is connected to the output of the filter, the gate of the NMOS tube is connected to the output of the inverter, the source of the NMOS tube is grounded, and the drain of the NMOS tube is connected to the output of the demodulation filter judgment circuit.

[0033] The output of the filter is also used as another output of the demodulation filter judgment circuit and is output to the subsequent module of the single bus power supply.

[0034] The data recovery module mainly achieves two purposes:

[0035] a) Determine which of the two points C and D is a low level and which is a high-low level combination continuous signal. This can be achieved using a filter. A simple low-pass filter with a suitable frequency can be used. Figure 3 The two filters inside are the same. When a low-level continuous signal passes through a low-pass filter, the output is usually low, while a continuous signal of a combination of high and low levels passes through a low-pass filter, and the output is usually high.

[0036] b) Restore the data VDATA sent by the host. Because it is uncertain which point is the continuous waveform of the high and low level combination, two identical demodulators are used here, and CH and DH are used to control the demodulator output. If C is a continuous waveform of the high and low level combination and D is a low level, CH is high, CHL is low, NMOS_C is disconnected, the demodulator output signal VC is output normally, DH output is low, DHL is high, NMOS_D is turned on, the demodulator output VD is pulled down to the ground, and VD output is low level. If D is a continuous waveform of the high and low level combination and C is a low level, CH is low, CHL is high, NMOS_C is turned on, the demodulator output signal VC is pulled down to the ground, VC output is low level, DH output is high, DHL is low, NMOS_D is disconnected, and the demodulator output signal VD is output normally. VC and VD pass through the OR gate and finally output the data VDATA.

[0037] The function of the demodulator is to separate the effective signal from the input signal and output it to the subsequent circuit for processing. Different circuits can be selected according to the different requirements of the input and output signals during system design. For example, if the input signal carries a carrier during system design, but the output signal does not require a carrier but only the envelope of the input signal, an RC filter can be selected to filter out the carrier; if there are no special requirements, only an inverter, Schmitt trigger, etc. are needed to shape the waveform.

[0038] Although the preferred embodiments of the utility model have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the utility model.

[0039] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A single bus power supply, characterized in that: include: A host chip and a slave chip, wherein the host chip includes two output contacts, PowerData and VSS, and the slave chip includes a first input contact C and a second input contact D, wherein the first input contact C is connected to the output contact PowerData of the host chip, and the first input contact D is connected to the output contact VSS of the host chip, or the first input contact D is connected to the output contact PowerData of the host chip, and the first input contact C is connected to the output contact VSS of the host chip.

2. The single bus power supply according to claim 1, characterized in that: The slave chip is provided with a bridge rectifier circuit, a voltage stabilizer and a data recovery module; The bridge rectifier circuit includes two inputs and two outputs, wherein the two inputs are respectively connected to the first input contact C and the second input contact D, wherein the two outputs respectively output a VREC voltage signal and a ground GND signal, and the VREC voltage signal is generated by the voltage regulator as a VREG voltage signal for providing energy to the subsequent module; The voltage input terminal of the data recovery module is connected to the VREG voltage signal. The data recovery module includes two inputs and one output, wherein the two inputs are respectively connected to the first input contact C and the second input contact D. The output of the data recovery module is a data signal recovered from the input signal.

3. The single bus power supply according to claim 2, characterized in that: The data recovery module comprises two demodulation filter judgment circuits and an OR gate circuit of the same structure; the OR gate circuit comprises two input terminals and one output terminal; the inputs of the two demodulation filter judgment circuits are respectively connected to the first input contact C and the second input contact D, and the outputs are respectively connected to the two input terminals of the OR gate circuit; The demodulation filter judgment circuit judges whether the current input is a low level according to the input signal, and if it is a low level, the output level of the current circuit is pulled down to the ground and output to the OR gate circuit; The OR gate circuit performs an OR operation on the input signals of the two input terminals and then outputs the result.

4. The single bus power supply according to claim 3, characterized in that: The demodulation and filtering judgment circuit includes a demodulator, a filter, an inverter and an NMOS tube; The input and output of the demodulator serve as the input and output of the demodulation filter judgment circuit, the input of the filter is connected to the input of the demodulation filter judgment circuit, the input of the inverter is connected to the output of the filter, the gate of the NMOS tube is connected to the output of the inverter, the source of the NMOS tube is grounded, and the drain of the NMOS tube is connected to the output of the demodulation filter judgment circuit.

5. The single bus power supply according to claim 4, characterized in that: The output of the filter is also used as another output of the demodulation filter judgment circuit and is output to the subsequent module of the single bus power supply.

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