Silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) capable of improving gate reliability
By using a double-layer composite gate dielectric, including silicon dioxide and low K dielectric in silicon carbide VDMOS devices, to form a trench gate structure, the problem of device gate breakdown is solved, the device reliability and switching speed are improved, and the loss is reduced.
Patent Information
- Application Number
- CN202421298662.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-07
- Publication Date
- 2025-03-07
- Estimated Expiration
- 2034-06-07
AI Technical Summary
Silicon carbide VDMOS devices are prone to concentrated electric fields at the gate corners, resulting in gate breakdown and affecting the reliability of the device.
A double-layer composite gate dielectric, including silica and a low dielectric constant (low K) dielectric, was used to prepare a silicon dioxide layer by an oxidation process, and a low K dielectric layer was prepared by a deposition method to form a trench gate structure to improve the voltage tolerance of the gate.
It effectively improves the reliability of the gate, reduces the driving loss of the device, increases the switching speed, and reduces the thickness and resistance of the P-type well region, and reduces the conduction loss of the body diode.
Smart Images
Figure CN222582867U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a silicon carbide VDMOS which improves grid reliability. Background Art
[0002] Silicon carbide MOSFET is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. The development of device structure and preparation process has promoted the reduction of device on-resistance and the improvement of reliability, but it is limited by the characteristics of silicon carbide materials. The quality of the silicon dioxide gate dielectric generated is relatively low compared to that of silicon process and the work function gap of the material has requirements on the thickness of the insulating layer of the gate dielectric, especially at the gate corner of the trench gate, where electric field concentration is prone to occur, resulting in gate breakdown. Utility Model Content
[0003] The technical problem to be solved by the utility model is to provide a silicon carbide VDMOS with improved gate reliability, which adopts a composite gate dielectric, can effectively withstand the gate voltage, and improves the gate reliability.
[0004] The utility model is implemented as follows: a silicon carbide VDMOS with improved gate reliability, comprising:
[0005] Silicon carbide substrate,
[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;
[0007] A current balancing layer, wherein the lower side of the current balancing layer is connected to the upper side of the drift layer, and a groove is provided on the current balancing layer;
[0008] A well region, wherein the lower side of the well region is connected to the upper side of the current balancing layer;
[0009] A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the well region;
[0010] An N-type source region, wherein the lower side of the N-type source region is connected to the well region, and the outer sidewall of the N-type source region is connected to the inner sidewall of the P-type source region;
[0011] A composite gate dielectric layer, the composite gate dielectric layer passes through the N-type source region and is connected to the groove; a groove is provided in the composite gate dielectric layer;
[0012] A source metal layer, the source metal layer is connected to the P-type source region and the N-type source region respectively;
[0013] A gate metal layer, wherein the gate metal layer is disposed in the groove;
[0014] and a drain metal layer connected to a lower side of the silicon carbide substrate.
[0015] The advantages of the utility model are:
[0016] 1. The device of the utility model adopts a trench gate structure, and adopts a double-layer composite gate dielectric of silicon dioxide and low-k dielectric. The silicon dioxide is close to the epitaxial side of silicon carbide and is prepared by oxidation process. It has good compatibility with the silicon carbide device preparation process, high interface quality with silicon carbide, few interface defects, and does not affect the conductive characteristics inside the device. The low-k dielectric adopts the deposition method, which can effectively withstand the gate voltage and improve the gate reliability;
[0017] Second, since the induction intensity of each point in the dielectric is in the same direction and equal in magnitude, the ratio of the field strength of the low-K dielectric and silicon dioxide is E1 / E2=ε2 / ε1, that is, the internal field strength is low when the dielectric constant is large, that is, the low-K dielectric is subjected to a large field strength, and silicon dioxide is subjected to a small field strength, thus improving the reliability of the device gate;
[0018] 3. After solving the problem of device gate reliability, the P-type well region no longer needs a higher thickness to protect the gate corners. The doping concentration of the P-type well region is increased, and the thickness of the P-type well region of the device is reduced to 100nm, thereby reducing the device gate charge, reducing the device drive loss, and increasing the device switching speed;
[0019] 4. The P-type well region with thinner thickness and higher doping concentration can reduce the resistance from the P-type source region to the P-type well region and reduce the conduction loss of the body diode. 5. The device constructs an N-type current equalizing layer. After the device body diode continues to flow or is turned on, the electrons from the source region are redistributed relatively evenly to the N-type drift layer to avoid burning caused by excessive electric field density due to current concentration. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.
[0021] Figure 1 The utility model is a schematic diagram of a silicon carbide VDMOS for improving gate reliability.
[0022] Figure 2 The utility model is a flow chart of a method for preparing a silicon carbide VDMOS for improving gate reliability.
[0023] Figure 3 This is a cross-sectional view of the process of a silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 1 .
[0024] Figure 4 This is a cross-sectional view of the process of a silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 2 .
[0025] Figure 5This is a cross-sectional view of the process of a silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 3 .
[0026] Figure 6 This is a cross-sectional view of the process of a silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 4 .
[0027] Figure 7 This is a cross-sectional view of the process of a silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 5 .
[0028] Figure 8 This is a cross-sectional view of the process of a silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 6 .
[0029] Fig. 9 This is a cross-sectional view of the process of a silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 7 .
[0030] Fig.10 This is a cross-sectional view of the process of a silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 8 .
[0031] Fig.11 This is a cross-sectional view of the process of a silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 9 .
[0032] Fig.12 This is a cross-sectional view of the process of a silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 10 .
[0033] Fig.13 This is a cross-sectional view of the process of a silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 10 one. DETAILED DESCRIPTION
[0034] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0036] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
[0037] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0038] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0039] like Figure 1 As shown, the embodiment of the present application provides a silicon carbide VDMOS with improved gate reliability, including:
[0040] Silicon carbide substrate 101,
[0041] A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101;
[0042] A current balancing layer 103, wherein the lower side of the current balancing layer 103 is connected to the upper side of the drift layer 102, and a groove 1031 is provided on the current balancing layer 103;
[0043] A well region 104, wherein the bottom side of the well region 104 is connected to the top side of the current balancing layer 103;
[0044] A P-type source region 105, wherein the lower side of the P-type source region 105 is connected to the upper side of the well region 104;
[0045] An N-type source region 106, wherein the lower side of the N-type source region 106 is connected to the well region 104, and the outer sidewall of the N-type source region 106 is connected to the inner sidewall of the P-type source region 105;
[0046] A composite gate dielectric layer 107, wherein the composite gate dielectric layer 107 passes through the N-type source region 106 and is connected to the groove 1031; a groove 1073 is provided in the composite gate dielectric layer 107;
[0047] A source metal layer 108 , wherein the source metal layer 108 is connected to the P-type source region 105 and the N-type source region 106 ;
[0048] A gate metal layer 109, wherein the gate metal layer 109 is disposed in the groove 1073;
[0049] and a drain metal layer 110 , wherein the drain metal layer 110 is connected to the lower side of the silicon carbide substrate 101 .
[0050] The composite gate dielectric layer 107 includes a first dielectric layer 1071 and a second dielectric layer 1073. The first dielectric layer 1071 is silicon dioxide, and the second dielectric layer 1073 is a low-K dielectric. The thickness of the first dielectric layer 1071 is 20-30nm, and the bottom thickness of the second dielectric layer 1072 is 40nm and the sidewall thickness is 30nm.
[0051] The silicon carbide substrate 101 , the drift layer 102 and the current-balancing layer 103 are all of N-type, and the well region 105 is of P-type.
[0052] The thickness of the silicon carbide substrate 101 of the device is 1 μm, the thickness of the drift layer 102 is 3-6 μm, and the thickness of the current balancing layer 103 is 500 nm. The thickness is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the P-type well region 104 is 100 nm. The doping concentration and thickness of the P-type well region are designed after improving the reliability of the gate dielectric of the device, on the basis of ensuring the reverse withstand voltage of the device, reducing the gate charge of the device, reducing the device driving loss, increasing the switching speed of the device, reducing the resistance from the P-type source region 105 to the P-type well region 104, and reducing the conduction loss of the body diode. The thickness of the N-type source region 106 and the P-type source region 105 is 300 nm, the thickness of the first dielectric layer 1071 is 20-30 nm, and the bottom of the second dielectric layer 1072 is 20-30 nm. The thickness of the top is 40nm and the thickness of the side wall is 30nm. This is designed from the perspectives of ensuring gate control capability and improving gate reliability. The thickness of the source metal layer 108 is 300nm; since the direction and magnitude of the electric induction intensity of each point in the medium are the same, the ratio of the field strength of the second dielectric layer 1072 to that of the first dielectric layer 1071 is E1 / E2=ε2 / ε1, that is, the internal field strength with a large dielectric constant is low, that is, the second dielectric layer 1072 is subjected to a large field strength, and the first dielectric layer 1071 is subjected to a small field strength, thereby improving the gate reliability of the device. The first dielectric layer 1071 is silicon dioxide, and the second dielectric layer 1072 is a low-K dielectric. The relative dielectric constant of silicon dioxide is 3.9, and the relative dielectric constant of the low-K dielectric is ≤3, such as silicone and silicon fluoride.
[0053] like Figures 2 to 13 As shown, the method for preparing the above silicon carbide VDMOS device comprises the following steps:
[0054] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110; epitaxially growing on the silicon carbide substrate 101 to form a drift layer 102, wherein the thickness of the drift layer 102 is 3-6 μm;
[0055] Step 2: epitaxially grow on the drift layer 102 to form a current balancing layer 103 with a thickness of 500 nm;
[0056] Step 3: growing on the current balancing layer 103 to form a well region 104 with a thickness of 400 nm;
[0057] Step 4: forming a barrier layer a above the well region 104, etching the barrier layer a to form a through hole, and performing ion implantation into the well region 104 to form a P source region 105, wherein the ion implantation energy is 10-100 keV and the depth is 300 nm;
[0058] Step 5, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, perform ion implantation on the well region 104, form an N-type source region 106, the implantation energy is 10-100kev, and the depth is 300nm;
[0059] Step 6: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, perform metal deposition, and form a source metal layer 108;
[0060] Step 7, remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a, the well region 104 and the current-balancing layer 103 to form a through hole and a groove 1031, perform oxidation to form a first dielectric layer 1071, remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through hole, and then perform low-K dielectric deposition to form a second dielectric layer 1072. The composite gate dielectric layer 107 includes the first dielectric layer 1071 and the second dielectric layer 1073;
[0061] Step 8, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a and the composite gate dielectric layer 107 to form a through hole and a groove 1073, deposit metal on the groove 1073 to form a gate metal layer 109; remove the barrier layer a, and complete the preparation.
[0062] The doping concentration of the silicon carbide substrate 101 is 2e18cm-3, the doping concentration of the drift layer 102 is 6e16cm-3, the doping concentration of the current equalizing layer 103 is 5e17cm-3, the doping concentration of the well region 104 is 5e17cm-3, the doping concentration of the N-type source region 106 is 8e18cm-3, and the doping concentration of the P-type source region 105 is 4e19cm-3; the doping concentration of the silicon carbide substrate 101 is to ensure the formation of low-resistance ohmic contact with the drain metal and reduce the overall on-resistance of the device; the doping concentration of the drift layer 102 is a compromise between the reverse withstand voltage and the on-resistance of the device; the doping concentration of the current equalizing layer 103 is to redistribute the current from the source region relatively evenly to the inside of the drift layer 102 to avoid the burning phenomenon caused by excessive electric field density due to current concentration; the doping concentrations of the N-type source region 106 and the P-type source region 105 are to form ohmic contact with the source metal layer 108 and reduce the contact resistance.
[0063] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.
Claims
1. A silicon carbide VDMOS with improved gate reliability, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; A current balancing layer, wherein the lower side of the current balancing layer is connected to the upper side of the drift layer, and a groove is provided on the current balancing layer; A well region, wherein the lower side of the well region is connected to the upper side of the current balancing layer; A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the well region; An N-type source region, wherein the lower side of the N-type source region is connected to the well region, and the outer sidewall of the N-type source region is connected to the inner sidewall of the P-type source region; A composite gate dielectric layer, the composite gate dielectric layer passes through the N-type source region and is connected to the groove; a groove is provided in the composite gate dielectric layer; A source metal layer, the source metal layer is connected to the P-type source region and the N-type source region respectively; A gate metal layer, wherein the gate metal layer is disposed in the groove; and a drain metal layer connected to a lower side of the silicon carbide substrate.
2. A silicon carbide VDMOS with improved gate reliability as claimed in claim 1, characterized in that: The composite gate dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer is silicon dioxide, and the second dielectric layer is a low-K dielectric.
3. A silicon carbide VDMOS with improved gate reliability as claimed in claim 2, characterized in that: The thickness of the first dielectric layer is 20-30 nm.
4. A silicon carbide VDMOS with improved gate reliability as claimed in claim 2, characterized in that: The bottom thickness of the second dielectric layer is 40 nm, and the side wall thickness is 30 nm.
5. The silicon carbide VDMOS with improved gate reliability as claimed in claim 1, characterized in that: The silicon carbide substrate, drift layer and current balancing layer are all N-type, and the well region is P-type.
6. The silicon carbide VDMOS with improved gate reliability as claimed in claim 1, characterized in that: The thickness of the flow balancing layer is 500 nm.
7. The silicon carbide VDMOS with improved gate reliability as claimed in claim 1, characterized in that: The thickness of the well region is 100 nm.