Display panel and display device

Abstract

The utility model provides a display panel and a display device. The display panel comprises a first substrate and a second substrate which are oppositely arranged. A plurality of data lines, a plurality of grid lines and a plurality of sub-pixel structures are arranged on one side, facing the second substrate, of the first substrate; each sub-pixel structure comprises a thin film transistor, a color filter part, a first insulating layer provided with a via hole and a shielding layer which are sequentially arranged in the direction away from the first substrate. The via hole exposes at least part of the drain electrode of the thin film transistor and is not overlapped with the orthographic projection of the color filter part on the first substrate. A black matrix is arranged on the side, facing the first substrate, of the second substrate and comprises a first part, and the orthographic projection of the first part on the first substrate is located on the side, away from the orthographic projection of the corresponding grid line on the first substrate, of the orthographic projection of the via hole on the first substrate. The orthographic projection of the shielding layer and the orthographic projection of the first part on the first substrate are overlapped. The light leakage phenomenon can be improved or avoided.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Liquid crystal display (LCD) panels have been successfully applied in all aspects of production and life, and have become a necessity in people's lives. With the increase in people's needs, COA (Color Filter on Array) technology has emerged to improve the display quality of display panels. COA technology is an integrated technology that directly manufactures color filters on array substrates. It can effectively solve the problems of light leakage caused by alignment deviation in the cell alignment process of liquid crystal display panels, and has the advantages of significantly improving the display aperture ratio. Summary of the invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and proposes a display panel and a display device.

[0004] In order to achieve the above-mentioned object, in a first aspect, the present disclosure provides a display panel, comprising: a first substrate and a second substrate arranged opposite to each other; a plurality of data lines, a plurality of gate lines and a plurality of sub-pixel structures are arranged on a side of the first substrate facing the second substrate; the data lines and the gate lines intersect to define a plurality of pixel areas, and the sub-pixel structures are located in the pixel areas;

[0005] The sub-pixel structure comprises a thin film transistor, a color filter portion, and a first insulating layer having a via hole, which are sequentially arranged in a direction away from the first substrate, the gate of the thin film transistor is electrically connected to the corresponding gate line, the via hole exposes at least a portion of the drain of the thin film transistor and has no overlap with the orthographic projection of the color filter portion on the first substrate;

[0006] A black matrix is ​​disposed on a side of the second substrate facing the first substrate, the black matrix comprising a first portion, an orthographic projection of the first portion on the first substrate being located on a side where an orthographic projection of the via hole on the first substrate is away from an orthographic projection of a corresponding gate line on the first substrate;

[0007] The sub-pixel structure further includes a shielding layer for shielding light, and the shielding layer overlaps with the orthographic projection of the first portion on the first substrate; the color of light shielded by the shielding layer at least includes the color of light that can be filtered out by the color filter portion.

[0008] Optionally, the material of the shielding layer includes metal, and the shielding layer is insulated from the thin film transistor.

[0009] Optionally, the shielding layer is provided at the same layer as part of the thin film transistor.

[0010] Optionally, a pixel electrode is disposed on the side of the color filter away from the first substrate; a second insulating layer is also disposed on the side of the layer where the pixel electrode is located away from the first substrate, and the shielding layer is located on the side of the second insulating layer away from the first substrate.

[0011] Optionally, a common electrode is further disposed on a side of the second insulating layer away from the first substrate, and a third insulating layer is disposed between the shielding layer and the common electrode.

[0012] Optionally, the orthographic projection of the shielding layer on the first substrate covers the orthographic projection of the via hole on the first substrate.

[0013] Optionally, the orthographic projection of the black matrix on the first substrate covers the orthographic projection of the shielding layer on the first substrate.

[0014] Optionally, an orthographic projection of the shielding layer on the first substrate has no overlap with an orthographic projection of the gate of the thin film transistor on the first substrate.

[0015] Optionally, a minimum distance between the via hole and an orthographic projection of the color filter portion on the first substrate is not less than 10 um.

[0016] Optionally, the drain of the thin film transistor includes a connection portion exposed by the via hole, the gate line includes a main body portion extending along a first direction and a bent portion connected to the main body portion, the bent portion is arranged opposite to the connection portion of the corresponding thin film transistor and is bent in a direction away from the connection portion;

[0017] The shielding layer and the color filter portion are connected to form an integrated structure, and the integrated structure has no overlap with an orthographic projection of the via hole on the first substrate.

[0018] Optionally, orthographic projections of the gate, the source and the drain of the thin film transistor on the first substrate overlap with orthographic projections of the integrated structure on the first substrate.

[0019] Optionally, the drain of the thin film transistor extends along a second direction, and the second direction intersects with the first direction.

[0020] Optionally, an angle between the second direction and the first direction is between 30° and 45°.

[0021] Optionally, a minimum distance between the via hole and an orthographic projection of the integrated structure on the first substrate is not less than 10 um.

[0022] In a second aspect, the present disclosure provides a display device, comprising a display panel as described in any one of the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0024] Figure 1 is a top view of a sub-pixel structure in a display panel in some embodiments;

[0025] Figure 2 is a cross-sectional structural diagram of a sub-pixel structure in a display panel in some embodiments;

[0026] Figure 3 is a cross-sectional structural diagram of a sub-pixel structure in a display panel in some embodiments of the present disclosure;

[0027] Figure 4 is a top view of a sub-pixel structure in a display panel in some embodiments of the present disclosure;

[0028] Figure 5 is a top view of each film layer of a sub-pixel structure in a display panel in some embodiments of the present disclosure;

[0029] Figure 6 is a top view of a sub-pixel structure in a display panel in some other embodiments of the present disclosure;

[0030] Figure 7 is a top view of each film layer of a sub-pixel structure in a display panel in some other embodiments of the present disclosure;

[0031] Figure 8 is a top view of a sub-pixel structure in a display panel in some other embodiments of the present disclosure;

[0032] Fig. 9 is a top view of each film layer of a sub-pixel structure in a display panel in some other embodiments of the present disclosure;

[0033] FIG. 10( a ) is a top view of a sub-pixel structure in a display panel in some other embodiments of the present disclosure;

[0034] FIG10( b ) is a top view of a sub-pixel structure in a display panel in some other embodiments of the present disclosure.

[0035] A. via hole; 104. first insulating layer; 3. color filter part; 10. black matrix; 100. first substrate; 200. second substrate; 1. data line; 9. gate line; 110. first part; 4. shielding layer; 31. red filter part; 32. green filter part; 2. touch signal line; 7. active layer; 101. gate insulating layer; 102. passivation layer; 11. pixel electrode; 12. common electrode; 106. third insulating layer; 105. second insulating layer; 13. spacer structure; 91. main body; 92. bending part; 300. integrated structure; 921. first connecting bar; 922. second connecting bar; 923. third connecting bar; 8. gate; 5. drain; 6. source. DETAILED DESCRIPTION

[0036] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0038] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not represent any order, quantity or importance, but are only used to distinguish different components. Similarly, "including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0039] As used herein, "parallel" and "perpendicular" include the described situation and the situation similar to the described situation, and the range of the similar situation is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°.

[0040] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0041] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0042] In some embodiments, the liquid crystal display device includes a liquid crystal display panel and a backlight source, the liquid crystal display panel includes an array substrate and a color filter substrate, the color filter substrate includes a color filter layer, and the backlight source emits white light and then passes through the color filter layer to achieve color display. In other embodiments, such as Figure 1 and Figure 2 As shown, in a liquid crystal display panel based on COA technology, a color filter layer is disposed on an array substrate. The liquid crystal display panel includes a plurality of data lines 1, a plurality of gate lines 9 and a plurality of sub-pixel structures located on a first substrate 100. The data lines 1 and the gate lines 9 intersect to define a plurality of pixel regions, and the sub-pixel structures are located in the pixel regions. The sub-pixel structure includes: a thin film transistor ( Figure 1Only part of the structure of the thin film transistor is shown, such as the drain electrode 5 of the thin film transistor, the gate insulating layer 101 and the active layer 7, wherein the gate of the thin film transistor is arranged in the same layer as the gate line 9), the first insulating layer 104, the color filter 3 and the pixel electrode 11. Among them, the color filter 3 is located between the thin film transistor and the first insulating layer 104, and there is a gap between the layer where the color filter 3 is located and the layer where the black matrix 10 is located. Among them, the first insulating layer 104 is provided with a via A, and the via A exposes a part of the drain electrode 5 of the thin film transistor, and the pixel electrode 11 is electrically connected to the drain electrode 5 of the thin film transistor through the via A. The pixel electrode 11 and the common electrode 12 are sequentially arranged on the side of the thin film transistor away from the first substrate 100. A third insulating layer 106 and a second insulating layer 105 are arranged between the pixel electrode 11 and the common electrode 12. A passivation layer 102 is arranged between the layer where the drain electrode 5 of the thin film transistor is located and the layer where the first insulating layer 104 is located (the material of the passivation layer 102 can be, for example, silicon nitride). Correspondingly, after the color filter layer is directly disposed on the array substrate, it is not necessary to further dispose a color filter layer on the second substrate 200 that is aligned with the array substrate, and only the black matrix 10 is required.

[0043] In order to prevent the material of the color filter 3 from falling into the via hole A opened in the first insulating layer 104 and causing adverse effects on the display panel, a certain distance d needs to be maintained between the via hole A opened in the first insulating layer 104 and the color filter 3. In this case, since there is a gap between the layer where the color filter 3 is located and the layer where the black matrix 10 is located, the wide-angle light from the backlight source will be directly emitted from the gap between the layer where the color filter 3 is located and the layer where the black matrix 10 is located, resulting in serious light leakage.

[0044] Therefore, in order to at least alleviate or solve one of the above-mentioned technical problems, the present disclosure provides a display panel and a display device.

[0045] In some embodiments, Figure 3 and Figure 4 As shown, the present disclosure provides a display panel, comprising: a first substrate 100 and a second substrate 200 arranged opposite to each other. A plurality of data lines 1, a plurality of gate lines 9 and a plurality of sub-pixel structures are arranged on the side of the first substrate 100 facing the second substrate 200. The data lines 1 and the gate lines 9 intersect to define a plurality of pixel regions, and the sub-pixel structures are located in the pixel regions.

[0046] The sub-pixel structure includes a thin film transistor, a color filter portion 3, and a first insulating layer 104 having a via A, which are sequentially arranged in a direction away from the first substrate 100. The gate electrode 8 of the thin film transistor is electrically connected to the corresponding gate line 9. The via A exposes at least a portion of the drain electrode 5 of the thin film transistor, and has no overlap with the orthographic projection of the color filter portion 3 on the first substrate 100. In the following description of the embodiments of the present disclosure, the gate line 9 refers to the gate line connected to the thin film transistor of the sub-pixel structure.

[0047] A black matrix 10 is disposed on the side of the second substrate 200 facing the first substrate 100. The black matrix 10 includes a first portion 110. The orthographic projection of the first portion 110 on the first substrate 100 is located on a side where the orthographic projection of the via A on the first substrate 100 is away from the orthographic projection of the corresponding gate line 9 on the first substrate 100.

[0048] In addition, the sub-pixel structure further includes a shielding layer 4 for shielding light. The shielding layer 4 overlaps with the orthographic projection of the first portion 110 on the first substrate 100. The color of the light blocked by the shielding layer 4 at least includes the color of the light that can be filtered out by the color filter portion 3. That is, it can be understood that the shielding layer 4 can filter out all color lights, that is, it can block all light from the backlight source, or the shielding layer 4 can block the color of the light that can be filtered out by the color filter portion 3.

[0049] For example, in a sub-pixel structure, the color filter section 3 may be a red filter section 31, or may be a green filter section 32, or may be a blue filter section. When the color filter section 3 in a sub-pixel structure is a red filter section 31, the shielding layer 4 in the sub-pixel structure may filter out light except red light. When the color filter section 3 in a sub-pixel structure is a green filter section 32, the shielding layer 4 in the sub-pixel structure may filter out light except green light.

[0050] Since the via A and the orthographic projection of the color filter section 3 on the first substrate 100 do not overlap, the white light from the backlight source may be incident between the color filter section 3 and the first portion 110 of the black matrix 10. In the embodiment of the present disclosure, by providing a shielding layer 4 and making the shielding layer 4 overlap with the orthographic projection of the first portion 110 on the first substrate 100, the light incident between the color filter section 3 and the first portion 110 of the black matrix 10 can be shielded (for example, absorbed or reflected), or filtered, thereby improving or avoiding light leakage between the color filter section 3 and the black matrix 10. For example, when the shielding layer 4 can filter out all color lights, the large-angle white light from the backlight source can be reflected back to the sub-pixel structure to avoid white light leakage. For another example, when the blocking layer can filter out the light color that the color filter portion 3 can filter out, the light color that the color filter portion 3 can filter out in the wide-angle white light can be filtered out, that is, the light color allowed to pass by the color filter portion 3 is retained, thereby improving the light leakage phenomenon and improving the utilization rate of light.

[0051] In the embodiment of the present disclosure, the material of the first insulating layer 104 may include an organic material.

[0052] In the embodiment of the present disclosure, a plurality of pixel regions are arranged in an array, for example, a thin film transistor in each row of pixel regions can be connected to a corresponding gate line, and a thin film transistor in each column of pixel regions can be connected to a corresponding data line. For another example, a dual-gate connection mode is adopted, that is, the number of gate lines is twice the number of pixel region rows, and the number of data lines is half the number of pixel region columns. At this time, a plurality of thin film transistors in the same row of pixel regions are electrically connected to two adjacent gate lines respectively; and the same data line is electrically connected to the thin film transistors in two adjacent columns respectively. The drawings of the embodiment of the present disclosure illustrate the dual-gate connection mode, and two columns of pixel regions are arranged between two adjacent data lines. In addition, in one example, the display panel can also be used as a touch display panel, and a touch signal line 2 is also arranged on the first substrate 100, and the touch signal line 2 is electrically connected to the touch electrode. For example, the common electrode can be reused as a touch electrode, and a touch signal line 2 is arranged between at least two adjacent data lines 1.

[0053] Figure 5 (a) to (g) in Figure 4 The schematic top view of each film layer of two adjacent sub-pixel structures is shown. Figure 5 (a) is a schematic top view of the gate line 9 and the gate 8. Figure 5 (b) is a schematic top view of the active layer 7. Figure 5 (c) is a schematic top view of the shielding layer 4. Figure 5 (d) is a schematic top view of the source 6 and the drain 5. Figure 5(e) is a schematic top view of the black matrix 10 . Figure 5 (f) in FIG. 1 is a schematic top view of the color filter section 3 , wherein, among two adjacent color filter sections 3 , one may be a red filter section 31 , and the other may be a green filter section 32 . Figure 5 (g) is a top view schematic diagram of the data line 1 and the touch signal line 2.

[0054] In some embodiments, the material of the shielding layer 4 includes metal, and the shielding layer 4 is insulated from the thin film transistor.

[0055] In the disclosed embodiment, the shielding layer is made of metal, which can make good use of the metal's opaque property to reflect large-angle light back to the sub-pixel structure to avoid light leakage. At the same time, the shielding layer 4 is insulated from the thin-film transistor, that is, the shielding layer 4 is a floating metal, thereby ensuring that there is no signal access to the shielding layer 4, thereby avoiding the shielding layer 4 from affecting the performance of the display panel.

[0056] In some embodiments, the shielding layer 4 is disposed at the same layer as a portion of the thin film transistor.

[0057] For example, the shielding layer 4 can be disposed in the same layer as the gate electrode 8 of the thin film transistor. Alternatively, the shielding layer 4 can be disposed in the same layer as the source electrode 6 and the drain electrode 5 of the thin film transistor.

[0058] The present invention discloses that the shielding layer 4 is arranged on the same layer as the gate electrode 8 of the thin film transistor, or the shielding layer 4 is arranged on the same layer as the source electrode 6 and the drain electrode 5 of the thin film transistor. Thus, the shielding layer 4 can be prepared at the same time as the gate electrode 8 of the thin film transistor is prepared, or at the same time as the source electrode 6 and the drain electrode 5 of the thin film transistor is prepared, thereby saving the entire preparation process of the display panel and saving costs.

[0059] In some embodiments, Figure 3 and Figure 6 As shown, a pixel electrode 11 is disposed on a side of the color filter portion 3 away from the first substrate 100. A second insulating layer 105 is also disposed on a side of the layer where the pixel electrode 11 is located away from the first substrate 100, and the shielding layer 4 is located on a side of the second insulating layer 105 away from the first substrate 100. For example, the first insulating layer 104 in the embodiment of the present disclosure can also serve as a planarization layer, and the pixel electrode 11 can be disposed on a surface of the first insulating layer 104 away from the first substrate 100, thereby ensuring the flatness of the pixel electrode 11.

[0060] Figure 7 (a) to (h) in Figure 6 The schematic top view of each film layer of two adjacent sub-pixel structures is shown. Figure 7 (a) is a schematic top view of the gate line 9 and the gate 8. Figure 7(b) is a schematic top view of the color filter section 3 , wherein, among two adjacent color filter sections 3 , one may be a red filter section 31 , and the other may be a green filter section 32 . Figure 7 (c) is a schematic top view of the shielding layer 4. Figure 7 (d) is a schematic top view of the source 6 and the drain 5. Figure 7 (e) is a schematic top view of the active layer 7. Figure 7 (f) in FIG. 1 is a schematic top view of the black matrix 10 . Figure 7 (g) is a top view schematic diagram of the data line 1 and the touch signal line 2. Figure 7 (g) is a schematic top view of the pixel electrode 11.

[0061] In some embodiments, Figure 3 and Figure 8 As shown, a common electrode 12 is further disposed on a side of the second insulating layer 105 away from the first substrate 100 , and a third insulating layer 106 is disposed between the shielding layer 4 and the common electrode 12 .

[0062] Fig. 9 (a) to (g) in Figure 8 The schematic top view of each film layer of two adjacent sub-pixel structures is shown. Fig. 9 (a) is a schematic top view of the gate line 9 and the gate 8. Fig. 9 (b) is a schematic top view of the color filter section 3, wherein, among two adjacent color filter sections 3, one may be a red filter section 31 and the other may be a green filter section 32. Fig. 9 (c) is a schematic top view of the pixel electrode 11. Fig. 9 (d) is a schematic top view of the common electrode 12 . Fig. 9 (e) is a schematic top view of the active layer 7. Fig. 9 (f) is a schematic top view of the source 6 and the drain 5. Fig. 9 (g) is a top view schematic diagram of the data line 1 and the touch signal line 2.

[0063] In addition, in the embodiments of the present disclosure, Figure 8 and Fig. 9 As shown, a spacer structure 13 is further provided between the first substrate 100 and the second substrate 200 for supporting the first substrate 100 and the second substrate 200 of the box, and the orthographic projection of the spacer structure 13 on the first substrate 100 does not overlap with the orthographic projection of the pixel electrode 11 on the first substrate 100.

[0064] The shielding layer 4 in the embodiment of the present disclosure can also be arranged between the pixel electrode 11 and the common electrode 12, and the shielding layer 4 is insulated and spaced apart from the pixel electrode 11 and the common electrode 12 respectively, so as to prevent the shielding layer 4 from affecting the signals on the pixel electrode 11 and the common electrode in the display panel while preventing large-angle light leakage.

[0065] In some embodiments, Figures 3 to 5 As shown, the orthographic projection of the shielding layer 4 on the first substrate 100 covers the orthographic projection of the via A on the first substrate 100 .

[0066] Since the orthographic projection of the color filter portion 3 on the first substrate 100 does not overlap with the orthographic projection of the via A on the first substrate 100, in the embodiment of the present disclosure, by making the orthographic projection of the shielding layer 4 on the first substrate 100 cover the orthographic projection of the via A on the first substrate 100, it is possible to improve or avoid light leakage through the shielding layer 4 while preventing the material of the color filter portion 3 from falling into the via A and affecting the performance of the display panel.

[0067] In some embodiments, Figures 3 to 5 As shown, the orthographic projection of the black matrix 10 on the first substrate 100 covers the orthographic projection of the shielding layer 4 on the first substrate 100 .

[0068] On the basis that the first portion 110 of the black matrix 10 overlaps with the orthographic projection of the shielding layer 4 on the first substrate 100, as shown in FIG. Figure 6 As shown, the orthographic projection of the black matrix 10 on the first substrate 100 can be further made to cover the orthographic projection of the shielding layer 4 on the first substrate 100, that is, to prevent the orthographic projection of the shielding layer 4 on the first substrate 100 from exceeding the range of the orthographic projection of the black matrix 10 on the first substrate 100. The disclosed embodiment can prevent the shielding layer 4 from blocking small-angle light when the orthographic projection of the shielding layer 4 on the first substrate 100 exceeds the range of the orthographic projection of the black matrix 10 on the first substrate 100. In some embodiments, the orthographic projection of the shielding layer 4 on the first substrate 100 does not overlap with the orthographic projection of the gate of the thin film transistor on the first substrate 100.

[0069] For example, the orthographic projection of the shielding layer 4 on the first substrate 100 does not overlap with the orthographic projections of the gate electrode 8 and the source electrode 6 of the thin film transistor on the first substrate 100 .

[0070] Since the material of the gate 8 of the thin film transistor can be metal, it can block light. Therefore, the present disclosure can save preparation process, save cost and improve utilization by making the orthographic projection of the shielding layer 4 on the first substrate 100 non-overlapping with the orthographic projection of the gate 8 of the thin film transistor on the first substrate 100.

[0071] In some embodiments, the minimum distance between the via hole A and the orthographic projection of the color filter portion 3 on the first substrate 100 is not less than 10 um.

[0072] In the embodiment of the present disclosure, by ensuring that the minimum distance between the via A and the orthographic projection of the color filter portion 3 on the first substrate 100 is not less than 10 um, the distance between the edge of the color filter portion 3 close to the via A and the orthographic projection of the via A on the first substrate 100 can be ensured, thereby preventing the material of the color filter portion 3 from falling into the via A, thereby causing adverse reactions to the display panel.

[0073] In some embodiments, Figure 7 and Figure 8 As shown, the drain electrode 5 of the thin film transistor includes a connecting portion (not shown in the figure) exposed by the via hole A, and the shape of the connecting portion corresponds to Figure 7 The gate line 9 includes a main body 91 extending along a first direction and a bent portion 92 connected to the main body 91. The bent portion 92 is arranged opposite to the connecting portion of the corresponding thin film transistor and is bent in a direction away from the connecting portion. The shielding layer 4 and the color filter portion 3 are connected to form an integrated structure 300, and the integrated structure 300 does not overlap with the orthographic projection of the via A on the first substrate 100. The first direction is the row direction in which the multiple pixel areas are arranged.

[0074] In the embodiment of the present disclosure, the gate line 9 is designed to include a main body 91 extending along a first direction and a bent portion 92 connected to the main body 91, and the bent portion 92 is arranged relative to the connection portion of the corresponding thin film transistor and is bent in a direction away from the connection portion. The drain electrode 5 can be moved in a direction close to the corresponding gate line 9, that is, correspondingly, the position of the via A will also move relatively in a direction close to the corresponding gate line 9. In this case, the shielding layer 4 can be arranged in the same layer as the color filter portion 3, and connected to the color filter portion 3 to form an integrated structure 300, that is, at this time, the shielding layer 4 has the same function as the color filter portion 3. Therefore, the embodiment of the present disclosure can achieve the goal of keeping the integrated structure 300 at a corresponding distance from the via A as a whole, avoiding the material of the color filter portion 3 from falling into the via A, and at the same time, the shielding layer 4 in the integrated structure 300 can be used to filter the color of large-angle light, thereby avoiding light leakage, and at the same time improving the utilization rate of light and optimizing the purity of color.

[0075] In one example, if Figure 8As shown in (a) of FIG. 1 , the first connecting bar 921, the second connecting bar 922 and the third connecting bar 923 are connected in sequence to the curved portion 92. The first connecting bar 921 is connected to the gate 8. The second connecting bar 922 extends along the first direction. The third connecting portion is connected to the main body 91. The extension direction of the first connecting bar 921 and the extension direction of the third connecting bar 923 both intersect with the first direction. That is, in the embodiment of the present disclosure, the curved portion 92 that bends toward a direction away from the connecting portion can be realized by the first connecting bar 921, the second connecting bar 922 and the third connecting bar 923.

[0076] Of course, in actual production, it is not limited to this design method and can be flexibly adjusted according to actual needs.

[0077] In some embodiments, the orthographic projections of the gate 8 , the source 6 , and the drain 5 of the thin film transistor on the first substrate 100 overlap with the orthographic projection of the integrated structure 300 on the first substrate 100 .

[0078] For example Figure 1 and Figure 7 The embodiments shown are compared and analyzed: Figure 1 The orthographic projections of the gate electrode 8, source electrode 6 and drain electrode 5 of the thin film transistor on the first substrate 100 do not overlap with the orthographic projection of the color filter portion 3 on the first substrate 100. This is because the color filter portion 3 needs to maintain a certain distance from the orthographic projection of the via hole A on the first substrate 100, and the via hole A is a part of the exposed drain electrode 5. Therefore, the orthographic projections of the color filter portion 3 and the drain electrode 5 on the first substrate 100 need to maintain a certain distance. Figure 7 In the embodiment shown, the orthographic projections of the gate 8, source 6 and drain 5 of the thin film transistor on the first substrate 100 overlap with the orthographic projection of the integrated structure 300 on the first substrate 100. For example, the gate 8, source 6 and drain 5 can be arranged along the second direction, wherein the second direction intersects with the first direction, so that the drain 5 can be arranged in a direction different from the first direction. Figure 1In the embodiment shown, it is closer to the gate line 9. On this basis, since the via A needs to expose part of the drain 5, the position of the via A can also be closer to the gate line 9 accordingly. In the case where the via A moves closer to the gate line 9, if the minimum distance between the color filter 3 and the orthographic projection of the via A on the first substrate 100 needs to be met, the color filter 3 can extend more in the direction close to the gate line 9. At this time, the extended part of the color filter 3 corresponds to the shielding layer 4 in this embodiment, that is, the original color filter 3 and the shielding layer 4 form an integrated structure 300. Further, under the premise that the black matrix 10 remains unchanged, it can be achieved that the integrated structure 300 overlaps with the orthographic projection of the black matrix 10 on the first substrate 100. Therefore, the embodiment of the present disclosure can filter the large-angle light between the black matrix 10 and the integrated structure 300 through the integrated structure 300, thereby avoiding light leakage while improving light utilization and color purity.

[0079] In some embodiments, Figure 7 and 9 As shown, the drain electrode 5 of the thin film transistor extends along the second direction, and the second direction intersects the first direction. Furthermore, the angle α between the second direction and the first direction can be between 30° and 50°. Optionally, the angle α between the second direction and the first direction can be between 30° and 45°.

[0080] For example, the angle α between the second direction and the first direction can be 30°, 31°, 32°, 33°, 34°, 35°, 36°, 37°, 38°, 39°, 40°, 41°, 42°, 43°, 44°, 45°, 46°, 47°, 48°, 49° or 50°.

[0081] As shown in the following table, in the embodiment of the present disclosure, the inclination angle of the drain electrode 5 is tested from 30° to 50°, and the inclination angle of the drain electrode 5 refers to the angle α between the second direction and the first direction. It can be seen from the table that for each sub-pixel structure (Pixel), properly inclining the drain electrode can increase Cgs and Clcst, where Cgs is the parasitic capacitance between the layer where the gate line is located and the layer where the data line is located, and Clcst is the liquid crystal capacitance.

[0082]

[0083]

[0084] The present disclosure sets the angle α between the extension direction of the drain electrode 5 of the thin film transistor and the first direction to be between 30° and 45°, which can effectively reduce the distance between the drain electrode 5 and the gate line 9, thereby reducing the distance between the via A and the orthographic projection of the gate line 9 on the first substrate 100, and further allows the color filter 3 to extend toward one side of the gate line 9, and the extended portion is the shielding layer 4, that is, the shielding layer 4 and the color filter 3 are connected to form an integrated structure 300, so as to filter the large-angle light between the black matrix 10 and the integrated structure 300. At the same time, the aperture ratio and the display performance of the display substrate can also be guaranteed.

[0085] In some embodiments, the minimum distance between the via hole A and the orthographic projection of the integrated structure 300 on the first substrate 100 is not less than 10 um.

[0086] In the embodiment of the present disclosure, since the shielding layer 4 and the color filter portion 3 are connected to form an integrated structure 300, the distance between the edge of the integrated structure 300 close to the via A and the orthographic projection of the via A on the first substrate 100 can be ensured by making the minimum distance between the via A and the orthographic projection of the integrated structure 300 on the first substrate 100 not less than 10um, thereby preventing the material of the integrated structure 300 from falling into the via A, thereby causing adverse reactions to the display panel.

[0087] In order to facilitate understanding of the technical solution of this application and Figure 6 and Figure 8 FIG. 10( a ) and FIG. 10( b ) respectively show the difference in sub-pixel structure in the embodiment shown in FIG. Figure 6 and Figure 8 A partial film layer structure diagram of a sub-pixel structure in the embodiment shown.

[0088] As shown in FIG. 10( a ), the orthographic projection of the first portion 110 of the black matrix 10 on the first substrate 100 is located on a side of the orthographic projection of the via on the first substrate 100 away from the orthographic projection of the gate line 9 on the first substrate 100. The shielding layer 4 overlaps with the orthographic projection of the first portion 110 on the first substrate 100.

[0089] As shown in FIG. 10( b ), a curved portion 92 is provided on the gate line 9, and the orthographic projection of the curved portion 92 on the first substrate 100 forms a receiving groove. Further, the extension direction of the drain electrode 5 is made to intersect with the first direction (the extension direction of the gate line 9 ), so that the orthographic projection of the drain electrode 5 on the first substrate 100 can be located in the receiving groove, so that the drain electrode 5 moves in a direction away from the center of the sub-pixel structure compared with the drain electrode in FIG. 10( a ). Correspondingly, since the via A needs to expose part of the drain electrode 5 (connecting portion), the position of the via A will be further away from the center of the pixel area compared with FIG. 10( a ). This will increase the distance between the original color filter portion 3 in FIG. 10( a ) and the orthographic projection of the via A on the first substrate 100. Therefore, in this case, the color filter portion 3 can be extended in a direction close to the gate line 9, that is, corresponding to the shielding layer 4 in FIG. 10( b ), so that the shielding layer 4 and the color filter portion 3 form an integrated structure 300.

[0090] In the embodiments shown in FIG. 10( a) and FIG. 10( b), since the distances from the via hole A to the center of the pixel area are different, the position of the first portion 110 of the black matrix 10 is also different accordingly. However, the same thing is that the distance between the via hole A and the color filter portion 3 in FIG. 10( a) and the distance between the via hole A and the integrated structure 300 in FIG. 10( b) are both kept at a sufficient distance to prevent the color filter material from falling into the via hole A.

[0091] In the embodiment shown in FIG. 10( a), the shielding layer 4 may be a metal. For example, in one example, the shielding layer 4 may be provided in the same layer as the gate line 9. Since metal has good light absorption or light reflection effects, the shielding layer 4 may absorb or reflect large-angle light back into the sub-pixel structure, thereby avoiding large-angle light leakage. In the embodiment shown in FIG. 10( b), the shielding layer 4 and the color filter section 3 are an integrated structure 300, so the function of the shielding layer 4 at this time is the same as that of the color filter section 3, that is, to filter out the light that the color filter section 3 can filter out in the large-angle light, and to transmit the light that the color filter section 3 allows to be transmitted. In this embodiment, in addition to avoiding large-angle light leakage, the utilization rate of large-angle light can also be improved, and the color purity of the sub-pixel structure can be improved.

[0092] In some embodiments, the present disclosure further provides a display device, comprising any display panel described in the present disclosure.

[0093] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display panel, characterized in that: include: A first substrate and a second substrate are arranged opposite to each other; a plurality of data lines, a plurality of gate lines and a plurality of sub-pixel structures are arranged on a side of the first substrate facing the second substrate; the data lines and the gate lines intersect to define a plurality of pixel areas, and the sub-pixel structures are located in the pixel areas; The sub-pixel structure comprises a thin film transistor, a color filter portion, and a first insulating layer having a via hole, which are sequentially arranged in a direction away from the first substrate, the gate of the thin film transistor is electrically connected to the corresponding gate line, the via hole exposes at least a portion of the drain of the thin film transistor and has no overlap with the orthographic projection of the color filter portion on the first substrate; A black matrix is ​​disposed on a side of the second substrate facing the first substrate, the black matrix comprising a first portion, an orthographic projection of the first portion on the first substrate being located on a side where an orthographic projection of the via hole on the first substrate is away from an orthographic projection of a corresponding gate line on the first substrate; The sub-pixel structure further includes a shielding layer for shielding light, and the shielding layer overlaps with the orthographic projection of the first portion on the first substrate; the color of light shielded by the shielding layer at least includes the color of light that can be filtered out by the color filter portion.

2. The display panel according to claim 1, characterized in that: The material of the shielding layer includes metal, and the shielding layer is insulated from the thin film transistor.

3. The display panel according to claim 2, characterized in that: The shielding layer is arranged at the same layer as a part of the thin film transistor.

4. The display panel according to claim 1, characterized in that: A pixel electrode is disposed on the side of the color filter away from the first substrate; a second insulating layer is also disposed on the side of the layer where the pixel electrode is located away from the first substrate, and the shielding layer is located on the side of the second insulating layer away from the first substrate.

5. The display panel according to claim 4, characterized in that: A common electrode is further disposed on a side of the second insulating layer away from the first substrate, and a third insulating layer is disposed between the shielding layer and the common electrode.

6. The display panel according to any one of claims 1 to 5, characterized in that: The orthographic projection of the shielding layer on the first substrate covers the orthographic projection of the via hole on the first substrate.

7. The display panel according to any one of claims 1 to 5, characterized in that: The orthographic projection of the black matrix on the first substrate covers the orthographic projection of the shielding layer on the first substrate.

8. The display panel according to any one of claims 1 to 5, characterized in that: The orthographic projection of the shielding layer on the first substrate does not overlap with the orthographic projection of the gate of the thin film transistor on the first substrate.

9. The display panel according to any one of claims 1 to 5, characterized in that: The minimum distance between the via hole and the orthographic projection of the color filter portion on the first substrate is not less than 10 um.

10. The display panel according to claim 1, characterized in that: The drain electrode of the thin film transistor includes a connection portion exposed by the via hole, the gate line includes a main body portion extending along a first direction and a bent portion connected to the main body portion, the bent portion is arranged opposite to the connection portion of the corresponding thin film transistor and is bent in a direction away from the connection portion; The shielding layer and the color filter portion are connected to form an integrated structure, and the integrated structure has no overlap with an orthographic projection of the via hole on the first substrate.

11. The display panel according to claim 10, characterized in that: The orthographic projections of the gate, the source and the drain of the thin film transistor on the first substrate overlap with the orthographic projection of the integrated structure on the first substrate.

12. The display panel according to claim 10 or 11, characterized in that: The drain electrode of the thin film transistor extends along a second direction, and the second direction intersects with the first direction.

13. The display panel according to claim 12, characterized in that: The angle between the second direction and the first direction is between 30° and 45°.

14. The display panel according to claim 10 or 11, characterized in that: The minimum distance between the via hole and the orthographic projection of the integrated structure on the first substrate is not less than 10 um.

15. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 14.

Images