Band-gap reference starting circuit

Abstract

The utility model discloses a band-gap reference starting circuit, which comprises a first metal oxide semiconductor (MOS) tube, a grid control circuit, a first bias current, a second bias current, a mirror image current and a band-gap reference circuit module, the first bias current and the mirror current are both connected with the grid control circuit, the control end of the grid control circuit is connected with the output end of the band-gap reference circuit, the output end of the grid control circuit is connected with the grid of the first MOS tube, the second bias current is connected with the input end of the first MOS tube, and the output end of the first MOS tube is connected with the band-gap reference circuit module. The problem that the starting circuit may fail when the band-gap reference circuit is at a low level is avoided, quiescent current is controllable, the on-off of the starting circuit is controlled by monitoring the working current of the band gap, the voltage is used as an auxiliary to ensure reliable control, and the circuit can be ensured to be reliably started under any condition.

Description

Technical Field

[0001] The utility model belongs to the field of electronic technology, and particularly relates to a bandgap reference starting circuit. Background Art

[0002] The bandgap reference circuit is a circuit used to generate a stable reference voltage. It can output a highly stable, low-noise voltage and is little affected by temperature changes. The bandgap reference circuit requires a startup circuit to start it up. Traditional startup circuits are divided into two types, one based on capacitor charging and discharging and the other based on voltage feedback.

[0003] like Figure 1 The figure shows a capacitor charging and discharging startup circuit. I1 and I2 are provided by the bias circuit. In the initial state, point A must be ensured to be at a low potential. When the power is turned on, current I1 charges the capacitor and I2 charges the band gap to activate the band gap. When the band gap is started, VBG (READY) completely shuts down PM1, and I1 pushes point A to a high level to shut down PM0, thereby shutting down the startup circuit. The advantage of this structure is that there is no static current in the startup circuit after startup. The disadvantages are: 1. The capacitor area is generally large; 2. VBG is generally an analog quantity, and PM1 cannot be completely shut down, resulting in static leakage. The generation of READY requires an additional circuit, which increases the complexity of the circuit and is prone to oscillation; 3. Frequent power-on and power-off may cause the potential of point A on C to not be at a relatively low level, resulting in PM0 being unable to turn on and the startup circuit failing; 4. When powered on, in order to ensure that point A is gradually pulled up, I1 must be much larger than the discharge capacity of PM1, which is not conducive to circuit design.

[0004] like Figure 2 The figure shows a voltage feedback startup circuit. I1 and I2 are provided by the bias circuit. This structure is a commonly used voltage feedback startup circuit. In the power-on stage, when the bandgap is not started, VBG is low, and the current I1 pulls point A high, NM0 is turned on, and I2 injects current into BGR to start the bandgap. After the bandgap is started, VBG rises, NM0 is turned on, point A is pulled low, and the startup circuit is turned off. The advantage of this structure is that the circuit structure is simpler, and no capacitor is required, and the area is relatively small. The disadvantage is that VBG may not be guaranteed to be low at the beginning, and may be in an abnormal situation (lower level, generally below 1V, usually around 0.5V, and varies with PVT conditions), resulting in point A cannot be pulled high to turn on NM0, so that the startup circuit cannot take effect and the circuit cannot start normally. If the circuit is to start normally and ensure that point A is pulled high, a larger current of I1 is required. After VBG increases, the power-carrying capacity of NM0 will also increase. In order to pull down point A and turn off NM0, the pull-down current of NM0 needs to be greater than I1. Therefore, the static current of the circuit is generally larger when it is working normally, and it varies greatly due to the influence of PVT. Summary of the invention

[0005] Purpose of the invention: In order to solve the problem that the startup circuit of the bandgap reference circuit module in the prior art has low reliability and is prone to startup failure, the utility model provides a bandgap reference startup circuit.

[0006] Technical solution: A bandgap reference startup circuit includes a first MOS tube, a gate control circuit, a first bias current, a second bias current, a mirror current and a bandgap reference circuit module, wherein the mirror current is a mirror image of the transistor current in the bandgap reference circuit module, the first bias current and the mirror current are both connected to the gate control circuit, the control end of the gate control circuit is connected to the output end of the bandgap reference circuit, the output end of the gate control circuit is connected to the gate of the first MOS tube, the second bias current is connected to the input end of the first MOS tube, and the output end of the first MOS tube is connected to the bandgap reference circuit module.

[0007] Furthermore, the first MOS tube is a first PMOS tube; the gate control circuit includes a second PMOS tube; the gate of the second PMOS tube is connected to the output end of the bandgap reference circuit module, the source is connected to the mirror current and the gate of the first PMOS tube, and the drain is connected to the first bias current.

[0008] Furthermore, when the bandgap reference circuit module is started, the current value of the mirror current is 2 to 4 times the first bias current.

[0009] Furthermore, the first MOS tube is a first NMOS tube; the gate control circuit includes a second NMOS tube and a third PMOS tube; and also includes a third bias current; a mirror current is connected between the gate of the third PMOS tube and a power supply, and a third bias current is connected between the gate and ground; a source of the third PMOS tube is connected to the first bias current, and a drain of the third PMOS tube is connected to the drain of the second NMOS tube and the gate of the first NMOS tube; the gate of the second NMOS tube is connected to the output end of the bandgap reference circuit module, and a source is connected to the first bias current.

[0010] Further, when the bandgap reference circuit module is not started, the mirror current is smaller than the third bias current; when the bandgap reference circuit module is started, the mirror current is larger than the third bias current.

[0011] Furthermore, the transistor current in the bandgap reference circuit module is the total current in the branch connecting the power supply and the transistor of the bandgap reference circuit module.

[0012] Compared with the prior art, the bandgap reference startup circuit provided by the utility model has the following beneficial effects: the circuit structure is simple and easy to implement; the dual monitoring of current and voltage is adopted to avoid the problem that the startup circuit may fail when VBG is at a low level, and the static current is controllable, and point A can also be used as a BG_READY signal for subsequent circuits. This circuit controls the switch of the startup circuit by monitoring the working current of the bandgap, and the voltage is used as an auxiliary to ensure reliable control, which can ensure that the circuit can be reliably turned on under any conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a starting circuit of the capacitor charging and discharging type in the prior art;

[0014] Figure 2 It is a voltage feedback type starting circuit in the prior art;

[0015] Figure 3 It is a circuit schematic diagram of a bandgap reference startup circuit of Embodiment 1;

[0016] Figure 4 This is a circuit schematic diagram of a bandgap reference startup circuit according to Embodiment 2. DETAILED DESCRIPTION

[0017] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments.

[0018] Embodiment 1

[0019] A bandgap reference startup circuit, such as Figure 3 , including a first MOS tube, a gate control circuit, a first bias current I1, a second bias current I2, a mirror current IM_BG and a bandgap reference circuit module BGR, wherein the mirror current IM_BG is a mirror image of the current in the bandgap reference circuit module, the first bias current I1 and the mirror current IM_BG are both connected to the gate control circuit, the control end of the gate control circuit is connected to the output end VBG of the bandgap reference circuit, the output end of the gate control circuit is connected to the gate of the first MOS tube, the second bias current is connected to the input end (source) of the first MOS tube, and the output end (drain) of the first MOS tube is connected to the bandgap reference circuit module. Among them, the current in the bandgap reference circuit module is the total current on the branch connecting the power supply VDD and the BJT (transistor) in the bandgap reference circuit module, that is, the total BJT current I_BG of the bandgap reference circuit.

[0020] In this embodiment, the first MOS transistor is a PMOS transistor, named as the first PMOS transistor PM1; the gate control circuit includes a second PMOS transistor PM0; the gate of the second PMOS transistor PM0 is connected to the output end of the bandgap reference circuit module, the source is connected to the mirror current IM_BG and the gate of the first PMOS transistor PM1, and the drain is connected to the first bias current I1.

[0021] like Figure 3 As shown, the first bias current I1 and the second bias current I2 are provided by the bias circuit, and the mirror current IM_BG is the mirror of the current in the bandgap reference circuit module. After power-on, if the bandgap reference circuit module is not started, point A is pulled down to VBG+VTH0 by the first bias current I1, and the second bias current I2 pulls the source end of the first PMOS tube PM1 up to VDD. When VDD≥(VBG+VTH0+VTH1) (VBG is generally at a low level when not started), the first PMOS tube PM1 is turned on, the startup circuit takes effect, and the bandgap reference circuit module is started. At the same time, the startup current is controlled by the second bias current I2 to prevent BG from overshooting. When the bandgap reference circuit module works, the mirror current IM_BG is generated, and VBG reaches the normal working level, suppressing the pull-down ability of the first bias circuit I1. Under the appropriate mirror current IM_BG current value (to ensure reliable shutdown under various PVT conditions, IM_BG is generally 2 to 4 times of I1), the mirror current IM_BG pulls point A up to completely shut down the first PMOS tube PM1 and shuts down the startup circuit.

[0022] Prior art Figure 2 The startup circuit is only controlled by the voltage VBG. When VBG is at a low level and begins to be sufficient to turn on NM0, the startup circuit fails and the startup function cannot be realized. Figure 2 In comparison, the startup circuit of this embodiment is controlled by the VBG voltage and the BGR transistor current. In the non-starting state, the transistor current of the bandgap reference circuit module is not affected by the VBG voltage. When VBG outputs a lower level (below 1V), although the gate voltage of the first PMOS tube PM0 is VBG, it may cause PM0 to be turned on, but because the BGR transistor current is almost zero in the non-starting state, the mirror current is also almost zero, so that point A is pulled down by the first bias current I1, and the startup circuit takes effect. Therefore, the bandgap reference startup circuit of this embodiment will not fail due to VBG being at a lower level. At the same time, the static current is controllable, and point A can also be used as a BG_READY signal for subsequent circuits. The switch of the startup circuit is controlled by monitoring the working current of the bandgap reference circuit module. The voltage is used as an auxiliary to ensure reliable control, which can ensure that the circuit can be reliably turned on under any conditions, thereby improving the stability and reliability of the startup circuit.

[0023] Embodiment 2

[0024] The difference between the second embodiment and the first embodiment is that the first MOS tube adopts an NMOS tube, which is named as the first NMOS tube NM1; the gate control circuit includes a second NMOS tube NM0 and a third PMOS tube PM0; and also includes a third bias current I0; the mirror current IM_BG is connected between the gate (point A) of the third PMOS tube PM0 and the power supply VDD, and the third bias current I0 is connected between the gate and the ground; the source of the third PMOS tube PM0 is connected to the first bias current I1, and the drain (point B) of the third PMOS tube PM0 is connected to the drain of the second NMOS tube NM0 and the gate of the first NMOS tube NM1; the gate of the second NMOS tube NM0 is connected to the output terminal VBG of the bandgap reference circuit module, and the source is connected to the first bias current I1.

[0025] In terms of parameter design, the mirror current IM_BG should be greater than the third bias current I0 after the bandgap reference circuit module is started. Before the bandgap reference circuit module is started, the mirror current IM_BG is less than the third bias current I0.

[0026] like Figure 4 As shown, the first bias current I1, the second bias current I2 and the third bias current I0 are all from the bias circuit, and the mirror current IM_BG is the triode working current of the bandgap reference current module. When the bandgap reference circuit module is not started, IM_BG is almost 0, the third bias current I0 reliably pulls point A down, the third PMOS tube PM0 is turned on, VBG is low, the second NMOS tube NM0 is not turned on or is not fully turned on, the first bias current I1 on the way pulls point B to a higher level, the first NMOS tube NM1 is turned on, and the second bias current I2 injects current into the bandgap reference circuit module to start the bandgap reference circuit module. After starting, because the mirror current IM_BG is greater than the third bias current I0, it can ensure that point A is pulled up, the third PMOS tube PM0 is turned off or turned on insufficiently, VBG controls the second NMOS tube NM0 to be fully turned on, the pull-down current becomes stronger, and point B is pulled to a lower potential, the first NMOS tube NM1 is turned off, and the startup circuit is disconnected.

[0027] This embodiment uses an NMOS tube to control the startup circuit switch to prevent leakage caused by the potential at point A failing to reach VDD, which results in the startup circuit not being completely shut down.

Claims

1. A bandgap reference startup circuit, characterized in that: The invention comprises a first MOS tube, a gate control circuit, a first bias current, a second bias current, a mirror current and a bandgap reference circuit module, wherein the mirror current is a mirror image of a triode current in the bandgap reference circuit module, the first bias current and the mirror current are both connected to the gate control circuit, the control end of the gate control circuit is connected to the output end of the bandgap reference circuit, the output end of the gate control circuit is connected to the gate of the first MOS tube, the second bias current is connected to the input end of the first MOS tube, and the output end of the first MOS tube is connected to the bandgap reference circuit module.

2. The bandgap reference startup circuit according to claim 1, characterized in that: The first MOS tube is a first PMOS tube; the gate control circuit includes a second PMOS tube; the gate of the second PMOS tube is connected to the output end of the bandgap reference circuit module, the source is connected to the mirror current and the gate of the first PMOS tube, and the drain is connected to the first bias current.

3. The bandgap reference startup circuit according to claim 2, characterized in that: When the bandgap reference circuit module is started, the current value of the mirror current is 2 to 4 times of the first bias current.

4. The bandgap reference startup circuit according to claim 1, characterized in that: The first MOS tube is a first NMOS tube; the gate control circuit includes a second NMOS tube and a third PMOS tube; and also includes a third bias current; a mirror current is connected between the gate of the third PMOS tube and a power supply, and a third bias current is connected between the gate and ground; a source of the third PMOS tube is connected to the first bias current, and a drain of the third PMOS tube is connected to the drain of the second NMOS tube and the gate of the first NMOS tube; The gate of the second NMOS tube is connected to the output end of the bandgap reference circuit module, and the source is connected to the first bias current.

5. The bandgap reference startup circuit according to claim 4, characterized in that: When the bandgap reference circuit module is not started, the mirror current is less than the third bias current; when the bandgap reference circuit module is started, the mirror current is greater than the third bias current.

6. The bandgap reference startup circuit according to any one of claims 1 to 5, characterized in that: The transistor current in the bandgap reference circuit module is the total current in the branch connecting the power supply and the transistor of the bandgap reference circuit module.

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